2 * C-Media CMI8788 driver - main driver module
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <sound/ac97_codec.h>
27 #include <sound/asoundef.h>
28 #include <sound/core.h>
29 #include <sound/info.h>
30 #include <sound/mpu401.h>
31 #include <sound/pcm.h>
35 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
36 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
37 MODULE_LICENSE("GPL v2");
39 #define DRIVER "oxygen"
41 static inline int oxygen_uart_input_ready(struct oxygen *chip)
43 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
46 static void oxygen_read_uart(struct oxygen *chip)
48 if (unlikely(!oxygen_uart_input_ready(chip))) {
49 /* no data, but read it anyway to clear the interrupt */
50 oxygen_read8(chip, OXYGEN_MPU401);
54 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
55 if (data == MPU401_ACK)
57 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
58 chip->uart_input_count = 0;
59 chip->uart_input[chip->uart_input_count++] = data;
60 } while (oxygen_uart_input_ready(chip));
61 if (chip->model.uart_input)
62 chip->model.uart_input(chip);
65 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
67 struct oxygen *chip = dev_id;
68 unsigned int status, clear, elapsed_streams, i;
70 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
74 spin_lock(&chip->reg_lock);
76 clear = status & (OXYGEN_CHANNEL_A |
79 OXYGEN_CHANNEL_SPDIF |
80 OXYGEN_CHANNEL_MULTICH |
82 OXYGEN_INT_SPDIF_IN_DETECT |
86 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
87 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
88 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
89 chip->interrupt_mask & ~clear);
90 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
91 chip->interrupt_mask);
94 elapsed_streams = status & chip->pcm_running;
96 spin_unlock(&chip->reg_lock);
98 for (i = 0; i < PCM_COUNT; ++i)
99 if ((elapsed_streams & (1 << i)) && chip->streams[i])
100 snd_pcm_period_elapsed(chip->streams[i]);
102 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
103 spin_lock(&chip->reg_lock);
104 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
105 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
106 OXYGEN_SPDIF_RATE_INT)) {
107 /* write the interrupt bit(s) to clear */
108 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
109 schedule_work(&chip->spdif_input_bits_work);
111 spin_unlock(&chip->reg_lock);
114 if (status & OXYGEN_INT_GPIO)
115 schedule_work(&chip->gpio_work);
117 if (status & OXYGEN_INT_MIDI) {
119 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
121 oxygen_read_uart(chip);
124 if (status & OXYGEN_INT_AC97)
125 wake_up(&chip->ac97_waitqueue);
130 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
132 struct oxygen *chip = container_of(work, struct oxygen,
133 spdif_input_bits_work);
137 * This function gets called when there is new activity on the SPDIF
138 * input, or when we lose lock on the input signal, or when the rate
142 spin_lock_irq(&chip->reg_lock);
143 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
144 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
145 OXYGEN_SPDIF_LOCK_STATUS))
146 == OXYGEN_SPDIF_SENSE_STATUS) {
148 * If we detect activity on the SPDIF input but cannot lock to
149 * a signal, the clock bit is likely to be wrong.
151 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
152 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
153 spin_unlock_irq(&chip->reg_lock);
155 spin_lock_irq(&chip->reg_lock);
156 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
157 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
158 OXYGEN_SPDIF_LOCK_STATUS))
159 == OXYGEN_SPDIF_SENSE_STATUS) {
160 /* nothing detected with either clock; give up */
161 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
162 == OXYGEN_SPDIF_IN_CLOCK_192) {
164 * Reset clock to <= 96 kHz because this is
165 * more likely to be received next time.
167 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
168 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
169 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
173 spin_unlock_irq(&chip->reg_lock);
175 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
176 spin_lock_irq(&chip->reg_lock);
177 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
178 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
179 chip->interrupt_mask);
180 spin_unlock_irq(&chip->reg_lock);
183 * We don't actually know that any channel status bits have
184 * changed, but let's send a notification just to be sure.
186 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
187 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
191 static void oxygen_gpio_changed(struct work_struct *work)
193 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
195 if (chip->model.gpio_changed)
196 chip->model.gpio_changed(chip);
199 static void oxygen_proc_read(struct snd_info_entry *entry,
200 struct snd_info_buffer *buffer)
202 struct oxygen *chip = entry->private_data;
205 switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) {
206 case OXYGEN_PACKAGE_ID_8786: i = '6'; break;
207 case OXYGEN_PACKAGE_ID_8787: i = '7'; break;
208 case OXYGEN_PACKAGE_ID_8788: i = '8'; break;
209 default: i = '?'; break;
211 snd_iprintf(buffer, "CMI878%c:\n", i);
212 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
213 snd_iprintf(buffer, "%02x:", i);
214 for (j = 0; j < 0x10; ++j)
215 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
216 snd_iprintf(buffer, "\n");
218 if (mutex_lock_interruptible(&chip->mutex) < 0)
220 if (chip->has_ac97_0) {
221 snd_iprintf(buffer, "\nAC97:\n");
222 for (i = 0; i < 0x80; i += 0x10) {
223 snd_iprintf(buffer, "%02x:", i);
224 for (j = 0; j < 0x10; j += 2)
225 snd_iprintf(buffer, " %04x",
226 oxygen_read_ac97(chip, 0, i + j));
227 snd_iprintf(buffer, "\n");
230 if (chip->has_ac97_1) {
231 snd_iprintf(buffer, "\nAC97 2:\n");
232 for (i = 0; i < 0x80; i += 0x10) {
233 snd_iprintf(buffer, "%02x:", i);
234 for (j = 0; j < 0x10; j += 2)
235 snd_iprintf(buffer, " %04x",
236 oxygen_read_ac97(chip, 1, i + j));
237 snd_iprintf(buffer, "\n");
240 mutex_unlock(&chip->mutex);
241 if (chip->model.dump_registers)
242 chip->model.dump_registers(chip, buffer);
245 static void oxygen_proc_init(struct oxygen *chip)
247 snd_card_ro_proc_new(chip->card, "oxygen", chip, oxygen_proc_read);
250 static const struct pci_device_id *
251 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
256 * Make sure the EEPROM pins are available, i.e., not used for SPI.
257 * (This function is called before we initialize or use SPI.)
259 oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
260 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
262 * Read the subsystem device ID directly from the EEPROM, because the
263 * chip didn't if the first EEPROM word was overwritten.
265 subdevice = oxygen_read_eeprom(chip, 2);
266 /* use default ID if EEPROM is missing */
267 if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff)
270 * We use only the subsystem device ID for searching because it is
271 * unique even without the subsystem vendor ID, which may have been
272 * overwritten in the EEPROM.
274 for (; ids->vendor; ++ids)
275 if (ids->subdevice == subdevice &&
276 ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
281 static void oxygen_restore_eeprom(struct oxygen *chip,
282 const struct pci_device_id *id)
286 eeprom_id = oxygen_read_eeprom(chip, 0);
287 if (eeprom_id != OXYGEN_EEPROM_ID &&
288 (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
290 * This function gets called only when a known card model has
291 * been detected, i.e., we know there is a valid subsystem
292 * product ID at index 2 in the EEPROM. Therefore, we have
293 * been able to deduce the correct subsystem vendor ID, and
294 * this is enough information to restore the original EEPROM
297 oxygen_write_eeprom(chip, 1, id->subvendor);
298 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
300 oxygen_set_bits8(chip, OXYGEN_MISC,
301 OXYGEN_MISC_WRITE_PCI_SUBID);
302 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
304 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
306 oxygen_clear_bits8(chip, OXYGEN_MISC,
307 OXYGEN_MISC_WRITE_PCI_SUBID);
309 dev_info(chip->card->dev, "EEPROM ID restored\n");
313 static void configure_pcie_bridge(struct pci_dev *pci)
315 enum { PEX811X, PI7C9X110, XIO2001 };
316 static const struct pci_device_id bridge_ids[] = {
317 { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X },
318 { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X },
319 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
320 { PCI_VDEVICE(TI, 0x8240), .driver_data = XIO2001 },
323 struct pci_dev *bridge;
324 const struct pci_device_id *id;
327 if (!pci->bus || !pci->bus->self)
329 bridge = pci->bus->self;
331 id = pci_match_id(bridge_ids, bridge);
335 switch (id->driver_data) {
336 case PEX811X: /* PLX PEX8111/PEX8112 PCIe/PCI bridge */
337 pci_read_config_dword(bridge, 0x48, &tmp);
338 tmp |= 1; /* enable blind prefetching */
339 tmp |= 1 << 11; /* enable beacon generation */
340 pci_write_config_dword(bridge, 0x48, tmp);
342 pci_write_config_dword(bridge, 0x84, 0x0c);
343 pci_read_config_dword(bridge, 0x88, &tmp);
345 tmp |= 2 << 27; /* set prefetch size to 128 bytes */
346 pci_write_config_dword(bridge, 0x88, tmp);
349 case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */
350 pci_read_config_dword(bridge, 0x40, &tmp);
351 tmp |= 1; /* park the PCI arbiter to the sound chip */
352 pci_write_config_dword(bridge, 0x40, tmp);
355 case XIO2001: /* Texas Instruments XIO2001 PCIe/PCI bridge */
356 pci_read_config_dword(bridge, 0xe8, &tmp);
357 tmp &= ~0xf; /* request length limit: 64 bytes */
359 tmp |= 1 << 8; /* request count limit: one buffer */
360 pci_write_config_dword(bridge, 0xe8, tmp);
365 static void oxygen_init(struct oxygen *chip)
369 chip->dac_routing = 1;
370 for (i = 0; i < 8; ++i)
371 chip->dac_volume[i] = chip->model.dac_volume_min;
373 chip->spdif_playback_enable = 0;
374 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
375 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
376 chip->spdif_pcm_bits = chip->spdif_bits;
378 if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2))
379 oxygen_set_bits8(chip, OXYGEN_MISC,
380 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
382 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
383 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
384 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
386 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
387 OXYGEN_FUNCTION_RESET_CODEC |
388 chip->model.function_flags,
389 OXYGEN_FUNCTION_RESET_CODEC |
390 OXYGEN_FUNCTION_2WIRE_SPI_MASK |
391 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
392 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
393 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
394 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
395 OXYGEN_PLAY_CHANNELS_2 |
396 OXYGEN_DMA_A_BURST_8 |
397 OXYGEN_DMA_MULTICH_BURST_8);
398 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
399 oxygen_write8_masked(chip, OXYGEN_MISC,
400 chip->model.misc_flags,
401 OXYGEN_MISC_WRITE_PCI_SUBID |
402 OXYGEN_MISC_REC_C_FROM_SPDIF |
403 OXYGEN_MISC_REC_B_FROM_AC97 |
404 OXYGEN_MISC_REC_A_FROM_MULTICH |
406 oxygen_write8(chip, OXYGEN_REC_FORMAT,
407 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
408 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
409 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
410 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
411 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
412 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
413 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
414 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
416 chip->model.dac_i2s_format |
417 OXYGEN_I2S_MCLK(chip->model.dac_mclks) |
421 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
422 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
424 chip->model.adc_i2s_format |
425 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
430 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
432 OXYGEN_I2S_MUTE_MCLK);
433 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
434 CAPTURE_2_FROM_I2S_2))
435 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
437 chip->model.adc_i2s_format |
438 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
443 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
445 OXYGEN_I2S_MUTE_MCLK);
446 if (chip->model.device_config & CAPTURE_3_FROM_I2S_3)
447 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
449 chip->model.adc_i2s_format |
450 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
455 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
457 OXYGEN_I2S_MUTE_MCLK);
458 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
459 OXYGEN_SPDIF_OUT_ENABLE |
460 OXYGEN_SPDIF_LOOPBACK);
461 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
462 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
463 OXYGEN_SPDIF_SENSE_MASK |
464 OXYGEN_SPDIF_LOCK_MASK |
465 OXYGEN_SPDIF_RATE_MASK |
466 OXYGEN_SPDIF_LOCK_PAR |
467 OXYGEN_SPDIF_IN_CLOCK_96,
468 OXYGEN_SPDIF_SENSE_MASK |
469 OXYGEN_SPDIF_LOCK_MASK |
470 OXYGEN_SPDIF_RATE_MASK |
471 OXYGEN_SPDIF_SENSE_PAR |
472 OXYGEN_SPDIF_LOCK_PAR |
473 OXYGEN_SPDIF_IN_CLOCK_MASK);
475 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
476 OXYGEN_SPDIF_SENSE_MASK |
477 OXYGEN_SPDIF_LOCK_MASK |
478 OXYGEN_SPDIF_RATE_MASK);
479 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
480 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
481 OXYGEN_2WIRE_LENGTH_8 |
482 OXYGEN_2WIRE_INTERRUPT_MASK |
483 OXYGEN_2WIRE_SPEED_STANDARD);
484 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
485 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
486 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
487 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
488 OXYGEN_PLAY_MULTICH_I2S_DAC |
489 OXYGEN_PLAY_SPDIF_SPDIF |
490 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
491 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
492 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
493 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
494 oxygen_write8(chip, OXYGEN_REC_ROUTING,
495 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
496 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
497 OXYGEN_REC_C_ROUTE_SPDIF);
498 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
499 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
500 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
501 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
502 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
503 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
505 if (chip->has_ac97_0 | chip->has_ac97_1)
506 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
507 OXYGEN_AC97_INT_READ_DONE |
508 OXYGEN_AC97_INT_WRITE_DONE);
510 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
511 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
512 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
513 if (!(chip->has_ac97_0 | chip->has_ac97_1))
514 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
515 OXYGEN_AC97_CLOCK_DISABLE);
516 if (!chip->has_ac97_0) {
517 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
518 OXYGEN_AC97_NO_CODEC_0);
520 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
522 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
523 CM9780_GPIO0IO | CM9780_GPIO1IO);
524 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
525 CM9780_BSTSEL | CM9780_STRO_MIC |
526 CM9780_MIX2FR | CM9780_PCBSW);
527 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
528 CM9780_RSOE | CM9780_CBOE |
529 CM9780_SSOE | CM9780_FROE |
530 CM9780_MIC2MIC | CM9780_LI2LI);
531 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
532 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
533 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
534 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
535 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
536 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
537 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
538 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
539 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
540 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
541 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
543 /* power down unused ADCs and DACs */
544 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
545 AC97_PD_PR0 | AC97_PD_PR1);
546 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
547 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
549 if (chip->has_ac97_1) {
550 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
551 OXYGEN_AC97_CODEC1_SLOT3 |
552 OXYGEN_AC97_CODEC1_SLOT4);
553 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
555 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
556 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
557 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
558 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
559 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
560 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
561 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
562 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
563 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
564 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
565 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
566 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
570 static void oxygen_shutdown(struct oxygen *chip)
572 spin_lock_irq(&chip->reg_lock);
573 chip->interrupt_mask = 0;
574 chip->pcm_running = 0;
575 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
576 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
577 spin_unlock_irq(&chip->reg_lock);
580 static void oxygen_card_free(struct snd_card *card)
582 struct oxygen *chip = card->private_data;
584 oxygen_shutdown(chip);
586 free_irq(chip->irq, chip);
587 flush_work(&chip->spdif_input_bits_work);
588 flush_work(&chip->gpio_work);
589 chip->model.cleanup(chip);
590 kfree(chip->model_data);
591 mutex_destroy(&chip->mutex);
592 pci_release_regions(chip->pci);
593 pci_disable_device(chip->pci);
596 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
597 struct module *owner,
598 const struct pci_device_id *ids,
599 int (*get_model)(struct oxygen *chip,
600 const struct pci_device_id *id
604 struct snd_card *card;
606 const struct pci_device_id *pci_id;
609 err = snd_card_new(&pci->dev, index, id, owner,
610 sizeof(*chip), &card);
614 chip = card->private_data;
618 spin_lock_init(&chip->reg_lock);
619 mutex_init(&chip->mutex);
620 INIT_WORK(&chip->spdif_input_bits_work,
621 oxygen_spdif_input_bits_changed);
622 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
623 init_waitqueue_head(&chip->ac97_waitqueue);
625 err = pci_enable_device(pci);
629 err = pci_request_regions(pci, DRIVER);
631 dev_err(card->dev, "cannot reserve PCI resources\n");
635 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
636 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
637 dev_err(card->dev, "invalid PCI I/O range\n");
639 goto err_pci_regions;
641 chip->addr = pci_resource_start(pci, 0);
643 pci_id = oxygen_search_pci_id(chip, ids);
646 goto err_pci_regions;
648 oxygen_restore_eeprom(chip, pci_id);
649 err = get_model(chip, pci_id);
651 goto err_pci_regions;
653 if (chip->model.model_data_size) {
654 chip->model_data = kzalloc(chip->model.model_data_size,
656 if (!chip->model_data) {
658 goto err_pci_regions;
663 card->private_free = oxygen_card_free;
665 configure_pcie_bridge(pci);
667 chip->model.init(chip);
669 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
670 KBUILD_MODNAME, chip);
672 dev_err(card->dev, "cannot grab interrupt %d\n", pci->irq);
675 chip->irq = pci->irq;
677 strcpy(card->driver, chip->model.chip);
678 strcpy(card->shortname, chip->model.shortname);
679 sprintf(card->longname, "%s at %#lx, irq %i",
680 chip->model.longname, chip->addr, chip->irq);
681 strcpy(card->mixername, chip->model.chip);
682 snd_component_add(card, chip->model.chip);
684 err = oxygen_pcm_init(chip);
688 err = oxygen_mixer_init(chip);
692 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
693 unsigned int info_flags =
694 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK;
695 if (chip->model.device_config & MIDI_OUTPUT)
696 info_flags |= MPU401_INFO_OUTPUT;
697 if (chip->model.device_config & MIDI_INPUT)
698 info_flags |= MPU401_INFO_INPUT;
699 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
700 chip->addr + OXYGEN_MPU401,
701 info_flags, -1, &chip->midi);
706 oxygen_proc_init(chip);
708 spin_lock_irq(&chip->reg_lock);
709 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
710 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
711 if (chip->has_ac97_0 | chip->has_ac97_1)
712 chip->interrupt_mask |= OXYGEN_INT_AC97;
713 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
714 spin_unlock_irq(&chip->reg_lock);
716 err = snd_card_register(card);
720 pci_set_drvdata(pci, card);
724 pci_release_regions(pci);
726 pci_disable_device(pci);
731 EXPORT_SYMBOL(oxygen_pci_probe);
733 void oxygen_pci_remove(struct pci_dev *pci)
735 snd_card_free(pci_get_drvdata(pci));
737 EXPORT_SYMBOL(oxygen_pci_remove);
739 #ifdef CONFIG_PM_SLEEP
740 static int oxygen_pci_suspend(struct device *dev)
742 struct snd_card *card = dev_get_drvdata(dev);
743 struct oxygen *chip = card->private_data;
744 unsigned int saved_interrupt_mask;
746 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
748 if (chip->model.suspend)
749 chip->model.suspend(chip);
751 spin_lock_irq(&chip->reg_lock);
752 saved_interrupt_mask = chip->interrupt_mask;
753 chip->interrupt_mask = 0;
754 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
755 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
756 spin_unlock_irq(&chip->reg_lock);
758 synchronize_irq(chip->irq);
759 flush_work(&chip->spdif_input_bits_work);
760 flush_work(&chip->gpio_work);
761 chip->interrupt_mask = saved_interrupt_mask;
765 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
766 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
767 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
769 static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
770 { 0x18284fa2, 0x03060000 },
771 { 0x00007fa6, 0x00200000 }
774 static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
776 return bitmap[bit / 32] & (1 << (bit & 31));
779 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
783 oxygen_write_ac97(chip, codec, AC97_RESET, 0);
785 for (i = 1; i < 0x40; ++i)
786 if (is_bit_set(ac97_registers_to_restore[codec], i))
787 oxygen_write_ac97(chip, codec, i * 2,
788 chip->saved_ac97_registers[codec][i]);
791 static int oxygen_pci_resume(struct device *dev)
793 struct snd_card *card = dev_get_drvdata(dev);
794 struct oxygen *chip = card->private_data;
797 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
798 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
799 for (i = 0; i < OXYGEN_IO_SIZE; ++i)
800 if (is_bit_set(registers_to_restore, i))
801 oxygen_write8(chip, i, chip->saved_registers._8[i]);
802 if (chip->has_ac97_0)
803 oxygen_restore_ac97(chip, 0);
804 if (chip->has_ac97_1)
805 oxygen_restore_ac97(chip, 1);
807 if (chip->model.resume)
808 chip->model.resume(chip);
810 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
812 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
816 SIMPLE_DEV_PM_OPS(oxygen_pci_pm, oxygen_pci_suspend, oxygen_pci_resume);
817 EXPORT_SYMBOL(oxygen_pci_pm);
818 #endif /* CONFIG_PM_SLEEP */
820 void oxygen_pci_shutdown(struct pci_dev *pci)
822 struct snd_card *card = pci_get_drvdata(pci);
823 struct oxygen *chip = card->private_data;
825 oxygen_shutdown(chip);
826 chip->model.cleanup(chip);
828 EXPORT_SYMBOL(oxygen_pci_shutdown);