sound/pci/maestro3.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
   4  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
   5  *                       Takashi Iwai <tiwai@suse.de>
   6  *
   7  * Most of the hardware init stuffs are based on maestro3 driver for
   8  * OSS/Free by Zach Brown.  Many thanks to Zach!
   9  *
  10  * ChangeLog:
  11  * Aug. 27, 2001
  12  *     - Fixed deadlock on capture
  13  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
  14  */
  15
  16 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
  17 #define DRIVER_NAME "Maestro3"
  18
  19 #include <linux/io.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/init.h>
  23 #include <linux/pci.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/slab.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/module.h>
  28 #include <linux/firmware.h>
  29 #include <linux/input.h>
  30 #include <sound/core.h>
  31 #include <sound/info.h>
  32 #include <sound/control.h>
  33 #include <sound/pcm.h>
  34 #include <sound/mpu401.h>
  35 #include <sound/ac97_codec.h>
  36 #include <sound/initval.h>
  37 #include <asm/byteorder.h>
  38
  39 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
  40 MODULE_DESCRIPTION("ESS Maestro3 PCI");
  41 MODULE_LICENSE("GPL");
  42 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
  43                 "{ESS,ES1988},"
  44                 "{ESS,Allegro PCI},"
  45                 "{ESS,Allegro-1 PCI},"
  46                 "{ESS,Canyon3D-2/LE PCI}}");
  47 MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
  48 MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
  49
  50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  51 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  52 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
  53 static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
  54 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
  55
  56 module_param_array(index, int, NULL, 0444);
  57 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  58 module_param_array(id, charp, NULL, 0444);
  59 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  60 module_param_array(enable, bool, NULL, 0444);
  61 MODULE_PARM_DESC(enable, "Enable this soundcard.");
  62 module_param_array(external_amp, bool, NULL, 0444);
  63 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
  64 module_param_array(amp_gpio, int, NULL, 0444);
  65 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
  66
  67 #define MAX_PLAYBACKS   2
  68 #define MAX_CAPTURES    1
  69 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
  70
  71
  72 /*
  73  * maestro3 registers
  74  */
  75
  76 /* Allegro PCI configuration registers */
  77 #define PCI_LEGACY_AUDIO_CTRL   0x40
  78 #define SOUND_BLASTER_ENABLE    0x00000001
  79 #define FM_SYNTHESIS_ENABLE     0x00000002
  80 #define GAME_PORT_ENABLE        0x00000004
  81 #define MPU401_IO_ENABLE        0x00000008
  82 #define MPU401_IRQ_ENABLE       0x00000010
  83 #define ALIAS_10BIT_IO          0x00000020
  84 #define SB_DMA_MASK             0x000000C0
  85 #define SB_DMA_0                0x00000040
  86 #define SB_DMA_1                0x00000040
  87 #define SB_DMA_R                0x00000080
  88 #define SB_DMA_3                0x000000C0
  89 #define SB_IRQ_MASK             0x00000700
  90 #define SB_IRQ_5                0x00000000
  91 #define SB_IRQ_7                0x00000100
  92 #define SB_IRQ_9                0x00000200
  93 #define SB_IRQ_10               0x00000300
  94 #define MIDI_IRQ_MASK           0x00003800
  95 #define SERIAL_IRQ_ENABLE       0x00004000
  96 #define DISABLE_LEGACY          0x00008000
  97
  98 #define PCI_ALLEGRO_CONFIG      0x50
  99 #define SB_ADDR_240             0x00000004
 100 #define MPU_ADDR_MASK           0x00000018
 101 #define MPU_ADDR_330            0x00000000
 102 #define MPU_ADDR_300            0x00000008
 103 #define MPU_ADDR_320            0x00000010
 104 #define MPU_ADDR_340            0x00000018
 105 #define USE_PCI_TIMING          0x00000040
 106 #define POSTED_WRITE_ENABLE     0x00000080
 107 #define DMA_POLICY_MASK         0x00000700
 108 #define DMA_DDMA                0x00000000
 109 #define DMA_TDMA                0x00000100
 110 #define DMA_PCPCI               0x00000200
 111 #define DMA_WBDMA16             0x00000400
 112 #define DMA_WBDMA4              0x00000500
 113 #define DMA_WBDMA2              0x00000600
 114 #define DMA_WBDMA1              0x00000700
 115 #define DMA_SAFE_GUARD          0x00000800
 116 #define HI_PERF_GP_ENABLE       0x00001000
 117 #define PIC_SNOOP_MODE_0        0x00002000
 118 #define PIC_SNOOP_MODE_1        0x00004000
 119 #define SOUNDBLASTER_IRQ_MASK   0x00008000
 120 #define RING_IN_ENABLE          0x00010000
 121 #define SPDIF_TEST_MODE         0x00020000
 122 #define CLK_MULT_MODE_SELECT_2  0x00040000
 123 #define EEPROM_WRITE_ENABLE     0x00080000
 124 #define CODEC_DIR_IN            0x00100000
 125 #define HV_BUTTON_FROM_GD       0x00200000
 126 #define REDUCED_DEBOUNCE        0x00400000
 127 #define HV_CTRL_ENABLE          0x00800000
 128 #define SPDIF_ENABLE            0x01000000
 129 #define CLK_DIV_SELECT          0x06000000
 130 #define CLK_DIV_BY_48           0x00000000
 131 #define CLK_DIV_BY_49           0x02000000
 132 #define CLK_DIV_BY_50           0x04000000
 133 #define CLK_DIV_RESERVED        0x06000000
 134 #define PM_CTRL_ENABLE          0x08000000
 135 #define CLK_MULT_MODE_SELECT    0x30000000
 136 #define CLK_MULT_MODE_SHIFT     28
 137 #define CLK_MULT_MODE_0         0x00000000
 138 #define CLK_MULT_MODE_1         0x10000000
 139 #define CLK_MULT_MODE_2         0x20000000
 140 #define CLK_MULT_MODE_3         0x30000000
 141 #define INT_CLK_SELECT          0x40000000
 142 #define INT_CLK_MULT_RESET      0x80000000
 143
 144 /* M3 */
 145 #define INT_CLK_SRC_NOT_PCI     0x00100000
 146 #define INT_CLK_MULT_ENABLE     0x80000000
 147
 148 #define PCI_ACPI_CONTROL        0x54
 149 #define PCI_ACPI_D0             0x00000000
 150 #define PCI_ACPI_D1             0xB4F70000
 151 #define PCI_ACPI_D2             0xB4F7B4F7
 152
 153 #define PCI_USER_CONFIG         0x58
 154 #define EXT_PCI_MASTER_ENABLE   0x00000001
 155 #define SPDIF_OUT_SELECT        0x00000002
 156 #define TEST_PIN_DIR_CTRL       0x00000004
 157 #define AC97_CODEC_TEST         0x00000020
 158 #define TRI_STATE_BUFFER        0x00000080
 159 #define IN_CLK_12MHZ_SELECT     0x00000100
 160 #define MULTI_FUNC_DISABLE      0x00000200
 161 #define EXT_MASTER_PAIR_SEL     0x00000400
 162 #define PCI_MASTER_SUPPORT      0x00000800
 163 #define STOP_CLOCK_ENABLE       0x00001000
 164 #define EAPD_DRIVE_ENABLE       0x00002000
 165 #define REQ_TRI_STATE_ENABLE    0x00004000
 166 #define REQ_LOW_ENABLE          0x00008000
 167 #define MIDI_1_ENABLE           0x00010000
 168 #define MIDI_2_ENABLE           0x00020000
 169 #define SB_AUDIO_SYNC           0x00040000
 170 #define HV_CTRL_TEST            0x00100000
 171 #define SOUNDBLASTER_TEST       0x00400000
 172
 173 #define PCI_USER_CONFIG_C       0x5C
 174
 175 #define PCI_DDMA_CTRL           0x60
 176 #define DDMA_ENABLE             0x00000001
 177
 178
 179 /* Allegro registers */
 180 #define HOST_INT_CTRL           0x18
 181 #define SB_INT_ENABLE           0x0001
 182 #define MPU401_INT_ENABLE       0x0002
 183 #define ASSP_INT_ENABLE         0x0010
 184 #define RING_INT_ENABLE         0x0020
 185 #define HV_INT_ENABLE           0x0040
 186 #define CLKRUN_GEN_ENABLE       0x0100
 187 #define HV_CTRL_TO_PME          0x0400
 188 #define SOFTWARE_RESET_ENABLE   0x8000
 189
 190 /*
 191  * should be using the above defines, probably.
 192  */
 193 #define REGB_ENABLE_RESET               0x01
 194 #define REGB_STOP_CLOCK                 0x10
 195
 196 #define HOST_INT_STATUS         0x1A
 197 #define SB_INT_PENDING          0x01
 198 #define MPU401_INT_PENDING      0x02
 199 #define ASSP_INT_PENDING        0x10
 200 #define RING_INT_PENDING        0x20
 201 #define HV_INT_PENDING          0x40
 202
 203 #define HARDWARE_VOL_CTRL       0x1B
 204 #define SHADOW_MIX_REG_VOICE    0x1C
 205 #define HW_VOL_COUNTER_VOICE    0x1D
 206 #define SHADOW_MIX_REG_MASTER   0x1E
 207 #define HW_VOL_COUNTER_MASTER   0x1F
 208
 209 #define CODEC_COMMAND           0x30
 210 #define CODEC_READ_B            0x80
 211
 212 #define CODEC_STATUS            0x30
 213 #define CODEC_BUSY_B            0x01
 214
 215 #define CODEC_DATA              0x32
 216
 217 #define RING_BUS_CTRL_A         0x36
 218 #define RAC_PME_ENABLE          0x0100
 219 #define RAC_SDFS_ENABLE         0x0200
 220 #define LAC_PME_ENABLE          0x0400
 221 #define LAC_SDFS_ENABLE         0x0800
 222 #define SERIAL_AC_LINK_ENABLE   0x1000
 223 #define IO_SRAM_ENABLE          0x2000
 224 #define IIS_INPUT_ENABLE        0x8000
 225
 226 #define RING_BUS_CTRL_B         0x38
 227 #define SECOND_CODEC_ID_MASK    0x0003
 228 #define SPDIF_FUNC_ENABLE       0x0010
 229 #define SECOND_AC_ENABLE        0x0020
 230 #define SB_MODULE_INTF_ENABLE   0x0040
 231 #define SSPE_ENABLE             0x0040
 232 #define M3I_DOCK_ENABLE         0x0080
 233
 234 #define SDO_OUT_DEST_CTRL       0x3A
 235 #define COMMAND_ADDR_OUT        0x0003
 236 #define PCM_LR_OUT_LOCAL        0x0000
 237 #define PCM_LR_OUT_REMOTE       0x0004
 238 #define PCM_LR_OUT_MUTE         0x0008
 239 #define PCM_LR_OUT_BOTH         0x000C
 240 #define LINE1_DAC_OUT_LOCAL     0x0000
 241 #define LINE1_DAC_OUT_REMOTE    0x0010
 242 #define LINE1_DAC_OUT_MUTE      0x0020
 243 #define LINE1_DAC_OUT_BOTH      0x0030
 244 #define PCM_CLS_OUT_LOCAL       0x0000
 245 #define PCM_CLS_OUT_REMOTE      0x0040
 246 #define PCM_CLS_OUT_MUTE        0x0080
 247 #define PCM_CLS_OUT_BOTH        0x00C0
 248 #define PCM_RLF_OUT_LOCAL       0x0000
 249 #define PCM_RLF_OUT_REMOTE      0x0100
 250 #define PCM_RLF_OUT_MUTE        0x0200
 251 #define PCM_RLF_OUT_BOTH        0x0300
 252 #define LINE2_DAC_OUT_LOCAL     0x0000
 253 #define LINE2_DAC_OUT_REMOTE    0x0400
 254 #define LINE2_DAC_OUT_MUTE      0x0800
 255 #define LINE2_DAC_OUT_BOTH      0x0C00
 256 #define HANDSET_OUT_LOCAL       0x0000
 257 #define HANDSET_OUT_REMOTE      0x1000
 258 #define HANDSET_OUT_MUTE        0x2000
 259 #define HANDSET_OUT_BOTH        0x3000
 260 #define IO_CTRL_OUT_LOCAL       0x0000
 261 #define IO_CTRL_OUT_REMOTE      0x4000
 262 #define IO_CTRL_OUT_MUTE        0x8000
 263 #define IO_CTRL_OUT_BOTH        0xC000
 264
 265 #define SDO_IN_DEST_CTRL        0x3C
 266 #define STATUS_ADDR_IN          0x0003
 267 #define PCM_LR_IN_LOCAL         0x0000
 268 #define PCM_LR_IN_REMOTE        0x0004
 269 #define PCM_LR_RESERVED         0x0008
 270 #define PCM_LR_IN_BOTH          0x000C
 271 #define LINE1_ADC_IN_LOCAL      0x0000
 272 #define LINE1_ADC_IN_REMOTE     0x0010
 273 #define LINE1_ADC_IN_MUTE       0x0020
 274 #define MIC_ADC_IN_LOCAL        0x0000
 275 #define MIC_ADC_IN_REMOTE       0x0040
 276 #define MIC_ADC_IN_MUTE         0x0080
 277 #define LINE2_DAC_IN_LOCAL      0x0000
 278 #define LINE2_DAC_IN_REMOTE     0x0400
 279 #define LINE2_DAC_IN_MUTE       0x0800
 280 #define HANDSET_IN_LOCAL        0x0000
 281 #define HANDSET_IN_REMOTE       0x1000
 282 #define HANDSET_IN_MUTE         0x2000
 283 #define IO_STATUS_IN_LOCAL      0x0000
 284 #define IO_STATUS_IN_REMOTE     0x4000
 285
 286 #define SPDIF_IN_CTRL           0x3E
 287 #define SPDIF_IN_ENABLE         0x0001
 288
 289 #define GPIO_DATA               0x60
 290 #define GPIO_DATA_MASK          0x0FFF
 291 #define GPIO_HV_STATUS          0x3000
 292 #define GPIO_PME_STATUS         0x4000
 293
 294 #define GPIO_MASK               0x64
 295 #define GPIO_DIRECTION          0x68
 296 #define GPO_PRIMARY_AC97        0x0001
 297 #define GPI_LINEOUT_SENSE       0x0004
 298 #define GPO_SECONDARY_AC97      0x0008
 299 #define GPI_VOL_DOWN            0x0010
 300 #define GPI_VOL_UP              0x0020
 301 #define GPI_IIS_CLK             0x0040
 302 #define GPI_IIS_LRCLK           0x0080
 303 #define GPI_IIS_DATA            0x0100
 304 #define GPI_DOCKING_STATUS      0x0100
 305 #define GPI_HEADPHONE_SENSE     0x0200
 306 #define GPO_EXT_AMP_SHUTDOWN    0x1000
 307
 308 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
 309 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
 310
 311 /* M3 */
 312 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
 313
 314 #define ASSP_INDEX_PORT         0x80
 315 #define ASSP_MEMORY_PORT        0x82
 316 #define ASSP_DATA_PORT          0x84
 317
 318 #define MPU401_DATA_PORT        0x98
 319 #define MPU401_STATUS_PORT      0x99
 320
 321 #define CLK_MULT_DATA_PORT      0x9C
 322
 323 #define ASSP_CONTROL_A          0xA2
 324 #define ASSP_0_WS_ENABLE        0x01
 325 #define ASSP_CTRL_A_RESERVED1   0x02
 326 #define ASSP_CTRL_A_RESERVED2   0x04
 327 #define ASSP_CLK_49MHZ_SELECT   0x08
 328 #define FAST_PLU_ENABLE         0x10
 329 #define ASSP_CTRL_A_RESERVED3   0x20
 330 #define DSP_CLK_36MHZ_SELECT    0x40
 331
 332 #define ASSP_CONTROL_B          0xA4
 333 #define RESET_ASSP              0x00
 334 #define RUN_ASSP                0x01
 335 #define ENABLE_ASSP_CLOCK       0x00
 336 #define STOP_ASSP_CLOCK         0x10
 337 #define RESET_TOGGLE            0x40
 338
 339 #define ASSP_CONTROL_C          0xA6
 340 #define ASSP_HOST_INT_ENABLE    0x01
 341 #define FM_ADDR_REMAP_DISABLE   0x02
 342 #define HOST_WRITE_PORT_ENABLE  0x08
 343
 344 #define ASSP_HOST_INT_STATUS    0xAC
 345 #define DSP2HOST_REQ_PIORECORD  0x01
 346 #define DSP2HOST_REQ_I2SRATE    0x02
 347 #define DSP2HOST_REQ_TIMER      0x04
 348
 349 /*
 350  * ASSP control regs
 351  */
 352 #define DSP_PORT_TIMER_COUNT    0x06
 353
 354 #define DSP_PORT_MEMORY_INDEX   0x80
 355
 356 #define DSP_PORT_MEMORY_TYPE    0x82
 357 #define MEMTYPE_INTERNAL_CODE   0x0002
 358 #define MEMTYPE_INTERNAL_DATA   0x0003
 359 #define MEMTYPE_MASK            0x0003
 360
 361 #define DSP_PORT_MEMORY_DATA    0x84
 362
 363 #define DSP_PORT_CONTROL_REG_A  0xA2
 364 #define DSP_PORT_CONTROL_REG_B  0xA4
 365 #define DSP_PORT_CONTROL_REG_C  0xA6
 366
 367 #define REV_A_CODE_MEMORY_BEGIN         0x0000
 368 #define REV_A_CODE_MEMORY_END           0x0FFF
 369 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
 370 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
 371
 372 #define REV_B_CODE_MEMORY_BEGIN         0x0000
 373 #define REV_B_CODE_MEMORY_END           0x0BFF
 374 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
 375 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
 376
 377 #define REV_A_DATA_MEMORY_BEGIN         0x1000
 378 #define REV_A_DATA_MEMORY_END           0x2FFF
 379 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
 380 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
 381
 382 #define REV_B_DATA_MEMORY_BEGIN         0x1000
 383 #define REV_B_DATA_MEMORY_END           0x2BFF
 384 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
 385 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
 386
 387
 388 #define NUM_UNITS_KERNEL_CODE          16
 389 #define NUM_UNITS_KERNEL_DATA           2
 390
 391 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
 392 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
 393
 394 /*
 395  * Kernel data layout
 396  */
 397
 398 #define DP_SHIFT_COUNT                  7
 399
 400 #define KDATA_BASE_ADDR                 0x1000
 401 #define KDATA_BASE_ADDR2                0x1080
 402
 403 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
 404 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
 405 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
 406 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
 407 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
 408 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
 409 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
 410 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
 411 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
 412
 413 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
 414 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
 415
 416 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
 417 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
 418 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
 419 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
 420 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
 421 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
 422 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
 423 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
 424 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
 425 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
 426
 427 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
 428 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
 429
 430 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
 431 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
 432
 433 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
 434 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
 435
 436 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
 437 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
 438 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
 439
 440 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
 441 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
 442 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
 443 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
 444 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
 445
 446 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
 447 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
 448 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
 449
 450 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
 451 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
 452 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
 453
 454 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
 455 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
 456 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
 457 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
 458 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
 459 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
 460 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
 461 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
 462 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
 463 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
 464
 465 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
 466 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
 467 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
 468
 469 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
 470 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
 471
 472 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
 473 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
 474 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
 475
 476 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
 477 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
 478 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
 479 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
 480 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
 481 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
 482
 483 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
 484 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
 485 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
 486 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
 487 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
 488 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
 489
 490 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)
 491 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
 492 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
 493 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
 494 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
 495 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
 496
 497 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
 498 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
 499 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
 500 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
 501
 502 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
 503 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
 504
 505 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
 506 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
 507
 508 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
 509 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
 510 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
 511 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
 512 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
 513
 514 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
 515 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
 516
 517 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
 518 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
 519 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
 520
 521 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
 522 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
 523
 524 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
 525
 526 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
 527 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
 528 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
 529 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
 530 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
 531 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
 532 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
 533 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
 534 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
 535 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
 536 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
 537 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
 538
 539 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
 540 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
 541 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
 542 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
 543
 544 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
 545 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
 546
 547 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
 548 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
 549 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
 550 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
 551
 552 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
 553 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
 554 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
 555 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
 556 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
 557
 558 /*
 559  * second 'segment' (?) reserved for mixer
 560  * buffers..
 561  */
 562
 563 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
 564 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
 565 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
 566 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
 567 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
 568 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
 569 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
 570 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
 571 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
 572 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
 573 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
 574 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
 575 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
 576 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
 577 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
 578 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
 579
 580 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
 581 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
 582 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
 583 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
 584 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
 585 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
 586 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
 587 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
 588 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
 589 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
 590 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
 591
 592 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
 593 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
 594 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
 595 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
 596 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
 597 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
 598
 599 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
 600 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
 601 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
 602 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
 603
 604 /*
 605  * client data area offsets
 606  */
 607 #define CDATA_INSTANCE_READY            0x00
 608
 609 #define CDATA_HOST_SRC_ADDRL            0x01
 610 #define CDATA_HOST_SRC_ADDRH            0x02
 611 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
 612 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
 613 #define CDATA_HOST_SRC_CURRENTL         0x05
 614 #define CDATA_HOST_SRC_CURRENTH         0x06
 615
 616 #define CDATA_IN_BUF_CONNECT            0x07
 617 #define CDATA_OUT_BUF_CONNECT           0x08
 618
 619 #define CDATA_IN_BUF_BEGIN              0x09
 620 #define CDATA_IN_BUF_END_PLUS_1         0x0A
 621 #define CDATA_IN_BUF_HEAD               0x0B
 622 #define CDATA_IN_BUF_TAIL               0x0C
 623 #define CDATA_OUT_BUF_BEGIN             0x0D
 624 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
 625 #define CDATA_OUT_BUF_HEAD              0x0F
 626 #define CDATA_OUT_BUF_TAIL              0x10
 627
 628 #define CDATA_DMA_CONTROL               0x11
 629 #define CDATA_RESERVED                  0x12
 630
 631 #define CDATA_FREQUENCY                 0x13
 632 #define CDATA_LEFT_VOLUME               0x14
 633 #define CDATA_RIGHT_VOLUME              0x15
 634 #define CDATA_LEFT_SUR_VOL              0x16
 635 #define CDATA_RIGHT_SUR_VOL             0x17
 636
 637 #define CDATA_HEADER_LEN                0x18
 638
 639 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
 640 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
 641 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
 642 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
 643 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
 644 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
 645 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
 646 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
 647
 648 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
 649 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
 650 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
 651 #define MINISRC_BIQUAD_STAGE    2
 652 #define MINISRC_COEF_LOC          0x175
 653
 654 #define DMACONTROL_BLOCK_MASK           0x000F
 655 #define  DMAC_BLOCK0_SELECTOR           0x0000
 656 #define  DMAC_BLOCK1_SELECTOR           0x0001
 657 #define  DMAC_BLOCK2_SELECTOR           0x0002
 658 #define  DMAC_BLOCK3_SELECTOR           0x0003
 659 #define  DMAC_BLOCK4_SELECTOR           0x0004
 660 #define  DMAC_BLOCK5_SELECTOR           0x0005
 661 #define  DMAC_BLOCK6_SELECTOR           0x0006
 662 #define  DMAC_BLOCK7_SELECTOR           0x0007
 663 #define  DMAC_BLOCK8_SELECTOR           0x0008
 664 #define  DMAC_BLOCK9_SELECTOR           0x0009
 665 #define  DMAC_BLOCKA_SELECTOR           0x000A
 666 #define  DMAC_BLOCKB_SELECTOR           0x000B
 667 #define  DMAC_BLOCKC_SELECTOR           0x000C
 668 #define  DMAC_BLOCKD_SELECTOR           0x000D
 669 #define  DMAC_BLOCKE_SELECTOR           0x000E
 670 #define  DMAC_BLOCKF_SELECTOR           0x000F
 671 #define DMACONTROL_PAGE_MASK            0x00F0
 672 #define  DMAC_PAGE0_SELECTOR            0x0030
 673 #define  DMAC_PAGE1_SELECTOR            0x0020
 674 #define  DMAC_PAGE2_SELECTOR            0x0010
 675 #define  DMAC_PAGE3_SELECTOR            0x0000
 676 #define DMACONTROL_AUTOREPEAT           0x1000
 677 #define DMACONTROL_STOPPED              0x2000
 678 #define DMACONTROL_DIRECTION            0x0100
 679
 680 /*
 681  * an arbitrary volume we set the internal
 682  * volume settings to so that the ac97 volume
 683  * range is a little less insane.  0x7fff is
 684  * max.
 685  */
 686 #define ARB_VOLUME ( 0x6800 )
 687
 688 /*
 689  */
 690
 691 struct m3_list {
 692         int curlen;
 693         int mem_addr;
 694         int max;
 695 };
 696
 697 struct m3_dma {
 698
 699         int number;
 700         struct snd_pcm_substream *substream;
 701
 702         struct assp_instance {
 703                 unsigned short code, data;
 704         } inst;
 705
 706         int running;
 707         int opened;
 708
 709         unsigned long buffer_addr;
 710         int dma_size;
 711         int period_size;
 712         unsigned int hwptr;
 713         int count;
 714
 715         int index[3];
 716         struct m3_list *index_list[3];
 717
 718         int in_lists;
 719
 720         struct list_head list;
 721
 722 };
 723
 724 struct snd_m3 {
 725
 726         struct snd_card *card;
 727
 728         unsigned long iobase;
 729
 730         int irq;
 731         unsigned int allegro_flag : 1;
 732
 733         struct snd_ac97 *ac97;
 734
 735         struct snd_pcm *pcm;
 736
 737         struct pci_dev *pci;
 738
 739         int dacs_active;
 740         int timer_users;
 741
 742         struct m3_list  msrc_list;
 743         struct m3_list  mixer_list;
 744         struct m3_list  adc1_list;
 745         struct m3_list  dma_list;
 746
 747         /* for storing reset state..*/
 748         u8 reset_state;
 749
 750         int external_amp;
 751         int amp_gpio;   /* gpio pin #  for external amp, -1 = default */
 752         unsigned int hv_config;         /* hardware-volume config bits */
 753         unsigned irda_workaround :1;    /* avoid to touch 0x10 on GPIO_DIRECTION
 754                                            (e.g. for IrDA on Dell Inspirons) */
 755         unsigned is_omnibook :1;        /* Do HP OmniBook GPIO magic? */
 756
 757         /* midi */
 758         struct snd_rawmidi *rmidi;
 759
 760         /* pcm streams */
 761         int num_substreams;
 762         struct m3_dma *substreams;
 763
 764         spinlock_t reg_lock;
 765
 766 #ifdef CONFIG_SND_MAESTRO3_INPUT
 767         struct input_dev *input_dev;
 768         char phys[64];                  /* physical device path */
 769 #else
 770         struct snd_kcontrol *master_switch;
 771         struct snd_kcontrol *master_volume;
 772 #endif
 773         struct work_struct hwvol_work;
 774
 775         unsigned int in_suspend;
 776
 777 #ifdef CONFIG_PM_SLEEP
 778         u16 *suspend_mem;
 779 #endif
 780
 781         const struct firmware *assp_kernel_image;
 782         const struct firmware *assp_minisrc_image;
 783 };
 784
 785 /*
 786  * pci ids
 787  */
 788 static const struct pci_device_id snd_m3_ids[] = {
 789         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
 790          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 791         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
 792          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 793         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
 794          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 795         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
 796          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 797         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
 798          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 799         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
 800          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 801         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
 802          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 803         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
 804          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
 805         {0,},
 806 };
 807
 808 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
 809
 810 static struct snd_pci_quirk m3_amp_quirk_list[] = {
 811         SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
 812         SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
 813         SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
 814         SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
 815         SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
 816         { } /* END */
 817 };
 818
 819 static struct snd_pci_quirk m3_irda_quirk_list[] = {
 820         SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
 821         SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
 822         SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
 823         { } /* END */
 824 };
 825
 826 /* hardware volume quirks */
 827 static struct snd_pci_quirk m3_hv_quirk_list[] = {
 828         /* Allegro chips */
 829         SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 830         SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 831         SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 832         SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 833         SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 834         SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 835         SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 836         SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 837         SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 838         SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 839         SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 840         SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 841         SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 842         SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 843         SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 844         SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 845         SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 846         SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 847         SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 848         SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 849         SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 850         SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 851         SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 852         SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 853         SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
 854         SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
 855                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 856         SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
 857                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 858         SND_PCI_QUIRK(0x107B, 0x340A, NULL,
 859                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 860         SND_PCI_QUIRK(0x107B, 0x3450, NULL,
 861                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 862         SND_PCI_QUIRK(0x109F, 0x3134, NULL,
 863                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 864         SND_PCI_QUIRK(0x109F, 0x3161, NULL,
 865                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 866         SND_PCI_QUIRK(0x144D, 0x3280, NULL,
 867                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 868         SND_PCI_QUIRK(0x144D, 0x3281, NULL,
 869                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 870         SND_PCI_QUIRK(0x144D, 0xC002, NULL,
 871                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 872         SND_PCI_QUIRK(0x144D, 0xC003, NULL,
 873                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 874         SND_PCI_QUIRK(0x1509, 0x1740, NULL,
 875                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 876         SND_PCI_QUIRK(0x1610, 0x0010, NULL,
 877                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
 878         SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
 879         SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
 880         SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
 881         SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
 882         SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
 883         /* Maestro3 chips */
 884         SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
 885         SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
 886         SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
 887         SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
 888         SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
 889         SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
 890         SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
 891         SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
 892         SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
 893         SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
 894         SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
 895         SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
 896         SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
 897         SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 898         SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 899         SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 900         SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
 901         { } /* END */
 902 };
 903
 904 /* HP Omnibook quirks */
 905 static struct snd_pci_quirk m3_omnibook_quirk_list[] = {
 906         SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
 907         SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
 908         { } /* END */
 909 };
 910
 911 /*
 912  * lowlevel functions
 913  */
 914
 915 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
 916 {
 917         outw(value, chip->iobase + reg);
 918 }
 919
 920 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
 921 {
 922         return inw(chip->iobase + reg);
 923 }
 924
 925 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
 926 {
 927         outb(value, chip->iobase + reg);
 928 }
 929
 930 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
 931 {
 932         return inb(chip->iobase + reg);
 933 }
 934
 935 /*
 936  * access 16bit words to the code or data regions of the dsp's memory.
 937  * index addresses 16bit words.
 938  */
 939 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
 940 {
 941         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
 942         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
 943         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
 944 }
 945
 946 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
 947 {
 948         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
 949         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
 950         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
 951 }
 952
 953 static void snd_m3_assp_halt(struct snd_m3 *chip)
 954 {
 955         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
 956         msleep(10);
 957         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
 958 }
 959
 960 static void snd_m3_assp_continue(struct snd_m3 *chip)
 961 {
 962         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
 963 }
 964
 965
 966 /*
 967  * This makes me sad. the maestro3 has lists
 968  * internally that must be packed.. 0 terminates,
 969  * apparently, or maybe all unused entries have
 970  * to be 0, the lists have static lengths set
 971  * by the binary code images.
 972  */
 973
 974 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
 975 {
 976         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
 977                           list->mem_addr + list->curlen,
 978                           val);
 979         return list->curlen++;
 980 }
 981
 982 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
 983 {
 984         u16  val;
 985         int lastindex = list->curlen - 1;
 986
 987         if (index != lastindex) {
 988                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
 989                                        list->mem_addr + lastindex);
 990                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
 991                                   list->mem_addr + index,
 992                                   val);
 993         }
 994
 995         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
 996                           list->mem_addr + lastindex,
 997                           0);
 998
 999         list->curlen--;
1000 }
1001
1002 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1003 {
1004         chip->timer_users++;
1005         if (chip->timer_users != 1)
1006                 return;
1007
1008         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1009                           KDATA_TIMER_COUNT_RELOAD,
1010                           240);
1011
1012         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1013                           KDATA_TIMER_COUNT_CURRENT,
1014                           240);
1015
1016         snd_m3_outw(chip,
1017                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1018                     HOST_INT_CTRL);
1019 }
1020
1021 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1022 {
1023         chip->timer_users--;
1024         if (chip->timer_users > 0)
1025                 return;
1026
1027         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1028                           KDATA_TIMER_COUNT_RELOAD,
1029                           0);
1030
1031         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1032                           KDATA_TIMER_COUNT_CURRENT,
1033                           0);
1034
1035         snd_m3_outw(chip,
1036                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1037                     HOST_INT_CTRL);
1038 }
1039
1040 /*
1041  * start/stop
1042  */
1043
1044 /* spinlock held! */
1045 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1046                             struct snd_pcm_substream *subs)
1047 {
1048         if (! s || ! subs)
1049                 return -EINVAL;
1050
1051         snd_m3_inc_timer_users(chip);
1052         switch (subs->stream) {
1053         case SNDRV_PCM_STREAM_PLAYBACK:
1054                 chip->dacs_active++;
1055                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1056                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1057                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1058                                   KDATA_MIXER_TASK_NUMBER,
1059                                   chip->dacs_active);
1060                 break;
1061         case SNDRV_PCM_STREAM_CAPTURE:
1062                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1063                                   KDATA_ADC1_REQUEST, 1);
1064                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1065                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1066                 break;
1067         }
1068         return 0;
1069 }
1070
1071 /* spinlock held! */
1072 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1073                            struct snd_pcm_substream *subs)
1074 {
1075         if (! s || ! subs)
1076                 return -EINVAL;
1077
1078         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1079                           s->inst.data + CDATA_INSTANCE_READY, 0);
1080         snd_m3_dec_timer_users(chip);
1081         switch (subs->stream) {
1082         case SNDRV_PCM_STREAM_PLAYBACK:
1083                 chip->dacs_active--;
1084                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1085                                   KDATA_MIXER_TASK_NUMBER,
1086                                   chip->dacs_active);
1087                 break;
1088         case SNDRV_PCM_STREAM_CAPTURE:
1089                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1090                                   KDATA_ADC1_REQUEST, 0);
1091                 break;
1092         }
1093         return 0;
1094 }
1095
1096 static int
1097 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1098 {
1099         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1100         struct m3_dma *s = subs->runtime->private_data;
1101         int err = -EINVAL;
1102
1103         if (snd_BUG_ON(!s))
1104                 return -ENXIO;
1105
1106         spin_lock(&chip->reg_lock);
1107         switch (cmd) {
1108         case SNDRV_PCM_TRIGGER_START:
1109         case SNDRV_PCM_TRIGGER_RESUME:
1110                 if (s->running)
1111                         err = -EBUSY;
1112                 else {
1113                         s->running = 1;
1114                         err = snd_m3_pcm_start(chip, s, subs);
1115                 }
1116                 break;
1117         case SNDRV_PCM_TRIGGER_STOP:
1118         case SNDRV_PCM_TRIGGER_SUSPEND:
1119                 if (! s->running)
1120                         err = 0; /* should return error? */
1121                 else {
1122                         s->running = 0;
1123                         err = snd_m3_pcm_stop(chip, s, subs);
1124                 }
1125                 break;
1126         }
1127         spin_unlock(&chip->reg_lock);
1128         return err;
1129 }
1130
1131 /*
1132  * setup
1133  */
1134 static void
1135 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1136 {
1137         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1138         struct snd_pcm_runtime *runtime = subs->runtime;
1139
1140         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1141                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1142                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1143         } else {
1144                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1145                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1146         }
1147         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1148         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1149
1150         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1151         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1152         s->hwptr = 0;
1153         s->count = 0;
1154
1155 #define LO(x) ((x) & 0xffff)
1156 #define HI(x) LO((x) >> 16)
1157
1158         /* host dma buffer pointers */
1159         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1160                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1161                           LO(s->buffer_addr));
1162
1163         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1164                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1165                           HI(s->buffer_addr));
1166
1167         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1168                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1169                           LO(s->buffer_addr + s->dma_size));
1170
1171         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1172                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1173                           HI(s->buffer_addr + s->dma_size));
1174
1175         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1176                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1177                           LO(s->buffer_addr));
1178
1179         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1180                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1181                           HI(s->buffer_addr));
1182 #undef LO
1183 #undef HI
1184
1185         /* dsp buffers */
1186
1187         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1188                           s->inst.data + CDATA_IN_BUF_BEGIN,
1189                           dsp_in_buffer);
1190
1191         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1192                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1193                           dsp_in_buffer + (dsp_in_size / 2));
1194
1195         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1196                           s->inst.data + CDATA_IN_BUF_HEAD,
1197                           dsp_in_buffer);
1198
1199         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1200                           s->inst.data + CDATA_IN_BUF_TAIL,
1201                           dsp_in_buffer);
1202
1203         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1204                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1205                           dsp_out_buffer);
1206
1207         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1208                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1209                           dsp_out_buffer + (dsp_out_size / 2));
1210
1211         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1212                           s->inst.data + CDATA_OUT_BUF_HEAD,
1213                           dsp_out_buffer);
1214
1215         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1216                           s->inst.data + CDATA_OUT_BUF_TAIL,
1217                           dsp_out_buffer);
1218 }
1219
1220 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1221                               struct snd_pcm_runtime *runtime)
1222 {
1223         u32 freq;
1224
1225         /*
1226          * put us in the lists if we're not already there
1227          */
1228         if (! s->in_lists) {
1229                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1230                                               s->inst.data >> DP_SHIFT_COUNT);
1231                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1232                                               s->inst.data >> DP_SHIFT_COUNT);
1233                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1234                                               s->inst.data >> DP_SHIFT_COUNT);
1235                 s->in_lists = 1;
1236         }
1237
1238         /* write to 'mono' word */
1239         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1240                           s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1241                           runtime->channels == 2 ? 0 : 1);
1242         /* write to '8bit' word */
1243         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1244                           s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1245                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1246
1247         /* set up dac/adc rate */
1248         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1249         if (freq)
1250                 freq--;
1251
1252         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1253                           s->inst.data + CDATA_FREQUENCY,
1254                           freq);
1255 }
1256
1257
1258 static const struct play_vals {
1259         u16 addr, val;
1260 } pv[] = {
1261         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1262         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1263         {SRC3_DIRECTION_OFFSET, 0} ,
1264         /* +1, +2 are stereo/16 bit */
1265         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1266         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1267         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1268         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1269         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1270         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1271         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1272         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1273         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1274         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1275         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1276         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1277         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1278         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1279         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1280         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1281         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1282 };
1283
1284
1285 /* the mode passed should be already shifted and masked */
1286 static void
1287 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1288                       struct snd_pcm_substream *subs)
1289 {
1290         unsigned int i;
1291
1292         /*
1293          * some per client initializers
1294          */
1295
1296         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1297                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1298                           s->inst.data + 40 + 8);
1299
1300         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1301                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1302                           s->inst.code + MINISRC_COEF_LOC);
1303
1304         /* enable or disable low pass filter? */
1305         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1306                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1307                           subs->runtime->rate > 45000 ? 0xff : 0);
1308
1309         /* tell it which way dma is going? */
1310         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1311                           s->inst.data + CDATA_DMA_CONTROL,
1312                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1313
1314         /*
1315          * set an armload of static initializers
1316          */
1317         for (i = 0; i < ARRAY_SIZE(pv); i++)
1318                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1319                                   s->inst.data + pv[i].addr, pv[i].val);
1320 }
1321
1322 /*
1323  *    Native record driver
1324  */
1325 static const struct rec_vals {
1326         u16 addr, val;
1327 } rv[] = {
1328         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1329         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1330         {SRC3_DIRECTION_OFFSET, 1} ,
1331         /* +1, +2 are stereo/16 bit */
1332         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1333         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1334         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1335         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1336         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1337         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1338         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1339         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1340         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1341         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1342         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1343         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1344         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1345         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1346         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1347         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1348         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1349         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1350         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1351 };
1352
1353 static void
1354 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1355 {
1356         unsigned int i;
1357
1358         /*
1359          * some per client initializers
1360          */
1361
1362         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1363                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1364                           s->inst.data + 40 + 8);
1365
1366         /* tell it which way dma is going? */
1367         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1368                           s->inst.data + CDATA_DMA_CONTROL,
1369                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1370                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1371
1372         /*
1373          * set an armload of static initializers
1374          */
1375         for (i = 0; i < ARRAY_SIZE(rv); i++)
1376                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1377                                   s->inst.data + rv[i].addr, rv[i].val);
1378 }
1379
1380 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1381                                 struct snd_pcm_hw_params *hw_params)
1382 {
1383         struct m3_dma *s = substream->runtime->private_data;
1384         int err;
1385
1386         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1387                 return err;
1388         /* set buffer address */
1389         s->buffer_addr = substream->runtime->dma_addr;
1390         if (s->buffer_addr & 0x3) {
1391                 dev_err(substream->pcm->card->dev, "oh my, not aligned\n");
1392                 s->buffer_addr = s->buffer_addr & ~0x3;
1393         }
1394         return 0;
1395 }
1396
1397 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1398 {
1399         struct m3_dma *s;
1400
1401         if (substream->runtime->private_data == NULL)
1402                 return 0;
1403         s = substream->runtime->private_data;
1404         snd_pcm_lib_free_pages(substream);
1405         s->buffer_addr = 0;
1406         return 0;
1407 }
1408
1409 static int
1410 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1411 {
1412         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1413         struct snd_pcm_runtime *runtime = subs->runtime;
1414         struct m3_dma *s = runtime->private_data;
1415
1416         if (snd_BUG_ON(!s))
1417                 return -ENXIO;
1418
1419         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1420             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1421                 return -EINVAL;
1422         if (runtime->rate > 48000 ||
1423             runtime->rate < 8000)
1424                 return -EINVAL;
1425
1426         spin_lock_irq(&chip->reg_lock);
1427
1428         snd_m3_pcm_setup1(chip, s, subs);
1429
1430         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1431                 snd_m3_playback_setup(chip, s, subs);
1432         else
1433                 snd_m3_capture_setup(chip, s, subs);
1434
1435         snd_m3_pcm_setup2(chip, s, runtime);
1436
1437         spin_unlock_irq(&chip->reg_lock);
1438
1439         return 0;
1440 }
1441
1442 /*
1443  * get current pointer
1444  */
1445 static unsigned int
1446 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1447 {
1448         u16 hi = 0, lo = 0;
1449         int retry = 10;
1450         u32 addr;
1451
1452         /*
1453          * try and get a valid answer
1454          */
1455         while (retry--) {
1456                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1457                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1458
1459                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1460                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1461
1462                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1463                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1464                         break;
1465         }
1466         addr = lo | ((u32)hi<<16);
1467         return (unsigned int)(addr - s->buffer_addr);
1468 }
1469
1470 static snd_pcm_uframes_t
1471 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1472 {
1473         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1474         unsigned int ptr;
1475         struct m3_dma *s = subs->runtime->private_data;
1476
1477         if (snd_BUG_ON(!s))
1478                 return 0;
1479
1480         spin_lock(&chip->reg_lock);
1481         ptr = snd_m3_get_pointer(chip, s, subs);
1482         spin_unlock(&chip->reg_lock);
1483         return bytes_to_frames(subs->runtime, ptr);
1484 }
1485
1486
1487 /* update pointer */
1488 /* spinlock held! */
1489 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1490 {
1491         struct snd_pcm_substream *subs = s->substream;
1492         unsigned int hwptr;
1493         int diff;
1494
1495         if (! s->running)
1496                 return;
1497
1498         hwptr = snd_m3_get_pointer(chip, s, subs);
1499
1500         /* try to avoid expensive modulo divisions */
1501         if (hwptr >= s->dma_size)
1502                 hwptr %= s->dma_size;
1503
1504         diff = s->dma_size + hwptr - s->hwptr;
1505         if (diff >= s->dma_size)
1506                 diff %= s->dma_size;
1507
1508         s->hwptr = hwptr;
1509         s->count += diff;
1510
1511         if (s->count >= (signed)s->period_size) {
1512
1513                 if (s->count < 2 * (signed)s->period_size)
1514                         s->count -= (signed)s->period_size;
1515                 else
1516                         s->count %= s->period_size;
1517
1518                 spin_unlock(&chip->reg_lock);
1519                 snd_pcm_period_elapsed(subs);
1520                 spin_lock(&chip->reg_lock);
1521         }
1522 }
1523
1524 /* The m3's hardware volume works by incrementing / decrementing 2 counters
1525    (without wrap around) in response to volume button presses and then
1526    generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1527    of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1528 static void snd_m3_update_hw_volume(struct work_struct *work)
1529 {
1530         struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work);
1531         int x, val;
1532
1533         /* Figure out which volume control button was pushed,
1534            based on differences from the default register
1535            values. */
1536         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1537
1538         /* Reset the volume counters to 4. Tests on the allegro integrated
1539            into a Compaq N600C laptop, have revealed that:
1540            1) Writing any value will result in the 2 counters being reset to
1541               4 so writing 0x88 is not strictly necessary
1542            2) Writing to any of the 4 involved registers will reset all 4
1543               of them (and reading them always returns the same value for all
1544               of them)
1545            It could be that a maestro deviates from this, so leave the code
1546            as is. */
1547         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1548         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1549         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1550         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1551
1552         /* Ignore spurious HV interrupts during suspend / resume, this avoids
1553            mistaking them for a mute button press. */
1554         if (chip->in_suspend)
1555                 return;
1556
1557 #ifndef CONFIG_SND_MAESTRO3_INPUT
1558         if (!chip->master_switch || !chip->master_volume)
1559                 return;
1560
1561         val = snd_ac97_read(chip->ac97, AC97_MASTER);
1562         switch (x) {
1563         case 0x88:
1564                 /* The counters have not changed, yet we've received a HV
1565                    interrupt. According to tests run by various people this
1566                    happens when pressing the mute button. */
1567                 val ^= 0x8000;
1568                 break;
1569         case 0xaa:
1570                 /* counters increased by 1 -> volume up */
1571                 if ((val & 0x7f) > 0)
1572                         val--;
1573                 if ((val & 0x7f00) > 0)
1574                         val -= 0x0100;
1575                 break;
1576         case 0x66:
1577                 /* counters decreased by 1 -> volume down */
1578                 if ((val & 0x7f) < 0x1f)
1579                         val++;
1580                 if ((val & 0x7f00) < 0x1f00)
1581                         val += 0x0100;
1582                 break;
1583         }
1584         if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1585                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1586                                &chip->master_switch->id);
1587 #else
1588         if (!chip->input_dev)
1589                 return;
1590
1591         val = 0;
1592         switch (x) {
1593         case 0x88:
1594                 /* The counters have not changed, yet we've received a HV
1595                    interrupt. According to tests run by various people this
1596                    happens when pressing the mute button. */
1597                 val = KEY_MUTE;
1598                 break;
1599         case 0xaa:
1600                 /* counters increased by 1 -> volume up */
1601                 val = KEY_VOLUMEUP;
1602                 break;
1603         case 0x66:
1604                 /* counters decreased by 1 -> volume down */
1605                 val = KEY_VOLUMEDOWN;
1606                 break;
1607         }
1608
1609         if (val) {
1610                 input_report_key(chip->input_dev, val, 1);
1611                 input_sync(chip->input_dev);
1612                 input_report_key(chip->input_dev, val, 0);
1613                 input_sync(chip->input_dev);
1614         }
1615 #endif
1616 }
1617
1618 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1619 {
1620         struct snd_m3 *chip = dev_id;
1621         u8 status;
1622         int i;
1623
1624         status = inb(chip->iobase + HOST_INT_STATUS);
1625
1626         if (status == 0xff)
1627                 return IRQ_NONE;
1628
1629         if (status & HV_INT_PENDING)
1630                 schedule_work(&chip->hwvol_work);
1631
1632         /*
1633          * ack an assp int if its running
1634          * and has an int pending
1635          */
1636         if (status & ASSP_INT_PENDING) {
1637                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1638                 if (!(ctl & STOP_ASSP_CLOCK)) {
1639                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1640                         if (ctl & DSP2HOST_REQ_TIMER) {
1641                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1642                                 /* update adc/dac info if it was a timer int */
1643                                 spin_lock(&chip->reg_lock);
1644                                 for (i = 0; i < chip->num_substreams; i++) {
1645                                         struct m3_dma *s = &chip->substreams[i];
1646                                         if (s->running)
1647                                                 snd_m3_update_ptr(chip, s);
1648                                 }
1649                                 spin_unlock(&chip->reg_lock);
1650                         }
1651                 }
1652         }
1653
1654 #if 0 /* TODO: not supported yet */
1655         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1656                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1657 #endif
1658
1659         /* ack ints */
1660         outb(status, chip->iobase + HOST_INT_STATUS);
1661
1662         return IRQ_HANDLED;
1663 }
1664
1665
1666 /*
1667  */
1668
1669 static const struct snd_pcm_hardware snd_m3_playback =
1670 {
1671         .info =                 (SNDRV_PCM_INFO_MMAP |
1672                                  SNDRV_PCM_INFO_INTERLEAVED |
1673                                  SNDRV_PCM_INFO_MMAP_VALID |
1674                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1675                                  /*SNDRV_PCM_INFO_PAUSE |*/
1676                                  SNDRV_PCM_INFO_RESUME),
1677         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1678         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1679         .rate_min =             8000,
1680         .rate_max =             48000,
1681         .channels_min =         1,
1682         .channels_max =         2,
1683         .buffer_bytes_max =     (512*1024),
1684         .period_bytes_min =     64,
1685         .period_bytes_max =     (512*1024),
1686         .periods_min =          1,
1687         .periods_max =          1024,
1688 };
1689
1690 static const struct snd_pcm_hardware snd_m3_capture =
1691 {
1692         .info =                 (SNDRV_PCM_INFO_MMAP |
1693                                  SNDRV_PCM_INFO_INTERLEAVED |
1694                                  SNDRV_PCM_INFO_MMAP_VALID |
1695                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1696                                  /*SNDRV_PCM_INFO_PAUSE |*/
1697                                  SNDRV_PCM_INFO_RESUME),
1698         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1699         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1700         .rate_min =             8000,
1701         .rate_max =             48000,
1702         .channels_min =         1,
1703         .channels_max =         2,
1704         .buffer_bytes_max =     (512*1024),
1705         .period_bytes_min =     64,
1706         .period_bytes_max =     (512*1024),
1707         .periods_min =          1,
1708         .periods_max =          1024,
1709 };
1710
1711
1712 /*
1713  */
1714
1715 static int
1716 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1717 {
1718         int i;
1719         struct m3_dma *s;
1720
1721         spin_lock_irq(&chip->reg_lock);
1722         for (i = 0; i < chip->num_substreams; i++) {
1723                 s = &chip->substreams[i];
1724                 if (! s->opened)
1725                         goto __found;
1726         }
1727         spin_unlock_irq(&chip->reg_lock);
1728         return -ENOMEM;
1729 __found:
1730         s->opened = 1;
1731         s->running = 0;
1732         spin_unlock_irq(&chip->reg_lock);
1733
1734         subs->runtime->private_data = s;
1735         s->substream = subs;
1736
1737         /* set list owners */
1738         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1739                 s->index_list[0] = &chip->mixer_list;
1740         } else
1741                 s->index_list[0] = &chip->adc1_list;
1742         s->index_list[1] = &chip->msrc_list;
1743         s->index_list[2] = &chip->dma_list;
1744
1745         return 0;
1746 }
1747
1748 static void
1749 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1750 {
1751         struct m3_dma *s = subs->runtime->private_data;
1752
1753         if (s == NULL)
1754                 return; /* not opened properly */
1755
1756         spin_lock_irq(&chip->reg_lock);
1757         if (s->substream && s->running)
1758                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1759         if (s->in_lists) {
1760                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1761                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1762                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1763                 s->in_lists = 0;
1764         }
1765         s->running = 0;
1766         s->opened = 0;
1767         spin_unlock_irq(&chip->reg_lock);
1768 }
1769
1770 static int
1771 snd_m3_playback_open(struct snd_pcm_substream *subs)
1772 {
1773         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1774         struct snd_pcm_runtime *runtime = subs->runtime;
1775         int err;
1776
1777         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1778                 return err;
1779
1780         runtime->hw = snd_m3_playback;
1781
1782         return 0;
1783 }
1784
1785 static int
1786 snd_m3_playback_close(struct snd_pcm_substream *subs)
1787 {
1788         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1789
1790         snd_m3_substream_close(chip, subs);
1791         return 0;
1792 }
1793
1794 static int
1795 snd_m3_capture_open(struct snd_pcm_substream *subs)
1796 {
1797         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1798         struct snd_pcm_runtime *runtime = subs->runtime;
1799         int err;
1800
1801         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1802                 return err;
1803
1804         runtime->hw = snd_m3_capture;
1805
1806         return 0;
1807 }
1808
1809 static int
1810 snd_m3_capture_close(struct snd_pcm_substream *subs)
1811 {
1812         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1813
1814         snd_m3_substream_close(chip, subs);
1815         return 0;
1816 }
1817
1818 /*
1819  * create pcm instance
1820  */
1821
1822 static const struct snd_pcm_ops snd_m3_playback_ops = {
1823         .open =         snd_m3_playback_open,
1824         .close =        snd_m3_playback_close,
1825         .ioctl =        snd_pcm_lib_ioctl,
1826         .hw_params =    snd_m3_pcm_hw_params,
1827         .hw_free =      snd_m3_pcm_hw_free,
1828         .prepare =      snd_m3_pcm_prepare,
1829         .trigger =      snd_m3_pcm_trigger,
1830         .pointer =      snd_m3_pcm_pointer,
1831 };
1832
1833 static const struct snd_pcm_ops snd_m3_capture_ops = {
1834         .open =         snd_m3_capture_open,
1835         .close =        snd_m3_capture_close,
1836         .ioctl =        snd_pcm_lib_ioctl,
1837         .hw_params =    snd_m3_pcm_hw_params,
1838         .hw_free =      snd_m3_pcm_hw_free,
1839         .prepare =      snd_m3_pcm_prepare,
1840         .trigger =      snd_m3_pcm_trigger,
1841         .pointer =      snd_m3_pcm_pointer,
1842 };
1843
1844 static int
1845 snd_m3_pcm(struct snd_m3 * chip, int device)
1846 {
1847         struct snd_pcm *pcm;
1848         int err;
1849
1850         err = snd_pcm_new(chip->card, chip->card->driver, device,
1851                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1852         if (err < 0)
1853                 return err;
1854
1855         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1856         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1857
1858         pcm->private_data = chip;
1859         pcm->info_flags = 0;
1860         strcpy(pcm->name, chip->card->driver);
1861         chip->pcm = pcm;
1862
1863         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1864                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1865
1866         return 0;
1867 }
1868
1869
1870 /*
1871  * ac97 interface
1872  */
1873
1874 /*
1875  * Wait for the ac97 serial bus to be free.
1876  * return nonzero if the bus is still busy.
1877  */
1878 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1879 {
1880         int i = 10000;
1881
1882         do {
1883                 if (! (snd_m3_inb(chip, 0x30) & 1))
1884                         return 0;
1885                 cpu_relax();
1886         } while (i-- > 0);
1887
1888         dev_err(chip->card->dev, "ac97 serial bus busy\n");
1889         return 1;
1890 }
1891
1892 static unsigned short
1893 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1894 {
1895         struct snd_m3 *chip = ac97->private_data;
1896         unsigned short data = 0xffff;
1897
1898         if (snd_m3_ac97_wait(chip))
1899                 goto fail;
1900         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1901         if (snd_m3_ac97_wait(chip))
1902                 goto fail;
1903         data = snd_m3_inw(chip, CODEC_DATA);
1904 fail:
1905         return data;
1906 }
1907
1908 static void
1909 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1910 {
1911         struct snd_m3 *chip = ac97->private_data;
1912
1913         if (snd_m3_ac97_wait(chip))
1914                 return;
1915         snd_m3_outw(chip, val, CODEC_DATA);
1916         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1917         /*
1918          * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent
1919          * until the MASTER volume or mute is touched (alsactl restore does not
1920          * work).
1921          */
1922         if (ac97->id == 0x45838308 && reg == AC97_MASTER) {
1923                 snd_m3_ac97_wait(chip);
1924                 snd_m3_outw(chip, val, CODEC_DATA);
1925                 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1926         }
1927 }
1928
1929
1930 static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote)
1931 {
1932         int io = chip->iobase;
1933         u16 tmp;
1934
1935         isremote = isremote ? 1 : 0;
1936
1937         tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK;
1938         /* enable dock on Dell Latitude C810 */
1939         if (chip->pci->subsystem_vendor == 0x1028 &&
1940             chip->pci->subsystem_device == 0x00e5)
1941                 tmp |= M3I_DOCK_ENABLE;
1942         outw(tmp | isremote, io + RING_BUS_CTRL_B);
1943         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1944              io + SDO_OUT_DEST_CTRL);
1945         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1946              io + SDO_IN_DEST_CTRL);
1947 }
1948
1949 /*
1950  * hack, returns non zero on err
1951  */
1952 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1953 {
1954         u16 ret;
1955
1956         if (snd_m3_ac97_wait(chip))
1957                 return 1;
1958
1959         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1960
1961         if (snd_m3_ac97_wait(chip))
1962                 return 1;
1963
1964         ret = snd_m3_inw(chip, 0x32);
1965
1966         return (ret == 0) || (ret == 0xffff);
1967 }
1968
1969 static void snd_m3_ac97_reset(struct snd_m3 *chip)
1970 {
1971         u16 dir;
1972         int delay1 = 0, delay2 = 0, i;
1973         int io = chip->iobase;
1974
1975         if (chip->allegro_flag) {
1976                 /*
1977                  * the onboard codec on the allegro seems
1978                  * to want to wait a very long time before
1979                  * coming back to life
1980                  */
1981                 delay1 = 50;
1982                 delay2 = 800;
1983         } else {
1984                 /* maestro3 */
1985                 delay1 = 20;
1986                 delay2 = 500;
1987         }
1988
1989         for (i = 0; i < 5; i++) {
1990                 dir = inw(io + GPIO_DIRECTION);
1991                 if (!chip->irda_workaround)
1992                         dir |= 0x10; /* assuming pci bus master? */
1993
1994                 snd_m3_remote_codec_config(chip, 0);
1995
1996                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
1997                 udelay(20);
1998
1999                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2000                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2001                 outw(0, io + GPIO_DATA);
2002                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2003
2004                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2005
2006                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2007                 udelay(5);
2008                 /* ok, bring back the ac-link */
2009                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2010                 outw(~0, io + GPIO_MASK);
2011
2012                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2013
2014                 if (! snd_m3_try_read_vendor(chip))
2015                         break;
2016
2017                 delay1 += 10;
2018                 delay2 += 100;
2019
2020                 dev_dbg(chip->card->dev,
2021                         "retrying codec reset with delays of %d and %d ms\n",
2022                            delay1, delay2);
2023         }
2024
2025 #if 0
2026         /* more gung-ho reset that doesn't
2027          * seem to work anywhere :)
2028          */
2029         tmp = inw(io + RING_BUS_CTRL_A);
2030         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2031         msleep(20);
2032         outw(tmp, io + RING_BUS_CTRL_A);
2033         msleep(50);
2034 #endif
2035 }
2036
2037 static int snd_m3_mixer(struct snd_m3 *chip)
2038 {
2039         struct snd_ac97_bus *pbus;
2040         struct snd_ac97_template ac97;
2041 #ifndef CONFIG_SND_MAESTRO3_INPUT
2042         struct snd_ctl_elem_id elem_id;
2043 #endif
2044         int err;
2045         static struct snd_ac97_bus_ops ops = {
2046                 .write = snd_m3_ac97_write,
2047                 .read = snd_m3_ac97_read,
2048         };
2049
2050         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2051                 return err;
2052
2053         memset(&ac97, 0, sizeof(ac97));
2054         ac97.private_data = chip;
2055         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2056                 return err;
2057
2058         /* seems ac97 PCM needs initialization.. hack hack.. */
2059         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2060         schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2061         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2062
2063 #ifndef CONFIG_SND_MAESTRO3_INPUT
2064         memset(&elem_id, 0, sizeof(elem_id));
2065         elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2066         strcpy(elem_id.name, "Master Playback Switch");
2067         chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2068         memset(&elem_id, 0, sizeof(elem_id));
2069         elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2070         strcpy(elem_id.name, "Master Playback Volume");
2071         chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2072 #endif
2073
2074         return 0;
2075 }
2076
2077
2078 /*
2079  * initialize ASSP
2080  */
2081
2082 #define MINISRC_LPF_LEN 10
2083 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2084         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2085         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2086 };
2087
2088 static void snd_m3_assp_init(struct snd_m3 *chip)
2089 {
2090         unsigned int i;
2091         const __le16 *data;
2092
2093         /* zero kernel data */
2094         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2095                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2096                                   KDATA_BASE_ADDR + i, 0);
2097
2098         /* zero mixer data? */
2099         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2100                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2101                                   KDATA_BASE_ADDR2 + i, 0);
2102
2103         /* init dma pointer */
2104         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2105                           KDATA_CURRENT_DMA,
2106                           KDATA_DMA_XFER0);
2107
2108         /* write kernel into code memory.. */
2109         data = (const __le16 *)chip->assp_kernel_image->data;
2110         for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2111                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2112                                   REV_B_CODE_MEMORY_BEGIN + i,
2113                                   le16_to_cpu(data[i]));
2114         }
2115
2116         /*
2117          * We only have this one client and we know that 0x400
2118          * is free in our kernel's mem map, so lets just
2119          * drop it there.  It seems that the minisrc doesn't
2120          * need vectors, so we won't bother with them..
2121          */
2122         data = (const __le16 *)chip->assp_minisrc_image->data;
2123         for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2124                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2125                                   0x400 + i, le16_to_cpu(data[i]));
2126         }
2127
2128         /*
2129          * write the coefficients for the low pass filter?
2130          */
2131         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2132                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2133                                   0x400 + MINISRC_COEF_LOC + i,
2134                                   minisrc_lpf[i]);
2135         }
2136
2137         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2138                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2139                           0x8000);
2140
2141         /*
2142          * the minisrc is the only thing on
2143          * our task list..
2144          */
2145         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2146                           KDATA_TASK0,
2147                           0x400);
2148
2149         /*
2150          * init the mixer number..
2151          */
2152
2153         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2154                           KDATA_MIXER_TASK_NUMBER,0);
2155
2156         /*
2157          * EXTREME KERNEL MASTER VOLUME
2158          */
2159         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2160                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2161         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2162                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2163
2164         chip->mixer_list.curlen = 0;
2165         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2166         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2167         chip->adc1_list.curlen = 0;
2168         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2169         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2170         chip->dma_list.curlen = 0;
2171         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2172         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2173         chip->msrc_list.curlen = 0;
2174         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2175         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2176 }
2177
2178
2179 static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2180 {
2181         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2182                                MINISRC_IN_BUFFER_SIZE / 2 +
2183                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2184         int address, i;
2185
2186         /*
2187          * the revb memory map has 0x1100 through 0x1c00
2188          * free.
2189          */
2190
2191         /*
2192          * align instance address to 256 bytes so that its
2193          * shifted list address is aligned.
2194          * list address = (mem address >> 1) >> 7;
2195          */
2196         data_bytes = ALIGN(data_bytes, 256);
2197         address = 0x1100 + ((data_bytes/2) * index);
2198
2199         if ((address + (data_bytes/2)) >= 0x1c00) {
2200                 dev_err(chip->card->dev,
2201                         "no memory for %d bytes at ind %d (addr 0x%x)\n",
2202                            data_bytes, index, address);
2203                 return -ENOMEM;
2204         }
2205
2206         s->number = index;
2207         s->inst.code = 0x400;
2208         s->inst.data = address;
2209
2210         for (i = data_bytes / 2; i > 0; address++, i--) {
2211                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2212                                   address, 0);
2213         }
2214
2215         return 0;
2216 }
2217
2218
2219 /*
2220  * this works for the reference board, have to find
2221  * out about others
2222  *
2223  * this needs more magic for 4 speaker, but..
2224  */
2225 static void
2226 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2227 {
2228         int io = chip->iobase;
2229         u16 gpo, polarity;
2230
2231         if (! chip->external_amp)
2232                 return;
2233
2234         polarity = enable ? 0 : 1;
2235         polarity = polarity << chip->amp_gpio;
2236         gpo = 1 << chip->amp_gpio;
2237
2238         outw(~gpo, io + GPIO_MASK);
2239
2240         outw(inw(io + GPIO_DIRECTION) | gpo,
2241              io + GPIO_DIRECTION);
2242
2243         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2244              io + GPIO_DATA);
2245
2246         outw(0xffff, io + GPIO_MASK);
2247 }
2248
2249 static void
2250 snd_m3_hv_init(struct snd_m3 *chip)
2251 {
2252         unsigned long io = chip->iobase;
2253         u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2254
2255         if (!chip->is_omnibook)
2256                 return;
2257
2258         /*
2259          * Volume buttons on some HP OmniBook laptops
2260          * require some GPIO magic to work correctly.
2261          */
2262         outw(0xffff, io + GPIO_MASK);
2263         outw(0x0000, io + GPIO_DATA);
2264
2265         outw(~val, io + GPIO_MASK);
2266         outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2267         outw(val, io + GPIO_MASK);
2268
2269         outw(0xffff, io + GPIO_MASK);
2270 }
2271
2272 static int
2273 snd_m3_chip_init(struct snd_m3 *chip)
2274 {
2275         struct pci_dev *pcidev = chip->pci;
2276         unsigned long io = chip->iobase;
2277         u32 n;
2278         u16 w;
2279         u8 t; /* makes as much sense as 'n', no? */
2280
2281         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2282         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2283                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2284                DISABLE_LEGACY);
2285         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2286
2287         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2288         n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2289         n |= chip->hv_config;
2290         /* For some reason we must always use reduced debounce. */
2291         n |= REDUCED_DEBOUNCE;
2292         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2293         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2294
2295         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2296         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2297         n &= ~INT_CLK_SELECT;
2298         if (!chip->allegro_flag) {
2299                 n &= ~INT_CLK_MULT_ENABLE;
2300                 n |= INT_CLK_SRC_NOT_PCI;
2301         }
2302         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2303         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2304
2305         if (chip->allegro_flag) {
2306                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2307                 n |= IN_CLK_12MHZ_SELECT;
2308                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2309         }
2310
2311         t = inb(chip->iobase + ASSP_CONTROL_A);
2312         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2313         t |= ASSP_CLK_49MHZ_SELECT;
2314         t |= ASSP_0_WS_ENABLE;
2315         outb(t, chip->iobase + ASSP_CONTROL_A);
2316
2317         snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2318         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2319
2320         outb(0x00, io + HARDWARE_VOL_CTRL);
2321         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2322         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2323         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2324         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2325
2326         return 0;
2327 }
2328
2329 static void
2330 snd_m3_enable_ints(struct snd_m3 *chip)
2331 {
2332         unsigned long io = chip->iobase;
2333         unsigned short val;
2334
2335         /* TODO: MPU401 not supported yet */
2336         val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2337         if (chip->hv_config & HV_CTRL_ENABLE)
2338                 val |= HV_INT_ENABLE;
2339         outb(val, chip->iobase + HOST_INT_STATUS);
2340         outw(val, io + HOST_INT_CTRL);
2341         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2342              io + ASSP_CONTROL_C);
2343 }
2344
2345
2346 /*
2347  */
2348
2349 static int snd_m3_free(struct snd_m3 *chip)
2350 {
2351         struct m3_dma *s;
2352         int i;
2353
2354         cancel_work_sync(&chip->hwvol_work);
2355 #ifdef CONFIG_SND_MAESTRO3_INPUT
2356         if (chip->input_dev)
2357                 input_unregister_device(chip->input_dev);
2358 #endif
2359
2360         if (chip->substreams) {
2361                 spin_lock_irq(&chip->reg_lock);
2362                 for (i = 0; i < chip->num_substreams; i++) {
2363                         s = &chip->substreams[i];
2364                         /* check surviving pcms; this should not happen though.. */
2365                         if (s->substream && s->running)
2366                                 snd_m3_pcm_stop(chip, s, s->substream);
2367                 }
2368                 spin_unlock_irq(&chip->reg_lock);
2369                 kfree(chip->substreams);
2370         }
2371         if (chip->iobase) {
2372                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2373         }
2374
2375 #ifdef CONFIG_PM_SLEEP
2376         vfree(chip->suspend_mem);
2377 #endif
2378
2379         if (chip->irq >= 0)
2380                 free_irq(chip->irq, chip);
2381
2382         if (chip->iobase)
2383                 pci_release_regions(chip->pci);
2384
2385         release_firmware(chip->assp_kernel_image);
2386         release_firmware(chip->assp_minisrc_image);
2387
2388         pci_disable_device(chip->pci);
2389         kfree(chip);
2390         return 0;
2391 }
2392
2393
2394 /*
2395  * APM support
2396  */
2397 #ifdef CONFIG_PM_SLEEP
2398 static int m3_suspend(struct device *dev)
2399 {
2400         struct snd_card *card = dev_get_drvdata(dev);
2401         struct snd_m3 *chip = card->private_data;
2402         int i, dsp_index;
2403
2404         if (chip->suspend_mem == NULL)
2405                 return 0;
2406
2407         chip->in_suspend = 1;
2408         cancel_work_sync(&chip->hwvol_work);
2409         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2410         snd_ac97_suspend(chip->ac97);
2411
2412         msleep(10); /* give the assp a chance to idle.. */
2413
2414         snd_m3_assp_halt(chip);
2415
2416         /* save dsp image */
2417         dsp_index = 0;
2418         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2419                 chip->suspend_mem[dsp_index++] =
2420                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2421         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2422                 chip->suspend_mem[dsp_index++] =
2423                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2424         return 0;
2425 }
2426
2427 static int m3_resume(struct device *dev)
2428 {
2429         struct snd_card *card = dev_get_drvdata(dev);
2430         struct snd_m3 *chip = card->private_data;
2431         int i, dsp_index;
2432
2433         if (chip->suspend_mem == NULL)
2434                 return 0;
2435
2436         /* first lets just bring everything back. .*/
2437         snd_m3_outw(chip, 0, 0x54);
2438         snd_m3_outw(chip, 0, 0x56);
2439
2440         snd_m3_chip_init(chip);
2441         snd_m3_assp_halt(chip);
2442         snd_m3_ac97_reset(chip);
2443
2444         /* restore dsp image */
2445         dsp_index = 0;
2446         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2447                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2448                                   chip->suspend_mem[dsp_index++]);
2449         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2450                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2451                                   chip->suspend_mem[dsp_index++]);
2452
2453         /* tell the dma engine to restart itself */
2454         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2455                           KDATA_DMA_ACTIVE, 0);
2456
2457         /* restore ac97 registers */
2458         snd_ac97_resume(chip->ac97);
2459
2460         snd_m3_assp_continue(chip);
2461         snd_m3_enable_ints(chip);
2462         snd_m3_amp_enable(chip, 1);
2463
2464         snd_m3_hv_init(chip);
2465
2466         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2467         chip->in_suspend = 0;
2468         return 0;
2469 }
2470
2471 static SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume);
2472 #define M3_PM_OPS       &m3_pm
2473 #else
2474 #define M3_PM_OPS       NULL
2475 #endif /* CONFIG_PM_SLEEP */
2476
2477 #ifdef CONFIG_SND_MAESTRO3_INPUT
2478 static int snd_m3_input_register(struct snd_m3 *chip)
2479 {
2480         struct input_dev *input_dev;
2481         int err;
2482
2483         input_dev = input_allocate_device();
2484         if (!input_dev)
2485                 return -ENOMEM;
2486
2487         snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2488                  pci_name(chip->pci));
2489
2490         input_dev->name = chip->card->driver;
2491         input_dev->phys = chip->phys;
2492         input_dev->id.bustype = BUS_PCI;
2493         input_dev->id.vendor  = chip->pci->vendor;
2494         input_dev->id.product = chip->pci->device;
2495         input_dev->dev.parent = &chip->pci->dev;
2496
2497         __set_bit(EV_KEY, input_dev->evbit);
2498         __set_bit(KEY_MUTE, input_dev->keybit);
2499         __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2500         __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2501
2502         err = input_register_device(input_dev);
2503         if (err) {
2504                 input_free_device(input_dev);
2505                 return err;
2506         }
2507
2508         chip->input_dev = input_dev;
2509         return 0;
2510 }
2511 #endif /* CONFIG_INPUT */
2512
2513 /*
2514  */
2515
2516 static int snd_m3_dev_free(struct snd_device *device)
2517 {
2518         struct snd_m3 *chip = device->device_data;
2519         return snd_m3_free(chip);
2520 }
2521
2522 static int
2523 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2524               int enable_amp,
2525               int amp_gpio,
2526               struct snd_m3 **chip_ret)
2527 {
2528         struct snd_m3 *chip;
2529         int i, err;
2530         const struct snd_pci_quirk *quirk;
2531         static struct snd_device_ops ops = {
2532                 .dev_free =     snd_m3_dev_free,
2533         };
2534
2535         *chip_ret = NULL;
2536
2537         if (pci_enable_device(pci))
2538                 return -EIO;
2539
2540         /* check, if we can restrict PCI DMA transfers to 28 bits */
2541         if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
2542             dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
2543                 dev_err(card->dev,
2544                         "architecture does not support 28bit PCI busmaster DMA\n");
2545                 pci_disable_device(pci);
2546                 return -ENXIO;
2547         }
2548
2549         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2550         if (chip == NULL) {
2551                 pci_disable_device(pci);
2552                 return -ENOMEM;
2553         }
2554
2555         spin_lock_init(&chip->reg_lock);
2556
2557         switch (pci->device) {
2558         case PCI_DEVICE_ID_ESS_ALLEGRO:
2559         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2560         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2561         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2562                 chip->allegro_flag = 1;
2563                 break;
2564         }
2565
2566         chip->card = card;
2567         chip->pci = pci;
2568         chip->irq = -1;
2569         INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume);
2570
2571         chip->external_amp = enable_amp;
2572         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2573                 chip->amp_gpio = amp_gpio;
2574         else {
2575                 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2576                 if (quirk) {
2577                         dev_info(card->dev, "set amp-gpio for '%s'\n",
2578                                  snd_pci_quirk_name(quirk));
2579                         chip->amp_gpio = quirk->value;
2580                 } else if (chip->allegro_flag)
2581                         chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2582                 else /* presumably this is for all 'maestro3's.. */
2583                         chip->amp_gpio = GPO_EXT_AMP_M3;
2584         }
2585
2586         quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2587         if (quirk) {
2588                 dev_info(card->dev, "enabled irda workaround for '%s'\n",
2589                          snd_pci_quirk_name(quirk));
2590                 chip->irda_workaround = 1;
2591         }
2592         quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2593         if (quirk)
2594                 chip->hv_config = quirk->value;
2595         if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2596                 chip->is_omnibook = 1;
2597
2598         chip->num_substreams = NR_DSPS;
2599         chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2600                                    GFP_KERNEL);
2601         if (chip->substreams == NULL) {
2602                 kfree(chip);
2603                 pci_disable_device(pci);
2604                 return -ENOMEM;
2605         }
2606
2607         err = request_firmware(&chip->assp_kernel_image,
2608                                "ess/maestro3_assp_kernel.fw", &pci->dev);
2609         if (err < 0)
2610                 goto free_chip;
2611
2612         err = request_firmware(&chip->assp_minisrc_image,
2613                                "ess/maestro3_assp_minisrc.fw", &pci->dev);
2614         if (err < 0)
2615                 goto free_chip;
2616
2617         err = pci_request_regions(pci, card->driver);
2618         if (err < 0)
2619                 goto free_chip;
2620
2621         chip->iobase = pci_resource_start(pci, 0);
2622
2623         /* just to be sure */
2624         pci_set_master(pci);
2625
2626         snd_m3_chip_init(chip);
2627         snd_m3_assp_halt(chip);
2628
2629         snd_m3_ac97_reset(chip);
2630
2631         snd_m3_amp_enable(chip, 1);
2632
2633         snd_m3_hv_init(chip);
2634
2635         if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2636                         KBUILD_MODNAME, chip)) {
2637                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2638                 err = -ENOMEM;
2639                 goto free_chip;
2640         }
2641         chip->irq = pci->irq;
2642
2643 #ifdef CONFIG_PM_SLEEP
2644         chip->suspend_mem =
2645                 vmalloc(array_size(sizeof(u16),
2646                                    REV_B_CODE_MEMORY_LENGTH +
2647                                         REV_B_DATA_MEMORY_LENGTH));
2648         if (chip->suspend_mem == NULL)
2649                 dev_warn(card->dev, "can't allocate apm buffer\n");
2650 #endif
2651
2652         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2653         if (err < 0)
2654                 goto free_chip;
2655
2656         if ((err = snd_m3_mixer(chip)) < 0)
2657                 return err;
2658
2659         for (i = 0; i < chip->num_substreams; i++) {
2660                 struct m3_dma *s = &chip->substreams[i];
2661                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2662                         return err;
2663         }
2664
2665         if ((err = snd_m3_pcm(chip, 0)) < 0)
2666                 return err;
2667
2668 #ifdef CONFIG_SND_MAESTRO3_INPUT
2669         if (chip->hv_config & HV_CTRL_ENABLE) {
2670                 err = snd_m3_input_register(chip);
2671                 if (err)
2672                         dev_warn(card->dev,
2673                                  "Input device registration failed with error %i",
2674                                  err);
2675         }
2676 #endif
2677
2678         snd_m3_enable_ints(chip);
2679         snd_m3_assp_continue(chip);
2680
2681         *chip_ret = chip;
2682
2683         return 0;
2684
2685 free_chip:
2686         snd_m3_free(chip);
2687         return err;
2688 }
2689
2690 /*
2691  */
2692 static int
2693 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2694 {
2695         static int dev;
2696         struct snd_card *card;
2697         struct snd_m3 *chip;
2698         int err;
2699
2700         /* don't pick up modems */
2701         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2702                 return -ENODEV;
2703
2704         if (dev >= SNDRV_CARDS)
2705                 return -ENODEV;
2706         if (!enable[dev]) {
2707                 dev++;
2708                 return -ENOENT;
2709         }
2710
2711         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2712                            0, &card);
2713         if (err < 0)
2714                 return err;
2715
2716         switch (pci->device) {
2717         case PCI_DEVICE_ID_ESS_ALLEGRO:
2718         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2719                 strcpy(card->driver, "Allegro");
2720                 break;
2721         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2722         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2723                 strcpy(card->driver, "Canyon3D-2");
2724                 break;
2725         default:
2726                 strcpy(card->driver, "Maestro3");
2727                 break;
2728         }
2729
2730         err = snd_m3_create(card, pci, external_amp[dev], amp_gpio[dev], &chip);
2731         if (err < 0)
2732                 goto free_card;
2733
2734         card->private_data = chip;
2735
2736         sprintf(card->shortname, "ESS %s PCI", card->driver);
2737         sprintf(card->longname, "%s at 0x%lx, irq %d",
2738                 card->shortname, chip->iobase, chip->irq);
2739
2740         err = snd_card_register(card);
2741         if (err < 0)
2742                 goto free_card;
2743
2744 #if 0 /* TODO: not supported yet */
2745         /* TODO enable MIDI IRQ and I/O */
2746         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2747                                   chip->iobase + MPU401_DATA_PORT,
2748                                   MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2749                                   -1, &chip->rmidi);
2750         if (err < 0)
2751                 dev_warn(card->dev, "no MIDI support.\n");
2752 #endif
2753
2754         pci_set_drvdata(pci, card);
2755         dev++;
2756         return 0;
2757
2758 free_card:
2759         snd_card_free(card);
2760         return err;
2761 }
2762
2763 static void snd_m3_remove(struct pci_dev *pci)
2764 {
2765         snd_card_free(pci_get_drvdata(pci));
2766 }
2767
2768 static struct pci_driver m3_driver = {
2769         .name = KBUILD_MODNAME,
2770         .id_table = snd_m3_ids,
2771         .probe = snd_m3_probe,
2772         .remove = snd_m3_remove,
2773         .driver = {
2774                 .pm = M3_PM_OPS,
2775         },
2776 };
2777
2778 module_pci_driver(m3_driver);