sound/pci/intel8x0.c

   1 /*
   2  *   ALSA driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
   5  *
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11  *
  12  *   This program is free software; you can redistribute it and/or modify
  13  *   it under the terms of the GNU General Public License as published by
  14  *   the Free Software Foundation; either version 2 of the License, or
  15  *   (at your option) any later version.
  16  *
  17  *   This program is distributed in the hope that it will be useful,
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *   GNU General Public License for more details.
  21  *
  22  *   You should have received a copy of the GNU General Public License
  23  *   along with this program; if not, write to the Free Software
  24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25
  26  *
  27  */
  28
  29 #include <linux/io.h>
  30 #include <linux/delay.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/init.h>
  33 #include <linux/pci.h>
  34 #include <linux/slab.h>
  35 #include <linux/module.h>
  36 #include <sound/core.h>
  37 #include <sound/pcm.h>
  38 #include <sound/ac97_codec.h>
  39 #include <sound/info.h>
  40 #include <sound/initval.h>
  41
  42 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  43 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  44 MODULE_LICENSE("GPL");
  45 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  46                 "{Intel,82901AB-ICH0},"
  47                 "{Intel,82801BA-ICH2},"
  48                 "{Intel,82801CA-ICH3},"
  49                 "{Intel,82801DB-ICH4},"
  50                 "{Intel,ICH5},"
  51                 "{Intel,ICH6},"
  52                 "{Intel,ICH7},"
  53                 "{Intel,6300ESB},"
  54                 "{Intel,ESB2},"
  55                 "{Intel,MX440},"
  56                 "{SiS,SI7012},"
  57                 "{NVidia,nForce Audio},"
  58                 "{NVidia,nForce2 Audio},"
  59                 "{NVidia,nForce3 Audio},"
  60                 "{NVidia,MCP04},"
  61                 "{NVidia,MCP501},"
  62                 "{NVidia,CK804},"
  63                 "{NVidia,CK8},"
  64                 "{NVidia,CK8S},"
  65                 "{AMD,AMD768},"
  66                 "{AMD,AMD8111},"
  67                 "{ALI,M5455}}");
  68
  69 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  70 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  71 static int ac97_clock;
  72 static char *ac97_quirk;
  73 static bool buggy_semaphore;
  74 static int buggy_irq = -1; /* auto-check */
  75 static bool xbox;
  76 static int spdif_aclink = -1;
  77 static int inside_vm = -1;
  78
  79 module_param(index, int, 0444);
  80 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  81 module_param(id, charp, 0444);
  82 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  83 module_param(ac97_clock, int, 0444);
  84 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
  85 module_param(ac97_quirk, charp, 0444);
  86 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  87 module_param(buggy_semaphore, bool, 0444);
  88 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  89 module_param(buggy_irq, bint, 0444);
  90 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  91 module_param(xbox, bool, 0444);
  92 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  93 module_param(spdif_aclink, int, 0444);
  94 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  95 module_param(inside_vm, bint, 0444);
  96 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
  97
  98 /* just for backward compatibility */
  99 static bool enable;
 100 module_param(enable, bool, 0444);
 101 static int joystick;
 102 module_param(joystick, int, 0444);
 103
 104 /*
 105  *  Direct registers
 106  */
 107 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
 108
 109 #define ICHREG(x) ICH_REG_##x
 110
 111 #define DEFINE_REGSET(name,base) \
 112 enum { \
 113         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 114         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 115         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 116         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 117         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 118         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 119         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 120 };
 121
 122 /* busmaster blocks */
 123 DEFINE_REGSET(OFF, 0);          /* offset */
 124 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 125 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 126 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 127
 128 /* ICH4 busmaster blocks */
 129 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 130 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 131 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 132
 133 /* values for each busmaster block */
 134
 135 /* LVI */
 136 #define ICH_REG_LVI_MASK                0x1f
 137
 138 /* SR */
 139 #define ICH_FIFOE                       0x10    /* FIFO error */
 140 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 141 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 142 #define ICH_CELV                        0x02    /* current equals last valid */
 143 #define ICH_DCH                         0x01    /* DMA controller halted */
 144
 145 /* PIV */
 146 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 147
 148 /* CR */
 149 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 150 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 151 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 152 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 153 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 154
 155
 156 /* global block */
 157 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 158 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 159 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 160 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 161 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 162 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 163 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 164 #define   ICH_PCM_246_MASK      0x00300000      /* chan mask (not all chips) */
 165 #define   ICH_PCM_8             0x00300000      /* 8 channels (not all chips) */
 166 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 167 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 168 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 169 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 170 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 171 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 172 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 173 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 174 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 175 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 176 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 177 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 178 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 179 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 180 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 181 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 182 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 183 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 184 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 185 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 186 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 187 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 188 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 189 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 190 #define   ICH_SIS_TRI           0x00080000      /* SIS: tertiary resume irq */
 191 #define   ICH_SIS_TCR           0x00040000      /* SIS: tertiary codec ready */
 192 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 193 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 194 #define   ICH_RCS               0x00008000      /* read completion status */
 195 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 196 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 197 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 198 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 199 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 200 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 201 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 202 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 203 #define   ICH_POINT             0x00000040      /* playback interrupt */
 204 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 205 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 206 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 207 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 208 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 209 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 210 #define   ICH_CAS               0x01            /* codec access semaphore */
 211 #define ICH_REG_SDM             0x80
 212 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 213 #define   ICH_DI2L_SHIFT        6
 214 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 215 #define   ICH_DI1L_SHIFT        4
 216 #define   ICH_SE                0x00000008      /* steer enable */
 217 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 218
 219 #define ICH_MAX_FRAGS           32              /* max hw frags */
 220
 221
 222 /*
 223  * registers for Ali5455
 224  */
 225
 226 /* ALi 5455 busmaster blocks */
 227 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 228 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 229 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 230 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 231 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 232 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 233 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 234 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 235 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 236 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 237 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 238
 239 enum {
 240         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 241         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 242         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 243         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 244         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 245         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 246         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 247         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 248         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 249         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 250         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 251         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 252         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 253         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 254         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 255         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 256         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 257         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 258         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 259         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 260         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 261 };
 262
 263 #define ALI_CAS_SEM_BUSY        0x80000000
 264 #define ALI_CPR_ADDR_SECONDARY  0x100
 265 #define ALI_CPR_ADDR_READ       0x80
 266 #define ALI_CSPSR_CODEC_READY   0x08
 267 #define ALI_CSPSR_READ_OK       0x02
 268 #define ALI_CSPSR_WRITE_OK      0x01
 269
 270 /* interrupts for the whole chip by interrupt status register finish */
 271
 272 #define ALI_INT_MICIN2          (1<<26)
 273 #define ALI_INT_PCMIN2          (1<<25)
 274 #define ALI_INT_I2SIN           (1<<24)
 275 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 276 #define ALI_INT_SPDIFIN         (1<<22)
 277 #define ALI_INT_LFEOUT          (1<<21)
 278 #define ALI_INT_CENTEROUT       (1<<20)
 279 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 280 #define ALI_INT_MICIN           (1<<18)
 281 #define ALI_INT_PCMOUT          (1<<17)
 282 #define ALI_INT_PCMIN           (1<<16)
 283 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 284 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 285 #define ALI_INT_GPIO            (1<<1)
 286 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
 287                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 288
 289 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 290 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 291 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 292 #define ICH_ALI_SC_IN_BITS      (3<<18)
 293 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 294 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 295 #define ICH_ALI_SC_PCM_4        (1<<8)
 296 #define ICH_ALI_SC_PCM_6        (2<<8)
 297 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 298
 299 #define ICH_ALI_SS_SEC_ID       (3<<5)
 300 #define ICH_ALI_SS_PRI_ID       (3<<3)
 301
 302 #define ICH_ALI_IF_AC97SP       (1<<21)
 303 #define ICH_ALI_IF_MC           (1<<20)
 304 #define ICH_ALI_IF_PI           (1<<19)
 305 #define ICH_ALI_IF_MC2          (1<<18)
 306 #define ICH_ALI_IF_PI2          (1<<17)
 307 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 308 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 309 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 310 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 311 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 312 #define ICH_ALI_IF_PO           (1<<1)
 313
 314 /*
 315  *
 316  */
 317
 318 enum {
 319         ICHD_PCMIN,
 320         ICHD_PCMOUT,
 321         ICHD_MIC,
 322         ICHD_MIC2,
 323         ICHD_PCM2IN,
 324         ICHD_SPBAR,
 325         ICHD_LAST = ICHD_SPBAR
 326 };
 327 enum {
 328         NVD_PCMIN,
 329         NVD_PCMOUT,
 330         NVD_MIC,
 331         NVD_SPBAR,
 332         NVD_LAST = NVD_SPBAR
 333 };
 334 enum {
 335         ALID_PCMIN,
 336         ALID_PCMOUT,
 337         ALID_MIC,
 338         ALID_AC97SPDIFOUT,
 339         ALID_SPDIFIN,
 340         ALID_SPDIFOUT,
 341         ALID_LAST = ALID_SPDIFOUT
 342 };
 343
 344 #define get_ichdev(substream) (substream->runtime->private_data)
 345
 346 struct ichdev {
 347         unsigned int ichd;                      /* ich device number */
 348         unsigned long reg_offset;               /* offset to bmaddr */
 349         __le32 *bdbar;                          /* CPU address (32bit) */
 350         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 351         struct snd_pcm_substream *substream;
 352         unsigned int physbuf;                   /* physical address (32bit) */
 353         unsigned int size;
 354         unsigned int fragsize;
 355         unsigned int fragsize1;
 356         unsigned int position;
 357         unsigned int pos_shift;
 358         unsigned int last_pos;
 359         int frags;
 360         int lvi;
 361         int lvi_frag;
 362         int civ;
 363         int ack;
 364         int ack_reload;
 365         unsigned int ack_bit;
 366         unsigned int roff_sr;
 367         unsigned int roff_picb;
 368         unsigned int int_sta_mask;              /* interrupt status mask */
 369         unsigned int ali_slot;                  /* ALI DMA slot */
 370         struct ac97_pcm *pcm;
 371         int pcm_open_flag;
 372         unsigned int suspended: 1;
 373 };
 374
 375 struct intel8x0 {
 376         unsigned int device_type;
 377
 378         int irq;
 379
 380         void __iomem *addr;
 381         void __iomem *bmaddr;
 382
 383         struct pci_dev *pci;
 384         struct snd_card *card;
 385
 386         int pcm_devs;
 387         struct snd_pcm *pcm[6];
 388         struct ichdev ichd[6];
 389
 390         unsigned multi4: 1,
 391                  multi6: 1,
 392                  multi8 :1,
 393                  dra: 1,
 394                  smp20bit: 1;
 395         unsigned in_ac97_init: 1,
 396                  in_sdin_init: 1;
 397         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 398         unsigned fix_nocache: 1;        /* workaround for 440MX */
 399         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 400         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 401         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
 402         unsigned inside_vm: 1;          /* enable VM optimization */
 403
 404         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 405         unsigned int sdm_saved; /* SDM reg value */
 406
 407         struct snd_ac97_bus *ac97_bus;
 408         struct snd_ac97 *ac97[3];
 409         unsigned int ac97_sdin[3];
 410         unsigned int max_codecs, ncodecs;
 411         unsigned int *codec_bit;
 412         unsigned int codec_isr_bits;
 413         unsigned int codec_ready_bits;
 414
 415         spinlock_t reg_lock;
 416
 417         u32 bdbars_count;
 418         struct snd_dma_buffer bdbars;
 419         u32 int_sta_reg;                /* interrupt status register */
 420         u32 int_sta_mask;               /* interrupt status mask */
 421 };
 422
 423 static const struct pci_device_id snd_intel8x0_ids[] = {
 424         { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL },   /* 82801AA */
 425         { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL },   /* 82901AB */
 426         { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL },   /* 82801BA */
 427         { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL },   /* ICH3 */
 428         { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
 429         { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
 430         { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
 431         { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
 432         { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
 433         { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
 434         { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL },   /* 440MX */
 435         { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS },        /* SI7012 */
 436         { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
 437         { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
 438         { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
 439         { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
 440         { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
 441         { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
 442         { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
 443         { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
 444         { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL },     /* AMD8111 */
 445         { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL },     /* AMD768 */
 446         { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },   /* Ali5455 */
 447         { 0, }
 448 };
 449
 450 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 451
 452 /*
 453  *  Lowlevel I/O - busmaster
 454  */
 455
 456 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
 457 {
 458         return ioread8(chip->bmaddr + offset);
 459 }
 460
 461 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
 462 {
 463         return ioread16(chip->bmaddr + offset);
 464 }
 465
 466 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
 467 {
 468         return ioread32(chip->bmaddr + offset);
 469 }
 470
 471 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
 472 {
 473         iowrite8(val, chip->bmaddr + offset);
 474 }
 475
 476 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
 477 {
 478         iowrite16(val, chip->bmaddr + offset);
 479 }
 480
 481 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
 482 {
 483         iowrite32(val, chip->bmaddr + offset);
 484 }
 485
 486 /*
 487  *  Lowlevel I/O - AC'97 registers
 488  */
 489
 490 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
 491 {
 492         return ioread16(chip->addr + offset);
 493 }
 494
 495 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
 496 {
 497         iowrite16(val, chip->addr + offset);
 498 }
 499
 500 /*
 501  *  Basic I/O
 502  */
 503
 504 /*
 505  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 506  */
 507
 508 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
 509 {
 510         int time;
 511
 512         if (codec > 2)
 513                 return -EIO;
 514         if (chip->in_sdin_init) {
 515                 /* we don't know the ready bit assignment at the moment */
 516                 /* so we check any */
 517                 codec = chip->codec_isr_bits;
 518         } else {
 519                 codec = chip->codec_bit[chip->ac97_sdin[codec]];
 520         }
 521
 522         /* codec ready ? */
 523         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 524                 return -EIO;
 525
 526         if (chip->buggy_semaphore)
 527                 return 0; /* just ignore ... */
 528
 529         /* Anyone holding a semaphore for 1 msec should be shot... */
 530         time = 100;
 531         do {
 532                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 533                         return 0;
 534                 udelay(10);
 535         } while (time--);
 536
 537         /* access to some forbidden (non existent) ac97 registers will not
 538          * reset the semaphore. So even if you don't get the semaphore, still
 539          * continue the access. We don't need the semaphore anyway. */
 540         dev_err(chip->card->dev,
 541                 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 542                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 543         iagetword(chip, 0);     /* clear semaphore flag */
 544         /* I don't care about the semaphore */
 545         return -EBUSY;
 546 }
 547
 548 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
 549                                      unsigned short reg,
 550                                      unsigned short val)
 551 {
 552         struct intel8x0 *chip = ac97->private_data;
 553
 554         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 555                 if (! chip->in_ac97_init)
 556                         dev_err(chip->card->dev,
 557                                 "codec_write %d: semaphore is not ready for register 0x%x\n",
 558                                 ac97->num, reg);
 559         }
 560         iaputword(chip, reg + ac97->num * 0x80, val);
 561 }
 562
 563 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
 564                                               unsigned short reg)
 565 {
 566         struct intel8x0 *chip = ac97->private_data;
 567         unsigned short res;
 568         unsigned int tmp;
 569
 570         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 571                 if (! chip->in_ac97_init)
 572                         dev_err(chip->card->dev,
 573                                 "codec_read %d: semaphore is not ready for register 0x%x\n",
 574                                 ac97->num, reg);
 575                 res = 0xffff;
 576         } else {
 577                 res = iagetword(chip, reg + ac97->num * 0x80);
 578                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 579                         /* reset RCS and preserve other R/WC bits */
 580                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 581                                   ~(chip->codec_ready_bits | ICH_GSCI));
 582                         if (! chip->in_ac97_init)
 583                                 dev_err(chip->card->dev,
 584                                         "codec_read %d: read timeout for register 0x%x\n",
 585                                         ac97->num, reg);
 586                         res = 0xffff;
 587                 }
 588         }
 589         return res;
 590 }
 591
 592 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
 593                                          unsigned int codec)
 594 {
 595         unsigned int tmp;
 596
 597         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 598                 iagetword(chip, codec * 0x80);
 599                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 600                         /* reset RCS and preserve other R/WC bits */
 601                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 602                                   ~(chip->codec_ready_bits | ICH_GSCI));
 603                 }
 604         }
 605 }
 606
 607 /*
 608  * access to AC97 for Ali5455
 609  */
 610 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
 611 {
 612         int count = 0;
 613         for (count = 0; count < 0x7f; count++) {
 614                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 615                 if (val & mask)
 616                         return 0;
 617         }
 618         if (! chip->in_ac97_init)
 619                 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
 620         return -EBUSY;
 621 }
 622
 623 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
 624 {
 625         int time = 100;
 626         if (chip->buggy_semaphore)
 627                 return 0; /* just ignore ... */
 628         while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 629                 udelay(1);
 630         if (! time && ! chip->in_ac97_init)
 631                 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
 632         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 633 }
 634
 635 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 636 {
 637         struct intel8x0 *chip = ac97->private_data;
 638         unsigned short data = 0xffff;
 639
 640         if (snd_intel8x0_ali_codec_semaphore(chip))
 641                 goto __err;
 642         reg |= ALI_CPR_ADDR_READ;
 643         if (ac97->num)
 644                 reg |= ALI_CPR_ADDR_SECONDARY;
 645         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 646         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 647                 goto __err;
 648         data = igetword(chip, ICHREG(ALI_SPR));
 649  __err:
 650         return data;
 651 }
 652
 653 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 654                                          unsigned short val)
 655 {
 656         struct intel8x0 *chip = ac97->private_data;
 657
 658         if (snd_intel8x0_ali_codec_semaphore(chip))
 659                 return;
 660         iputword(chip, ICHREG(ALI_CPR), val);
 661         if (ac97->num)
 662                 reg |= ALI_CPR_ADDR_SECONDARY;
 663         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 664         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 665 }
 666
 667
 668 /*
 669  * DMA I/O
 670  */
 671 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
 672 {
 673         int idx;
 674         __le32 *bdbar = ichdev->bdbar;
 675         unsigned long port = ichdev->reg_offset;
 676
 677         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 678         if (ichdev->size == ichdev->fragsize) {
 679                 ichdev->ack_reload = ichdev->ack = 2;
 680                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 681                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 682                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 683                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 684                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 685                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 686                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 687                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 688                 }
 689                 ichdev->frags = 2;
 690         } else {
 691                 ichdev->ack_reload = ichdev->ack = 1;
 692                 ichdev->fragsize1 = ichdev->fragsize;
 693                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 694                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
 695                                                      (((idx >> 1) * ichdev->fragsize) %
 696                                                       ichdev->size));
 697                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 698                                                      ichdev->fragsize >> ichdev->pos_shift);
 699 #if 0
 700                         dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
 701                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 702 #endif
 703                 }
 704                 ichdev->frags = ichdev->size / ichdev->fragsize;
 705         }
 706         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 707         ichdev->civ = 0;
 708         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 709         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 710         ichdev->position = 0;
 711 #if 0
 712         dev_dbg(chip->card->dev,
 713                 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 714                ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
 715                ichdev->fragsize1);
 716 #endif
 717         /* clear interrupts */
 718         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 719 }
 720
 721 /*
 722  *  Interrupt handler
 723  */
 724
 725 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
 726 {
 727         unsigned long port = ichdev->reg_offset;
 728         unsigned long flags;
 729         int status, civ, i, step;
 730         int ack = 0;
 731
 732         spin_lock_irqsave(&chip->reg_lock, flags);
 733         status = igetbyte(chip, port + ichdev->roff_sr);
 734         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 735         if (!(status & ICH_BCIS)) {
 736                 step = 0;
 737         } else if (civ == ichdev->civ) {
 738                 // snd_printd("civ same %d\n", civ);
 739                 step = 1;
 740                 ichdev->civ++;
 741                 ichdev->civ &= ICH_REG_LVI_MASK;
 742         } else {
 743                 step = civ - ichdev->civ;
 744                 if (step < 0)
 745                         step += ICH_REG_LVI_MASK + 1;
 746                 // if (step != 1)
 747                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 748                 ichdev->civ = civ;
 749         }
 750
 751         ichdev->position += step * ichdev->fragsize1;
 752         if (! chip->in_measurement)
 753                 ichdev->position %= ichdev->size;
 754         ichdev->lvi += step;
 755         ichdev->lvi &= ICH_REG_LVI_MASK;
 756         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 757         for (i = 0; i < step; i++) {
 758                 ichdev->lvi_frag++;
 759                 ichdev->lvi_frag %= ichdev->frags;
 760                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 761 #if 0
 762         dev_dbg(chip->card->dev,
 763                 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
 764                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
 765                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
 766                inl(port + 4), inb(port + ICH_REG_OFF_CR));
 767 #endif
 768                 if (--ichdev->ack == 0) {
 769                         ichdev->ack = ichdev->ack_reload;
 770                         ack = 1;
 771                 }
 772         }
 773         spin_unlock_irqrestore(&chip->reg_lock, flags);
 774         if (ack && ichdev->substream) {
 775                 snd_pcm_period_elapsed(ichdev->substream);
 776         }
 777         iputbyte(chip, port + ichdev->roff_sr,
 778                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 779 }
 780
 781 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
 782 {
 783         struct intel8x0 *chip = dev_id;
 784         struct ichdev *ichdev;
 785         unsigned int status;
 786         unsigned int i;
 787
 788         status = igetdword(chip, chip->int_sta_reg);
 789         if (status == 0xffffffff)       /* we are not yet resumed */
 790                 return IRQ_NONE;
 791
 792         if ((status & chip->int_sta_mask) == 0) {
 793                 if (status) {
 794                         /* ack */
 795                         iputdword(chip, chip->int_sta_reg, status);
 796                         if (! chip->buggy_irq)
 797                                 status = 0;
 798                 }
 799                 return IRQ_RETVAL(status);
 800         }
 801
 802         for (i = 0; i < chip->bdbars_count; i++) {
 803                 ichdev = &chip->ichd[i];
 804                 if (status & ichdev->int_sta_mask)
 805                         snd_intel8x0_update(chip, ichdev);
 806         }
 807
 808         /* ack them */
 809         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 810
 811         return IRQ_HANDLED;
 812 }
 813
 814 /*
 815  *  PCM part
 816  */
 817
 818 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 819 {
 820         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 821         struct ichdev *ichdev = get_ichdev(substream);
 822         unsigned char val = 0;
 823         unsigned long port = ichdev->reg_offset;
 824
 825         switch (cmd) {
 826         case SNDRV_PCM_TRIGGER_RESUME:
 827                 ichdev->suspended = 0;
 828                 /* fall through */
 829         case SNDRV_PCM_TRIGGER_START:
 830         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 831                 val = ICH_IOCE | ICH_STARTBM;
 832                 ichdev->last_pos = ichdev->position;
 833                 break;
 834         case SNDRV_PCM_TRIGGER_SUSPEND:
 835                 ichdev->suspended = 1;
 836                 /* fall through */
 837         case SNDRV_PCM_TRIGGER_STOP:
 838                 val = 0;
 839                 break;
 840         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 841                 val = ICH_IOCE;
 842                 break;
 843         default:
 844                 return -EINVAL;
 845         }
 846         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 847         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 848                 /* wait until DMA stopped */
 849                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 850                 /* reset whole DMA things */
 851                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 852         }
 853         return 0;
 854 }
 855
 856 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
 857 {
 858         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 859         struct ichdev *ichdev = get_ichdev(substream);
 860         unsigned long port = ichdev->reg_offset;
 861         static int fiforeg[] = {
 862                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
 863         };
 864         unsigned int val, fifo;
 865
 866         val = igetdword(chip, ICHREG(ALI_DMACR));
 867         switch (cmd) {
 868         case SNDRV_PCM_TRIGGER_RESUME:
 869                 ichdev->suspended = 0;
 870                 /* fall through */
 871         case SNDRV_PCM_TRIGGER_START:
 872         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 873                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 874                         /* clear FIFO for synchronization of channels */
 875                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 876                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 877                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 878                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 879                 }
 880                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 881                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 882                 /* start DMA */
 883                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
 884                 break;
 885         case SNDRV_PCM_TRIGGER_SUSPEND:
 886                 ichdev->suspended = 1;
 887                 /* fall through */
 888         case SNDRV_PCM_TRIGGER_STOP:
 889         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 890                 /* pause */
 891                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
 892                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 893                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 894                         ;
 895                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 896                         break;
 897                 /* reset whole DMA things */
 898                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 899                 /* clear interrupts */
 900                 iputbyte(chip, port + ICH_REG_OFF_SR,
 901                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 902                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 903                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 904                 break;
 905         default:
 906                 return -EINVAL;
 907         }
 908         return 0;
 909 }
 910
 911 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
 912                                   struct snd_pcm_hw_params *hw_params)
 913 {
 914         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 915         struct ichdev *ichdev = get_ichdev(substream);
 916         int dbl = params_rate(hw_params) > 48000;
 917         int err;
 918
 919         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 920         if (err < 0)
 921                 return err;
 922         if (ichdev->pcm_open_flag) {
 923                 snd_ac97_pcm_close(ichdev->pcm);
 924                 ichdev->pcm_open_flag = 0;
 925         }
 926         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 927                                 params_channels(hw_params),
 928                                 ichdev->pcm->r[dbl].slots);
 929         if (err >= 0) {
 930                 ichdev->pcm_open_flag = 1;
 931                 /* Force SPDIF setting */
 932                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 933                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
 934                                           params_rate(hw_params));
 935         }
 936         return err;
 937 }
 938
 939 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
 940 {
 941         struct ichdev *ichdev = get_ichdev(substream);
 942
 943         if (ichdev->pcm_open_flag) {
 944                 snd_ac97_pcm_close(ichdev->pcm);
 945                 ichdev->pcm_open_flag = 0;
 946         }
 947         return snd_pcm_lib_free_pages(substream);
 948 }
 949
 950 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
 951                                        struct snd_pcm_runtime *runtime)
 952 {
 953         unsigned int cnt;
 954         int dbl = runtime->rate > 48000;
 955
 956         spin_lock_irq(&chip->reg_lock);
 957         switch (chip->device_type) {
 958         case DEVICE_ALI:
 959                 cnt = igetdword(chip, ICHREG(ALI_SCR));
 960                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
 961                 if (runtime->channels == 4 || dbl)
 962                         cnt |= ICH_ALI_SC_PCM_4;
 963                 else if (runtime->channels == 6)
 964                         cnt |= ICH_ALI_SC_PCM_6;
 965                 iputdword(chip, ICHREG(ALI_SCR), cnt);
 966                 break;
 967         case DEVICE_SIS:
 968                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 969                 cnt &= ~ICH_SIS_PCM_246_MASK;
 970                 if (runtime->channels == 4 || dbl)
 971                         cnt |= ICH_SIS_PCM_4;
 972                 else if (runtime->channels == 6)
 973                         cnt |= ICH_SIS_PCM_6;
 974                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 975                 break;
 976         default:
 977                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 978                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
 979                 if (runtime->channels == 4 || dbl)
 980                         cnt |= ICH_PCM_4;
 981                 else if (runtime->channels == 6)
 982                         cnt |= ICH_PCM_6;
 983                 else if (runtime->channels == 8)
 984                         cnt |= ICH_PCM_8;
 985                 if (chip->device_type == DEVICE_NFORCE) {
 986                         /* reset to 2ch once to keep the 6 channel data in alignment,
 987                          * to start from Front Left always
 988                          */
 989                         if (cnt & ICH_PCM_246_MASK) {
 990                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
 991                                 spin_unlock_irq(&chip->reg_lock);
 992                                 msleep(50); /* grrr... */
 993                                 spin_lock_irq(&chip->reg_lock);
 994                         }
 995                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
 996                         if (runtime->sample_bits > 16)
 997                                 cnt |= ICH_PCM_20BIT;
 998                 }
 999                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1000                 break;
1001         }
1002         spin_unlock_irq(&chip->reg_lock);
1003 }
1004
1005 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1006 {
1007         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1008         struct snd_pcm_runtime *runtime = substream->runtime;
1009         struct ichdev *ichdev = get_ichdev(substream);
1010
1011         ichdev->physbuf = runtime->dma_addr;
1012         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1013         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1014         if (ichdev->ichd == ICHD_PCMOUT) {
1015                 snd_intel8x0_setup_pcm_out(chip, runtime);
1016                 if (chip->device_type == DEVICE_INTEL_ICH4)
1017                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1018         }
1019         snd_intel8x0_setup_periods(chip, ichdev);
1020         return 0;
1021 }
1022
1023 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1024 {
1025         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1026         struct ichdev *ichdev = get_ichdev(substream);
1027         size_t ptr1, ptr;
1028         int civ, timeout = 10;
1029         unsigned int position;
1030
1031         spin_lock(&chip->reg_lock);
1032         do {
1033                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1034                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1035                 position = ichdev->position;
1036                 if (ptr1 == 0) {
1037                         udelay(10);
1038                         continue;
1039                 }
1040                 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1041                         continue;
1042
1043                 /* IO read operation is very expensive inside virtual machine
1044                  * as it is emulated. The probability that subsequent PICB read
1045                  * will return different result is high enough to loop till
1046                  * timeout here.
1047                  * Same CIV is strict enough condition to be sure that PICB
1048                  * is valid inside VM on emulated card. */
1049                 if (chip->inside_vm)
1050                         break;
1051                 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1052                         break;
1053         } while (timeout--);
1054         ptr = ichdev->last_pos;
1055         if (ptr1 != 0) {
1056                 ptr1 <<= ichdev->pos_shift;
1057                 ptr = ichdev->fragsize1 - ptr1;
1058                 ptr += position;
1059                 if (ptr < ichdev->last_pos) {
1060                         unsigned int pos_base, last_base;
1061                         pos_base = position / ichdev->fragsize1;
1062                         last_base = ichdev->last_pos / ichdev->fragsize1;
1063                         /* another sanity check; ptr1 can go back to full
1064                          * before the base position is updated
1065                          */
1066                         if (pos_base == last_base)
1067                                 ptr = ichdev->last_pos;
1068                 }
1069         }
1070         ichdev->last_pos = ptr;
1071         spin_unlock(&chip->reg_lock);
1072         if (ptr >= ichdev->size)
1073                 return 0;
1074         return bytes_to_frames(substream->runtime, ptr);
1075 }
1076
1077 static const struct snd_pcm_hardware snd_intel8x0_stream =
1078 {
1079         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1080                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1081                                  SNDRV_PCM_INFO_MMAP_VALID |
1082                                  SNDRV_PCM_INFO_PAUSE |
1083                                  SNDRV_PCM_INFO_RESUME),
1084         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1085         .rates =                SNDRV_PCM_RATE_48000,
1086         .rate_min =             48000,
1087         .rate_max =             48000,
1088         .channels_min =         2,
1089         .channels_max =         2,
1090         .buffer_bytes_max =     128 * 1024,
1091         .period_bytes_min =     32,
1092         .period_bytes_max =     128 * 1024,
1093         .periods_min =          1,
1094         .periods_max =          1024,
1095         .fifo_size =            0,
1096 };
1097
1098 static const unsigned int channels4[] = {
1099         2, 4,
1100 };
1101
1102 static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1103         .count = ARRAY_SIZE(channels4),
1104         .list = channels4,
1105         .mask = 0,
1106 };
1107
1108 static const unsigned int channels6[] = {
1109         2, 4, 6,
1110 };
1111
1112 static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1113         .count = ARRAY_SIZE(channels6),
1114         .list = channels6,
1115         .mask = 0,
1116 };
1117
1118 static const unsigned int channels8[] = {
1119         2, 4, 6, 8,
1120 };
1121
1122 static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1123         .count = ARRAY_SIZE(channels8),
1124         .list = channels8,
1125         .mask = 0,
1126 };
1127
1128 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1129 {
1130         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1131         struct snd_pcm_runtime *runtime = substream->runtime;
1132         int err;
1133
1134         ichdev->substream = substream;
1135         runtime->hw = snd_intel8x0_stream;
1136         runtime->hw.rates = ichdev->pcm->rates;
1137         snd_pcm_limit_hw_rates(runtime);
1138         if (chip->device_type == DEVICE_SIS) {
1139                 runtime->hw.buffer_bytes_max = 64*1024;
1140                 runtime->hw.period_bytes_max = 64*1024;
1141         }
1142         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1143                 return err;
1144         runtime->private_data = ichdev;
1145         return 0;
1146 }
1147
1148 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1149 {
1150         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1151         struct snd_pcm_runtime *runtime = substream->runtime;
1152         int err;
1153
1154         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1155         if (err < 0)
1156                 return err;
1157
1158         if (chip->multi8) {
1159                 runtime->hw.channels_max = 8;
1160                 snd_pcm_hw_constraint_list(runtime, 0,
1161                                                 SNDRV_PCM_HW_PARAM_CHANNELS,
1162                                                 &hw_constraints_channels8);
1163         } else if (chip->multi6) {
1164                 runtime->hw.channels_max = 6;
1165                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1166                                            &hw_constraints_channels6);
1167         } else if (chip->multi4) {
1168                 runtime->hw.channels_max = 4;
1169                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1170                                            &hw_constraints_channels4);
1171         }
1172         if (chip->dra) {
1173                 snd_ac97_pcm_double_rate_rules(runtime);
1174         }
1175         if (chip->smp20bit) {
1176                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1177                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1178         }
1179         return 0;
1180 }
1181
1182 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1183 {
1184         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1185
1186         chip->ichd[ICHD_PCMOUT].substream = NULL;
1187         return 0;
1188 }
1189
1190 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1191 {
1192         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1193
1194         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1195 }
1196
1197 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1198 {
1199         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1200
1201         chip->ichd[ICHD_PCMIN].substream = NULL;
1202         return 0;
1203 }
1204
1205 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1206 {
1207         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1208
1209         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1210 }
1211
1212 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1213 {
1214         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1215
1216         chip->ichd[ICHD_MIC].substream = NULL;
1217         return 0;
1218 }
1219
1220 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1221 {
1222         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1223
1224         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1225 }
1226
1227 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1228 {
1229         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1230
1231         chip->ichd[ICHD_MIC2].substream = NULL;
1232         return 0;
1233 }
1234
1235 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1236 {
1237         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1238
1239         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1240 }
1241
1242 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1243 {
1244         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1245
1246         chip->ichd[ICHD_PCM2IN].substream = NULL;
1247         return 0;
1248 }
1249
1250 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1251 {
1252         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1253         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1254
1255         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1256 }
1257
1258 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1259 {
1260         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1261         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1262
1263         chip->ichd[idx].substream = NULL;
1264         return 0;
1265 }
1266
1267 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1268 {
1269         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1270         unsigned int val;
1271
1272         spin_lock_irq(&chip->reg_lock);
1273         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1274         val |= ICH_ALI_IF_AC97SP;
1275         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1276         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1277         spin_unlock_irq(&chip->reg_lock);
1278
1279         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1280 }
1281
1282 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1283 {
1284         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1285         unsigned int val;
1286
1287         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1288         spin_lock_irq(&chip->reg_lock);
1289         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1290         val &= ~ICH_ALI_IF_AC97SP;
1291         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1292         spin_unlock_irq(&chip->reg_lock);
1293
1294         return 0;
1295 }
1296
1297 #if 0 // NYI
1298 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1299 {
1300         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1301
1302         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1303 }
1304
1305 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1306 {
1307         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1308
1309         chip->ichd[ALID_SPDIFIN].substream = NULL;
1310         return 0;
1311 }
1312
1313 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1314 {
1315         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1316
1317         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1318 }
1319
1320 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1321 {
1322         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1323
1324         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1325         return 0;
1326 }
1327 #endif
1328
1329 static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1330         .open =         snd_intel8x0_playback_open,
1331         .close =        snd_intel8x0_playback_close,
1332         .ioctl =        snd_pcm_lib_ioctl,
1333         .hw_params =    snd_intel8x0_hw_params,
1334         .hw_free =      snd_intel8x0_hw_free,
1335         .prepare =      snd_intel8x0_pcm_prepare,
1336         .trigger =      snd_intel8x0_pcm_trigger,
1337         .pointer =      snd_intel8x0_pcm_pointer,
1338 };
1339
1340 static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1341         .open =         snd_intel8x0_capture_open,
1342         .close =        snd_intel8x0_capture_close,
1343         .ioctl =        snd_pcm_lib_ioctl,
1344         .hw_params =    snd_intel8x0_hw_params,
1345         .hw_free =      snd_intel8x0_hw_free,
1346         .prepare =      snd_intel8x0_pcm_prepare,
1347         .trigger =      snd_intel8x0_pcm_trigger,
1348         .pointer =      snd_intel8x0_pcm_pointer,
1349 };
1350
1351 static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1352         .open =         snd_intel8x0_mic_open,
1353         .close =        snd_intel8x0_mic_close,
1354         .ioctl =        snd_pcm_lib_ioctl,
1355         .hw_params =    snd_intel8x0_hw_params,
1356         .hw_free =      snd_intel8x0_hw_free,
1357         .prepare =      snd_intel8x0_pcm_prepare,
1358         .trigger =      snd_intel8x0_pcm_trigger,
1359         .pointer =      snd_intel8x0_pcm_pointer,
1360 };
1361
1362 static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1363         .open =         snd_intel8x0_mic2_open,
1364         .close =        snd_intel8x0_mic2_close,
1365         .ioctl =        snd_pcm_lib_ioctl,
1366         .hw_params =    snd_intel8x0_hw_params,
1367         .hw_free =      snd_intel8x0_hw_free,
1368         .prepare =      snd_intel8x0_pcm_prepare,
1369         .trigger =      snd_intel8x0_pcm_trigger,
1370         .pointer =      snd_intel8x0_pcm_pointer,
1371 };
1372
1373 static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1374         .open =         snd_intel8x0_capture2_open,
1375         .close =        snd_intel8x0_capture2_close,
1376         .ioctl =        snd_pcm_lib_ioctl,
1377         .hw_params =    snd_intel8x0_hw_params,
1378         .hw_free =      snd_intel8x0_hw_free,
1379         .prepare =      snd_intel8x0_pcm_prepare,
1380         .trigger =      snd_intel8x0_pcm_trigger,
1381         .pointer =      snd_intel8x0_pcm_pointer,
1382 };
1383
1384 static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1385         .open =         snd_intel8x0_spdif_open,
1386         .close =        snd_intel8x0_spdif_close,
1387         .ioctl =        snd_pcm_lib_ioctl,
1388         .hw_params =    snd_intel8x0_hw_params,
1389         .hw_free =      snd_intel8x0_hw_free,
1390         .prepare =      snd_intel8x0_pcm_prepare,
1391         .trigger =      snd_intel8x0_pcm_trigger,
1392         .pointer =      snd_intel8x0_pcm_pointer,
1393 };
1394
1395 static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1396         .open =         snd_intel8x0_playback_open,
1397         .close =        snd_intel8x0_playback_close,
1398         .ioctl =        snd_pcm_lib_ioctl,
1399         .hw_params =    snd_intel8x0_hw_params,
1400         .hw_free =      snd_intel8x0_hw_free,
1401         .prepare =      snd_intel8x0_pcm_prepare,
1402         .trigger =      snd_intel8x0_ali_trigger,
1403         .pointer =      snd_intel8x0_pcm_pointer,
1404 };
1405
1406 static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1407         .open =         snd_intel8x0_capture_open,
1408         .close =        snd_intel8x0_capture_close,
1409         .ioctl =        snd_pcm_lib_ioctl,
1410         .hw_params =    snd_intel8x0_hw_params,
1411         .hw_free =      snd_intel8x0_hw_free,
1412         .prepare =      snd_intel8x0_pcm_prepare,
1413         .trigger =      snd_intel8x0_ali_trigger,
1414         .pointer =      snd_intel8x0_pcm_pointer,
1415 };
1416
1417 static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1418         .open =         snd_intel8x0_mic_open,
1419         .close =        snd_intel8x0_mic_close,
1420         .ioctl =        snd_pcm_lib_ioctl,
1421         .hw_params =    snd_intel8x0_hw_params,
1422         .hw_free =      snd_intel8x0_hw_free,
1423         .prepare =      snd_intel8x0_pcm_prepare,
1424         .trigger =      snd_intel8x0_ali_trigger,
1425         .pointer =      snd_intel8x0_pcm_pointer,
1426 };
1427
1428 static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1429         .open =         snd_intel8x0_ali_ac97spdifout_open,
1430         .close =        snd_intel8x0_ali_ac97spdifout_close,
1431         .ioctl =        snd_pcm_lib_ioctl,
1432         .hw_params =    snd_intel8x0_hw_params,
1433         .hw_free =      snd_intel8x0_hw_free,
1434         .prepare =      snd_intel8x0_pcm_prepare,
1435         .trigger =      snd_intel8x0_ali_trigger,
1436         .pointer =      snd_intel8x0_pcm_pointer,
1437 };
1438
1439 #if 0 // NYI
1440 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1441         .open =         snd_intel8x0_ali_spdifin_open,
1442         .close =        snd_intel8x0_ali_spdifin_close,
1443         .ioctl =        snd_pcm_lib_ioctl,
1444         .hw_params =    snd_intel8x0_hw_params,
1445         .hw_free =      snd_intel8x0_hw_free,
1446         .prepare =      snd_intel8x0_pcm_prepare,
1447         .trigger =      snd_intel8x0_pcm_trigger,
1448         .pointer =      snd_intel8x0_pcm_pointer,
1449 };
1450
1451 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1452         .open =         snd_intel8x0_ali_spdifout_open,
1453         .close =        snd_intel8x0_ali_spdifout_close,
1454         .ioctl =        snd_pcm_lib_ioctl,
1455         .hw_params =    snd_intel8x0_hw_params,
1456         .hw_free =      snd_intel8x0_hw_free,
1457         .prepare =      snd_intel8x0_pcm_prepare,
1458         .trigger =      snd_intel8x0_pcm_trigger,
1459         .pointer =      snd_intel8x0_pcm_pointer,
1460 };
1461 #endif // NYI
1462
1463 struct ich_pcm_table {
1464         char *suffix;
1465         const struct snd_pcm_ops *playback_ops;
1466         const struct snd_pcm_ops *capture_ops;
1467         size_t prealloc_size;
1468         size_t prealloc_max_size;
1469         int ac97_idx;
1470 };
1471
1472 #define intel8x0_dma_type(chip) \
1473         ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_UC : SNDRV_DMA_TYPE_DEV)
1474
1475 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1476                              struct ich_pcm_table *rec)
1477 {
1478         struct snd_pcm *pcm;
1479         int err;
1480         char name[32];
1481
1482         if (rec->suffix)
1483                 sprintf(name, "Intel ICH - %s", rec->suffix);
1484         else
1485                 strcpy(name, "Intel ICH");
1486         err = snd_pcm_new(chip->card, name, device,
1487                           rec->playback_ops ? 1 : 0,
1488                           rec->capture_ops ? 1 : 0, &pcm);
1489         if (err < 0)
1490                 return err;
1491
1492         if (rec->playback_ops)
1493                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1494         if (rec->capture_ops)
1495                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1496
1497         pcm->private_data = chip;
1498         pcm->info_flags = 0;
1499         if (rec->suffix)
1500                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1501         else
1502                 strcpy(pcm->name, chip->card->shortname);
1503         chip->pcm[device] = pcm;
1504
1505         snd_pcm_lib_preallocate_pages_for_all(pcm, intel8x0_dma_type(chip),
1506                                               snd_dma_pci_data(chip->pci),
1507                                               rec->prealloc_size, rec->prealloc_max_size);
1508
1509         if (rec->playback_ops &&
1510             rec->playback_ops->open == snd_intel8x0_playback_open) {
1511                 struct snd_pcm_chmap *chmap;
1512                 int chs = 2;
1513                 if (chip->multi8)
1514                         chs = 8;
1515                 else if (chip->multi6)
1516                         chs = 6;
1517                 else if (chip->multi4)
1518                         chs = 4;
1519                 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1520                                              snd_pcm_alt_chmaps, chs, 0,
1521                                              &chmap);
1522                 if (err < 0)
1523                         return err;
1524                 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1525                 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1526         }
1527
1528         return 0;
1529 }
1530
1531 static struct ich_pcm_table intel_pcms[] = {
1532         {
1533                 .playback_ops = &snd_intel8x0_playback_ops,
1534                 .capture_ops = &snd_intel8x0_capture_ops,
1535                 .prealloc_size = 64 * 1024,
1536                 .prealloc_max_size = 128 * 1024,
1537         },
1538         {
1539                 .suffix = "MIC ADC",
1540                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1541                 .prealloc_size = 0,
1542                 .prealloc_max_size = 128 * 1024,
1543                 .ac97_idx = ICHD_MIC,
1544         },
1545         {
1546                 .suffix = "MIC2 ADC",
1547                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1548                 .prealloc_size = 0,
1549                 .prealloc_max_size = 128 * 1024,
1550                 .ac97_idx = ICHD_MIC2,
1551         },
1552         {
1553                 .suffix = "ADC2",
1554                 .capture_ops = &snd_intel8x0_capture2_ops,
1555                 .prealloc_size = 0,
1556                 .prealloc_max_size = 128 * 1024,
1557                 .ac97_idx = ICHD_PCM2IN,
1558         },
1559         {
1560                 .suffix = "IEC958",
1561                 .playback_ops = &snd_intel8x0_spdif_ops,
1562                 .prealloc_size = 64 * 1024,
1563                 .prealloc_max_size = 128 * 1024,
1564                 .ac97_idx = ICHD_SPBAR,
1565         },
1566 };
1567
1568 static struct ich_pcm_table nforce_pcms[] = {
1569         {
1570                 .playback_ops = &snd_intel8x0_playback_ops,
1571                 .capture_ops = &snd_intel8x0_capture_ops,
1572                 .prealloc_size = 64 * 1024,
1573                 .prealloc_max_size = 128 * 1024,
1574         },
1575         {
1576                 .suffix = "MIC ADC",
1577                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1578                 .prealloc_size = 0,
1579                 .prealloc_max_size = 128 * 1024,
1580                 .ac97_idx = NVD_MIC,
1581         },
1582         {
1583                 .suffix = "IEC958",
1584                 .playback_ops = &snd_intel8x0_spdif_ops,
1585                 .prealloc_size = 64 * 1024,
1586                 .prealloc_max_size = 128 * 1024,
1587                 .ac97_idx = NVD_SPBAR,
1588         },
1589 };
1590
1591 static struct ich_pcm_table ali_pcms[] = {
1592         {
1593                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1594                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1595                 .prealloc_size = 64 * 1024,
1596                 .prealloc_max_size = 128 * 1024,
1597         },
1598         {
1599                 .suffix = "MIC ADC",
1600                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1601                 .prealloc_size = 0,
1602                 .prealloc_max_size = 128 * 1024,
1603                 .ac97_idx = ALID_MIC,
1604         },
1605         {
1606                 .suffix = "IEC958",
1607                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1608                 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1609                 .prealloc_size = 64 * 1024,
1610                 .prealloc_max_size = 128 * 1024,
1611                 .ac97_idx = ALID_AC97SPDIFOUT,
1612         },
1613 #if 0 // NYI
1614         {
1615                 .suffix = "HW IEC958",
1616                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1617                 .prealloc_size = 64 * 1024,
1618                 .prealloc_max_size = 128 * 1024,
1619         },
1620 #endif
1621 };
1622
1623 static int snd_intel8x0_pcm(struct intel8x0 *chip)
1624 {
1625         int i, tblsize, device, err;
1626         struct ich_pcm_table *tbl, *rec;
1627
1628         switch (chip->device_type) {
1629         case DEVICE_INTEL_ICH4:
1630                 tbl = intel_pcms;
1631                 tblsize = ARRAY_SIZE(intel_pcms);
1632                 if (spdif_aclink)
1633                         tblsize--;
1634                 break;
1635         case DEVICE_NFORCE:
1636                 tbl = nforce_pcms;
1637                 tblsize = ARRAY_SIZE(nforce_pcms);
1638                 if (spdif_aclink)
1639                         tblsize--;
1640                 break;
1641         case DEVICE_ALI:
1642                 tbl = ali_pcms;
1643                 tblsize = ARRAY_SIZE(ali_pcms);
1644                 break;
1645         default:
1646                 tbl = intel_pcms;
1647                 tblsize = 2;
1648                 break;
1649         }
1650
1651         device = 0;
1652         for (i = 0; i < tblsize; i++) {
1653                 rec = tbl + i;
1654                 if (i > 0 && rec->ac97_idx) {
1655                         /* activate PCM only when associated AC'97 codec */
1656                         if (! chip->ichd[rec->ac97_idx].pcm)
1657                                 continue;
1658                 }
1659                 err = snd_intel8x0_pcm1(chip, device, rec);
1660                 if (err < 0)
1661                         return err;
1662                 device++;
1663         }
1664
1665         chip->pcm_devs = device;
1666         return 0;
1667 }
1668
1669
1670 /*
1671  *  Mixer part
1672  */
1673
1674 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1675 {
1676         struct intel8x0 *chip = bus->private_data;
1677         chip->ac97_bus = NULL;
1678 }
1679
1680 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1681 {
1682         struct intel8x0 *chip = ac97->private_data;
1683         chip->ac97[ac97->num] = NULL;
1684 }
1685
1686 static const struct ac97_pcm ac97_pcm_defs[] = {
1687         /* front PCM */
1688         {
1689                 .exclusive = 1,
1690                 .r = {  {
1691                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1692                                          (1 << AC97_SLOT_PCM_RIGHT) |
1693                                          (1 << AC97_SLOT_PCM_CENTER) |
1694                                          (1 << AC97_SLOT_PCM_SLEFT) |
1695                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1696                                          (1 << AC97_SLOT_LFE)
1697                         },
1698                         {
1699                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1700                                          (1 << AC97_SLOT_PCM_RIGHT) |
1701                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1702                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1703                         }
1704                 }
1705         },
1706         /* PCM IN #1 */
1707         {
1708                 .stream = 1,
1709                 .exclusive = 1,
1710                 .r = {  {
1711                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1712                                          (1 << AC97_SLOT_PCM_RIGHT)
1713                         }
1714                 }
1715         },
1716         /* MIC IN #1 */
1717         {
1718                 .stream = 1,
1719                 .exclusive = 1,
1720                 .r = {  {
1721                                 .slots = (1 << AC97_SLOT_MIC)
1722                         }
1723                 }
1724         },
1725         /* S/PDIF PCM */
1726         {
1727                 .exclusive = 1,
1728                 .spdif = 1,
1729                 .r = {  {
1730                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1731                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1732                         }
1733                 }
1734         },
1735         /* PCM IN #2 */
1736         {
1737                 .stream = 1,
1738                 .exclusive = 1,
1739                 .r = {  {
1740                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1741                                          (1 << AC97_SLOT_PCM_RIGHT)
1742                         }
1743                 }
1744         },
1745         /* MIC IN #2 */
1746         {
1747                 .stream = 1,
1748                 .exclusive = 1,
1749                 .r = {  {
1750                                 .slots = (1 << AC97_SLOT_MIC)
1751                         }
1752                 }
1753         },
1754 };
1755
1756 static const struct ac97_quirk ac97_quirks[] = {
1757         {
1758                 .subvendor = 0x0e11,
1759                 .subdevice = 0x000e,
1760                 .name = "Compaq Deskpro EN",    /* AD1885 */
1761                 .type = AC97_TUNE_HP_ONLY
1762         },
1763         {
1764                 .subvendor = 0x0e11,
1765                 .subdevice = 0x008a,
1766                 .name = "Compaq Evo W4000",     /* AD1885 */
1767                 .type = AC97_TUNE_HP_ONLY
1768         },
1769         {
1770                 .subvendor = 0x0e11,
1771                 .subdevice = 0x00b8,
1772                 .name = "Compaq Evo D510C",
1773                 .type = AC97_TUNE_HP_ONLY
1774         },
1775         {
1776                 .subvendor = 0x0e11,
1777                 .subdevice = 0x0860,
1778                 .name = "HP/Compaq nx7010",
1779                 .type = AC97_TUNE_MUTE_LED
1780         },
1781         {
1782                 .subvendor = 0x1014,
1783                 .subdevice = 0x0534,
1784                 .name = "ThinkPad X31",
1785                 .type = AC97_TUNE_INV_EAPD
1786         },
1787         {
1788                 .subvendor = 0x1014,
1789                 .subdevice = 0x1f00,
1790                 .name = "MS-9128",
1791                 .type = AC97_TUNE_ALC_JACK
1792         },
1793         {
1794                 .subvendor = 0x1014,
1795                 .subdevice = 0x0267,
1796                 .name = "IBM NetVista A30p",    /* AD1981B */
1797                 .type = AC97_TUNE_HP_ONLY
1798         },
1799         {
1800                 .subvendor = 0x1025,
1801                 .subdevice = 0x0082,
1802                 .name = "Acer Travelmate 2310",
1803                 .type = AC97_TUNE_HP_ONLY
1804         },
1805         {
1806                 .subvendor = 0x1025,
1807                 .subdevice = 0x0083,
1808                 .name = "Acer Aspire 3003LCi",
1809                 .type = AC97_TUNE_HP_ONLY
1810         },
1811         {
1812                 .subvendor = 0x1028,
1813                 .subdevice = 0x00d8,
1814                 .name = "Dell Precision 530",   /* AD1885 */
1815                 .type = AC97_TUNE_HP_ONLY
1816         },
1817         {
1818                 .subvendor = 0x1028,
1819                 .subdevice = 0x010d,
1820                 .name = "Dell", /* which model?  AD1885 */
1821                 .type = AC97_TUNE_HP_ONLY
1822         },
1823         {
1824                 .subvendor = 0x1028,
1825                 .subdevice = 0x0126,
1826                 .name = "Dell Optiplex GX260",  /* AD1981A */
1827                 .type = AC97_TUNE_HP_ONLY
1828         },
1829         {
1830                 .subvendor = 0x1028,
1831                 .subdevice = 0x012c,
1832                 .name = "Dell Precision 650",   /* AD1981A */
1833                 .type = AC97_TUNE_HP_ONLY
1834         },
1835         {
1836                 .subvendor = 0x1028,
1837                 .subdevice = 0x012d,
1838                 .name = "Dell Precision 450",   /* AD1981B*/
1839                 .type = AC97_TUNE_HP_ONLY
1840         },
1841         {
1842                 .subvendor = 0x1028,
1843                 .subdevice = 0x0147,
1844                 .name = "Dell", /* which model?  AD1981B*/
1845                 .type = AC97_TUNE_HP_ONLY
1846         },
1847         {
1848                 .subvendor = 0x1028,
1849                 .subdevice = 0x0151,
1850                 .name = "Dell Optiplex GX270",  /* AD1981B */
1851                 .type = AC97_TUNE_HP_ONLY
1852         },
1853         {
1854                 .subvendor = 0x1028,
1855                 .subdevice = 0x014e,
1856                 .name = "Dell D800", /* STAC9750/51 */
1857                 .type = AC97_TUNE_HP_ONLY
1858         },
1859         {
1860                 .subvendor = 0x1028,
1861                 .subdevice = 0x0163,
1862                 .name = "Dell Unknown", /* STAC9750/51 */
1863                 .type = AC97_TUNE_HP_ONLY
1864         },
1865         {
1866                 .subvendor = 0x1028,
1867                 .subdevice = 0x016a,
1868                 .name = "Dell Inspiron 8600",   /* STAC9750/51 */
1869                 .type = AC97_TUNE_HP_ONLY
1870         },
1871         {
1872                 .subvendor = 0x1028,
1873                 .subdevice = 0x0182,
1874                 .name = "Dell Latitude D610",   /* STAC9750/51 */
1875                 .type = AC97_TUNE_HP_ONLY
1876         },
1877         {
1878                 .subvendor = 0x1028,
1879                 .subdevice = 0x0186,
1880                 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1881                 .type = AC97_TUNE_HP_MUTE_LED
1882         },
1883         {
1884                 .subvendor = 0x1028,
1885                 .subdevice = 0x0188,
1886                 .name = "Dell Inspiron 6000",
1887                 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1888         },
1889         {
1890                 .subvendor = 0x1028,
1891                 .subdevice = 0x0189,
1892                 .name = "Dell Inspiron 9300",
1893                 .type = AC97_TUNE_HP_MUTE_LED
1894         },
1895         {
1896                 .subvendor = 0x1028,
1897                 .subdevice = 0x0191,
1898                 .name = "Dell Inspiron 8600",
1899                 .type = AC97_TUNE_HP_ONLY
1900         },
1901         {
1902                 .subvendor = 0x103c,
1903                 .subdevice = 0x006d,
1904                 .name = "HP zv5000",
1905                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1906         },
1907         {       /* FIXME: which codec? */
1908                 .subvendor = 0x103c,
1909                 .subdevice = 0x00c3,
1910                 .name = "HP xw6000",
1911                 .type = AC97_TUNE_HP_ONLY
1912         },
1913         {
1914                 .subvendor = 0x103c,
1915                 .subdevice = 0x088c,
1916                 .name = "HP nc8000",
1917                 .type = AC97_TUNE_HP_MUTE_LED
1918         },
1919         {
1920                 .subvendor = 0x103c,
1921                 .subdevice = 0x0890,
1922                 .name = "HP nc6000",
1923                 .type = AC97_TUNE_MUTE_LED
1924         },
1925         {
1926                 .subvendor = 0x103c,
1927                 .subdevice = 0x129d,
1928                 .name = "HP xw8000",
1929                 .type = AC97_TUNE_HP_ONLY
1930         },
1931         {
1932                 .subvendor = 0x103c,
1933                 .subdevice = 0x0938,
1934                 .name = "HP nc4200",
1935                 .type = AC97_TUNE_HP_MUTE_LED
1936         },
1937         {
1938                 .subvendor = 0x103c,
1939                 .subdevice = 0x099c,
1940                 .name = "HP nx6110/nc6120",
1941                 .type = AC97_TUNE_HP_MUTE_LED
1942         },
1943         {
1944                 .subvendor = 0x103c,
1945                 .subdevice = 0x0944,
1946                 .name = "HP nc6220",
1947                 .type = AC97_TUNE_HP_MUTE_LED
1948         },
1949         {
1950                 .subvendor = 0x103c,
1951                 .subdevice = 0x0934,
1952                 .name = "HP nc8220",
1953                 .type = AC97_TUNE_HP_MUTE_LED
1954         },
1955         {
1956                 .subvendor = 0x103c,
1957                 .subdevice = 0x12f1,
1958                 .name = "HP xw8200",    /* AD1981B*/
1959                 .type = AC97_TUNE_HP_ONLY
1960         },
1961         {
1962                 .subvendor = 0x103c,
1963                 .subdevice = 0x12f2,
1964                 .name = "HP xw6200",
1965                 .type = AC97_TUNE_HP_ONLY
1966         },
1967         {
1968                 .subvendor = 0x103c,
1969                 .subdevice = 0x3008,
1970                 .name = "HP xw4200",    /* AD1981B*/
1971                 .type = AC97_TUNE_HP_ONLY
1972         },
1973         {
1974                 .subvendor = 0x104d,
1975                 .subdevice = 0x8144,
1976                 .name = "Sony",
1977                 .type = AC97_TUNE_INV_EAPD
1978         },
1979         {
1980                 .subvendor = 0x104d,
1981                 .subdevice = 0x8197,
1982                 .name = "Sony S1XP",
1983                 .type = AC97_TUNE_INV_EAPD
1984         },
1985         {
1986                 .subvendor = 0x104d,
1987                 .subdevice = 0x81c0,
1988                 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1989                 .type = AC97_TUNE_INV_EAPD
1990         },
1991         {
1992                 .subvendor = 0x104d,
1993                 .subdevice = 0x81c5,
1994                 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1995                 .type = AC97_TUNE_INV_EAPD
1996         },
1997         {
1998                 .subvendor = 0x1043,
1999                 .subdevice = 0x80f3,
2000                 .name = "ASUS ICH5/AD1985",
2001                 .type = AC97_TUNE_AD_SHARING
2002         },
2003         {
2004                 .subvendor = 0x10cf,
2005                 .subdevice = 0x11c3,
2006                 .name = "Fujitsu-Siemens E4010",
2007                 .type = AC97_TUNE_HP_ONLY
2008         },
2009         {
2010                 .subvendor = 0x10cf,
2011                 .subdevice = 0x1225,
2012                 .name = "Fujitsu-Siemens T3010",
2013                 .type = AC97_TUNE_HP_ONLY
2014         },
2015         {
2016                 .subvendor = 0x10cf,
2017                 .subdevice = 0x1253,
2018                 .name = "Fujitsu S6210",        /* STAC9750/51 */
2019                 .type = AC97_TUNE_HP_ONLY
2020         },
2021         {
2022                 .subvendor = 0x10cf,
2023                 .subdevice = 0x127d,
2024                 .name = "Fujitsu Lifebook P7010",
2025                 .type = AC97_TUNE_HP_ONLY
2026         },
2027         {
2028                 .subvendor = 0x10cf,
2029                 .subdevice = 0x127e,
2030                 .name = "Fujitsu Lifebook C1211D",
2031                 .type = AC97_TUNE_HP_ONLY
2032         },
2033         {
2034                 .subvendor = 0x10cf,
2035                 .subdevice = 0x12ec,
2036                 .name = "Fujitsu-Siemens 4010",
2037                 .type = AC97_TUNE_HP_ONLY
2038         },
2039         {
2040                 .subvendor = 0x10cf,
2041                 .subdevice = 0x12f2,
2042                 .name = "Fujitsu-Siemens Celsius H320",
2043                 .type = AC97_TUNE_SWAP_HP
2044         },
2045         {
2046                 .subvendor = 0x10f1,
2047                 .subdevice = 0x2665,
2048                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
2049                 .type = AC97_TUNE_HP_ONLY
2050         },
2051         {
2052                 .subvendor = 0x10f1,
2053                 .subdevice = 0x2885,
2054                 .name = "AMD64 Mobo",   /* ALC650 */
2055                 .type = AC97_TUNE_HP_ONLY
2056         },
2057         {
2058                 .subvendor = 0x10f1,
2059                 .subdevice = 0x2895,
2060                 .name = "Tyan Thunder K8WE",
2061                 .type = AC97_TUNE_HP_ONLY
2062         },
2063         {
2064                 .subvendor = 0x10f7,
2065                 .subdevice = 0x834c,
2066                 .name = "Panasonic CF-R4",
2067                 .type = AC97_TUNE_HP_ONLY,
2068         },
2069         {
2070                 .subvendor = 0x110a,
2071                 .subdevice = 0x0056,
2072                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
2073                 .type = AC97_TUNE_HP_ONLY
2074         },
2075         {
2076                 .subvendor = 0x11d4,
2077                 .subdevice = 0x5375,
2078                 .name = "ADI AD1985 (discrete)",
2079                 .type = AC97_TUNE_HP_ONLY
2080         },
2081         {
2082                 .subvendor = 0x1462,
2083                 .subdevice = 0x5470,
2084                 .name = "MSI P4 ATX 645 Ultra",
2085                 .type = AC97_TUNE_HP_ONLY
2086         },
2087         {
2088                 .subvendor = 0x161f,
2089                 .subdevice = 0x202f,
2090                 .name = "Gateway M520",
2091                 .type = AC97_TUNE_INV_EAPD
2092         },
2093         {
2094                 .subvendor = 0x161f,
2095                 .subdevice = 0x203a,
2096                 .name = "Gateway 4525GZ",               /* AD1981B */
2097                 .type = AC97_TUNE_INV_EAPD
2098         },
2099         {
2100                 .subvendor = 0x1734,
2101                 .subdevice = 0x0088,
2102                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
2103                 .type = AC97_TUNE_HP_ONLY
2104         },
2105         {
2106                 .subvendor = 0x8086,
2107                 .subdevice = 0x2000,
2108                 .mask = 0xfff0,
2109                 .name = "Intel ICH5/AD1985",
2110                 .type = AC97_TUNE_AD_SHARING
2111         },
2112         {
2113                 .subvendor = 0x8086,
2114                 .subdevice = 0x4000,
2115                 .mask = 0xfff0,
2116                 .name = "Intel ICH5/AD1985",
2117                 .type = AC97_TUNE_AD_SHARING
2118         },
2119         {
2120                 .subvendor = 0x8086,
2121                 .subdevice = 0x4856,
2122                 .name = "Intel D845WN (82801BA)",
2123                 .type = AC97_TUNE_SWAP_HP
2124         },
2125         {
2126                 .subvendor = 0x8086,
2127                 .subdevice = 0x4d44,
2128                 .name = "Intel D850EMV2",       /* AD1885 */
2129                 .type = AC97_TUNE_HP_ONLY
2130         },
2131         {
2132                 .subvendor = 0x8086,
2133                 .subdevice = 0x4d56,
2134                 .name = "Intel ICH/AD1885",
2135                 .type = AC97_TUNE_HP_ONLY
2136         },
2137         {
2138                 .subvendor = 0x8086,
2139                 .subdevice = 0x6000,
2140                 .mask = 0xfff0,
2141                 .name = "Intel ICH5/AD1985",
2142                 .type = AC97_TUNE_AD_SHARING
2143         },
2144         {
2145                 .subvendor = 0x8086,
2146                 .subdevice = 0xe000,
2147                 .mask = 0xfff0,
2148                 .name = "Intel ICH5/AD1985",
2149                 .type = AC97_TUNE_AD_SHARING
2150         },
2151 #if 0 /* FIXME: this seems wrong on most boards */
2152         {
2153                 .subvendor = 0x8086,
2154                 .subdevice = 0xa000,
2155                 .mask = 0xfff0,
2156                 .name = "Intel ICH5/AD1985",
2157                 .type = AC97_TUNE_HP_ONLY
2158         },
2159 #endif
2160         { } /* terminator */
2161 };
2162
2163 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2164                               const char *quirk_override)
2165 {
2166         struct snd_ac97_bus *pbus;
2167         struct snd_ac97_template ac97;
2168         int err;
2169         unsigned int i, codecs;
2170         unsigned int glob_sta = 0;
2171         struct snd_ac97_bus_ops *ops;
2172         static struct snd_ac97_bus_ops standard_bus_ops = {
2173                 .write = snd_intel8x0_codec_write,
2174                 .read = snd_intel8x0_codec_read,
2175         };
2176         static struct snd_ac97_bus_ops ali_bus_ops = {
2177                 .write = snd_intel8x0_ali_codec_write,
2178                 .read = snd_intel8x0_ali_codec_read,
2179         };
2180
2181         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2182         if (!spdif_aclink) {
2183                 switch (chip->device_type) {
2184                 case DEVICE_NFORCE:
2185                         chip->spdif_idx = NVD_SPBAR;
2186                         break;
2187                 case DEVICE_ALI:
2188                         chip->spdif_idx = ALID_AC97SPDIFOUT;
2189                         break;
2190                 case DEVICE_INTEL_ICH4:
2191                         chip->spdif_idx = ICHD_SPBAR;
2192                         break;
2193                 }
2194         }
2195
2196         chip->in_ac97_init = 1;
2197
2198         memset(&ac97, 0, sizeof(ac97));
2199         ac97.private_data = chip;
2200         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2201         ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2202         if (chip->xbox)
2203                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2204         if (chip->device_type != DEVICE_ALI) {
2205                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2206                 ops = &standard_bus_ops;
2207                 chip->in_sdin_init = 1;
2208                 codecs = 0;
2209                 for (i = 0; i < chip->max_codecs; i++) {
2210                         if (! (glob_sta & chip->codec_bit[i]))
2211                                 continue;
2212                         if (chip->device_type == DEVICE_INTEL_ICH4) {
2213                                 snd_intel8x0_codec_read_test(chip, codecs);
2214                                 chip->ac97_sdin[codecs] =
2215                                         igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2216                                 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2217                                         chip->ac97_sdin[codecs] = 0;
2218                         } else
2219                                 chip->ac97_sdin[codecs] = i;
2220                         codecs++;
2221                 }
2222                 chip->in_sdin_init = 0;
2223                 if (! codecs)
2224                         codecs = 1;
2225         } else {
2226                 ops = &ali_bus_ops;
2227                 codecs = 1;
2228                 /* detect the secondary codec */
2229                 for (i = 0; i < 100; i++) {
2230                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2231                         if (reg & 0x40) {
2232                                 codecs = 2;
2233                                 break;
2234                         }
2235                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2236                         udelay(1);
2237                 }
2238         }
2239         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2240                 goto __err;
2241         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2242         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2243                 pbus->clock = ac97_clock;
2244         /* FIXME: my test board doesn't work well with VRA... */
2245         if (chip->device_type == DEVICE_ALI)
2246                 pbus->no_vra = 1;
2247         else
2248                 pbus->dra = 1;
2249         chip->ac97_bus = pbus;
2250         chip->ncodecs = codecs;
2251
2252         ac97.pci = chip->pci;
2253         for (i = 0; i < codecs; i++) {
2254                 ac97.num = i;
2255                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2256                         if (err != -EACCES)
2257                                 dev_err(chip->card->dev,
2258                                         "Unable to initialize codec #%d\n", i);
2259                         if (i == 0)
2260                                 goto __err;
2261                 }
2262         }
2263         /* tune up the primary codec */
2264         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2265         /* enable separate SDINs for ICH4 */
2266         if (chip->device_type == DEVICE_INTEL_ICH4)
2267                 pbus->isdin = 1;
2268         /* find the available PCM streams */
2269         i = ARRAY_SIZE(ac97_pcm_defs);
2270         if (chip->device_type != DEVICE_INTEL_ICH4)
2271                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2272         if (chip->spdif_idx < 0)
2273                 i--;            /* do not allocate S/PDIF */
2274         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2275         if (err < 0)
2276                 goto __err;
2277         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2278         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2279         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2280         if (chip->spdif_idx >= 0)
2281                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2282         if (chip->device_type == DEVICE_INTEL_ICH4) {
2283                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2284                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2285         }
2286         /* enable separate SDINs for ICH4 */
2287         if (chip->device_type == DEVICE_INTEL_ICH4) {
2288                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2289                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2290                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2291                 if (pcm) {
2292                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2293                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2294                         for (i = 1; i < 4; i++) {
2295                                 if (pcm->r[0].codec[i]) {
2296                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2297                                         break;
2298                                 }
2299                         }
2300                 } else {
2301                         tmp &= ~ICH_SE; /* steer disable */
2302                 }
2303                 iputbyte(chip, ICHREG(SDM), tmp);
2304         }
2305         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2306                 chip->multi4 = 1;
2307                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2308                         chip->multi6 = 1;
2309                         if (chip->ac97[0]->flags & AC97_HAS_8CH)
2310                                 chip->multi8 = 1;
2311                 }
2312         }
2313         if (pbus->pcms[0].r[1].rslots[0]) {
2314                 chip->dra = 1;
2315         }
2316         if (chip->device_type == DEVICE_INTEL_ICH4) {
2317                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2318                         chip->smp20bit = 1;
2319         }
2320         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2321                 /* 48kHz only */
2322                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2323         }
2324         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2325                 /* use slot 10/11 for SPDIF */
2326                 u32 val;
2327                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2328                 val |= ICH_PCM_SPDIF_1011;
2329                 iputdword(chip, ICHREG(GLOB_CNT), val);
2330                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2331         }
2332         chip->in_ac97_init = 0;
2333         return 0;
2334
2335  __err:
2336         /* clear the cold-reset bit for the next chance */
2337         if (chip->device_type != DEVICE_ALI)
2338                 iputdword(chip, ICHREG(GLOB_CNT),
2339                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2340         return err;
2341 }
2342
2343
2344 /*
2345  *
2346  */
2347
2348 static void do_ali_reset(struct intel8x0 *chip)
2349 {
2350         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2351         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2352         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2353         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2354         iputdword(chip, ICHREG(ALI_INTERFACECR),
2355                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2356         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2357         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2358 }
2359
2360 #ifdef CONFIG_SND_AC97_POWER_SAVE
2361 static struct snd_pci_quirk ich_chip_reset_mode[] = {
2362         SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2363         { } /* end */
2364 };
2365
2366 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2367 {
2368         unsigned int cnt;
2369         /* ACLink on, 2 channels */
2370
2371         if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2372                 return -EIO;
2373
2374         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2375         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2376
2377         /* do cold reset - the full ac97 powerdown may leave the controller
2378          * in a warm state but actually it cannot communicate with the codec.
2379          */
2380         iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2381         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2382         udelay(10);
2383         iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2384         msleep(1);
2385         return 0;
2386 }
2387 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2388         (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2389 #else
2390 #define snd_intel8x0_ich_chip_cold_reset(chip)  0
2391 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2392 #endif
2393
2394 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2395 {
2396         unsigned long end_time;
2397         unsigned int cnt;
2398         /* ACLink on, 2 channels */
2399         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2400         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2401         /* finish cold or do warm reset */
2402         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2403         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2404         end_time = (jiffies + (HZ / 4)) + 1;
2405         do {
2406                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2407                         return 0;
2408                 schedule_timeout_uninterruptible(1);
2409         } while (time_after_eq(end_time, jiffies));
2410         dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2411                    igetdword(chip, ICHREG(GLOB_CNT)));
2412         return -EIO;
2413 }
2414
2415 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2416 {
2417         unsigned long end_time;
2418         unsigned int status, nstatus;
2419         unsigned int cnt;
2420         int err;
2421
2422         /* put logic to right state */
2423         /* first clear status bits */
2424         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2425         if (chip->device_type == DEVICE_NFORCE)
2426                 status |= ICH_NVSPINT;
2427         cnt = igetdword(chip, ICHREG(GLOB_STA));
2428         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2429
2430         if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2431                 err = snd_intel8x0_ich_chip_cold_reset(chip);
2432         else
2433                 err = snd_intel8x0_ich_chip_reset(chip);
2434         if (err < 0)
2435                 return err;
2436
2437         if (probing) {
2438                 /* wait for any codec ready status.
2439                  * Once it becomes ready it should remain ready
2440                  * as long as we do not disable the ac97 link.
2441                  */
2442                 end_time = jiffies + HZ;
2443                 do {
2444                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2445                                 chip->codec_isr_bits;
2446                         if (status)
2447                                 break;
2448                         schedule_timeout_uninterruptible(1);
2449                 } while (time_after_eq(end_time, jiffies));
2450                 if (! status) {
2451                         /* no codec is found */
2452                         dev_err(chip->card->dev,
2453                                 "codec_ready: codec is not ready [0x%x]\n",
2454                                    igetdword(chip, ICHREG(GLOB_STA)));
2455                         return -EIO;
2456                 }
2457
2458                 /* wait for other codecs ready status. */
2459                 end_time = jiffies + HZ / 4;
2460                 while (status != chip->codec_isr_bits &&
2461                        time_after_eq(end_time, jiffies)) {
2462                         schedule_timeout_uninterruptible(1);
2463                         status |= igetdword(chip, ICHREG(GLOB_STA)) &
2464                                 chip->codec_isr_bits;
2465                 }
2466
2467         } else {
2468                 /* resume phase */
2469                 int i;
2470                 status = 0;
2471                 for (i = 0; i < chip->ncodecs; i++)
2472                         if (chip->ac97[i])
2473                                 status |= chip->codec_bit[chip->ac97_sdin[i]];
2474                 /* wait until all the probed codecs are ready */
2475                 end_time = jiffies + HZ;
2476                 do {
2477                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2478                                 chip->codec_isr_bits;
2479                         if (status == nstatus)
2480                                 break;
2481                         schedule_timeout_uninterruptible(1);
2482                 } while (time_after_eq(end_time, jiffies));
2483         }
2484
2485         if (chip->device_type == DEVICE_SIS) {
2486                 /* unmute the output on SIS7012 */
2487                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2488         }
2489         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2490                 /* enable SPDIF interrupt */
2491                 unsigned int val;
2492                 pci_read_config_dword(chip->pci, 0x4c, &val);
2493                 val |= 0x1000000;
2494                 pci_write_config_dword(chip->pci, 0x4c, val);
2495         }
2496         return 0;
2497 }
2498
2499 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2500 {
2501         u32 reg;
2502         int i = 0;
2503
2504         reg = igetdword(chip, ICHREG(ALI_SCR));
2505         if ((reg & 2) == 0)     /* Cold required */
2506                 reg |= 2;
2507         else
2508                 reg |= 1;       /* Warm */
2509         reg &= ~0x80000000;     /* ACLink on */
2510         iputdword(chip, ICHREG(ALI_SCR), reg);
2511
2512         for (i = 0; i < HZ / 2; i++) {
2513                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2514                         goto __ok;
2515                 schedule_timeout_uninterruptible(1);
2516         }
2517         dev_err(chip->card->dev, "AC'97 reset failed.\n");
2518         if (probing)
2519                 return -EIO;
2520
2521  __ok:
2522         for (i = 0; i < HZ / 2; i++) {
2523                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2524                 if (reg & 0x80) /* primary codec */
2525                         break;
2526                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2527                 schedule_timeout_uninterruptible(1);
2528         }
2529
2530         do_ali_reset(chip);
2531         return 0;
2532 }
2533
2534 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2535 {
2536         unsigned int i, timeout;
2537         int err;
2538
2539         if (chip->device_type != DEVICE_ALI) {
2540                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2541                         return err;
2542                 iagetword(chip, 0);     /* clear semaphore flag */
2543         } else {
2544                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2545                         return err;
2546         }
2547
2548         /* disable interrupts */
2549         for (i = 0; i < chip->bdbars_count; i++)
2550                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2551         /* reset channels */
2552         for (i = 0; i < chip->bdbars_count; i++)
2553                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2554         for (i = 0; i < chip->bdbars_count; i++) {
2555                 timeout = 100000;
2556                 while (--timeout != 0) {
2557                         if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2558                                 break;
2559                 }
2560                 if (timeout == 0)
2561                         dev_err(chip->card->dev, "reset of registers failed?\n");
2562         }
2563         /* initialize Buffer Descriptor Lists */
2564         for (i = 0; i < chip->bdbars_count; i++)
2565                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2566                           chip->ichd[i].bdbar_addr);
2567         return 0;
2568 }
2569
2570 static int snd_intel8x0_free(struct intel8x0 *chip)
2571 {
2572         unsigned int i;
2573
2574         if (chip->irq < 0)
2575                 goto __hw_end;
2576         /* disable interrupts */
2577         for (i = 0; i < chip->bdbars_count; i++)
2578                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2579         /* reset channels */
2580         for (i = 0; i < chip->bdbars_count; i++)
2581                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2582         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2583                 /* stop the spdif interrupt */
2584                 unsigned int val;
2585                 pci_read_config_dword(chip->pci, 0x4c, &val);
2586                 val &= ~0x1000000;
2587                 pci_write_config_dword(chip->pci, 0x4c, val);
2588         }
2589         /* --- */
2590
2591       __hw_end:
2592         if (chip->irq >= 0)
2593                 free_irq(chip->irq, chip);
2594         if (chip->bdbars.area)
2595                 snd_dma_free_pages(&chip->bdbars);
2596         if (chip->addr)
2597                 pci_iounmap(chip->pci, chip->addr);
2598         if (chip->bmaddr)
2599                 pci_iounmap(chip->pci, chip->bmaddr);
2600         pci_release_regions(chip->pci);
2601         pci_disable_device(chip->pci);
2602         kfree(chip);
2603         return 0;
2604 }
2605
2606 #ifdef CONFIG_PM_SLEEP
2607 /*
2608  * power management
2609  */
2610 static int intel8x0_suspend(struct device *dev)
2611 {
2612         struct snd_card *card = dev_get_drvdata(dev);
2613         struct intel8x0 *chip = card->private_data;
2614         int i;
2615
2616         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2617         for (i = 0; i < chip->pcm_devs; i++)
2618                 snd_pcm_suspend_all(chip->pcm[i]);
2619         for (i = 0; i < chip->ncodecs; i++)
2620                 snd_ac97_suspend(chip->ac97[i]);
2621         if (chip->device_type == DEVICE_INTEL_ICH4)
2622                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2623
2624         if (chip->irq >= 0) {
2625                 free_irq(chip->irq, chip);
2626                 chip->irq = -1;
2627         }
2628         return 0;
2629 }
2630
2631 static int intel8x0_resume(struct device *dev)
2632 {
2633         struct pci_dev *pci = to_pci_dev(dev);
2634         struct snd_card *card = dev_get_drvdata(dev);
2635         struct intel8x0 *chip = card->private_data;
2636         int i;
2637
2638         snd_intel8x0_chip_init(chip, 0);
2639         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2640                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
2641                 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2642                         pci->irq);
2643                 snd_card_disconnect(card);
2644                 return -EIO;
2645         }
2646         chip->irq = pci->irq;
2647         synchronize_irq(chip->irq);
2648
2649         /* re-initialize mixer stuff */
2650         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2651                 /* enable separate SDINs for ICH4 */
2652                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2653                 /* use slot 10/11 for SPDIF */
2654                 iputdword(chip, ICHREG(GLOB_CNT),
2655                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2656                           ICH_PCM_SPDIF_1011);
2657         }
2658
2659         for (i = 0; i < chip->ncodecs; i++)
2660                 snd_ac97_resume(chip->ac97[i]);
2661
2662         /* resume status */
2663         for (i = 0; i < chip->bdbars_count; i++) {
2664                 struct ichdev *ichdev = &chip->ichd[i];
2665                 unsigned long port = ichdev->reg_offset;
2666                 if (! ichdev->substream || ! ichdev->suspended)
2667                         continue;
2668                 if (ichdev->ichd == ICHD_PCMOUT)
2669                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2670                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2671                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2672                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2673                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2674         }
2675
2676         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2677         return 0;
2678 }
2679
2680 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2681 #define INTEL8X0_PM_OPS &intel8x0_pm
2682 #else
2683 #define INTEL8X0_PM_OPS NULL
2684 #endif /* CONFIG_PM_SLEEP */
2685
2686 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2687
2688 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2689 {
2690         struct snd_pcm_substream *subs;
2691         struct ichdev *ichdev;
2692         unsigned long port;
2693         unsigned long pos, pos1, t;
2694         int civ, timeout = 1000, attempt = 1;
2695         ktime_t start_time, stop_time;
2696
2697         if (chip->ac97_bus->clock != 48000)
2698                 return; /* specified in module option */
2699
2700       __again:
2701         subs = chip->pcm[0]->streams[0].substream;
2702         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2703                 dev_warn(chip->card->dev,
2704                          "no playback buffer allocated - aborting measure ac97 clock\n");
2705                 return;
2706         }
2707         ichdev = &chip->ichd[ICHD_PCMOUT];
2708         ichdev->physbuf = subs->dma_buffer.addr;
2709         ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2710         ichdev->substream = NULL; /* don't process interrupts */
2711
2712         /* set rate */
2713         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2714                 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2715                         chip->ac97_bus->clock);
2716                 return;
2717         }
2718         snd_intel8x0_setup_periods(chip, ichdev);
2719         port = ichdev->reg_offset;
2720         spin_lock_irq(&chip->reg_lock);
2721         chip->in_measurement = 1;
2722         /* trigger */
2723         if (chip->device_type != DEVICE_ALI)
2724                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2725         else {
2726                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2727                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2728         }
2729         start_time = ktime_get();
2730         spin_unlock_irq(&chip->reg_lock);
2731         msleep(50);
2732         spin_lock_irq(&chip->reg_lock);
2733         /* check the position */
2734         do {
2735                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2736                 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2737                 if (pos1 == 0) {
2738                         udelay(10);
2739                         continue;
2740                 }
2741                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2742                     pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2743                         break;
2744         } while (timeout--);
2745         if (pos1 == 0) {        /* oops, this value is not reliable */
2746                 pos = 0;
2747         } else {
2748                 pos = ichdev->fragsize1;
2749                 pos -= pos1 << ichdev->pos_shift;
2750                 pos += ichdev->position;
2751         }
2752         chip->in_measurement = 0;
2753         stop_time = ktime_get();
2754         /* stop */
2755         if (chip->device_type == DEVICE_ALI) {
2756                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2757                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2758                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2759                         ;
2760         } else {
2761                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2762                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2763                         ;
2764         }
2765         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2766         spin_unlock_irq(&chip->reg_lock);
2767
2768         if (pos == 0) {
2769                 dev_err(chip->card->dev,
2770                         "measure - unreliable DMA position..\n");
2771               __retry:
2772                 if (attempt < 3) {
2773                         msleep(300);
2774                         attempt++;
2775                         goto __again;
2776                 }
2777                 goto __end;
2778         }
2779
2780         pos /= 4;
2781         t = ktime_us_delta(stop_time, start_time);
2782         dev_info(chip->card->dev,
2783                  "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2784         if (t == 0) {
2785                 dev_err(chip->card->dev, "?? calculation error..\n");
2786                 goto __retry;
2787         }
2788         pos *= 1000;
2789         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2790         if (pos < 40000 || pos >= 60000) {
2791                 /* abnormal value. hw problem? */
2792                 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2793                 goto __retry;
2794         } else if (pos > 40500 && pos < 41500)
2795                 /* first exception - 41000Hz reference clock */
2796                 chip->ac97_bus->clock = 41000;
2797         else if (pos > 43600 && pos < 44600)
2798                 /* second exception - 44100HZ reference clock */
2799                 chip->ac97_bus->clock = 44100;
2800         else if (pos < 47500 || pos > 48500)
2801                 /* not 48000Hz, tuning the clock.. */
2802                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2803       __end:
2804         dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2805         snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2806 }
2807
2808 static struct snd_pci_quirk intel8x0_clock_list[] = {
2809         SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2810         SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2811         SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2812         SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2813         SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2814         SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2815         { }     /* terminator */
2816 };
2817
2818 static int intel8x0_in_clock_list(struct intel8x0 *chip)
2819 {
2820         struct pci_dev *pci = chip->pci;
2821         const struct snd_pci_quirk *wl;
2822
2823         wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2824         if (!wl)
2825                 return 0;
2826         dev_info(chip->card->dev, "white list rate for %04x:%04x is %i\n",
2827                pci->subsystem_vendor, pci->subsystem_device, wl->value);
2828         chip->ac97_bus->clock = wl->value;
2829         return 1;
2830 }
2831
2832 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2833                                    struct snd_info_buffer *buffer)
2834 {
2835         struct intel8x0 *chip = entry->private_data;
2836         unsigned int tmp;
2837
2838         snd_iprintf(buffer, "Intel8x0\n\n");
2839         if (chip->device_type == DEVICE_ALI)
2840                 return;
2841         tmp = igetdword(chip, ICHREG(GLOB_STA));
2842         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2843         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2844         if (chip->device_type == DEVICE_INTEL_ICH4)
2845                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2846         snd_iprintf(buffer, "AC'97 codecs ready    :");
2847         if (tmp & chip->codec_isr_bits) {
2848                 int i;
2849                 static const char *codecs[3] = {
2850                         "primary", "secondary", "tertiary"
2851                 };
2852                 for (i = 0; i < chip->max_codecs; i++)
2853                         if (tmp & chip->codec_bit[i])
2854                                 snd_iprintf(buffer, " %s", codecs[i]);
2855         } else
2856                 snd_iprintf(buffer, " none");
2857         snd_iprintf(buffer, "\n");
2858         if (chip->device_type == DEVICE_INTEL_ICH4 ||
2859             chip->device_type == DEVICE_SIS)
2860                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2861                         chip->ac97_sdin[0],
2862                         chip->ac97_sdin[1],
2863                         chip->ac97_sdin[2]);
2864 }
2865
2866 static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2867 {
2868         struct snd_info_entry *entry;
2869
2870         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2871                 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2872 }
2873
2874 static int snd_intel8x0_dev_free(struct snd_device *device)
2875 {
2876         struct intel8x0 *chip = device->device_data;
2877         return snd_intel8x0_free(chip);
2878 }
2879
2880 struct ich_reg_info {
2881         unsigned int int_sta_mask;
2882         unsigned int offset;
2883 };
2884
2885 static unsigned int ich_codec_bits[3] = {
2886         ICH_PCR, ICH_SCR, ICH_TCR
2887 };
2888 static unsigned int sis_codec_bits[3] = {
2889         ICH_PCR, ICH_SCR, ICH_SIS_TCR
2890 };
2891
2892 static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2893 {
2894         int result  = inside_vm;
2895         char *msg   = NULL;
2896
2897         /* check module parameter first (override detection) */
2898         if (result >= 0) {
2899                 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2900                 goto fini;
2901         }
2902
2903         /* check for known (emulated) devices */
2904         result = 0;
2905         if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2906             pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2907                 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2908                 msg = "enable KVM";
2909                 result = 1;
2910         } else if (pci->subsystem_vendor == 0x1ab8) {
2911                 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2912                 msg = "enable Parallels VM";
2913                 result = 1;
2914         }
2915
2916 fini:
2917         if (msg != NULL)
2918                 dev_info(&pci->dev, "%s optimization\n", msg);
2919
2920         return result;
2921 }
2922
2923 static int snd_intel8x0_create(struct snd_card *card,
2924                                struct pci_dev *pci,
2925                                unsigned long device_type,
2926                                struct intel8x0 **r_intel8x0)
2927 {
2928         struct intel8x0 *chip;
2929         int err;
2930         unsigned int i;
2931         unsigned int int_sta_masks;
2932         struct ichdev *ichdev;
2933         static struct snd_device_ops ops = {
2934                 .dev_free =     snd_intel8x0_dev_free,
2935         };
2936
2937         static unsigned int bdbars[] = {
2938                 3, /* DEVICE_INTEL */
2939                 6, /* DEVICE_INTEL_ICH4 */
2940                 3, /* DEVICE_SIS */
2941                 6, /* DEVICE_ALI */
2942                 4, /* DEVICE_NFORCE */
2943         };
2944         static struct ich_reg_info intel_regs[6] = {
2945                 { ICH_PIINT, 0 },
2946                 { ICH_POINT, 0x10 },
2947                 { ICH_MCINT, 0x20 },
2948                 { ICH_M2INT, 0x40 },
2949                 { ICH_P2INT, 0x50 },
2950                 { ICH_SPINT, 0x60 },
2951         };
2952         static struct ich_reg_info nforce_regs[4] = {
2953                 { ICH_PIINT, 0 },
2954                 { ICH_POINT, 0x10 },
2955                 { ICH_MCINT, 0x20 },
2956                 { ICH_NVSPINT, 0x70 },
2957         };
2958         static struct ich_reg_info ali_regs[6] = {
2959                 { ALI_INT_PCMIN, 0x40 },
2960                 { ALI_INT_PCMOUT, 0x50 },
2961                 { ALI_INT_MICIN, 0x60 },
2962                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2963                 { ALI_INT_SPDIFIN, 0xa0 },
2964                 { ALI_INT_SPDIFOUT, 0xb0 },
2965         };
2966         struct ich_reg_info *tbl;
2967
2968         *r_intel8x0 = NULL;
2969
2970         if ((err = pci_enable_device(pci)) < 0)
2971                 return err;
2972
2973         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2974         if (chip == NULL) {
2975                 pci_disable_device(pci);
2976                 return -ENOMEM;
2977         }
2978         spin_lock_init(&chip->reg_lock);
2979         chip->device_type = device_type;
2980         chip->card = card;
2981         chip->pci = pci;
2982         chip->irq = -1;
2983
2984         /* module parameters */
2985         chip->buggy_irq = buggy_irq;
2986         chip->buggy_semaphore = buggy_semaphore;
2987         if (xbox)
2988                 chip->xbox = 1;
2989
2990         chip->inside_vm = snd_intel8x0_inside_vm(pci);
2991
2992         /*
2993          * Intel 82443MX running a 100MHz processor system bus has a hardware
2994          * bug, which aborts PCI busmaster for audio transfer.  A workaround
2995          * is to set the pages as non-cached.  For details, see the errata in
2996          *     http://download.intel.com/design/chipsets/specupdt/24505108.pdf
2997          */
2998         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2999             pci->device == PCI_DEVICE_ID_INTEL_440MX)
3000                 chip->fix_nocache = 1; /* enable workaround */
3001
3002         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
3003                 kfree(chip);
3004                 pci_disable_device(pci);
3005                 return err;
3006         }
3007
3008         if (device_type == DEVICE_ALI) {
3009                 /* ALI5455 has no ac97 region */
3010                 chip->bmaddr = pci_iomap(pci, 0, 0);
3011                 goto port_inited;
3012         }
3013
3014         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
3015                 chip->addr = pci_iomap(pci, 2, 0);
3016         else
3017                 chip->addr = pci_iomap(pci, 0, 0);
3018         if (!chip->addr) {
3019                 dev_err(card->dev, "AC'97 space ioremap problem\n");
3020                 snd_intel8x0_free(chip);
3021                 return -EIO;
3022         }
3023         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
3024                 chip->bmaddr = pci_iomap(pci, 3, 0);
3025         else
3026                 chip->bmaddr = pci_iomap(pci, 1, 0);
3027
3028  port_inited:
3029         if (!chip->bmaddr) {
3030                 dev_err(card->dev, "Controller space ioremap problem\n");
3031                 snd_intel8x0_free(chip);
3032                 return -EIO;
3033         }
3034         chip->bdbars_count = bdbars[device_type];
3035
3036         /* initialize offsets */
3037         switch (device_type) {
3038         case DEVICE_NFORCE:
3039                 tbl = nforce_regs;
3040                 break;
3041         case DEVICE_ALI:
3042                 tbl = ali_regs;
3043                 break;
3044         default:
3045                 tbl = intel_regs;
3046                 break;
3047         }
3048         for (i = 0; i < chip->bdbars_count; i++) {
3049                 ichdev = &chip->ichd[i];
3050                 ichdev->ichd = i;
3051                 ichdev->reg_offset = tbl[i].offset;
3052                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3053                 if (device_type == DEVICE_SIS) {
3054                         /* SiS 7012 swaps the registers */
3055                         ichdev->roff_sr = ICH_REG_OFF_PICB;
3056                         ichdev->roff_picb = ICH_REG_OFF_SR;
3057                 } else {
3058                         ichdev->roff_sr = ICH_REG_OFF_SR;
3059                         ichdev->roff_picb = ICH_REG_OFF_PICB;
3060                 }
3061                 if (device_type == DEVICE_ALI)
3062                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3063                 /* SIS7012 handles the pcm data in bytes, others are in samples */
3064                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3065         }
3066
3067         /* allocate buffer descriptor lists */
3068         /* the start of each lists must be aligned to 8 bytes */
3069         if (snd_dma_alloc_pages(intel8x0_dma_type(chip), snd_dma_pci_data(pci),
3070                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3071                                 &chip->bdbars) < 0) {
3072                 snd_intel8x0_free(chip);
3073                 dev_err(card->dev, "cannot allocate buffer descriptors\n");
3074                 return -ENOMEM;
3075         }
3076         /* tables must be aligned to 8 bytes here, but the kernel pages
3077            are much bigger, so we don't care (on i386) */
3078         int_sta_masks = 0;
3079         for (i = 0; i < chip->bdbars_count; i++) {
3080                 ichdev = &chip->ichd[i];
3081                 ichdev->bdbar = ((__le32 *)chip->bdbars.area) +
3082                         (i * ICH_MAX_FRAGS * 2);
3083                 ichdev->bdbar_addr = chip->bdbars.addr +
3084                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3085                 int_sta_masks |= ichdev->int_sta_mask;
3086         }
3087         chip->int_sta_reg = device_type == DEVICE_ALI ?
3088                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3089         chip->int_sta_mask = int_sta_masks;
3090
3091         pci_set_master(pci);
3092
3093         switch(chip->device_type) {
3094         case DEVICE_INTEL_ICH4:
3095                 /* ICH4 can have three codecs */
3096                 chip->max_codecs = 3;
3097                 chip->codec_bit = ich_codec_bits;
3098                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3099                 break;
3100         case DEVICE_SIS:
3101                 /* recent SIS7012 can have three codecs */
3102                 chip->max_codecs = 3;
3103                 chip->codec_bit = sis_codec_bits;
3104                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3105                 break;
3106         default:
3107                 /* others up to two codecs */
3108                 chip->max_codecs = 2;
3109                 chip->codec_bit = ich_codec_bits;
3110                 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3111                 break;
3112         }
3113         for (i = 0; i < chip->max_codecs; i++)
3114                 chip->codec_isr_bits |= chip->codec_bit[i];
3115
3116         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3117                 snd_intel8x0_free(chip);
3118                 return err;
3119         }
3120
3121         /* request irq after initializaing int_sta_mask, etc */
3122         if (request_irq(pci->irq, snd_intel8x0_interrupt,
3123                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
3124                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3125                 snd_intel8x0_free(chip);
3126                 return -EBUSY;
3127         }
3128         chip->irq = pci->irq;
3129
3130         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3131                 snd_intel8x0_free(chip);
3132                 return err;
3133         }
3134
3135         *r_intel8x0 = chip;
3136         return 0;
3137 }
3138
3139 static struct shortname_table {
3140         unsigned int id;
3141         const char *s;
3142 } shortnames[] = {
3143         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3144         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3145         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3146         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3147         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3148         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3149         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3150         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3151         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3152         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3153         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3154         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3155         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3156         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3157         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3158         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3159         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3160         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3161         { 0x003a, "NVidia MCP04" },
3162         { 0x746d, "AMD AMD8111" },
3163         { 0x7445, "AMD AMD768" },
3164         { 0x5455, "ALi M5455" },
3165         { 0, NULL },
3166 };
3167
3168 static struct snd_pci_quirk spdif_aclink_defaults[] = {
3169         SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3170         { } /* end */
3171 };
3172
3173 /* look up white/black list for SPDIF over ac-link */
3174 static int check_default_spdif_aclink(struct pci_dev *pci)
3175 {
3176         const struct snd_pci_quirk *w;
3177
3178         w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3179         if (w) {
3180                 if (w->value)
3181                         dev_dbg(&pci->dev,
3182                                 "Using SPDIF over AC-Link for %s\n",
3183                                     snd_pci_quirk_name(w));
3184                 else
3185                         dev_dbg(&pci->dev,
3186                                 "Using integrated SPDIF DMA for %s\n",
3187                                     snd_pci_quirk_name(w));
3188                 return w->value;
3189         }
3190         return 0;
3191 }
3192
3193 static int snd_intel8x0_probe(struct pci_dev *pci,
3194                               const struct pci_device_id *pci_id)
3195 {
3196         struct snd_card *card;
3197         struct intel8x0 *chip;
3198         int err;
3199         struct shortname_table *name;
3200
3201         err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
3202         if (err < 0)
3203                 return err;
3204
3205         if (spdif_aclink < 0)
3206                 spdif_aclink = check_default_spdif_aclink(pci);
3207
3208         strcpy(card->driver, "ICH");
3209         if (!spdif_aclink) {
3210                 switch (pci_id->driver_data) {
3211                 case DEVICE_NFORCE:
3212                         strcpy(card->driver, "NFORCE");
3213                         break;
3214                 case DEVICE_INTEL_ICH4:
3215                         strcpy(card->driver, "ICH4");
3216                 }
3217         }
3218
3219         strcpy(card->shortname, "Intel ICH");
3220         for (name = shortnames; name->id; name++) {
3221                 if (pci->device == name->id) {
3222                         strcpy(card->shortname, name->s);
3223                         break;
3224                 }
3225         }
3226
3227         if (buggy_irq < 0) {
3228                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3229                  * Needs to return IRQ_HANDLED for unknown irqs.
3230                  */
3231                 if (pci_id->driver_data == DEVICE_NFORCE)
3232                         buggy_irq = 1;
3233                 else
3234                         buggy_irq = 0;
3235         }
3236
3237         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3238                                        &chip)) < 0) {
3239                 snd_card_free(card);
3240                 return err;
3241         }
3242         card->private_data = chip;
3243
3244         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3245                 snd_card_free(card);
3246                 return err;
3247         }
3248         if ((err = snd_intel8x0_pcm(chip)) < 0) {
3249                 snd_card_free(card);
3250                 return err;
3251         }
3252
3253         snd_intel8x0_proc_init(chip);
3254
3255         snprintf(card->longname, sizeof(card->longname),
3256                  "%s with %s at irq %i", card->shortname,
3257                  snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3258
3259         if (ac97_clock == 0 || ac97_clock == 1) {
3260                 if (ac97_clock == 0) {
3261                         if (intel8x0_in_clock_list(chip) == 0)
3262                                 intel8x0_measure_ac97_clock(chip);
3263                 } else {
3264                         intel8x0_measure_ac97_clock(chip);
3265                 }
3266         }
3267
3268         if ((err = snd_card_register(card)) < 0) {
3269                 snd_card_free(card);
3270                 return err;
3271         }
3272         pci_set_drvdata(pci, card);
3273         return 0;
3274 }
3275
3276 static void snd_intel8x0_remove(struct pci_dev *pci)
3277 {
3278         snd_card_free(pci_get_drvdata(pci));
3279 }
3280
3281 static struct pci_driver intel8x0_driver = {
3282         .name = KBUILD_MODNAME,
3283         .id_table = snd_intel8x0_ids,
3284         .probe = snd_intel8x0_probe,
3285         .remove = snd_intel8x0_remove,
3286         .driver = {
3287                 .pm = INTEL8X0_PM_OPS,
3288         },
3289 };
3290
3291 module_pci_driver(intel8x0_driver);