sound/pci/intel8x0.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *   ALSA driver for Intel ICH (i8x0) chipsets
   4  *
   5  *      Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/ac97_codec.h>
  24 #include <sound/info.h>
  25 #include <sound/initval.h>
  26
  27 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  28 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  29 MODULE_LICENSE("GPL");
  30 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  31                 "{Intel,82901AB-ICH0},"
  32                 "{Intel,82801BA-ICH2},"
  33                 "{Intel,82801CA-ICH3},"
  34                 "{Intel,82801DB-ICH4},"
  35                 "{Intel,ICH5},"
  36                 "{Intel,ICH6},"
  37                 "{Intel,ICH7},"
  38                 "{Intel,6300ESB},"
  39                 "{Intel,ESB2},"
  40                 "{Intel,MX440},"
  41                 "{SiS,SI7012},"
  42                 "{NVidia,nForce Audio},"
  43                 "{NVidia,nForce2 Audio},"
  44                 "{NVidia,nForce3 Audio},"
  45                 "{NVidia,MCP04},"
  46                 "{NVidia,MCP501},"
  47                 "{NVidia,CK804},"
  48                 "{NVidia,CK8},"
  49                 "{NVidia,CK8S},"
  50                 "{AMD,AMD768},"
  51                 "{AMD,AMD8111},"
  52                 "{ALI,M5455}}");
  53
  54 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
  55 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
  56 static int ac97_clock;
  57 static char *ac97_quirk;
  58 static bool buggy_semaphore;
  59 static int buggy_irq = -1; /* auto-check */
  60 static bool xbox;
  61 static int spdif_aclink = -1;
  62 static int inside_vm = -1;
  63
  64 module_param(index, int, 0444);
  65 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  66 module_param(id, charp, 0444);
  67 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  68 module_param(ac97_clock, int, 0444);
  69 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect).");
  70 module_param(ac97_quirk, charp, 0444);
  71 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  72 module_param(buggy_semaphore, bool, 0444);
  73 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  74 module_param(buggy_irq, bint, 0444);
  75 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  76 module_param(xbox, bool, 0444);
  77 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  78 module_param(spdif_aclink, int, 0444);
  79 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  80 module_param(inside_vm, bint, 0444);
  81 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
  82
  83 /* just for backward compatibility */
  84 static bool enable;
  85 module_param(enable, bool, 0444);
  86 static int joystick;
  87 module_param(joystick, int, 0444);
  88
  89 /*
  90  *  Direct registers
  91  */
  92 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
  93
  94 #define ICHREG(x) ICH_REG_##x
  95
  96 #define DEFINE_REGSET(name,base) \
  97 enum { \
  98         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
  99         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 100         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 101         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 102         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 103         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 104         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 105 };
 106
 107 /* busmaster blocks */
 108 DEFINE_REGSET(OFF, 0);          /* offset */
 109 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 110 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 111 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 112
 113 /* ICH4 busmaster blocks */
 114 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 115 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 116 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 117
 118 /* values for each busmaster block */
 119
 120 /* LVI */
 121 #define ICH_REG_LVI_MASK                0x1f
 122
 123 /* SR */
 124 #define ICH_FIFOE                       0x10    /* FIFO error */
 125 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 126 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 127 #define ICH_CELV                        0x02    /* current equals last valid */
 128 #define ICH_DCH                         0x01    /* DMA controller halted */
 129
 130 /* PIV */
 131 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 132
 133 /* CR */
 134 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 135 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 136 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 137 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 138 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 139
 140
 141 /* global block */
 142 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 143 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 144 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 145 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 146 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 147 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 148 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 149 #define   ICH_PCM_246_MASK      0x00300000      /* chan mask (not all chips) */
 150 #define   ICH_PCM_8             0x00300000      /* 8 channels (not all chips) */
 151 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 152 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 153 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 154 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 155 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 156 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 157 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 158 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 159 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 160 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 161 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 162 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 163 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 164 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 165 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 166 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 167 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 168 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 169 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 170 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 171 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 172 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 173 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 174 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 175 #define   ICH_SIS_TRI           0x00080000      /* SIS: tertiary resume irq */
 176 #define   ICH_SIS_TCR           0x00040000      /* SIS: tertiary codec ready */
 177 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 178 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 179 #define   ICH_RCS               0x00008000      /* read completion status */
 180 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 181 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 182 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 183 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 184 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 185 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 186 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 187 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 188 #define   ICH_POINT             0x00000040      /* playback interrupt */
 189 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 190 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 191 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 192 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 193 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 194 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 195 #define   ICH_CAS               0x01            /* codec access semaphore */
 196 #define ICH_REG_SDM             0x80
 197 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 198 #define   ICH_DI2L_SHIFT        6
 199 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 200 #define   ICH_DI1L_SHIFT        4
 201 #define   ICH_SE                0x00000008      /* steer enable */
 202 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 203
 204 #define ICH_MAX_FRAGS           32              /* max hw frags */
 205
 206
 207 /*
 208  * registers for Ali5455
 209  */
 210
 211 /* ALi 5455 busmaster blocks */
 212 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 213 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 214 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 215 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 216 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 217 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 218 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 219 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 220 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 221 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 222 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 223
 224 enum {
 225         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 226         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 227         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 228         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 229         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 230         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 231         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 232         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 233         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 234         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 235         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 236         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 237         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 238         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 239         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 240         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 241         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 242         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 243         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 244         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 245         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 246 };
 247
 248 #define ALI_CAS_SEM_BUSY        0x80000000
 249 #define ALI_CPR_ADDR_SECONDARY  0x100
 250 #define ALI_CPR_ADDR_READ       0x80
 251 #define ALI_CSPSR_CODEC_READY   0x08
 252 #define ALI_CSPSR_READ_OK       0x02
 253 #define ALI_CSPSR_WRITE_OK      0x01
 254
 255 /* interrupts for the whole chip by interrupt status register finish */
 256
 257 #define ALI_INT_MICIN2          (1<<26)
 258 #define ALI_INT_PCMIN2          (1<<25)
 259 #define ALI_INT_I2SIN           (1<<24)
 260 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 261 #define ALI_INT_SPDIFIN         (1<<22)
 262 #define ALI_INT_LFEOUT          (1<<21)
 263 #define ALI_INT_CENTEROUT       (1<<20)
 264 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 265 #define ALI_INT_MICIN           (1<<18)
 266 #define ALI_INT_PCMOUT          (1<<17)
 267 #define ALI_INT_PCMIN           (1<<16)
 268 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 269 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 270 #define ALI_INT_GPIO            (1<<1)
 271 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
 272                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 273
 274 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 275 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 276 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 277 #define ICH_ALI_SC_IN_BITS      (3<<18)
 278 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 279 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 280 #define ICH_ALI_SC_PCM_4        (1<<8)
 281 #define ICH_ALI_SC_PCM_6        (2<<8)
 282 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 283
 284 #define ICH_ALI_SS_SEC_ID       (3<<5)
 285 #define ICH_ALI_SS_PRI_ID       (3<<3)
 286
 287 #define ICH_ALI_IF_AC97SP       (1<<21)
 288 #define ICH_ALI_IF_MC           (1<<20)
 289 #define ICH_ALI_IF_PI           (1<<19)
 290 #define ICH_ALI_IF_MC2          (1<<18)
 291 #define ICH_ALI_IF_PI2          (1<<17)
 292 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 293 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 294 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 295 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 296 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 297 #define ICH_ALI_IF_PO           (1<<1)
 298
 299 /*
 300  *
 301  */
 302
 303 enum {
 304         ICHD_PCMIN,
 305         ICHD_PCMOUT,
 306         ICHD_MIC,
 307         ICHD_MIC2,
 308         ICHD_PCM2IN,
 309         ICHD_SPBAR,
 310         ICHD_LAST = ICHD_SPBAR
 311 };
 312 enum {
 313         NVD_PCMIN,
 314         NVD_PCMOUT,
 315         NVD_MIC,
 316         NVD_SPBAR,
 317         NVD_LAST = NVD_SPBAR
 318 };
 319 enum {
 320         ALID_PCMIN,
 321         ALID_PCMOUT,
 322         ALID_MIC,
 323         ALID_AC97SPDIFOUT,
 324         ALID_SPDIFIN,
 325         ALID_SPDIFOUT,
 326         ALID_LAST = ALID_SPDIFOUT
 327 };
 328
 329 #define get_ichdev(substream) (substream->runtime->private_data)
 330
 331 struct ichdev {
 332         unsigned int ichd;                      /* ich device number */
 333         unsigned long reg_offset;               /* offset to bmaddr */
 334         __le32 *bdbar;                          /* CPU address (32bit) */
 335         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 336         struct snd_pcm_substream *substream;
 337         unsigned int physbuf;                   /* physical address (32bit) */
 338         unsigned int size;
 339         unsigned int fragsize;
 340         unsigned int fragsize1;
 341         unsigned int position;
 342         unsigned int pos_shift;
 343         unsigned int last_pos;
 344         int frags;
 345         int lvi;
 346         int lvi_frag;
 347         int civ;
 348         int ack;
 349         int ack_reload;
 350         unsigned int ack_bit;
 351         unsigned int roff_sr;
 352         unsigned int roff_picb;
 353         unsigned int int_sta_mask;              /* interrupt status mask */
 354         unsigned int ali_slot;                  /* ALI DMA slot */
 355         struct ac97_pcm *pcm;
 356         int pcm_open_flag;
 357         unsigned int suspended: 1;
 358 };
 359
 360 struct intel8x0 {
 361         unsigned int device_type;
 362
 363         int irq;
 364
 365         void __iomem *addr;
 366         void __iomem *bmaddr;
 367
 368         struct pci_dev *pci;
 369         struct snd_card *card;
 370
 371         int pcm_devs;
 372         struct snd_pcm *pcm[6];
 373         struct ichdev ichd[6];
 374
 375         unsigned multi4: 1,
 376                  multi6: 1,
 377                  multi8 :1,
 378                  dra: 1,
 379                  smp20bit: 1;
 380         unsigned in_ac97_init: 1,
 381                  in_sdin_init: 1;
 382         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 383         unsigned fix_nocache: 1;        /* workaround for 440MX */
 384         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 385         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 386         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
 387         unsigned inside_vm: 1;          /* enable VM optimization */
 388
 389         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 390         unsigned int sdm_saved; /* SDM reg value */
 391
 392         struct snd_ac97_bus *ac97_bus;
 393         struct snd_ac97 *ac97[3];
 394         unsigned int ac97_sdin[3];
 395         unsigned int max_codecs, ncodecs;
 396         const unsigned int *codec_bit;
 397         unsigned int codec_isr_bits;
 398         unsigned int codec_ready_bits;
 399
 400         spinlock_t reg_lock;
 401
 402         u32 bdbars_count;
 403         struct snd_dma_buffer bdbars;
 404         u32 int_sta_reg;                /* interrupt status register */
 405         u32 int_sta_mask;               /* interrupt status mask */
 406 };
 407
 408 static const struct pci_device_id snd_intel8x0_ids[] = {
 409         { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL },   /* 82801AA */
 410         { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL },   /* 82901AB */
 411         { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL },   /* 82801BA */
 412         { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL },   /* ICH3 */
 413         { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
 414         { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
 415         { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
 416         { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
 417         { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
 418         { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
 419         { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL },   /* 440MX */
 420         { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS },        /* SI7012 */
 421         { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
 422         { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
 423         { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
 424         { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
 425         { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
 426         { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
 427         { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
 428         { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
 429         { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL },     /* AMD8111 */
 430         { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL },     /* AMD768 */
 431         { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },   /* Ali5455 */
 432         { 0, }
 433 };
 434
 435 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 436
 437 /*
 438  *  Lowlevel I/O - busmaster
 439  */
 440
 441 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
 442 {
 443         return ioread8(chip->bmaddr + offset);
 444 }
 445
 446 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
 447 {
 448         return ioread16(chip->bmaddr + offset);
 449 }
 450
 451 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
 452 {
 453         return ioread32(chip->bmaddr + offset);
 454 }
 455
 456 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
 457 {
 458         iowrite8(val, chip->bmaddr + offset);
 459 }
 460
 461 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
 462 {
 463         iowrite16(val, chip->bmaddr + offset);
 464 }
 465
 466 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
 467 {
 468         iowrite32(val, chip->bmaddr + offset);
 469 }
 470
 471 /*
 472  *  Lowlevel I/O - AC'97 registers
 473  */
 474
 475 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
 476 {
 477         return ioread16(chip->addr + offset);
 478 }
 479
 480 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
 481 {
 482         iowrite16(val, chip->addr + offset);
 483 }
 484
 485 /*
 486  *  Basic I/O
 487  */
 488
 489 /*
 490  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 491  */
 492
 493 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
 494 {
 495         int time;
 496
 497         if (codec > 2)
 498                 return -EIO;
 499         if (chip->in_sdin_init) {
 500                 /* we don't know the ready bit assignment at the moment */
 501                 /* so we check any */
 502                 codec = chip->codec_isr_bits;
 503         } else {
 504                 codec = chip->codec_bit[chip->ac97_sdin[codec]];
 505         }
 506
 507         /* codec ready ? */
 508         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 509                 return -EIO;
 510
 511         if (chip->buggy_semaphore)
 512                 return 0; /* just ignore ... */
 513
 514         /* Anyone holding a semaphore for 1 msec should be shot... */
 515         time = 100;
 516         do {
 517                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 518                         return 0;
 519                 udelay(10);
 520         } while (time--);
 521
 522         /* access to some forbidden (non existent) ac97 registers will not
 523          * reset the semaphore. So even if you don't get the semaphore, still
 524          * continue the access. We don't need the semaphore anyway. */
 525         dev_err(chip->card->dev,
 526                 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 527                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 528         iagetword(chip, 0);     /* clear semaphore flag */
 529         /* I don't care about the semaphore */
 530         return -EBUSY;
 531 }
 532
 533 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
 534                                      unsigned short reg,
 535                                      unsigned short val)
 536 {
 537         struct intel8x0 *chip = ac97->private_data;
 538
 539         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 540                 if (! chip->in_ac97_init)
 541                         dev_err(chip->card->dev,
 542                                 "codec_write %d: semaphore is not ready for register 0x%x\n",
 543                                 ac97->num, reg);
 544         }
 545         iaputword(chip, reg + ac97->num * 0x80, val);
 546 }
 547
 548 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
 549                                               unsigned short reg)
 550 {
 551         struct intel8x0 *chip = ac97->private_data;
 552         unsigned short res;
 553         unsigned int tmp;
 554
 555         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 556                 if (! chip->in_ac97_init)
 557                         dev_err(chip->card->dev,
 558                                 "codec_read %d: semaphore is not ready for register 0x%x\n",
 559                                 ac97->num, reg);
 560                 res = 0xffff;
 561         } else {
 562                 res = iagetword(chip, reg + ac97->num * 0x80);
 563                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 564                         /* reset RCS and preserve other R/WC bits */
 565                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 566                                   ~(chip->codec_ready_bits | ICH_GSCI));
 567                         if (! chip->in_ac97_init)
 568                                 dev_err(chip->card->dev,
 569                                         "codec_read %d: read timeout for register 0x%x\n",
 570                                         ac97->num, reg);
 571                         res = 0xffff;
 572                 }
 573         }
 574         return res;
 575 }
 576
 577 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
 578                                          unsigned int codec)
 579 {
 580         unsigned int tmp;
 581
 582         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 583                 iagetword(chip, codec * 0x80);
 584                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 585                         /* reset RCS and preserve other R/WC bits */
 586                         iputdword(chip, ICHREG(GLOB_STA), tmp &
 587                                   ~(chip->codec_ready_bits | ICH_GSCI));
 588                 }
 589         }
 590 }
 591
 592 /*
 593  * access to AC97 for Ali5455
 594  */
 595 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
 596 {
 597         int count = 0;
 598         for (count = 0; count < 0x7f; count++) {
 599                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 600                 if (val & mask)
 601                         return 0;
 602         }
 603         if (! chip->in_ac97_init)
 604                 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
 605         return -EBUSY;
 606 }
 607
 608 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
 609 {
 610         int time = 100;
 611         if (chip->buggy_semaphore)
 612                 return 0; /* just ignore ... */
 613         while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 614                 udelay(1);
 615         if (! time && ! chip->in_ac97_init)
 616                 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
 617         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 618 }
 619
 620 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 621 {
 622         struct intel8x0 *chip = ac97->private_data;
 623         unsigned short data = 0xffff;
 624
 625         if (snd_intel8x0_ali_codec_semaphore(chip))
 626                 goto __err;
 627         reg |= ALI_CPR_ADDR_READ;
 628         if (ac97->num)
 629                 reg |= ALI_CPR_ADDR_SECONDARY;
 630         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 631         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 632                 goto __err;
 633         data = igetword(chip, ICHREG(ALI_SPR));
 634  __err:
 635         return data;
 636 }
 637
 638 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 639                                          unsigned short val)
 640 {
 641         struct intel8x0 *chip = ac97->private_data;
 642
 643         if (snd_intel8x0_ali_codec_semaphore(chip))
 644                 return;
 645         iputword(chip, ICHREG(ALI_CPR), val);
 646         if (ac97->num)
 647                 reg |= ALI_CPR_ADDR_SECONDARY;
 648         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 649         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 650 }
 651
 652
 653 /*
 654  * DMA I/O
 655  */
 656 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
 657 {
 658         int idx;
 659         __le32 *bdbar = ichdev->bdbar;
 660         unsigned long port = ichdev->reg_offset;
 661
 662         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 663         if (ichdev->size == ichdev->fragsize) {
 664                 ichdev->ack_reload = ichdev->ack = 2;
 665                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 666                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 667                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 668                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 669                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 670                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 671                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 672                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 673                 }
 674                 ichdev->frags = 2;
 675         } else {
 676                 ichdev->ack_reload = ichdev->ack = 1;
 677                 ichdev->fragsize1 = ichdev->fragsize;
 678                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 679                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
 680                                                      (((idx >> 1) * ichdev->fragsize) %
 681                                                       ichdev->size));
 682                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 683                                                      ichdev->fragsize >> ichdev->pos_shift);
 684 #if 0
 685                         dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
 686                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 687 #endif
 688                 }
 689                 ichdev->frags = ichdev->size / ichdev->fragsize;
 690         }
 691         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 692         ichdev->civ = 0;
 693         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 694         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 695         ichdev->position = 0;
 696 #if 0
 697         dev_dbg(chip->card->dev,
 698                 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 699                ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
 700                ichdev->fragsize1);
 701 #endif
 702         /* clear interrupts */
 703         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 704 }
 705
 706 /*
 707  *  Interrupt handler
 708  */
 709
 710 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
 711 {
 712         unsigned long port = ichdev->reg_offset;
 713         unsigned long flags;
 714         int status, civ, i, step;
 715         int ack = 0;
 716
 717         spin_lock_irqsave(&chip->reg_lock, flags);
 718         status = igetbyte(chip, port + ichdev->roff_sr);
 719         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 720         if (!(status & ICH_BCIS)) {
 721                 step = 0;
 722         } else if (civ == ichdev->civ) {
 723                 // snd_printd("civ same %d\n", civ);
 724                 step = 1;
 725                 ichdev->civ++;
 726                 ichdev->civ &= ICH_REG_LVI_MASK;
 727         } else {
 728                 step = civ - ichdev->civ;
 729                 if (step < 0)
 730                         step += ICH_REG_LVI_MASK + 1;
 731                 // if (step != 1)
 732                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 733                 ichdev->civ = civ;
 734         }
 735
 736         ichdev->position += step * ichdev->fragsize1;
 737         if (! chip->in_measurement)
 738                 ichdev->position %= ichdev->size;
 739         ichdev->lvi += step;
 740         ichdev->lvi &= ICH_REG_LVI_MASK;
 741         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 742         for (i = 0; i < step; i++) {
 743                 ichdev->lvi_frag++;
 744                 ichdev->lvi_frag %= ichdev->frags;
 745                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 746 #if 0
 747         dev_dbg(chip->card->dev,
 748                 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
 749                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
 750                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
 751                inl(port + 4), inb(port + ICH_REG_OFF_CR));
 752 #endif
 753                 if (--ichdev->ack == 0) {
 754                         ichdev->ack = ichdev->ack_reload;
 755                         ack = 1;
 756                 }
 757         }
 758         spin_unlock_irqrestore(&chip->reg_lock, flags);
 759         if (ack && ichdev->substream) {
 760                 snd_pcm_period_elapsed(ichdev->substream);
 761         }
 762         iputbyte(chip, port + ichdev->roff_sr,
 763                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 764 }
 765
 766 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
 767 {
 768         struct intel8x0 *chip = dev_id;
 769         struct ichdev *ichdev;
 770         unsigned int status;
 771         unsigned int i;
 772
 773         status = igetdword(chip, chip->int_sta_reg);
 774         if (status == 0xffffffff)       /* we are not yet resumed */
 775                 return IRQ_NONE;
 776
 777         if ((status & chip->int_sta_mask) == 0) {
 778                 if (status) {
 779                         /* ack */
 780                         iputdword(chip, chip->int_sta_reg, status);
 781                         if (! chip->buggy_irq)
 782                                 status = 0;
 783                 }
 784                 return IRQ_RETVAL(status);
 785         }
 786
 787         for (i = 0; i < chip->bdbars_count; i++) {
 788                 ichdev = &chip->ichd[i];
 789                 if (status & ichdev->int_sta_mask)
 790                         snd_intel8x0_update(chip, ichdev);
 791         }
 792
 793         /* ack them */
 794         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 795
 796         return IRQ_HANDLED;
 797 }
 798
 799 /*
 800  *  PCM part
 801  */
 802
 803 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 804 {
 805         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 806         struct ichdev *ichdev = get_ichdev(substream);
 807         unsigned char val = 0;
 808         unsigned long port = ichdev->reg_offset;
 809
 810         switch (cmd) {
 811         case SNDRV_PCM_TRIGGER_RESUME:
 812                 ichdev->suspended = 0;
 813                 fallthrough;
 814         case SNDRV_PCM_TRIGGER_START:
 815         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 816                 val = ICH_IOCE | ICH_STARTBM;
 817                 ichdev->last_pos = ichdev->position;
 818                 break;
 819         case SNDRV_PCM_TRIGGER_SUSPEND:
 820                 ichdev->suspended = 1;
 821                 fallthrough;
 822         case SNDRV_PCM_TRIGGER_STOP:
 823                 val = 0;
 824                 break;
 825         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 826                 val = ICH_IOCE;
 827                 break;
 828         default:
 829                 return -EINVAL;
 830         }
 831         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 832         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 833                 /* wait until DMA stopped */
 834                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 835                 /* reset whole DMA things */
 836                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 837         }
 838         return 0;
 839 }
 840
 841 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
 842 {
 843         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 844         struct ichdev *ichdev = get_ichdev(substream);
 845         unsigned long port = ichdev->reg_offset;
 846         static const int fiforeg[] = {
 847                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
 848         };
 849         unsigned int val, fifo;
 850
 851         val = igetdword(chip, ICHREG(ALI_DMACR));
 852         switch (cmd) {
 853         case SNDRV_PCM_TRIGGER_RESUME:
 854                 ichdev->suspended = 0;
 855                 fallthrough;
 856         case SNDRV_PCM_TRIGGER_START:
 857         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 858                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 859                         /* clear FIFO for synchronization of channels */
 860                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 861                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 862                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 863                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 864                 }
 865                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 866                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 867                 /* start DMA */
 868                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
 869                 break;
 870         case SNDRV_PCM_TRIGGER_SUSPEND:
 871                 ichdev->suspended = 1;
 872                 fallthrough;
 873         case SNDRV_PCM_TRIGGER_STOP:
 874         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 875                 /* pause */
 876                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
 877                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 878                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 879                         ;
 880                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 881                         break;
 882                 /* reset whole DMA things */
 883                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 884                 /* clear interrupts */
 885                 iputbyte(chip, port + ICH_REG_OFF_SR,
 886                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 887                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 888                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 889                 break;
 890         default:
 891                 return -EINVAL;
 892         }
 893         return 0;
 894 }
 895
 896 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
 897                                   struct snd_pcm_hw_params *hw_params)
 898 {
 899         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 900         struct ichdev *ichdev = get_ichdev(substream);
 901         int dbl = params_rate(hw_params) > 48000;
 902         int err;
 903
 904         if (ichdev->pcm_open_flag) {
 905                 snd_ac97_pcm_close(ichdev->pcm);
 906                 ichdev->pcm_open_flag = 0;
 907         }
 908         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 909                                 params_channels(hw_params),
 910                                 ichdev->pcm->r[dbl].slots);
 911         if (err >= 0) {
 912                 ichdev->pcm_open_flag = 1;
 913                 /* Force SPDIF setting */
 914                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 915                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
 916                                           params_rate(hw_params));
 917         }
 918         return err;
 919 }
 920
 921 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
 922 {
 923         struct ichdev *ichdev = get_ichdev(substream);
 924
 925         if (ichdev->pcm_open_flag) {
 926                 snd_ac97_pcm_close(ichdev->pcm);
 927                 ichdev->pcm_open_flag = 0;
 928         }
 929         return 0;
 930 }
 931
 932 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
 933                                        struct snd_pcm_runtime *runtime)
 934 {
 935         unsigned int cnt;
 936         int dbl = runtime->rate > 48000;
 937
 938         spin_lock_irq(&chip->reg_lock);
 939         switch (chip->device_type) {
 940         case DEVICE_ALI:
 941                 cnt = igetdword(chip, ICHREG(ALI_SCR));
 942                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
 943                 if (runtime->channels == 4 || dbl)
 944                         cnt |= ICH_ALI_SC_PCM_4;
 945                 else if (runtime->channels == 6)
 946                         cnt |= ICH_ALI_SC_PCM_6;
 947                 iputdword(chip, ICHREG(ALI_SCR), cnt);
 948                 break;
 949         case DEVICE_SIS:
 950                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 951                 cnt &= ~ICH_SIS_PCM_246_MASK;
 952                 if (runtime->channels == 4 || dbl)
 953                         cnt |= ICH_SIS_PCM_4;
 954                 else if (runtime->channels == 6)
 955                         cnt |= ICH_SIS_PCM_6;
 956                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 957                 break;
 958         default:
 959                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 960                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
 961                 if (runtime->channels == 4 || dbl)
 962                         cnt |= ICH_PCM_4;
 963                 else if (runtime->channels == 6)
 964                         cnt |= ICH_PCM_6;
 965                 else if (runtime->channels == 8)
 966                         cnt |= ICH_PCM_8;
 967                 if (chip->device_type == DEVICE_NFORCE) {
 968                         /* reset to 2ch once to keep the 6 channel data in alignment,
 969                          * to start from Front Left always
 970                          */
 971                         if (cnt & ICH_PCM_246_MASK) {
 972                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
 973                                 spin_unlock_irq(&chip->reg_lock);
 974                                 msleep(50); /* grrr... */
 975                                 spin_lock_irq(&chip->reg_lock);
 976                         }
 977                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
 978                         if (runtime->sample_bits > 16)
 979                                 cnt |= ICH_PCM_20BIT;
 980                 }
 981                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 982                 break;
 983         }
 984         spin_unlock_irq(&chip->reg_lock);
 985 }
 986
 987 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
 988 {
 989         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
 990         struct snd_pcm_runtime *runtime = substream->runtime;
 991         struct ichdev *ichdev = get_ichdev(substream);
 992
 993         ichdev->physbuf = runtime->dma_addr;
 994         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
 995         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
 996         if (ichdev->ichd == ICHD_PCMOUT) {
 997                 snd_intel8x0_setup_pcm_out(chip, runtime);
 998                 if (chip->device_type == DEVICE_INTEL_ICH4)
 999                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1000         }
1001         snd_intel8x0_setup_periods(chip, ichdev);
1002         return 0;
1003 }
1004
1005 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1006 {
1007         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1008         struct ichdev *ichdev = get_ichdev(substream);
1009         size_t ptr1, ptr;
1010         int civ, timeout = 10;
1011         unsigned int position;
1012
1013         spin_lock(&chip->reg_lock);
1014         do {
1015                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1016                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1017                 position = ichdev->position;
1018                 if (ptr1 == 0) {
1019                         udelay(10);
1020                         continue;
1021                 }
1022                 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
1023                         continue;
1024
1025                 /* IO read operation is very expensive inside virtual machine
1026                  * as it is emulated. The probability that subsequent PICB read
1027                  * will return different result is high enough to loop till
1028                  * timeout here.
1029                  * Same CIV is strict enough condition to be sure that PICB
1030                  * is valid inside VM on emulated card. */
1031                 if (chip->inside_vm)
1032                         break;
1033                 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1034                         break;
1035         } while (timeout--);
1036         ptr = ichdev->last_pos;
1037         if (ptr1 != 0) {
1038                 ptr1 <<= ichdev->pos_shift;
1039                 ptr = ichdev->fragsize1 - ptr1;
1040                 ptr += position;
1041                 if (ptr < ichdev->last_pos) {
1042                         unsigned int pos_base, last_base;
1043                         pos_base = position / ichdev->fragsize1;
1044                         last_base = ichdev->last_pos / ichdev->fragsize1;
1045                         /* another sanity check; ptr1 can go back to full
1046                          * before the base position is updated
1047                          */
1048                         if (pos_base == last_base)
1049                                 ptr = ichdev->last_pos;
1050                 }
1051         }
1052         ichdev->last_pos = ptr;
1053         spin_unlock(&chip->reg_lock);
1054         if (ptr >= ichdev->size)
1055                 return 0;
1056         return bytes_to_frames(substream->runtime, ptr);
1057 }
1058
1059 static const struct snd_pcm_hardware snd_intel8x0_stream =
1060 {
1061         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1062                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1063                                  SNDRV_PCM_INFO_MMAP_VALID |
1064                                  SNDRV_PCM_INFO_PAUSE |
1065                                  SNDRV_PCM_INFO_RESUME),
1066         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1067         .rates =                SNDRV_PCM_RATE_48000,
1068         .rate_min =             48000,
1069         .rate_max =             48000,
1070         .channels_min =         2,
1071         .channels_max =         2,
1072         .buffer_bytes_max =     128 * 1024,
1073         .period_bytes_min =     32,
1074         .period_bytes_max =     128 * 1024,
1075         .periods_min =          1,
1076         .periods_max =          1024,
1077         .fifo_size =            0,
1078 };
1079
1080 static const unsigned int channels4[] = {
1081         2, 4,
1082 };
1083
1084 static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1085         .count = ARRAY_SIZE(channels4),
1086         .list = channels4,
1087         .mask = 0,
1088 };
1089
1090 static const unsigned int channels6[] = {
1091         2, 4, 6,
1092 };
1093
1094 static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1095         .count = ARRAY_SIZE(channels6),
1096         .list = channels6,
1097         .mask = 0,
1098 };
1099
1100 static const unsigned int channels8[] = {
1101         2, 4, 6, 8,
1102 };
1103
1104 static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
1105         .count = ARRAY_SIZE(channels8),
1106         .list = channels8,
1107         .mask = 0,
1108 };
1109
1110 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1111 {
1112         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1113         struct snd_pcm_runtime *runtime = substream->runtime;
1114         int err;
1115
1116         ichdev->substream = substream;
1117         runtime->hw = snd_intel8x0_stream;
1118         runtime->hw.rates = ichdev->pcm->rates;
1119         snd_pcm_limit_hw_rates(runtime);
1120         if (chip->device_type == DEVICE_SIS) {
1121                 runtime->hw.buffer_bytes_max = 64*1024;
1122                 runtime->hw.period_bytes_max = 64*1024;
1123         }
1124         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1125                 return err;
1126         runtime->private_data = ichdev;
1127         return 0;
1128 }
1129
1130 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1131 {
1132         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1133         struct snd_pcm_runtime *runtime = substream->runtime;
1134         int err;
1135
1136         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1137         if (err < 0)
1138                 return err;
1139
1140         if (chip->multi8) {
1141                 runtime->hw.channels_max = 8;
1142                 snd_pcm_hw_constraint_list(runtime, 0,
1143                                                 SNDRV_PCM_HW_PARAM_CHANNELS,
1144                                                 &hw_constraints_channels8);
1145         } else if (chip->multi6) {
1146                 runtime->hw.channels_max = 6;
1147                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1148                                            &hw_constraints_channels6);
1149         } else if (chip->multi4) {
1150                 runtime->hw.channels_max = 4;
1151                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1152                                            &hw_constraints_channels4);
1153         }
1154         if (chip->dra) {
1155                 snd_ac97_pcm_double_rate_rules(runtime);
1156         }
1157         if (chip->smp20bit) {
1158                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1159                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1160         }
1161         return 0;
1162 }
1163
1164 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1165 {
1166         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1167
1168         chip->ichd[ICHD_PCMOUT].substream = NULL;
1169         return 0;
1170 }
1171
1172 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1173 {
1174         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1175
1176         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1177 }
1178
1179 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1180 {
1181         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1182
1183         chip->ichd[ICHD_PCMIN].substream = NULL;
1184         return 0;
1185 }
1186
1187 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1188 {
1189         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1190
1191         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1192 }
1193
1194 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1195 {
1196         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1197
1198         chip->ichd[ICHD_MIC].substream = NULL;
1199         return 0;
1200 }
1201
1202 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1203 {
1204         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1205
1206         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1207 }
1208
1209 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1210 {
1211         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1212
1213         chip->ichd[ICHD_MIC2].substream = NULL;
1214         return 0;
1215 }
1216
1217 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1218 {
1219         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1220
1221         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1222 }
1223
1224 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1225 {
1226         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1227
1228         chip->ichd[ICHD_PCM2IN].substream = NULL;
1229         return 0;
1230 }
1231
1232 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1233 {
1234         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1235         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1236
1237         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1238 }
1239
1240 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1241 {
1242         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1243         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1244
1245         chip->ichd[idx].substream = NULL;
1246         return 0;
1247 }
1248
1249 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1250 {
1251         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1252         unsigned int val;
1253
1254         spin_lock_irq(&chip->reg_lock);
1255         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1256         val |= ICH_ALI_IF_AC97SP;
1257         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1258         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1259         spin_unlock_irq(&chip->reg_lock);
1260
1261         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1262 }
1263
1264 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1265 {
1266         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1267         unsigned int val;
1268
1269         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1270         spin_lock_irq(&chip->reg_lock);
1271         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1272         val &= ~ICH_ALI_IF_AC97SP;
1273         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1274         spin_unlock_irq(&chip->reg_lock);
1275
1276         return 0;
1277 }
1278
1279 #if 0 // NYI
1280 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1281 {
1282         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1283
1284         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1285 }
1286
1287 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1288 {
1289         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1290
1291         chip->ichd[ALID_SPDIFIN].substream = NULL;
1292         return 0;
1293 }
1294
1295 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1296 {
1297         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1298
1299         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1300 }
1301
1302 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1303 {
1304         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1305
1306         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1307         return 0;
1308 }
1309 #endif
1310
1311 static const struct snd_pcm_ops snd_intel8x0_playback_ops = {
1312         .open =         snd_intel8x0_playback_open,
1313         .close =        snd_intel8x0_playback_close,
1314         .hw_params =    snd_intel8x0_hw_params,
1315         .hw_free =      snd_intel8x0_hw_free,
1316         .prepare =      snd_intel8x0_pcm_prepare,
1317         .trigger =      snd_intel8x0_pcm_trigger,
1318         .pointer =      snd_intel8x0_pcm_pointer,
1319 };
1320
1321 static const struct snd_pcm_ops snd_intel8x0_capture_ops = {
1322         .open =         snd_intel8x0_capture_open,
1323         .close =        snd_intel8x0_capture_close,
1324         .hw_params =    snd_intel8x0_hw_params,
1325         .hw_free =      snd_intel8x0_hw_free,
1326         .prepare =      snd_intel8x0_pcm_prepare,
1327         .trigger =      snd_intel8x0_pcm_trigger,
1328         .pointer =      snd_intel8x0_pcm_pointer,
1329 };
1330
1331 static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1332         .open =         snd_intel8x0_mic_open,
1333         .close =        snd_intel8x0_mic_close,
1334         .hw_params =    snd_intel8x0_hw_params,
1335         .hw_free =      snd_intel8x0_hw_free,
1336         .prepare =      snd_intel8x0_pcm_prepare,
1337         .trigger =      snd_intel8x0_pcm_trigger,
1338         .pointer =      snd_intel8x0_pcm_pointer,
1339 };
1340
1341 static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1342         .open =         snd_intel8x0_mic2_open,
1343         .close =        snd_intel8x0_mic2_close,
1344         .hw_params =    snd_intel8x0_hw_params,
1345         .hw_free =      snd_intel8x0_hw_free,
1346         .prepare =      snd_intel8x0_pcm_prepare,
1347         .trigger =      snd_intel8x0_pcm_trigger,
1348         .pointer =      snd_intel8x0_pcm_pointer,
1349 };
1350
1351 static const struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1352         .open =         snd_intel8x0_capture2_open,
1353         .close =        snd_intel8x0_capture2_close,
1354         .hw_params =    snd_intel8x0_hw_params,
1355         .hw_free =      snd_intel8x0_hw_free,
1356         .prepare =      snd_intel8x0_pcm_prepare,
1357         .trigger =      snd_intel8x0_pcm_trigger,
1358         .pointer =      snd_intel8x0_pcm_pointer,
1359 };
1360
1361 static const struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1362         .open =         snd_intel8x0_spdif_open,
1363         .close =        snd_intel8x0_spdif_close,
1364         .hw_params =    snd_intel8x0_hw_params,
1365         .hw_free =      snd_intel8x0_hw_free,
1366         .prepare =      snd_intel8x0_pcm_prepare,
1367         .trigger =      snd_intel8x0_pcm_trigger,
1368         .pointer =      snd_intel8x0_pcm_pointer,
1369 };
1370
1371 static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1372         .open =         snd_intel8x0_playback_open,
1373         .close =        snd_intel8x0_playback_close,
1374         .hw_params =    snd_intel8x0_hw_params,
1375         .hw_free =      snd_intel8x0_hw_free,
1376         .prepare =      snd_intel8x0_pcm_prepare,
1377         .trigger =      snd_intel8x0_ali_trigger,
1378         .pointer =      snd_intel8x0_pcm_pointer,
1379 };
1380
1381 static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1382         .open =         snd_intel8x0_capture_open,
1383         .close =        snd_intel8x0_capture_close,
1384         .hw_params =    snd_intel8x0_hw_params,
1385         .hw_free =      snd_intel8x0_hw_free,
1386         .prepare =      snd_intel8x0_pcm_prepare,
1387         .trigger =      snd_intel8x0_ali_trigger,
1388         .pointer =      snd_intel8x0_pcm_pointer,
1389 };
1390
1391 static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1392         .open =         snd_intel8x0_mic_open,
1393         .close =        snd_intel8x0_mic_close,
1394         .hw_params =    snd_intel8x0_hw_params,
1395         .hw_free =      snd_intel8x0_hw_free,
1396         .prepare =      snd_intel8x0_pcm_prepare,
1397         .trigger =      snd_intel8x0_ali_trigger,
1398         .pointer =      snd_intel8x0_pcm_pointer,
1399 };
1400
1401 static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1402         .open =         snd_intel8x0_ali_ac97spdifout_open,
1403         .close =        snd_intel8x0_ali_ac97spdifout_close,
1404         .hw_params =    snd_intel8x0_hw_params,
1405         .hw_free =      snd_intel8x0_hw_free,
1406         .prepare =      snd_intel8x0_pcm_prepare,
1407         .trigger =      snd_intel8x0_ali_trigger,
1408         .pointer =      snd_intel8x0_pcm_pointer,
1409 };
1410
1411 #if 0 // NYI
1412 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1413         .open =         snd_intel8x0_ali_spdifin_open,
1414         .close =        snd_intel8x0_ali_spdifin_close,
1415         .hw_params =    snd_intel8x0_hw_params,
1416         .hw_free =      snd_intel8x0_hw_free,
1417         .prepare =      snd_intel8x0_pcm_prepare,
1418         .trigger =      snd_intel8x0_pcm_trigger,
1419         .pointer =      snd_intel8x0_pcm_pointer,
1420 };
1421
1422 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1423         .open =         snd_intel8x0_ali_spdifout_open,
1424         .close =        snd_intel8x0_ali_spdifout_close,
1425         .hw_params =    snd_intel8x0_hw_params,
1426         .hw_free =      snd_intel8x0_hw_free,
1427         .prepare =      snd_intel8x0_pcm_prepare,
1428         .trigger =      snd_intel8x0_pcm_trigger,
1429         .pointer =      snd_intel8x0_pcm_pointer,
1430 };
1431 #endif // NYI
1432
1433 struct ich_pcm_table {
1434         char *suffix;
1435         const struct snd_pcm_ops *playback_ops;
1436         const struct snd_pcm_ops *capture_ops;
1437         size_t prealloc_size;
1438         size_t prealloc_max_size;
1439         int ac97_idx;
1440 };
1441
1442 #define intel8x0_dma_type(chip) \
1443         ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_UC : SNDRV_DMA_TYPE_DEV)
1444
1445 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1446                              const struct ich_pcm_table *rec)
1447 {
1448         struct snd_pcm *pcm;
1449         int err;
1450         char name[32];
1451
1452         if (rec->suffix)
1453                 sprintf(name, "Intel ICH - %s", rec->suffix);
1454         else
1455                 strcpy(name, "Intel ICH");
1456         err = snd_pcm_new(chip->card, name, device,
1457                           rec->playback_ops ? 1 : 0,
1458                           rec->capture_ops ? 1 : 0, &pcm);
1459         if (err < 0)
1460                 return err;
1461
1462         if (rec->playback_ops)
1463                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1464         if (rec->capture_ops)
1465                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1466
1467         pcm->private_data = chip;
1468         pcm->info_flags = 0;
1469         if (rec->suffix)
1470                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1471         else
1472                 strcpy(pcm->name, chip->card->shortname);
1473         chip->pcm[device] = pcm;
1474
1475         snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip),
1476                                        &chip->pci->dev,
1477                                        rec->prealloc_size, rec->prealloc_max_size);
1478
1479         if (rec->playback_ops &&
1480             rec->playback_ops->open == snd_intel8x0_playback_open) {
1481                 struct snd_pcm_chmap *chmap;
1482                 int chs = 2;
1483                 if (chip->multi8)
1484                         chs = 8;
1485                 else if (chip->multi6)
1486                         chs = 6;
1487                 else if (chip->multi4)
1488                         chs = 4;
1489                 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1490                                              snd_pcm_alt_chmaps, chs, 0,
1491                                              &chmap);
1492                 if (err < 0)
1493                         return err;
1494                 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1495                 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1496         }
1497
1498         return 0;
1499 }
1500
1501 static const struct ich_pcm_table intel_pcms[] = {
1502         {
1503                 .playback_ops = &snd_intel8x0_playback_ops,
1504                 .capture_ops = &snd_intel8x0_capture_ops,
1505                 .prealloc_size = 64 * 1024,
1506                 .prealloc_max_size = 128 * 1024,
1507         },
1508         {
1509                 .suffix = "MIC ADC",
1510                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1511                 .prealloc_size = 0,
1512                 .prealloc_max_size = 128 * 1024,
1513                 .ac97_idx = ICHD_MIC,
1514         },
1515         {
1516                 .suffix = "MIC2 ADC",
1517                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1518                 .prealloc_size = 0,
1519                 .prealloc_max_size = 128 * 1024,
1520                 .ac97_idx = ICHD_MIC2,
1521         },
1522         {
1523                 .suffix = "ADC2",
1524                 .capture_ops = &snd_intel8x0_capture2_ops,
1525                 .prealloc_size = 0,
1526                 .prealloc_max_size = 128 * 1024,
1527                 .ac97_idx = ICHD_PCM2IN,
1528         },
1529         {
1530                 .suffix = "IEC958",
1531                 .playback_ops = &snd_intel8x0_spdif_ops,
1532                 .prealloc_size = 64 * 1024,
1533                 .prealloc_max_size = 128 * 1024,
1534                 .ac97_idx = ICHD_SPBAR,
1535         },
1536 };
1537
1538 static const struct ich_pcm_table nforce_pcms[] = {
1539         {
1540                 .playback_ops = &snd_intel8x0_playback_ops,
1541                 .capture_ops = &snd_intel8x0_capture_ops,
1542                 .prealloc_size = 64 * 1024,
1543                 .prealloc_max_size = 128 * 1024,
1544         },
1545         {
1546                 .suffix = "MIC ADC",
1547                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1548                 .prealloc_size = 0,
1549                 .prealloc_max_size = 128 * 1024,
1550                 .ac97_idx = NVD_MIC,
1551         },
1552         {
1553                 .suffix = "IEC958",
1554                 .playback_ops = &snd_intel8x0_spdif_ops,
1555                 .prealloc_size = 64 * 1024,
1556                 .prealloc_max_size = 128 * 1024,
1557                 .ac97_idx = NVD_SPBAR,
1558         },
1559 };
1560
1561 static const struct ich_pcm_table ali_pcms[] = {
1562         {
1563                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1564                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1565                 .prealloc_size = 64 * 1024,
1566                 .prealloc_max_size = 128 * 1024,
1567         },
1568         {
1569                 .suffix = "MIC ADC",
1570                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1571                 .prealloc_size = 0,
1572                 .prealloc_max_size = 128 * 1024,
1573                 .ac97_idx = ALID_MIC,
1574         },
1575         {
1576                 .suffix = "IEC958",
1577                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1578                 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1579                 .prealloc_size = 64 * 1024,
1580                 .prealloc_max_size = 128 * 1024,
1581                 .ac97_idx = ALID_AC97SPDIFOUT,
1582         },
1583 #if 0 // NYI
1584         {
1585                 .suffix = "HW IEC958",
1586                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1587                 .prealloc_size = 64 * 1024,
1588                 .prealloc_max_size = 128 * 1024,
1589         },
1590 #endif
1591 };
1592
1593 static int snd_intel8x0_pcm(struct intel8x0 *chip)
1594 {
1595         int i, tblsize, device, err;
1596         const struct ich_pcm_table *tbl, *rec;
1597
1598         switch (chip->device_type) {
1599         case DEVICE_INTEL_ICH4:
1600                 tbl = intel_pcms;
1601                 tblsize = ARRAY_SIZE(intel_pcms);
1602                 if (spdif_aclink)
1603                         tblsize--;
1604                 break;
1605         case DEVICE_NFORCE:
1606                 tbl = nforce_pcms;
1607                 tblsize = ARRAY_SIZE(nforce_pcms);
1608                 if (spdif_aclink)
1609                         tblsize--;
1610                 break;
1611         case DEVICE_ALI:
1612                 tbl = ali_pcms;
1613                 tblsize = ARRAY_SIZE(ali_pcms);
1614                 break;
1615         default:
1616                 tbl = intel_pcms;
1617                 tblsize = 2;
1618                 break;
1619         }
1620
1621         device = 0;
1622         for (i = 0; i < tblsize; i++) {
1623                 rec = tbl + i;
1624                 if (i > 0 && rec->ac97_idx) {
1625                         /* activate PCM only when associated AC'97 codec */
1626                         if (! chip->ichd[rec->ac97_idx].pcm)
1627                                 continue;
1628                 }
1629                 err = snd_intel8x0_pcm1(chip, device, rec);
1630                 if (err < 0)
1631                         return err;
1632                 device++;
1633         }
1634
1635         chip->pcm_devs = device;
1636         return 0;
1637 }
1638
1639
1640 /*
1641  *  Mixer part
1642  */
1643
1644 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1645 {
1646         struct intel8x0 *chip = bus->private_data;
1647         chip->ac97_bus = NULL;
1648 }
1649
1650 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1651 {
1652         struct intel8x0 *chip = ac97->private_data;
1653         chip->ac97[ac97->num] = NULL;
1654 }
1655
1656 static const struct ac97_pcm ac97_pcm_defs[] = {
1657         /* front PCM */
1658         {
1659                 .exclusive = 1,
1660                 .r = {  {
1661                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1662                                          (1 << AC97_SLOT_PCM_RIGHT) |
1663                                          (1 << AC97_SLOT_PCM_CENTER) |
1664                                          (1 << AC97_SLOT_PCM_SLEFT) |
1665                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1666                                          (1 << AC97_SLOT_LFE)
1667                         },
1668                         {
1669                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1670                                          (1 << AC97_SLOT_PCM_RIGHT) |
1671                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1672                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1673                         }
1674                 }
1675         },
1676         /* PCM IN #1 */
1677         {
1678                 .stream = 1,
1679                 .exclusive = 1,
1680                 .r = {  {
1681                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1682                                          (1 << AC97_SLOT_PCM_RIGHT)
1683                         }
1684                 }
1685         },
1686         /* MIC IN #1 */
1687         {
1688                 .stream = 1,
1689                 .exclusive = 1,
1690                 .r = {  {
1691                                 .slots = (1 << AC97_SLOT_MIC)
1692                         }
1693                 }
1694         },
1695         /* S/PDIF PCM */
1696         {
1697                 .exclusive = 1,
1698                 .spdif = 1,
1699                 .r = {  {
1700                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1701                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1702                         }
1703                 }
1704         },
1705         /* PCM IN #2 */
1706         {
1707                 .stream = 1,
1708                 .exclusive = 1,
1709                 .r = {  {
1710                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1711                                          (1 << AC97_SLOT_PCM_RIGHT)
1712                         }
1713                 }
1714         },
1715         /* MIC IN #2 */
1716         {
1717                 .stream = 1,
1718                 .exclusive = 1,
1719                 .r = {  {
1720                                 .slots = (1 << AC97_SLOT_MIC)
1721                         }
1722                 }
1723         },
1724 };
1725
1726 static const struct ac97_quirk ac97_quirks[] = {
1727         {
1728                 .subvendor = 0x0e11,
1729                 .subdevice = 0x000e,
1730                 .name = "Compaq Deskpro EN",    /* AD1885 */
1731                 .type = AC97_TUNE_HP_ONLY
1732         },
1733         {
1734                 .subvendor = 0x0e11,
1735                 .subdevice = 0x008a,
1736                 .name = "Compaq Evo W4000",     /* AD1885 */
1737                 .type = AC97_TUNE_HP_ONLY
1738         },
1739         {
1740                 .subvendor = 0x0e11,
1741                 .subdevice = 0x00b8,
1742                 .name = "Compaq Evo D510C",
1743                 .type = AC97_TUNE_HP_ONLY
1744         },
1745         {
1746                 .subvendor = 0x0e11,
1747                 .subdevice = 0x0860,
1748                 .name = "HP/Compaq nx7010",
1749                 .type = AC97_TUNE_MUTE_LED
1750         },
1751         {
1752                 .subvendor = 0x1014,
1753                 .subdevice = 0x0534,
1754                 .name = "ThinkPad X31",
1755                 .type = AC97_TUNE_INV_EAPD
1756         },
1757         {
1758                 .subvendor = 0x1014,
1759                 .subdevice = 0x1f00,
1760                 .name = "MS-9128",
1761                 .type = AC97_TUNE_ALC_JACK
1762         },
1763         {
1764                 .subvendor = 0x1014,
1765                 .subdevice = 0x0267,
1766                 .name = "IBM NetVista A30p",    /* AD1981B */
1767                 .type = AC97_TUNE_HP_ONLY
1768         },
1769         {
1770                 .subvendor = 0x1025,
1771                 .subdevice = 0x0082,
1772                 .name = "Acer Travelmate 2310",
1773                 .type = AC97_TUNE_HP_ONLY
1774         },
1775         {
1776                 .subvendor = 0x1025,
1777                 .subdevice = 0x0083,
1778                 .name = "Acer Aspire 3003LCi",
1779                 .type = AC97_TUNE_HP_ONLY
1780         },
1781         {
1782                 .subvendor = 0x1028,
1783                 .subdevice = 0x00d8,
1784                 .name = "Dell Precision 530",   /* AD1885 */
1785                 .type = AC97_TUNE_HP_ONLY
1786         },
1787         {
1788                 .subvendor = 0x1028,
1789                 .subdevice = 0x010d,
1790                 .name = "Dell", /* which model?  AD1885 */
1791                 .type = AC97_TUNE_HP_ONLY
1792         },
1793         {
1794                 .subvendor = 0x1028,
1795                 .subdevice = 0x0126,
1796                 .name = "Dell Optiplex GX260",  /* AD1981A */
1797                 .type = AC97_TUNE_HP_ONLY
1798         },
1799         {
1800                 .subvendor = 0x1028,
1801                 .subdevice = 0x012c,
1802                 .name = "Dell Precision 650",   /* AD1981A */
1803                 .type = AC97_TUNE_HP_ONLY
1804         },
1805         {
1806                 .subvendor = 0x1028,
1807                 .subdevice = 0x012d,
1808                 .name = "Dell Precision 450",   /* AD1981B*/
1809                 .type = AC97_TUNE_HP_ONLY
1810         },
1811         {
1812                 .subvendor = 0x1028,
1813                 .subdevice = 0x0147,
1814                 .name = "Dell", /* which model?  AD1981B*/
1815                 .type = AC97_TUNE_HP_ONLY
1816         },
1817         {
1818                 .subvendor = 0x1028,
1819                 .subdevice = 0x0151,
1820                 .name = "Dell Optiplex GX270",  /* AD1981B */
1821                 .type = AC97_TUNE_HP_ONLY
1822         },
1823         {
1824                 .subvendor = 0x1028,
1825                 .subdevice = 0x014e,
1826                 .name = "Dell D800", /* STAC9750/51 */
1827                 .type = AC97_TUNE_HP_ONLY
1828         },
1829         {
1830                 .subvendor = 0x1028,
1831                 .subdevice = 0x0163,
1832                 .name = "Dell Unknown", /* STAC9750/51 */
1833                 .type = AC97_TUNE_HP_ONLY
1834         },
1835         {
1836                 .subvendor = 0x1028,
1837                 .subdevice = 0x016a,
1838                 .name = "Dell Inspiron 8600",   /* STAC9750/51 */
1839                 .type = AC97_TUNE_HP_ONLY
1840         },
1841         {
1842                 .subvendor = 0x1028,
1843                 .subdevice = 0x0182,
1844                 .name = "Dell Latitude D610",   /* STAC9750/51 */
1845                 .type = AC97_TUNE_HP_ONLY
1846         },
1847         {
1848                 .subvendor = 0x1028,
1849                 .subdevice = 0x0186,
1850                 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1851                 .type = AC97_TUNE_HP_MUTE_LED
1852         },
1853         {
1854                 .subvendor = 0x1028,
1855                 .subdevice = 0x0188,
1856                 .name = "Dell Inspiron 6000",
1857                 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1858         },
1859         {
1860                 .subvendor = 0x1028,
1861                 .subdevice = 0x0189,
1862                 .name = "Dell Inspiron 9300",
1863                 .type = AC97_TUNE_HP_MUTE_LED
1864         },
1865         {
1866                 .subvendor = 0x1028,
1867                 .subdevice = 0x0191,
1868                 .name = "Dell Inspiron 8600",
1869                 .type = AC97_TUNE_HP_ONLY
1870         },
1871         {
1872                 .subvendor = 0x103c,
1873                 .subdevice = 0x006d,
1874                 .name = "HP zv5000",
1875                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1876         },
1877         {       /* FIXME: which codec? */
1878                 .subvendor = 0x103c,
1879                 .subdevice = 0x00c3,
1880                 .name = "HP xw6000",
1881                 .type = AC97_TUNE_HP_ONLY
1882         },
1883         {
1884                 .subvendor = 0x103c,
1885                 .subdevice = 0x088c,
1886                 .name = "HP nc8000",
1887                 .type = AC97_TUNE_HP_MUTE_LED
1888         },
1889         {
1890                 .subvendor = 0x103c,
1891                 .subdevice = 0x0890,
1892                 .name = "HP nc6000",
1893                 .type = AC97_TUNE_MUTE_LED
1894         },
1895         {
1896                 .subvendor = 0x103c,
1897                 .subdevice = 0x129d,
1898                 .name = "HP xw8000",
1899                 .type = AC97_TUNE_HP_ONLY
1900         },
1901         {
1902                 .subvendor = 0x103c,
1903                 .subdevice = 0x0938,
1904                 .name = "HP nc4200",
1905                 .type = AC97_TUNE_HP_MUTE_LED
1906         },
1907         {
1908                 .subvendor = 0x103c,
1909                 .subdevice = 0x099c,
1910                 .name = "HP nx6110/nc6120",
1911                 .type = AC97_TUNE_HP_MUTE_LED
1912         },
1913         {
1914                 .subvendor = 0x103c,
1915                 .subdevice = 0x0944,
1916                 .name = "HP nc6220",
1917                 .type = AC97_TUNE_HP_MUTE_LED
1918         },
1919         {
1920                 .subvendor = 0x103c,
1921                 .subdevice = 0x0934,
1922                 .name = "HP nc8220",
1923                 .type = AC97_TUNE_HP_MUTE_LED
1924         },
1925         {
1926                 .subvendor = 0x103c,
1927                 .subdevice = 0x12f1,
1928                 .name = "HP xw8200",    /* AD1981B*/
1929                 .type = AC97_TUNE_HP_ONLY
1930         },
1931         {
1932                 .subvendor = 0x103c,
1933                 .subdevice = 0x12f2,
1934                 .name = "HP xw6200",
1935                 .type = AC97_TUNE_HP_ONLY
1936         },
1937         {
1938                 .subvendor = 0x103c,
1939                 .subdevice = 0x3008,
1940                 .name = "HP xw4200",    /* AD1981B*/
1941                 .type = AC97_TUNE_HP_ONLY
1942         },
1943         {
1944                 .subvendor = 0x104d,
1945                 .subdevice = 0x8144,
1946                 .name = "Sony",
1947                 .type = AC97_TUNE_INV_EAPD
1948         },
1949         {
1950                 .subvendor = 0x104d,
1951                 .subdevice = 0x8197,
1952                 .name = "Sony S1XP",
1953                 .type = AC97_TUNE_INV_EAPD
1954         },
1955         {
1956                 .subvendor = 0x104d,
1957                 .subdevice = 0x81c0,
1958                 .name = "Sony VAIO VGN-T350P", /*AD1981B*/
1959                 .type = AC97_TUNE_INV_EAPD
1960         },
1961         {
1962                 .subvendor = 0x104d,
1963                 .subdevice = 0x81c5,
1964                 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
1965                 .type = AC97_TUNE_INV_EAPD
1966         },
1967         {
1968                 .subvendor = 0x1043,
1969                 .subdevice = 0x80f3,
1970                 .name = "ASUS ICH5/AD1985",
1971                 .type = AC97_TUNE_AD_SHARING
1972         },
1973         {
1974                 .subvendor = 0x10cf,
1975                 .subdevice = 0x11c3,
1976                 .name = "Fujitsu-Siemens E4010",
1977                 .type = AC97_TUNE_HP_ONLY
1978         },
1979         {
1980                 .subvendor = 0x10cf,
1981                 .subdevice = 0x1225,
1982                 .name = "Fujitsu-Siemens T3010",
1983                 .type = AC97_TUNE_HP_ONLY
1984         },
1985         {
1986                 .subvendor = 0x10cf,
1987                 .subdevice = 0x1253,
1988                 .name = "Fujitsu S6210",        /* STAC9750/51 */
1989                 .type = AC97_TUNE_HP_ONLY
1990         },
1991         {
1992                 .subvendor = 0x10cf,
1993                 .subdevice = 0x127d,
1994                 .name = "Fujitsu Lifebook P7010",
1995                 .type = AC97_TUNE_HP_ONLY
1996         },
1997         {
1998                 .subvendor = 0x10cf,
1999                 .subdevice = 0x127e,
2000                 .name = "Fujitsu Lifebook C1211D",
2001                 .type = AC97_TUNE_HP_ONLY
2002         },
2003         {
2004                 .subvendor = 0x10cf,
2005                 .subdevice = 0x12ec,
2006                 .name = "Fujitsu-Siemens 4010",
2007                 .type = AC97_TUNE_HP_ONLY
2008         },
2009         {
2010                 .subvendor = 0x10cf,
2011                 .subdevice = 0x12f2,
2012                 .name = "Fujitsu-Siemens Celsius H320",
2013                 .type = AC97_TUNE_SWAP_HP
2014         },
2015         {
2016                 .subvendor = 0x10f1,
2017                 .subdevice = 0x2665,
2018                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
2019                 .type = AC97_TUNE_HP_ONLY
2020         },
2021         {
2022                 .subvendor = 0x10f1,
2023                 .subdevice = 0x2885,
2024                 .name = "AMD64 Mobo",   /* ALC650 */
2025                 .type = AC97_TUNE_HP_ONLY
2026         },
2027         {
2028                 .subvendor = 0x10f1,
2029                 .subdevice = 0x2895,
2030                 .name = "Tyan Thunder K8WE",
2031                 .type = AC97_TUNE_HP_ONLY
2032         },
2033         {
2034                 .subvendor = 0x10f7,
2035                 .subdevice = 0x834c,
2036                 .name = "Panasonic CF-R4",
2037                 .type = AC97_TUNE_HP_ONLY,
2038         },
2039         {
2040                 .subvendor = 0x110a,
2041                 .subdevice = 0x0056,
2042                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
2043                 .type = AC97_TUNE_HP_ONLY
2044         },
2045         {
2046                 .subvendor = 0x11d4,
2047                 .subdevice = 0x5375,
2048                 .name = "ADI AD1985 (discrete)",
2049                 .type = AC97_TUNE_HP_ONLY
2050         },
2051         {
2052                 .subvendor = 0x1462,
2053                 .subdevice = 0x5470,
2054                 .name = "MSI P4 ATX 645 Ultra",
2055                 .type = AC97_TUNE_HP_ONLY
2056         },
2057         {
2058                 .subvendor = 0x161f,
2059                 .subdevice = 0x202f,
2060                 .name = "Gateway M520",
2061                 .type = AC97_TUNE_INV_EAPD
2062         },
2063         {
2064                 .subvendor = 0x161f,
2065                 .subdevice = 0x203a,
2066                 .name = "Gateway 4525GZ",               /* AD1981B */
2067                 .type = AC97_TUNE_INV_EAPD
2068         },
2069         {
2070                 .subvendor = 0x1734,
2071                 .subdevice = 0x0088,
2072                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
2073                 .type = AC97_TUNE_HP_ONLY
2074         },
2075         {
2076                 .subvendor = 0x8086,
2077                 .subdevice = 0x2000,
2078                 .mask = 0xfff0,
2079                 .name = "Intel ICH5/AD1985",
2080                 .type = AC97_TUNE_AD_SHARING
2081         },
2082         {
2083                 .subvendor = 0x8086,
2084                 .subdevice = 0x4000,
2085                 .mask = 0xfff0,
2086                 .name = "Intel ICH5/AD1985",
2087                 .type = AC97_TUNE_AD_SHARING
2088         },
2089         {
2090                 .subvendor = 0x8086,
2091                 .subdevice = 0x4856,
2092                 .name = "Intel D845WN (82801BA)",
2093                 .type = AC97_TUNE_SWAP_HP
2094         },
2095         {
2096                 .subvendor = 0x8086,
2097                 .subdevice = 0x4d44,
2098                 .name = "Intel D850EMV2",       /* AD1885 */
2099                 .type = AC97_TUNE_HP_ONLY
2100         },
2101         {
2102                 .subvendor = 0x8086,
2103                 .subdevice = 0x4d56,
2104                 .name = "Intel ICH/AD1885",
2105                 .type = AC97_TUNE_HP_ONLY
2106         },
2107         {
2108                 .subvendor = 0x8086,
2109                 .subdevice = 0x6000,
2110                 .mask = 0xfff0,
2111                 .name = "Intel ICH5/AD1985",
2112                 .type = AC97_TUNE_AD_SHARING
2113         },
2114         {
2115                 .subvendor = 0x8086,
2116                 .subdevice = 0xe000,
2117                 .mask = 0xfff0,
2118                 .name = "Intel ICH5/AD1985",
2119                 .type = AC97_TUNE_AD_SHARING
2120         },
2121 #if 0 /* FIXME: this seems wrong on most boards */
2122         {
2123                 .subvendor = 0x8086,
2124                 .subdevice = 0xa000,
2125                 .mask = 0xfff0,
2126                 .name = "Intel ICH5/AD1985",
2127                 .type = AC97_TUNE_HP_ONLY
2128         },
2129 #endif
2130         { } /* terminator */
2131 };
2132
2133 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2134                               const char *quirk_override)
2135 {
2136         struct snd_ac97_bus *pbus;
2137         struct snd_ac97_template ac97;
2138         int err;
2139         unsigned int i, codecs;
2140         unsigned int glob_sta = 0;
2141         const struct snd_ac97_bus_ops *ops;
2142         static const struct snd_ac97_bus_ops standard_bus_ops = {
2143                 .write = snd_intel8x0_codec_write,
2144                 .read = snd_intel8x0_codec_read,
2145         };
2146         static const struct snd_ac97_bus_ops ali_bus_ops = {
2147                 .write = snd_intel8x0_ali_codec_write,
2148                 .read = snd_intel8x0_ali_codec_read,
2149         };
2150
2151         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2152         if (!spdif_aclink) {
2153                 switch (chip->device_type) {
2154                 case DEVICE_NFORCE:
2155                         chip->spdif_idx = NVD_SPBAR;
2156                         break;
2157                 case DEVICE_ALI:
2158                         chip->spdif_idx = ALID_AC97SPDIFOUT;
2159                         break;
2160                 case DEVICE_INTEL_ICH4:
2161                         chip->spdif_idx = ICHD_SPBAR;
2162                         break;
2163                 }
2164         }
2165
2166         chip->in_ac97_init = 1;
2167
2168         memset(&ac97, 0, sizeof(ac97));
2169         ac97.private_data = chip;
2170         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2171         ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2172         if (chip->xbox)
2173                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2174         if (chip->device_type != DEVICE_ALI) {
2175                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2176                 ops = &standard_bus_ops;
2177                 chip->in_sdin_init = 1;
2178                 codecs = 0;
2179                 for (i = 0; i < chip->max_codecs; i++) {
2180                         if (! (glob_sta & chip->codec_bit[i]))
2181                                 continue;
2182                         if (chip->device_type == DEVICE_INTEL_ICH4) {
2183                                 snd_intel8x0_codec_read_test(chip, codecs);
2184                                 chip->ac97_sdin[codecs] =
2185                                         igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2186                                 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
2187                                         chip->ac97_sdin[codecs] = 0;
2188                         } else
2189                                 chip->ac97_sdin[codecs] = i;
2190                         codecs++;
2191                 }
2192                 chip->in_sdin_init = 0;
2193                 if (! codecs)
2194                         codecs = 1;
2195         } else {
2196                 ops = &ali_bus_ops;
2197                 codecs = 1;
2198                 /* detect the secondary codec */
2199                 for (i = 0; i < 100; i++) {
2200                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2201                         if (reg & 0x40) {
2202                                 codecs = 2;
2203                                 break;
2204                         }
2205                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2206                         udelay(1);
2207                 }
2208         }
2209         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2210                 goto __err;
2211         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2212         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2213                 pbus->clock = ac97_clock;
2214         /* FIXME: my test board doesn't work well with VRA... */
2215         if (chip->device_type == DEVICE_ALI)
2216                 pbus->no_vra = 1;
2217         else
2218                 pbus->dra = 1;
2219         chip->ac97_bus = pbus;
2220         chip->ncodecs = codecs;
2221
2222         ac97.pci = chip->pci;
2223         for (i = 0; i < codecs; i++) {
2224                 ac97.num = i;
2225                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2226                         if (err != -EACCES)
2227                                 dev_err(chip->card->dev,
2228                                         "Unable to initialize codec #%d\n", i);
2229                         if (i == 0)
2230                                 goto __err;
2231                 }
2232         }
2233         /* tune up the primary codec */
2234         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2235         /* enable separate SDINs for ICH4 */
2236         if (chip->device_type == DEVICE_INTEL_ICH4)
2237                 pbus->isdin = 1;
2238         /* find the available PCM streams */
2239         i = ARRAY_SIZE(ac97_pcm_defs);
2240         if (chip->device_type != DEVICE_INTEL_ICH4)
2241                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2242         if (chip->spdif_idx < 0)
2243                 i--;            /* do not allocate S/PDIF */
2244         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2245         if (err < 0)
2246                 goto __err;
2247         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2248         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2249         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2250         if (chip->spdif_idx >= 0)
2251                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2252         if (chip->device_type == DEVICE_INTEL_ICH4) {
2253                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2254                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2255         }
2256         /* enable separate SDINs for ICH4 */
2257         if (chip->device_type == DEVICE_INTEL_ICH4) {
2258                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2259                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2260                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2261                 if (pcm) {
2262                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2263                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2264                         for (i = 1; i < 4; i++) {
2265                                 if (pcm->r[0].codec[i]) {
2266                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2267                                         break;
2268                                 }
2269                         }
2270                 } else {
2271                         tmp &= ~ICH_SE; /* steer disable */
2272                 }
2273                 iputbyte(chip, ICHREG(SDM), tmp);
2274         }
2275         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2276                 chip->multi4 = 1;
2277                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
2278                         chip->multi6 = 1;
2279                         if (chip->ac97[0]->flags & AC97_HAS_8CH)
2280                                 chip->multi8 = 1;
2281                 }
2282         }
2283         if (pbus->pcms[0].r[1].rslots[0]) {
2284                 chip->dra = 1;
2285         }
2286         if (chip->device_type == DEVICE_INTEL_ICH4) {
2287                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2288                         chip->smp20bit = 1;
2289         }
2290         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2291                 /* 48kHz only */
2292                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2293         }
2294         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2295                 /* use slot 10/11 for SPDIF */
2296                 u32 val;
2297                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2298                 val |= ICH_PCM_SPDIF_1011;
2299                 iputdword(chip, ICHREG(GLOB_CNT), val);
2300                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2301         }
2302         chip->in_ac97_init = 0;
2303         return 0;
2304
2305  __err:
2306         /* clear the cold-reset bit for the next chance */
2307         if (chip->device_type != DEVICE_ALI)
2308                 iputdword(chip, ICHREG(GLOB_CNT),
2309                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2310         return err;
2311 }
2312
2313
2314 /*
2315  *
2316  */
2317
2318 static void do_ali_reset(struct intel8x0 *chip)
2319 {
2320         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2321         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2322         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2323         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2324         iputdword(chip, ICHREG(ALI_INTERFACECR),
2325                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2326         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2327         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2328 }
2329
2330 #ifdef CONFIG_SND_AC97_POWER_SAVE
2331 static const struct snd_pci_quirk ich_chip_reset_mode[] = {
2332         SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
2333         { } /* end */
2334 };
2335
2336 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
2337 {
2338         unsigned int cnt;
2339         /* ACLink on, 2 channels */
2340
2341         if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2342                 return -EIO;
2343
2344         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2345         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2346
2347         /* do cold reset - the full ac97 powerdown may leave the controller
2348          * in a warm state but actually it cannot communicate with the codec.
2349          */
2350         iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2351         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2352         udelay(10);
2353         iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2354         msleep(1);
2355         return 0;
2356 }
2357 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
2358         (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2359 #else
2360 #define snd_intel8x0_ich_chip_cold_reset(chip)  0
2361 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
2362 #endif
2363
2364 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
2365 {
2366         unsigned long end_time;
2367         unsigned int cnt;
2368         /* ACLink on, 2 channels */
2369         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2370         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2371         /* finish cold or do warm reset */
2372         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2373         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2374         end_time = (jiffies + (HZ / 4)) + 1;
2375         do {
2376                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2377                         return 0;
2378                 schedule_timeout_uninterruptible(1);
2379         } while (time_after_eq(end_time, jiffies));
2380         dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
2381                    igetdword(chip, ICHREG(GLOB_CNT)));
2382         return -EIO;
2383 }
2384
2385 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2386 {
2387         unsigned long end_time;
2388         unsigned int status, nstatus;
2389         unsigned int cnt;
2390         int err;
2391
2392         /* put logic to right state */
2393         /* first clear status bits */
2394         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2395         if (chip->device_type == DEVICE_NFORCE)
2396                 status |= ICH_NVSPINT;
2397         cnt = igetdword(chip, ICHREG(GLOB_STA));
2398         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2399
2400         if (snd_intel8x0_ich_chip_can_cold_reset(chip))
2401                 err = snd_intel8x0_ich_chip_cold_reset(chip);
2402         else
2403                 err = snd_intel8x0_ich_chip_reset(chip);
2404         if (err < 0)
2405                 return err;
2406
2407         if (probing) {
2408                 /* wait for any codec ready status.
2409                  * Once it becomes ready it should remain ready
2410                  * as long as we do not disable the ac97 link.
2411                  */
2412                 end_time = jiffies + HZ;
2413                 do {
2414                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2415                                 chip->codec_isr_bits;
2416                         if (status)
2417                                 break;
2418                         schedule_timeout_uninterruptible(1);
2419                 } while (time_after_eq(end_time, jiffies));
2420                 if (! status) {
2421                         /* no codec is found */
2422                         dev_err(chip->card->dev,
2423                                 "codec_ready: codec is not ready [0x%x]\n",
2424                                    igetdword(chip, ICHREG(GLOB_STA)));
2425                         return -EIO;
2426                 }
2427
2428                 /* wait for other codecs ready status. */
2429                 end_time = jiffies + HZ / 4;
2430                 while (status != chip->codec_isr_bits &&
2431                        time_after_eq(end_time, jiffies)) {
2432                         schedule_timeout_uninterruptible(1);
2433                         status |= igetdword(chip, ICHREG(GLOB_STA)) &
2434                                 chip->codec_isr_bits;
2435                 }
2436
2437         } else {
2438                 /* resume phase */
2439                 int i;
2440                 status = 0;
2441                 for (i = 0; i < chip->ncodecs; i++)
2442                         if (chip->ac97[i])
2443                                 status |= chip->codec_bit[chip->ac97_sdin[i]];
2444                 /* wait until all the probed codecs are ready */
2445                 end_time = jiffies + HZ;
2446                 do {
2447                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2448                                 chip->codec_isr_bits;
2449                         if (status == nstatus)
2450                                 break;
2451                         schedule_timeout_uninterruptible(1);
2452                 } while (time_after_eq(end_time, jiffies));
2453         }
2454
2455         if (chip->device_type == DEVICE_SIS) {
2456                 /* unmute the output on SIS7012 */
2457                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2458         }
2459         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2460                 /* enable SPDIF interrupt */
2461                 unsigned int val;
2462                 pci_read_config_dword(chip->pci, 0x4c, &val);
2463                 val |= 0x1000000;
2464                 pci_write_config_dword(chip->pci, 0x4c, val);
2465         }
2466         return 0;
2467 }
2468
2469 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2470 {
2471         u32 reg;
2472         int i = 0;
2473
2474         reg = igetdword(chip, ICHREG(ALI_SCR));
2475         if ((reg & 2) == 0)     /* Cold required */
2476                 reg |= 2;
2477         else
2478                 reg |= 1;       /* Warm */
2479         reg &= ~0x80000000;     /* ACLink on */
2480         iputdword(chip, ICHREG(ALI_SCR), reg);
2481
2482         for (i = 0; i < HZ / 2; i++) {
2483                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2484                         goto __ok;
2485                 schedule_timeout_uninterruptible(1);
2486         }
2487         dev_err(chip->card->dev, "AC'97 reset failed.\n");
2488         if (probing)
2489                 return -EIO;
2490
2491  __ok:
2492         for (i = 0; i < HZ / 2; i++) {
2493                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2494                 if (reg & 0x80) /* primary codec */
2495                         break;
2496                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2497                 schedule_timeout_uninterruptible(1);
2498         }
2499
2500         do_ali_reset(chip);
2501         return 0;
2502 }
2503
2504 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2505 {
2506         unsigned int i, timeout;
2507         int err;
2508
2509         if (chip->device_type != DEVICE_ALI) {
2510                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2511                         return err;
2512                 iagetword(chip, 0);     /* clear semaphore flag */
2513         } else {
2514                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2515                         return err;
2516         }
2517
2518         /* disable interrupts */
2519         for (i = 0; i < chip->bdbars_count; i++)
2520                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2521         /* reset channels */
2522         for (i = 0; i < chip->bdbars_count; i++)
2523                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2524         for (i = 0; i < chip->bdbars_count; i++) {
2525                 timeout = 100000;
2526                 while (--timeout != 0) {
2527                         if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2528                                 break;
2529                 }
2530                 if (timeout == 0)
2531                         dev_err(chip->card->dev, "reset of registers failed?\n");
2532         }
2533         /* initialize Buffer Descriptor Lists */
2534         for (i = 0; i < chip->bdbars_count; i++)
2535                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2536                           chip->ichd[i].bdbar_addr);
2537         return 0;
2538 }
2539
2540 static int snd_intel8x0_free(struct intel8x0 *chip)
2541 {
2542         unsigned int i;
2543
2544         if (chip->irq < 0)
2545                 goto __hw_end;
2546         /* disable interrupts */
2547         for (i = 0; i < chip->bdbars_count; i++)
2548                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2549         /* reset channels */
2550         for (i = 0; i < chip->bdbars_count; i++)
2551                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2552         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2553                 /* stop the spdif interrupt */
2554                 unsigned int val;
2555                 pci_read_config_dword(chip->pci, 0x4c, &val);
2556                 val &= ~0x1000000;
2557                 pci_write_config_dword(chip->pci, 0x4c, val);
2558         }
2559         /* --- */
2560
2561       __hw_end:
2562         if (chip->irq >= 0)
2563                 free_irq(chip->irq, chip);
2564         if (chip->bdbars.area)
2565                 snd_dma_free_pages(&chip->bdbars);
2566         if (chip->addr)
2567                 pci_iounmap(chip->pci, chip->addr);
2568         if (chip->bmaddr)
2569                 pci_iounmap(chip->pci, chip->bmaddr);
2570         pci_release_regions(chip->pci);
2571         pci_disable_device(chip->pci);
2572         kfree(chip);
2573         return 0;
2574 }
2575
2576 #ifdef CONFIG_PM_SLEEP
2577 /*
2578  * power management
2579  */
2580 static int intel8x0_suspend(struct device *dev)
2581 {
2582         struct snd_card *card = dev_get_drvdata(dev);
2583         struct intel8x0 *chip = card->private_data;
2584         int i;
2585
2586         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2587         for (i = 0; i < chip->ncodecs; i++)
2588                 snd_ac97_suspend(chip->ac97[i]);
2589         if (chip->device_type == DEVICE_INTEL_ICH4)
2590                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2591
2592         if (chip->irq >= 0) {
2593                 free_irq(chip->irq, chip);
2594                 chip->irq = -1;
2595                 card->sync_irq = -1;
2596         }
2597         return 0;
2598 }
2599
2600 static int intel8x0_resume(struct device *dev)
2601 {
2602         struct pci_dev *pci = to_pci_dev(dev);
2603         struct snd_card *card = dev_get_drvdata(dev);
2604         struct intel8x0 *chip = card->private_data;
2605         int i;
2606
2607         snd_intel8x0_chip_init(chip, 0);
2608         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2609                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
2610                 dev_err(dev, "unable to grab IRQ %d, disabling device\n",
2611                         pci->irq);
2612                 snd_card_disconnect(card);
2613                 return -EIO;
2614         }
2615         chip->irq = pci->irq;
2616         card->sync_irq = chip->irq;
2617
2618         /* re-initialize mixer stuff */
2619         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2620                 /* enable separate SDINs for ICH4 */
2621                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2622                 /* use slot 10/11 for SPDIF */
2623                 iputdword(chip, ICHREG(GLOB_CNT),
2624                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2625                           ICH_PCM_SPDIF_1011);
2626         }
2627
2628         for (i = 0; i < chip->ncodecs; i++)
2629                 snd_ac97_resume(chip->ac97[i]);
2630
2631         /* resume status */
2632         for (i = 0; i < chip->bdbars_count; i++) {
2633                 struct ichdev *ichdev = &chip->ichd[i];
2634                 unsigned long port = ichdev->reg_offset;
2635                 if (! ichdev->substream || ! ichdev->suspended)
2636                         continue;
2637                 if (ichdev->ichd == ICHD_PCMOUT)
2638                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2639                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2640                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2641                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2642                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2643         }
2644
2645         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2646         return 0;
2647 }
2648
2649 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
2650 #define INTEL8X0_PM_OPS &intel8x0_pm
2651 #else
2652 #define INTEL8X0_PM_OPS NULL
2653 #endif /* CONFIG_PM_SLEEP */
2654
2655 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2656
2657 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2658 {
2659         struct snd_pcm_substream *subs;
2660         struct ichdev *ichdev;
2661         unsigned long port;
2662         unsigned long pos, pos1, t;
2663         int civ, timeout = 1000, attempt = 1;
2664         ktime_t start_time, stop_time;
2665
2666         if (chip->ac97_bus->clock != 48000)
2667                 return; /* specified in module option */
2668
2669       __again:
2670         subs = chip->pcm[0]->streams[0].substream;
2671         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2672                 dev_warn(chip->card->dev,
2673                          "no playback buffer allocated - aborting measure ac97 clock\n");
2674                 return;
2675         }
2676         ichdev = &chip->ichd[ICHD_PCMOUT];
2677         ichdev->physbuf = subs->dma_buffer.addr;
2678         ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
2679         ichdev->substream = NULL; /* don't process interrupts */
2680
2681         /* set rate */
2682         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2683                 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
2684                         chip->ac97_bus->clock);
2685                 return;
2686         }
2687         snd_intel8x0_setup_periods(chip, ichdev);
2688         port = ichdev->reg_offset;
2689         spin_lock_irq(&chip->reg_lock);
2690         chip->in_measurement = 1;
2691         /* trigger */
2692         if (chip->device_type != DEVICE_ALI)
2693                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2694         else {
2695                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2696                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2697         }
2698         start_time = ktime_get();
2699         spin_unlock_irq(&chip->reg_lock);
2700         msleep(50);
2701         spin_lock_irq(&chip->reg_lock);
2702         /* check the position */
2703         do {
2704                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
2705                 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
2706                 if (pos1 == 0) {
2707                         udelay(10);
2708                         continue;
2709                 }
2710                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
2711                     pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
2712                         break;
2713         } while (timeout--);
2714         if (pos1 == 0) {        /* oops, this value is not reliable */
2715                 pos = 0;
2716         } else {
2717                 pos = ichdev->fragsize1;
2718                 pos -= pos1 << ichdev->pos_shift;
2719                 pos += ichdev->position;
2720         }
2721         chip->in_measurement = 0;
2722         stop_time = ktime_get();
2723         /* stop */
2724         if (chip->device_type == DEVICE_ALI) {
2725                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2726                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2727                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2728                         ;
2729         } else {
2730                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2731                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2732                         ;
2733         }
2734         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2735         spin_unlock_irq(&chip->reg_lock);
2736
2737         if (pos == 0) {
2738                 dev_err(chip->card->dev,
2739                         "measure - unreliable DMA position..\n");
2740               __retry:
2741                 if (attempt < 3) {
2742                         msleep(300);
2743                         attempt++;
2744                         goto __again;
2745                 }
2746                 goto __end;
2747         }
2748
2749         pos /= 4;
2750         t = ktime_us_delta(stop_time, start_time);
2751         dev_info(chip->card->dev,
2752                  "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
2753         if (t == 0) {
2754                 dev_err(chip->card->dev, "?? calculation error..\n");
2755                 goto __retry;
2756         }
2757         pos *= 1000;
2758         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2759         if (pos < 40000 || pos >= 60000) {
2760                 /* abnormal value. hw problem? */
2761                 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
2762                 goto __retry;
2763         } else if (pos > 40500 && pos < 41500)
2764                 /* first exception - 41000Hz reference clock */
2765                 chip->ac97_bus->clock = 41000;
2766         else if (pos > 43600 && pos < 44600)
2767                 /* second exception - 44100HZ reference clock */
2768                 chip->ac97_bus->clock = 44100;
2769         else if (pos < 47500 || pos > 48500)
2770                 /* not 48000Hz, tuning the clock.. */
2771                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2772       __end:
2773         dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
2774         snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2775 }
2776
2777 static const struct snd_pci_quirk intel8x0_clock_list[] = {
2778         SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
2779         SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
2780         SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
2781         SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2782         SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2783         SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
2784         { }     /* terminator */
2785 };
2786
2787 static int intel8x0_in_clock_list(struct intel8x0 *chip)
2788 {
2789         struct pci_dev *pci = chip->pci;
2790         const struct snd_pci_quirk *wl;
2791
2792         wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2793         if (!wl)
2794                 return 0;
2795         dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n",
2796                pci->subsystem_vendor, pci->subsystem_device, wl->value);
2797         chip->ac97_bus->clock = wl->value;
2798         return 1;
2799 }
2800
2801 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2802                                    struct snd_info_buffer *buffer)
2803 {
2804         struct intel8x0 *chip = entry->private_data;
2805         unsigned int tmp;
2806
2807         snd_iprintf(buffer, "Intel8x0\n\n");
2808         if (chip->device_type == DEVICE_ALI)
2809                 return;
2810         tmp = igetdword(chip, ICHREG(GLOB_STA));
2811         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2812         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2813         if (chip->device_type == DEVICE_INTEL_ICH4)
2814                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2815         snd_iprintf(buffer, "AC'97 codecs ready    :");
2816         if (tmp & chip->codec_isr_bits) {
2817                 int i;
2818                 static const char *codecs[3] = {
2819                         "primary", "secondary", "tertiary"
2820                 };
2821                 for (i = 0; i < chip->max_codecs; i++)
2822                         if (tmp & chip->codec_bit[i])
2823                                 snd_iprintf(buffer, " %s", codecs[i]);
2824         } else
2825                 snd_iprintf(buffer, " none");
2826         snd_iprintf(buffer, "\n");
2827         if (chip->device_type == DEVICE_INTEL_ICH4 ||
2828             chip->device_type == DEVICE_SIS)
2829                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2830                         chip->ac97_sdin[0],
2831                         chip->ac97_sdin[1],
2832                         chip->ac97_sdin[2]);
2833 }
2834
2835 static void snd_intel8x0_proc_init(struct intel8x0 *chip)
2836 {
2837         snd_card_ro_proc_new(chip->card, "intel8x0", chip,
2838                              snd_intel8x0_proc_read);
2839 }
2840
2841 static int snd_intel8x0_dev_free(struct snd_device *device)
2842 {
2843         struct intel8x0 *chip = device->device_data;
2844         return snd_intel8x0_free(chip);
2845 }
2846
2847 struct ich_reg_info {
2848         unsigned int int_sta_mask;
2849         unsigned int offset;
2850 };
2851
2852 static const unsigned int ich_codec_bits[3] = {
2853         ICH_PCR, ICH_SCR, ICH_TCR
2854 };
2855 static const unsigned int sis_codec_bits[3] = {
2856         ICH_PCR, ICH_SCR, ICH_SIS_TCR
2857 };
2858
2859 static int snd_intel8x0_inside_vm(struct pci_dev *pci)
2860 {
2861         int result  = inside_vm;
2862         char *msg   = NULL;
2863
2864         /* check module parameter first (override detection) */
2865         if (result >= 0) {
2866                 msg = result ? "enable (forced) VM" : "disable (forced) VM";
2867                 goto fini;
2868         }
2869
2870         /* check for known (emulated) devices */
2871         result = 0;
2872         if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
2873             pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) {
2874                 /* KVM emulated sound, PCI SSID: 1af4:1100 */
2875                 msg = "enable KVM";
2876                 result = 1;
2877         } else if (pci->subsystem_vendor == 0x1ab8) {
2878                 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
2879                 msg = "enable Parallels VM";
2880                 result = 1;
2881         }
2882
2883 fini:
2884         if (msg != NULL)
2885                 dev_info(&pci->dev, "%s optimization\n", msg);
2886
2887         return result;
2888 }
2889
2890 static int snd_intel8x0_create(struct snd_card *card,
2891                                struct pci_dev *pci,
2892                                unsigned long device_type,
2893                                struct intel8x0 **r_intel8x0)
2894 {
2895         struct intel8x0 *chip;
2896         int err;
2897         unsigned int i;
2898         unsigned int int_sta_masks;
2899         struct ichdev *ichdev;
2900         static const struct snd_device_ops ops = {
2901                 .dev_free =     snd_intel8x0_dev_free,
2902         };
2903
2904         static const unsigned int bdbars[] = {
2905                 3, /* DEVICE_INTEL */
2906                 6, /* DEVICE_INTEL_ICH4 */
2907                 3, /* DEVICE_SIS */
2908                 6, /* DEVICE_ALI */
2909                 4, /* DEVICE_NFORCE */
2910         };
2911         static const struct ich_reg_info intel_regs[6] = {
2912                 { ICH_PIINT, 0 },
2913                 { ICH_POINT, 0x10 },
2914                 { ICH_MCINT, 0x20 },
2915                 { ICH_M2INT, 0x40 },
2916                 { ICH_P2INT, 0x50 },
2917                 { ICH_SPINT, 0x60 },
2918         };
2919         static const struct ich_reg_info nforce_regs[4] = {
2920                 { ICH_PIINT, 0 },
2921                 { ICH_POINT, 0x10 },
2922                 { ICH_MCINT, 0x20 },
2923                 { ICH_NVSPINT, 0x70 },
2924         };
2925         static const struct ich_reg_info ali_regs[6] = {
2926                 { ALI_INT_PCMIN, 0x40 },
2927                 { ALI_INT_PCMOUT, 0x50 },
2928                 { ALI_INT_MICIN, 0x60 },
2929                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2930                 { ALI_INT_SPDIFIN, 0xa0 },
2931                 { ALI_INT_SPDIFOUT, 0xb0 },
2932         };
2933         const struct ich_reg_info *tbl;
2934
2935         *r_intel8x0 = NULL;
2936
2937         if ((err = pci_enable_device(pci)) < 0)
2938                 return err;
2939
2940         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2941         if (chip == NULL) {
2942                 pci_disable_device(pci);
2943                 return -ENOMEM;
2944         }
2945         spin_lock_init(&chip->reg_lock);
2946         chip->device_type = device_type;
2947         chip->card = card;
2948         chip->pci = pci;
2949         chip->irq = -1;
2950
2951         /* module parameters */
2952         chip->buggy_irq = buggy_irq;
2953         chip->buggy_semaphore = buggy_semaphore;
2954         if (xbox)
2955                 chip->xbox = 1;
2956
2957         chip->inside_vm = snd_intel8x0_inside_vm(pci);
2958
2959         /*
2960          * Intel 82443MX running a 100MHz processor system bus has a hardware
2961          * bug, which aborts PCI busmaster for audio transfer.  A workaround
2962          * is to set the pages as non-cached.  For details, see the errata in
2963          *     http://download.intel.com/design/chipsets/specupdt/24505108.pdf
2964          */
2965         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2966             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2967                 chip->fix_nocache = 1; /* enable workaround */
2968
2969         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2970                 kfree(chip);
2971                 pci_disable_device(pci);
2972                 return err;
2973         }
2974
2975         if (device_type == DEVICE_ALI) {
2976                 /* ALI5455 has no ac97 region */
2977                 chip->bmaddr = pci_iomap(pci, 0, 0);
2978                 goto port_inited;
2979         }
2980
2981         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2982                 chip->addr = pci_iomap(pci, 2, 0);
2983         else
2984                 chip->addr = pci_iomap(pci, 0, 0);
2985         if (!chip->addr) {
2986                 dev_err(card->dev, "AC'97 space ioremap problem\n");
2987                 snd_intel8x0_free(chip);
2988                 return -EIO;
2989         }
2990         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2991                 chip->bmaddr = pci_iomap(pci, 3, 0);
2992         else
2993                 chip->bmaddr = pci_iomap(pci, 1, 0);
2994
2995  port_inited:
2996         if (!chip->bmaddr) {
2997                 dev_err(card->dev, "Controller space ioremap problem\n");
2998                 snd_intel8x0_free(chip);
2999                 return -EIO;
3000         }
3001         chip->bdbars_count = bdbars[device_type];
3002
3003         /* initialize offsets */
3004         switch (device_type) {
3005         case DEVICE_NFORCE:
3006                 tbl = nforce_regs;
3007                 break;
3008         case DEVICE_ALI:
3009                 tbl = ali_regs;
3010                 break;
3011         default:
3012                 tbl = intel_regs;
3013                 break;
3014         }
3015         for (i = 0; i < chip->bdbars_count; i++) {
3016                 ichdev = &chip->ichd[i];
3017                 ichdev->ichd = i;
3018                 ichdev->reg_offset = tbl[i].offset;
3019                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
3020                 if (device_type == DEVICE_SIS) {
3021                         /* SiS 7012 swaps the registers */
3022                         ichdev->roff_sr = ICH_REG_OFF_PICB;
3023                         ichdev->roff_picb = ICH_REG_OFF_SR;
3024                 } else {
3025                         ichdev->roff_sr = ICH_REG_OFF_SR;
3026                         ichdev->roff_picb = ICH_REG_OFF_PICB;
3027                 }
3028                 if (device_type == DEVICE_ALI)
3029                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
3030                 /* SIS7012 handles the pcm data in bytes, others are in samples */
3031                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
3032         }
3033
3034         /* allocate buffer descriptor lists */
3035         /* the start of each lists must be aligned to 8 bytes */
3036         if (snd_dma_alloc_pages(intel8x0_dma_type(chip), &pci->dev,
3037                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
3038                                 &chip->bdbars) < 0) {
3039                 snd_intel8x0_free(chip);
3040                 dev_err(card->dev, "cannot allocate buffer descriptors\n");
3041                 return -ENOMEM;
3042         }
3043         /* tables must be aligned to 8 bytes here, but the kernel pages
3044            are much bigger, so we don't care (on i386) */
3045         int_sta_masks = 0;
3046         for (i = 0; i < chip->bdbars_count; i++) {
3047                 ichdev = &chip->ichd[i];
3048                 ichdev->bdbar = ((__le32 *)chip->bdbars.area) +
3049                         (i * ICH_MAX_FRAGS * 2);
3050                 ichdev->bdbar_addr = chip->bdbars.addr +
3051                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
3052                 int_sta_masks |= ichdev->int_sta_mask;
3053         }
3054         chip->int_sta_reg = device_type == DEVICE_ALI ?
3055                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
3056         chip->int_sta_mask = int_sta_masks;
3057
3058         pci_set_master(pci);
3059
3060         switch(chip->device_type) {
3061         case DEVICE_INTEL_ICH4:
3062                 /* ICH4 can have three codecs */
3063                 chip->max_codecs = 3;
3064                 chip->codec_bit = ich_codec_bits;
3065                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
3066                 break;
3067         case DEVICE_SIS:
3068                 /* recent SIS7012 can have three codecs */
3069                 chip->max_codecs = 3;
3070                 chip->codec_bit = sis_codec_bits;
3071                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
3072                 break;
3073         default:
3074                 /* others up to two codecs */
3075                 chip->max_codecs = 2;
3076                 chip->codec_bit = ich_codec_bits;
3077                 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
3078                 break;
3079         }
3080         for (i = 0; i < chip->max_codecs; i++)
3081                 chip->codec_isr_bits |= chip->codec_bit[i];
3082
3083         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
3084                 snd_intel8x0_free(chip);
3085                 return err;
3086         }
3087
3088         /* request irq after initializaing int_sta_mask, etc */
3089         if (request_irq(pci->irq, snd_intel8x0_interrupt,
3090                         IRQF_SHARED, KBUILD_MODNAME, chip)) {
3091                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3092                 snd_intel8x0_free(chip);
3093                 return -EBUSY;
3094         }
3095         chip->irq = pci->irq;
3096         card->sync_irq = chip->irq;
3097
3098         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3099                 snd_intel8x0_free(chip);
3100                 return err;
3101         }
3102
3103         *r_intel8x0 = chip;
3104         return 0;
3105 }
3106
3107 static struct shortname_table {
3108         unsigned int id;
3109         const char *s;
3110 } shortnames[] = {
3111         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
3112         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
3113         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
3114         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3115         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
3116         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
3117         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
3118         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
3119         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
3120         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3121         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
3122         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3123         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
3124         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
3125         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
3126         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
3127         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
3128         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
3129         { 0x003a, "NVidia MCP04" },
3130         { 0x746d, "AMD AMD8111" },
3131         { 0x7445, "AMD AMD768" },
3132         { 0x5455, "ALi M5455" },
3133         { 0, NULL },
3134 };
3135
3136 static const struct snd_pci_quirk spdif_aclink_defaults[] = {
3137         SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
3138         { } /* end */
3139 };
3140
3141 /* look up allow/deny list for SPDIF over ac-link */
3142 static int check_default_spdif_aclink(struct pci_dev *pci)
3143 {
3144         const struct snd_pci_quirk *w;
3145
3146         w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
3147         if (w) {
3148                 if (w->value)
3149                         dev_dbg(&pci->dev,
3150                                 "Using SPDIF over AC-Link for %s\n",
3151                                     snd_pci_quirk_name(w));
3152                 else
3153                         dev_dbg(&pci->dev,
3154                                 "Using integrated SPDIF DMA for %s\n",
3155                                     snd_pci_quirk_name(w));
3156                 return w->value;
3157         }
3158         return 0;
3159 }
3160
3161 static int snd_intel8x0_probe(struct pci_dev *pci,
3162                               const struct pci_device_id *pci_id)
3163 {
3164         struct snd_card *card;
3165         struct intel8x0 *chip;
3166         int err;
3167         struct shortname_table *name;
3168
3169         err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
3170         if (err < 0)
3171                 return err;
3172
3173         if (spdif_aclink < 0)
3174                 spdif_aclink = check_default_spdif_aclink(pci);
3175
3176         strcpy(card->driver, "ICH");
3177         if (!spdif_aclink) {
3178                 switch (pci_id->driver_data) {
3179                 case DEVICE_NFORCE:
3180                         strcpy(card->driver, "NFORCE");
3181                         break;
3182                 case DEVICE_INTEL_ICH4:
3183                         strcpy(card->driver, "ICH4");
3184                 }
3185         }
3186
3187         strcpy(card->shortname, "Intel ICH");
3188         for (name = shortnames; name->id; name++) {
3189                 if (pci->device == name->id) {
3190                         strcpy(card->shortname, name->s);
3191                         break;
3192                 }
3193         }
3194
3195         if (buggy_irq < 0) {
3196                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3197                  * Needs to return IRQ_HANDLED for unknown irqs.
3198                  */
3199                 if (pci_id->driver_data == DEVICE_NFORCE)
3200                         buggy_irq = 1;
3201                 else
3202                         buggy_irq = 0;
3203         }
3204
3205         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3206                                        &chip)) < 0) {
3207                 snd_card_free(card);
3208                 return err;
3209         }
3210         card->private_data = chip;
3211
3212         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3213                 snd_card_free(card);
3214                 return err;
3215         }
3216         if ((err = snd_intel8x0_pcm(chip)) < 0) {
3217                 snd_card_free(card);
3218                 return err;
3219         }
3220
3221         snd_intel8x0_proc_init(chip);
3222
3223         snprintf(card->longname, sizeof(card->longname),
3224                  "%s with %s at irq %i", card->shortname,
3225                  snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3226
3227         if (ac97_clock == 0 || ac97_clock == 1) {
3228                 if (ac97_clock == 0) {
3229                         if (intel8x0_in_clock_list(chip) == 0)
3230                                 intel8x0_measure_ac97_clock(chip);
3231                 } else {
3232                         intel8x0_measure_ac97_clock(chip);
3233                 }
3234         }
3235
3236         if ((err = snd_card_register(card)) < 0) {
3237                 snd_card_free(card);
3238                 return err;
3239         }
3240         pci_set_drvdata(pci, card);
3241         return 0;
3242 }
3243
3244 static void snd_intel8x0_remove(struct pci_dev *pci)
3245 {
3246         snd_card_free(pci_get_drvdata(pci));
3247 }
3248
3249 static struct pci_driver intel8x0_driver = {
3250         .name = KBUILD_MODNAME,
3251         .id_table = snd_intel8x0_ids,
3252         .probe = snd_intel8x0_probe,
3253         .remove = snd_intel8x0_remove,
3254         .driver = {
3255                 .pm = INTEL8X0_PM_OPS,
3256         },
3257 };
3258
3259 module_pci_driver(intel8x0_driver);