1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
13 * Wu Fengguang <wfg@linux.intel.com>
16 * Wu Fengguang <wfg@linux.intel.com>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/asoundef.h>
28 #include <sound/tlv.h>
29 #include <sound/hdaudio.h>
30 #include <sound/hda_i915.h>
31 #include <sound/hda_chmap.h>
32 #include <sound/hda_codec.h>
33 #include "hda_local.h"
35 #include "hda_controller.h"
37 static bool static_hdmi_pcm;
38 module_param(static_hdmi_pcm, bool, 0644);
39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
41 static bool enable_acomp = true;
42 module_param(enable_acomp, bool, 0444);
43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
45 static bool enable_silent_stream =
46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47 module_param(enable_silent_stream, bool, 0644);
48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
50 static bool enable_all_pins;
51 module_param(enable_all_pins, bool, 0444);
52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins");
54 struct hdmi_spec_per_cvt {
56 bool assigned; /* the stream has been assigned */
57 bool silent_stream; /* silent stream activated */
58 unsigned int channels_min;
59 unsigned int channels_max;
65 /* max. connections to a widget */
66 #define HDA_MAX_CONNECTIONS 32
68 struct hdmi_spec_per_pin {
71 /* pin idx, different device entries on the same pin use the same idx */
74 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
78 struct hda_codec *codec;
79 struct hdmi_eld sink_eld;
81 struct delayed_work work;
82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
84 int prev_pcm_idx; /* previously assigned pcm index */
86 bool setup; /* the stream has been set up by prepare callback */
88 int channels; /* current number of channels */
90 bool chmap_set; /* channel-map override by ALSA API? */
91 unsigned char chmap[8]; /* ALSA API channel-map */
92 #ifdef CONFIG_SND_PROC_FS
93 struct snd_info_entry *proc_entry;
97 /* operations used by generic code that can be overridden by patches */
99 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
100 int dev_id, unsigned char *buf, int *eld_size);
102 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
104 int ca, int active_channels, int conn_type);
106 /* enable/disable HBR (HD passthrough) */
107 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
108 int dev_id, bool hbr);
110 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
111 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
114 void (*pin_cvt_fixup)(struct hda_codec *codec,
115 struct hdmi_spec_per_pin *per_pin,
121 struct snd_jack *jack;
122 struct snd_kcontrol *eld_ctl;
126 SILENT_STREAM_OFF = 0,
127 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */
128 SILENT_STREAM_I915, /* Intel i915 extension */
132 struct hda_codec *codec;
134 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
135 hda_nid_t cvt_nids[4]; /* only for haswell fix */
138 * num_pins is the number of virtual pins
139 * for example, there are 3 pins, and each pin
140 * has 4 device entries, then the num_pins is 12
144 * num_nids is the number of real pins
145 * In the above example, num_nids is 3
149 * dev_num is the number of device entries
151 * In the above example, dev_num is 4
154 struct snd_array pins; /* struct hdmi_spec_per_pin */
155 struct hdmi_pcm pcm_rec[8];
156 struct mutex pcm_lock;
157 struct mutex bind_lock; /* for audio component binding */
158 /* pcm_bitmap means which pcms have been assigned to pins*/
159 unsigned long pcm_bitmap;
160 int pcm_used; /* counter of pcm_rec[] */
161 /* bitmap shows whether the pcm is opened in user space
162 * bit 0 means the first playback PCM (PCM3);
163 * bit 1 means the second playback PCM, and so on.
165 unsigned long pcm_in_use;
167 struct hdmi_eld temp_eld;
171 bool static_pcm_mapping;
172 /* hdmi interrupt trigger control flag for Nvidia codec */
173 bool hdmi_intr_trig_ctrl;
174 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */
176 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
178 * Non-generic VIA/NVIDIA specific
180 struct hda_multi_out multiout;
181 struct hda_pcm_stream pcm_playback;
183 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
184 bool acomp_registered; /* audio component registered in this driver */
185 bool force_connect; /* force connectivity */
186 struct drm_audio_component_audio_ops drm_audio_ops;
187 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
189 struct hdac_chmap chmap;
190 hda_nid_t vendor_nid;
193 int silent_stream_type;
196 #ifdef CONFIG_SND_HDA_COMPONENT
197 static inline bool codec_has_acomp(struct hda_codec *codec)
199 struct hdmi_spec *spec = codec->spec;
200 return spec->use_acomp_notifier;
203 #define codec_has_acomp(codec) false
206 struct hdmi_audio_infoframe {
213 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
217 u8 LFEPBL01_LSV36_DM_INH7;
220 struct dp_audio_infoframe {
223 u8 ver; /* 0x11 << 2 */
225 u8 CC02_CT47; /* match with HDMI infoframe from this on */
229 u8 LFEPBL01_LSV36_DM_INH7;
232 union audio_infoframe {
233 struct hdmi_audio_infoframe hdmi;
234 struct dp_audio_infoframe dp;
235 DECLARE_FLEX_ARRAY(u8, bytes);
242 #define get_pin(spec, idx) \
243 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
244 #define get_cvt(spec, idx) \
245 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
246 /* obtain hdmi_pcm object assigned to idx */
247 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
248 /* obtain hda_pcm object assigned to idx */
249 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
251 static int pin_id_to_pin_index(struct hda_codec *codec,
252 hda_nid_t pin_nid, int dev_id)
254 struct hdmi_spec *spec = codec->spec;
256 struct hdmi_spec_per_pin *per_pin;
259 * (dev_id == -1) means it is NON-MST pin
260 * return the first virtual pin on this port
265 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
266 per_pin = get_pin(spec, pin_idx);
267 if ((per_pin->pin_nid == pin_nid) &&
268 (per_pin->dev_id == dev_id))
272 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid);
276 static int hinfo_to_pcm_index(struct hda_codec *codec,
277 struct hda_pcm_stream *hinfo)
279 struct hdmi_spec *spec = codec->spec;
282 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
283 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
286 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
290 static int hinfo_to_pin_index(struct hda_codec *codec,
291 struct hda_pcm_stream *hinfo)
293 struct hdmi_spec *spec = codec->spec;
294 struct hdmi_spec_per_pin *per_pin;
297 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
298 per_pin = get_pin(spec, pin_idx);
300 per_pin->pcm->pcm->stream == hinfo)
304 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
305 hinfo_to_pcm_index(codec, hinfo));
309 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
313 struct hdmi_spec_per_pin *per_pin;
315 for (i = 0; i < spec->num_pins; i++) {
316 per_pin = get_pin(spec, i);
317 if (per_pin->pcm_idx == pcm_idx)
323 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
325 struct hdmi_spec *spec = codec->spec;
328 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
329 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
332 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid);
336 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
337 struct snd_ctl_elem_info *uinfo)
339 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
340 struct hdmi_spec *spec = codec->spec;
341 struct hdmi_spec_per_pin *per_pin;
342 struct hdmi_eld *eld;
345 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
347 pcm_idx = kcontrol->private_value;
348 mutex_lock(&spec->pcm_lock);
349 per_pin = pcm_idx_to_pin(spec, pcm_idx);
351 /* no pin is bound to the pcm */
355 eld = &per_pin->sink_eld;
356 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
359 mutex_unlock(&spec->pcm_lock);
363 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
364 struct snd_ctl_elem_value *ucontrol)
366 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
367 struct hdmi_spec *spec = codec->spec;
368 struct hdmi_spec_per_pin *per_pin;
369 struct hdmi_eld *eld;
373 pcm_idx = kcontrol->private_value;
374 mutex_lock(&spec->pcm_lock);
375 per_pin = pcm_idx_to_pin(spec, pcm_idx);
377 /* no pin is bound to the pcm */
378 memset(ucontrol->value.bytes.data, 0,
379 ARRAY_SIZE(ucontrol->value.bytes.data));
383 eld = &per_pin->sink_eld;
384 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
385 eld->eld_size > ELD_MAX_SIZE) {
391 memset(ucontrol->value.bytes.data, 0,
392 ARRAY_SIZE(ucontrol->value.bytes.data));
394 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
398 mutex_unlock(&spec->pcm_lock);
402 static const struct snd_kcontrol_new eld_bytes_ctl = {
403 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
404 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
405 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
407 .info = hdmi_eld_ctl_info,
408 .get = hdmi_eld_ctl_get,
411 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
414 struct snd_kcontrol *kctl;
415 struct hdmi_spec *spec = codec->spec;
418 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
421 kctl->private_value = pcm_idx;
422 kctl->id.device = device;
424 /* no pin nid is associated with the kctl now
425 * tbd: associate pin nid to eld ctl later
427 err = snd_hda_ctl_add(codec, 0, kctl);
431 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
436 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
437 int *packet_index, int *byte_index)
441 val = snd_hda_codec_read(codec, pin_nid, 0,
442 AC_VERB_GET_HDMI_DIP_INDEX, 0);
444 *packet_index = val >> 5;
445 *byte_index = val & 0x1f;
449 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
450 int packet_index, int byte_index)
454 val = (packet_index << 5) | (byte_index & 0x1f);
456 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
459 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
462 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
465 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
467 struct hdmi_spec *spec = codec->spec;
471 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
472 snd_hda_codec_write(codec, pin_nid, 0,
473 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
475 if (spec->dyn_pin_out)
476 /* Disable pin out until stream is active */
479 /* Enable pin out: some machines with GM965 gets broken output
480 * when the pin is disabled or changed while using with HDMI
484 snd_hda_codec_write(codec, pin_nid, 0,
485 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
492 #ifdef CONFIG_SND_PROC_FS
493 static void print_eld_info(struct snd_info_entry *entry,
494 struct snd_info_buffer *buffer)
496 struct hdmi_spec_per_pin *per_pin = entry->private_data;
498 mutex_lock(&per_pin->lock);
499 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid,
500 per_pin->dev_id, per_pin->cvt_nid);
501 mutex_unlock(&per_pin->lock);
504 static void write_eld_info(struct snd_info_entry *entry,
505 struct snd_info_buffer *buffer)
507 struct hdmi_spec_per_pin *per_pin = entry->private_data;
509 mutex_lock(&per_pin->lock);
510 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
511 mutex_unlock(&per_pin->lock);
514 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
517 struct hda_codec *codec = per_pin->codec;
518 struct snd_info_entry *entry;
521 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
522 err = snd_card_proc_new(codec->card, name, &entry);
526 snd_info_set_text_ops(entry, per_pin, print_eld_info);
527 entry->c.text.write = write_eld_info;
529 per_pin->proc_entry = entry;
534 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
536 if (!per_pin->codec->bus->shutdown) {
537 snd_info_free_entry(per_pin->proc_entry);
538 per_pin->proc_entry = NULL;
542 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
547 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
553 * Audio InfoFrame routines
557 * Enable Audio InfoFrame Transmission
559 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
562 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
563 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
568 * Disable Audio InfoFrame Transmission
570 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
573 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
574 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
578 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
580 #ifdef CONFIG_SND_DEBUG_VERBOSE
584 size = snd_hdmi_get_eld_size(codec, pin_nid);
585 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
587 for (i = 0; i < 8; i++) {
588 size = snd_hda_codec_read(codec, pin_nid, 0,
589 AC_VERB_GET_HDMI_DIP_SIZE, i);
590 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
595 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
601 for (i = 0; i < 8; i++) {
602 size = snd_hda_codec_read(codec, pin_nid, 0,
603 AC_VERB_GET_HDMI_DIP_SIZE, i);
607 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
608 for (j = 1; j < 1000; j++) {
609 hdmi_write_dip_byte(codec, pin_nid, 0x0);
610 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
612 codec_dbg(codec, "dip index %d: %d != %d\n",
614 if (bi == 0) /* byte index wrapped around */
618 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
624 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
626 u8 *bytes = (u8 *)hdmi_ai;
630 hdmi_ai->checksum = 0;
632 for (i = 0; i < sizeof(*hdmi_ai); i++)
635 hdmi_ai->checksum = -sum;
638 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
644 hdmi_debug_dip_size(codec, pin_nid);
645 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
647 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
648 for (i = 0; i < size; i++)
649 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
652 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
658 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
659 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
663 for (i = 0; i < size; i++) {
664 val = snd_hda_codec_read(codec, pin_nid, 0,
665 AC_VERB_GET_HDMI_DIP_DATA, 0);
673 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
674 int dev_id, unsigned char *buf, int *eld_size)
676 snd_hda_set_dev_select(codec, nid, dev_id);
678 return snd_hdmi_get_eld(codec, nid, buf, eld_size);
681 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
682 hda_nid_t pin_nid, int dev_id,
683 int ca, int active_channels,
686 struct hdmi_spec *spec = codec->spec;
687 union audio_infoframe ai;
689 memset(&ai, 0, sizeof(ai));
690 if ((conn_type == 0) || /* HDMI */
691 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */
692 (conn_type == 1 && spec->nv_dp_workaround)) {
693 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
695 if (conn_type == 0) { /* HDMI */
696 hdmi_ai->type = 0x84;
699 } else {/* Nvidia DP */
700 hdmi_ai->type = 0x84;
702 hdmi_ai->len = 0x11 << 2;
704 hdmi_ai->CC02_CT47 = active_channels - 1;
706 hdmi_checksum_audio_infoframe(hdmi_ai);
707 } else if (conn_type == 1) { /* DisplayPort */
708 struct dp_audio_infoframe *dp_ai = &ai.dp;
712 dp_ai->ver = 0x11 << 2;
713 dp_ai->CC02_CT47 = active_channels - 1;
716 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid);
720 snd_hda_set_dev_select(codec, pin_nid, dev_id);
723 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
724 * sizeof(*dp_ai) to avoid partial match/update problems when
725 * the user switches between HDMI/DP monitors.
727 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
729 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n",
730 __func__, pin_nid, active_channels, ca);
731 hdmi_stop_infoframe_trans(codec, pin_nid);
732 hdmi_fill_audio_infoframe(codec, pin_nid,
733 ai.bytes, sizeof(ai));
734 hdmi_start_infoframe_trans(codec, pin_nid);
738 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
739 struct hdmi_spec_per_pin *per_pin,
742 struct hdmi_spec *spec = codec->spec;
743 struct hdac_chmap *chmap = &spec->chmap;
744 hda_nid_t pin_nid = per_pin->pin_nid;
745 int dev_id = per_pin->dev_id;
746 int channels = per_pin->channels;
748 struct hdmi_eld *eld;
754 snd_hda_set_dev_select(codec, pin_nid, dev_id);
756 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
757 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
758 snd_hda_codec_write(codec, pin_nid, 0,
759 AC_VERB_SET_AMP_GAIN_MUTE,
762 eld = &per_pin->sink_eld;
764 ca = snd_hdac_channel_allocation(&codec->core,
765 eld->info.spk_alloc, channels,
766 per_pin->chmap_set, non_pcm, per_pin->chmap);
768 active_channels = snd_hdac_get_active_channels(ca);
770 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
774 * always configure channel mapping, it may have been changed by the
775 * user in the meantime
777 snd_hdac_setup_channel_mapping(&spec->chmap,
778 pin_nid, non_pcm, ca, channels,
779 per_pin->chmap, per_pin->chmap_set);
781 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
782 ca, active_channels, eld->info.conn_type);
784 per_pin->non_pcm = non_pcm;
791 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
793 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
796 struct hdmi_spec *spec = codec->spec;
797 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
801 mutex_lock(&spec->pcm_lock);
802 hdmi_present_sense(get_pin(spec, pin_idx), 1);
803 mutex_unlock(&spec->pcm_lock);
806 static void jack_callback(struct hda_codec *codec,
807 struct hda_jack_callback *jack)
809 /* stop polling when notification is enabled */
810 if (codec_has_acomp(codec))
813 check_presence_and_report(codec, jack->nid, jack->dev_id);
816 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
817 struct hda_jack_tbl *jack)
819 jack->jack_dirty = 1;
822 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
823 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
824 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
826 check_presence_and_report(codec, jack->nid, jack->dev_id);
829 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
831 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
832 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
833 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
834 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
837 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
854 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
856 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
857 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
858 struct hda_jack_tbl *jack;
860 if (codec_has_acomp(codec))
865 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
867 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
869 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
873 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
878 hdmi_intrinsic_event(codec, res, jack);
880 hdmi_non_intrinsic_event(codec, res);
883 static void haswell_verify_D0(struct hda_codec *codec,
884 hda_nid_t cvt_nid, hda_nid_t nid)
888 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
889 * thus pins could only choose converter 0 for use. Make sure the
890 * converters are in correct power state */
891 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
892 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
894 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
895 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
898 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
899 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
900 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr);
908 /* HBR should be Non-PCM, 8 channels */
909 #define is_hbr_format(format) \
910 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
912 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
913 int dev_id, bool hbr)
915 int pinctl, new_pinctl;
917 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
918 snd_hda_set_dev_select(codec, pin_nid, dev_id);
919 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
920 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
923 return hbr ? -EINVAL : 0;
925 new_pinctl = pinctl & ~AC_PINCTL_EPT;
927 new_pinctl |= AC_PINCTL_EPT_HBR;
929 new_pinctl |= AC_PINCTL_EPT_NATIVE;
932 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
934 pinctl == new_pinctl ? "" : "new-",
937 if (pinctl != new_pinctl)
938 snd_hda_codec_write(codec, pin_nid, 0,
939 AC_VERB_SET_PIN_WIDGET_CONTROL,
947 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
948 hda_nid_t pin_nid, int dev_id,
949 u32 stream_tag, int format)
951 struct hdmi_spec *spec = codec->spec;
955 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
956 is_hbr_format(format));
959 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
963 if (spec->intel_hsw_fixup) {
966 * on recent platforms IEC Coding Type is required for HBR
967 * support, read current Digital Converter settings and set
968 * ICT bitfield if needed.
970 param = snd_hda_codec_read(codec, cvt_nid, 0,
971 AC_VERB_GET_DIGI_CONVERT_1, 0);
973 param = (param >> 16) & ~(AC_DIG3_ICT);
975 /* on recent platforms ICT mode is required for HBR support */
976 if (is_hbr_format(format))
979 snd_hda_codec_write(codec, cvt_nid, 0,
980 AC_VERB_SET_DIGI_CONVERT_3, param);
983 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
987 /* Try to find an available converter
988 * If pin_idx is less then zero, just try to find an available converter.
989 * Otherwise, try to find an available converter and get the cvt mux index
992 static int hdmi_choose_cvt(struct hda_codec *codec,
993 int pin_idx, int *cvt_id,
996 struct hdmi_spec *spec = codec->spec;
997 struct hdmi_spec_per_pin *per_pin;
998 struct hdmi_spec_per_cvt *per_cvt = NULL;
999 int cvt_idx, mux_idx = 0;
1001 /* pin_idx < 0 means no pin will be bound to the converter */
1005 per_pin = get_pin(spec, pin_idx);
1007 if (per_pin && per_pin->silent_stream) {
1008 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1009 per_cvt = get_cvt(spec, cvt_idx);
1010 if (per_cvt->assigned && !silent)
1017 /* Dynamically assign converter to stream */
1018 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1019 per_cvt = get_cvt(spec, cvt_idx);
1021 /* Must not already be assigned */
1022 if (per_cvt->assigned || per_cvt->silent_stream)
1024 if (per_pin == NULL)
1026 /* Must be in pin's mux's list of converters */
1027 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1028 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1030 /* Not in mux list */
1031 if (mux_idx == per_pin->num_mux_nids)
1036 /* No free converters */
1037 if (cvt_idx == spec->num_cvts)
1040 if (per_pin != NULL)
1041 per_pin->mux_idx = mux_idx;
1049 /* Assure the pin select the right convetor */
1050 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1051 struct hdmi_spec_per_pin *per_pin)
1053 hda_nid_t pin_nid = per_pin->pin_nid;
1056 mux_idx = per_pin->mux_idx;
1057 curr = snd_hda_codec_read(codec, pin_nid, 0,
1058 AC_VERB_GET_CONNECT_SEL, 0);
1059 if (curr != mux_idx)
1060 snd_hda_codec_write_cache(codec, pin_nid, 0,
1061 AC_VERB_SET_CONNECT_SEL,
1065 /* get the mux index for the converter of the pins
1066 * converter's mux index is the same for all pins on Intel platform
1068 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1073 for (i = 0; i < spec->num_cvts; i++)
1074 if (spec->cvt_nids[i] == cvt_nid)
1079 /* Intel HDMI workaround to fix audio routing issue:
1080 * For some Intel display codecs, pins share the same connection list.
1081 * So a conveter can be selected by multiple pins and playback on any of these
1082 * pins will generate sound on the external display, because audio flows from
1083 * the same converter to the display pipeline. Also muting one pin may make
1084 * other pins have no sound output.
1085 * So this function assures that an assigned converter for a pin is not selected
1086 * by any other pins.
1088 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1090 int dev_id, int mux_idx)
1092 struct hdmi_spec *spec = codec->spec;
1095 struct hdmi_spec_per_cvt *per_cvt;
1096 struct hdmi_spec_per_pin *per_pin;
1099 /* configure the pins connections */
1100 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1104 per_pin = get_pin(spec, pin_idx);
1106 * pin not connected to monitor
1107 * no need to operate on it
1112 if ((per_pin->pin_nid == pin_nid) &&
1113 (per_pin->dev_id == dev_id))
1117 * if per_pin->dev_id >= dev_num,
1118 * snd_hda_get_dev_select() will fail,
1119 * and the following operation is unpredictable.
1120 * So skip this situation.
1122 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1123 if (per_pin->dev_id >= dev_num)
1126 nid = per_pin->pin_nid;
1129 * Calling this function should not impact
1130 * on the device entry selection
1131 * So let's save the dev id for each pin,
1132 * and restore it when return
1134 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1135 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1136 curr = snd_hda_codec_read(codec, nid, 0,
1137 AC_VERB_GET_CONNECT_SEL, 0);
1138 if (curr != mux_idx) {
1139 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1144 /* choose an unassigned converter. The conveters in the
1145 * connection list are in the same order as in the codec.
1147 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1148 per_cvt = get_cvt(spec, cvt_idx);
1149 if (!per_cvt->assigned) {
1151 "choose cvt %d for pin NID 0x%x\n",
1153 snd_hda_codec_write_cache(codec, nid, 0,
1154 AC_VERB_SET_CONNECT_SEL,
1159 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1163 /* A wrapper of intel_not_share_asigned_cvt() */
1164 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1165 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1168 struct hdmi_spec *spec = codec->spec;
1170 /* On Intel platform, the mapping of converter nid to
1171 * mux index of the pins are always the same.
1172 * The pin nid may be 0, this means all pins will not
1173 * share the converter.
1175 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1177 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1180 /* skeleton caller of pin_cvt_fixup ops */
1181 static void pin_cvt_fixup(struct hda_codec *codec,
1182 struct hdmi_spec_per_pin *per_pin,
1185 struct hdmi_spec *spec = codec->spec;
1187 if (spec->ops.pin_cvt_fixup)
1188 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1191 /* called in hdmi_pcm_open when no pin is assigned to the PCM */
1192 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1193 struct hda_codec *codec,
1194 struct snd_pcm_substream *substream)
1196 struct hdmi_spec *spec = codec->spec;
1197 struct snd_pcm_runtime *runtime = substream->runtime;
1198 int cvt_idx, pcm_idx;
1199 struct hdmi_spec_per_cvt *per_cvt = NULL;
1202 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1206 err = hdmi_choose_cvt(codec, -1, &cvt_idx, false);
1210 per_cvt = get_cvt(spec, cvt_idx);
1211 per_cvt->assigned = true;
1212 hinfo->nid = per_cvt->cvt_nid;
1214 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1216 set_bit(pcm_idx, &spec->pcm_in_use);
1217 /* todo: setup spdif ctls assign */
1219 /* Initially set the converter's capabilities */
1220 hinfo->channels_min = per_cvt->channels_min;
1221 hinfo->channels_max = per_cvt->channels_max;
1222 hinfo->rates = per_cvt->rates;
1223 hinfo->formats = per_cvt->formats;
1224 hinfo->maxbps = per_cvt->maxbps;
1226 /* Store the updated parameters */
1227 runtime->hw.channels_min = hinfo->channels_min;
1228 runtime->hw.channels_max = hinfo->channels_max;
1229 runtime->hw.formats = hinfo->formats;
1230 runtime->hw.rates = hinfo->rates;
1232 snd_pcm_hw_constraint_step(substream->runtime, 0,
1233 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1240 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1241 struct hda_codec *codec,
1242 struct snd_pcm_substream *substream)
1244 struct hdmi_spec *spec = codec->spec;
1245 struct snd_pcm_runtime *runtime = substream->runtime;
1246 int pin_idx, cvt_idx, pcm_idx;
1247 struct hdmi_spec_per_pin *per_pin;
1248 struct hdmi_eld *eld;
1249 struct hdmi_spec_per_cvt *per_cvt = NULL;
1252 /* Validate hinfo */
1253 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1257 mutex_lock(&spec->pcm_lock);
1258 pin_idx = hinfo_to_pin_index(codec, hinfo);
1259 /* no pin is assigned to the PCM
1260 * PA need pcm open successfully when probe
1263 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1267 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false);
1271 per_cvt = get_cvt(spec, cvt_idx);
1272 /* Claim converter */
1273 per_cvt->assigned = true;
1275 set_bit(pcm_idx, &spec->pcm_in_use);
1276 per_pin = get_pin(spec, pin_idx);
1277 per_pin->cvt_nid = per_cvt->cvt_nid;
1278 hinfo->nid = per_cvt->cvt_nid;
1280 /* flip stripe flag for the assigned stream if supported */
1281 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1282 azx_stream(get_azx_dev(substream))->stripe = 1;
1284 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1285 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1286 AC_VERB_SET_CONNECT_SEL,
1289 /* configure unused pins to choose other converters */
1290 pin_cvt_fixup(codec, per_pin, 0);
1292 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1294 /* Initially set the converter's capabilities */
1295 hinfo->channels_min = per_cvt->channels_min;
1296 hinfo->channels_max = per_cvt->channels_max;
1297 hinfo->rates = per_cvt->rates;
1298 hinfo->formats = per_cvt->formats;
1299 hinfo->maxbps = per_cvt->maxbps;
1301 eld = &per_pin->sink_eld;
1302 /* Restrict capabilities by ELD if this isn't disabled */
1303 if (!static_hdmi_pcm && eld->eld_valid) {
1304 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1305 if (hinfo->channels_min > hinfo->channels_max ||
1306 !hinfo->rates || !hinfo->formats) {
1307 per_cvt->assigned = false;
1309 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1315 /* Store the updated parameters */
1316 runtime->hw.channels_min = hinfo->channels_min;
1317 runtime->hw.channels_max = hinfo->channels_max;
1318 runtime->hw.formats = hinfo->formats;
1319 runtime->hw.rates = hinfo->rates;
1321 snd_pcm_hw_constraint_step(substream->runtime, 0,
1322 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1324 mutex_unlock(&spec->pcm_lock);
1329 * HDA/HDMI auto parsing
1331 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1333 struct hdmi_spec *spec = codec->spec;
1334 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1335 hda_nid_t pin_nid = per_pin->pin_nid;
1336 int dev_id = per_pin->dev_id;
1339 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1341 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n",
1342 pin_nid, get_wcaps(codec, pin_nid));
1346 snd_hda_set_dev_select(codec, pin_nid, dev_id);
1348 if (spec->intel_hsw_fixup) {
1349 conns = spec->num_cvts;
1350 memcpy(per_pin->mux_nids, spec->cvt_nids,
1351 sizeof(hda_nid_t) * conns);
1353 conns = snd_hda_get_raw_connections(codec, pin_nid,
1355 HDA_MAX_CONNECTIONS);
1358 /* all the device entries on the same pin have the same conn list */
1359 per_pin->num_mux_nids = conns;
1364 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1365 struct hdmi_spec_per_pin *per_pin)
1369 for (i = 0; i < spec->pcm_used; i++) {
1370 if (!test_bit(i, &spec->pcm_bitmap))
1376 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1377 struct hdmi_spec_per_pin *per_pin)
1381 /* pcm already be attached to the pin */
1384 /* try the previously used slot at first */
1385 idx = per_pin->prev_pcm_idx;
1387 if (!test_bit(idx, &spec->pcm_bitmap))
1389 per_pin->prev_pcm_idx = -1; /* no longer valid, clear it */
1391 idx = hdmi_find_pcm_slot(spec, per_pin);
1395 per_pin->pcm_idx = idx;
1396 per_pin->pcm = get_hdmi_pcm(spec, idx);
1397 set_bit(idx, &spec->pcm_bitmap);
1400 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1401 struct hdmi_spec_per_pin *per_pin)
1405 /* pcm already be detached from the pin */
1408 idx = per_pin->pcm_idx;
1409 per_pin->pcm_idx = -1;
1410 per_pin->prev_pcm_idx = idx; /* remember the previous index */
1411 per_pin->pcm = NULL;
1412 if (idx >= 0 && idx < spec->pcm_used)
1413 clear_bit(idx, &spec->pcm_bitmap);
1416 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1417 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1421 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1422 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1427 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1429 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1430 struct hdmi_spec_per_pin *per_pin)
1432 struct hda_codec *codec = per_pin->codec;
1433 struct hda_pcm *pcm;
1434 struct hda_pcm_stream *hinfo;
1435 struct snd_pcm_substream *substream;
1439 if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used)
1441 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1444 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1447 /* hdmi audio only uses playback and one substream */
1448 hinfo = pcm->stream;
1449 substream = pcm->pcm->streams[0].substream;
1451 per_pin->cvt_nid = hinfo->nid;
1453 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1454 if (mux_idx < per_pin->num_mux_nids) {
1455 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1457 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1458 AC_VERB_SET_CONNECT_SEL,
1461 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1463 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1464 if (substream->runtime)
1465 per_pin->channels = substream->runtime->channels;
1466 per_pin->setup = true;
1467 per_pin->mux_idx = mux_idx;
1469 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1472 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1473 struct hdmi_spec_per_pin *per_pin)
1475 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1476 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1478 per_pin->chmap_set = false;
1479 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1481 per_pin->setup = false;
1482 per_pin->channels = 0;
1485 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1486 struct hdmi_spec_per_pin *per_pin)
1488 struct hdmi_spec *spec = codec->spec;
1490 if (per_pin->pcm_idx >= 0)
1491 return spec->pcm_rec[per_pin->pcm_idx].jack;
1496 /* update per_pin ELD from the given new ELD;
1497 * setup info frame and notification accordingly
1498 * also notify ELD kctl and report jack status changes
1500 static void update_eld(struct hda_codec *codec,
1501 struct hdmi_spec_per_pin *per_pin,
1502 struct hdmi_eld *eld,
1505 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1506 struct hdmi_spec *spec = codec->spec;
1507 struct snd_jack *pcm_jack;
1508 bool old_eld_valid = pin_eld->eld_valid;
1512 if (eld->eld_valid) {
1513 if (eld->eld_size <= 0 ||
1514 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1515 eld->eld_size) < 0) {
1516 eld->eld_valid = false;
1518 schedule_delayed_work(&per_pin->work,
1519 msecs_to_jiffies(300));
1525 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) {
1526 eld->eld_valid = false;
1530 /* for monitor disconnection, save pcm_idx firstly */
1531 pcm_idx = per_pin->pcm_idx;
1534 * pcm_idx >=0 before update_eld() means it is in monitor
1535 * disconnected event. Jack must be fetched before update_eld().
1537 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1539 if (!spec->static_pcm_mapping) {
1540 if (eld->eld_valid) {
1541 hdmi_attach_hda_pcm(spec, per_pin);
1542 hdmi_pcm_setup_pin(spec, per_pin);
1544 hdmi_pcm_reset_pin(spec, per_pin);
1545 hdmi_detach_hda_pcm(spec, per_pin);
1549 /* if pcm_idx == -1, it means this is in monitor connection event
1550 * we can get the correct pcm_idx now.
1553 pcm_idx = per_pin->pcm_idx;
1555 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1558 snd_hdmi_show_eld(codec, &eld->info);
1560 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1561 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1562 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1563 if (pin_eld->eld_size != eld->eld_size ||
1564 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1565 eld->eld_size) != 0)
1569 pin_eld->monitor_present = eld->monitor_present;
1570 pin_eld->eld_valid = eld->eld_valid;
1571 pin_eld->eld_size = eld->eld_size;
1573 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1575 pin_eld->info = eld->info;
1579 * Re-setup pin and infoframe. This is needed e.g. when
1580 * - sink is first plugged-in
1581 * - transcoder can change during stream playback on Haswell
1582 * and this can make HW reset converter selection on a pin.
1584 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1585 pin_cvt_fixup(codec, per_pin, 0);
1586 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1589 if (eld_changed && pcm_idx >= 0)
1590 snd_ctl_notify(codec->card,
1591 SNDRV_CTL_EVENT_MASK_VALUE |
1592 SNDRV_CTL_EVENT_MASK_INFO,
1593 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1595 if (eld_changed && pcm_jack)
1596 snd_jack_report(pcm_jack,
1597 (eld->monitor_present && eld->eld_valid) ?
1598 SND_JACK_AVOUT : 0);
1601 /* update ELD and jack state via HD-audio verbs */
1602 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1605 struct hda_codec *codec = per_pin->codec;
1606 struct hdmi_spec *spec = codec->spec;
1607 struct hdmi_eld *eld = &spec->temp_eld;
1608 struct device *dev = hda_codec_dev(codec);
1609 hda_nid_t pin_nid = per_pin->pin_nid;
1610 int dev_id = per_pin->dev_id;
1612 * Always execute a GetPinSense verb here, even when called from
1613 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1614 * response's PD bit is not the real PD value, but indicates that
1615 * the real PD value changed. An older version of the HD-audio
1616 * specification worked this way. Hence, we just ignore the data in
1617 * the unsolicited response to avoid custom WARs.
1623 if (dev->power.runtime_status == RPM_SUSPENDING)
1627 ret = snd_hda_power_up_pm(codec);
1628 if (ret < 0 && pm_runtime_suspended(dev))
1631 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1633 mutex_lock(&per_pin->lock);
1634 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1635 if (eld->monitor_present)
1636 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1638 eld->eld_valid = false;
1641 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n",
1642 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1644 if (eld->eld_valid) {
1645 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1646 eld->eld_buffer, &eld->eld_size) < 0)
1647 eld->eld_valid = false;
1650 update_eld(codec, per_pin, eld, repoll);
1651 mutex_unlock(&per_pin->lock);
1653 snd_hda_power_down_pm(codec);
1656 #define I915_SILENT_RATE 48000
1657 #define I915_SILENT_CHANNELS 2
1658 #define I915_SILENT_FORMAT_BITS 16
1659 #define I915_SILENT_FMT_MASK 0xf
1661 static void silent_stream_enable_i915(struct hda_codec *codec,
1662 struct hdmi_spec_per_pin *per_pin)
1664 unsigned int format;
1666 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1667 per_pin->dev_id, I915_SILENT_RATE);
1669 /* trigger silent stream generation in hw */
1670 format = snd_hdac_stream_format(I915_SILENT_CHANNELS, I915_SILENT_FORMAT_BITS,
1672 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
1673 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
1674 usleep_range(100, 200);
1675 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);
1677 per_pin->channels = I915_SILENT_CHANNELS;
1678 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1681 static void silent_stream_set_kae(struct hda_codec *codec,
1682 struct hdmi_spec_per_pin *per_pin,
1687 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid);
1689 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0);
1690 param = (param >> 16) & 0xff;
1693 param |= AC_DIG3_KAE;
1695 param &= ~AC_DIG3_KAE;
1697 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param);
1700 static void silent_stream_enable(struct hda_codec *codec,
1701 struct hdmi_spec_per_pin *per_pin)
1703 struct hdmi_spec *spec = codec->spec;
1704 struct hdmi_spec_per_cvt *per_cvt;
1705 int cvt_idx, pin_idx, err;
1709 * Power-up will call hdmi_present_sense, so the PM calls
1710 * have to be done without mutex held.
1713 err = snd_hda_power_up_pm(codec);
1714 if (err < 0 && err != -EACCES) {
1716 "Failed to power up codec for silent stream enable ret=[%d]\n", err);
1717 snd_hda_power_down_pm(codec);
1721 mutex_lock(&per_pin->lock);
1723 if (per_pin->setup) {
1724 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n");
1729 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id);
1730 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true);
1732 codec_err(codec, "hdmi: no free converter to enable silent mode\n");
1736 per_cvt = get_cvt(spec, cvt_idx);
1737 per_cvt->silent_stream = true;
1738 per_pin->cvt_nid = per_cvt->cvt_nid;
1739 per_pin->silent_stream = true;
1741 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n",
1742 per_pin->pin_nid, per_cvt->cvt_nid);
1744 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1745 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1746 AC_VERB_SET_CONNECT_SEL,
1749 /* configure unused pins to choose other converters */
1750 pin_cvt_fixup(codec, per_pin, 0);
1752 switch (spec->silent_stream_type) {
1753 case SILENT_STREAM_KAE:
1754 silent_stream_enable_i915(codec, per_pin);
1755 silent_stream_set_kae(codec, per_pin, true);
1757 case SILENT_STREAM_I915:
1758 silent_stream_enable_i915(codec, per_pin);
1766 mutex_unlock(&per_pin->lock);
1768 if (err || !keep_power)
1769 snd_hda_power_down_pm(codec);
1772 static void silent_stream_disable(struct hda_codec *codec,
1773 struct hdmi_spec_per_pin *per_pin)
1775 struct hdmi_spec *spec = codec->spec;
1776 struct hdmi_spec_per_cvt *per_cvt;
1779 err = snd_hda_power_up_pm(codec);
1780 if (err < 0 && err != -EACCES) {
1782 "Failed to power up codec for silent stream disable ret=[%d]\n",
1784 snd_hda_power_down_pm(codec);
1788 mutex_lock(&per_pin->lock);
1789 if (!per_pin->silent_stream)
1792 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n",
1793 per_pin->pin_nid, per_pin->cvt_nid);
1795 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1796 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) {
1797 per_cvt = get_cvt(spec, cvt_idx);
1798 per_cvt->silent_stream = false;
1801 if (spec->silent_stream_type == SILENT_STREAM_I915) {
1802 /* release ref taken in silent_stream_enable() */
1803 snd_hda_power_down_pm(codec);
1804 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) {
1805 silent_stream_set_kae(codec, per_pin, false);
1808 per_pin->cvt_nid = 0;
1809 per_pin->silent_stream = false;
1812 mutex_unlock(&per_pin->lock);
1814 snd_hda_power_down_pm(codec);
1817 /* update ELD and jack state via audio component */
1818 static void sync_eld_via_acomp(struct hda_codec *codec,
1819 struct hdmi_spec_per_pin *per_pin)
1821 struct hdmi_spec *spec = codec->spec;
1822 struct hdmi_eld *eld = &spec->temp_eld;
1823 bool monitor_prev, monitor_next;
1825 mutex_lock(&per_pin->lock);
1826 eld->monitor_present = false;
1827 monitor_prev = per_pin->sink_eld.monitor_present;
1828 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1829 per_pin->dev_id, &eld->monitor_present,
1830 eld->eld_buffer, ELD_MAX_SIZE);
1831 eld->eld_valid = (eld->eld_size > 0);
1832 update_eld(codec, per_pin, eld, 0);
1833 monitor_next = per_pin->sink_eld.monitor_present;
1834 mutex_unlock(&per_pin->lock);
1836 if (spec->silent_stream_type) {
1837 if (!monitor_prev && monitor_next)
1838 silent_stream_enable(codec, per_pin);
1839 else if (monitor_prev && !monitor_next)
1840 silent_stream_disable(codec, per_pin);
1844 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1846 struct hda_codec *codec = per_pin->codec;
1848 if (!codec_has_acomp(codec))
1849 hdmi_present_sense_via_verbs(per_pin, repoll);
1851 sync_eld_via_acomp(codec, per_pin);
1854 static void hdmi_repoll_eld(struct work_struct *work)
1856 struct hdmi_spec_per_pin *per_pin =
1857 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1858 struct hda_codec *codec = per_pin->codec;
1859 struct hdmi_spec *spec = codec->spec;
1860 struct hda_jack_tbl *jack;
1862 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1865 jack->jack_dirty = 1;
1867 if (per_pin->repoll_count++ > 6)
1868 per_pin->repoll_count = 0;
1870 mutex_lock(&spec->pcm_lock);
1871 hdmi_present_sense(per_pin, per_pin->repoll_count);
1872 mutex_unlock(&spec->pcm_lock);
1875 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1877 struct hdmi_spec *spec = codec->spec;
1878 unsigned int caps, config;
1880 struct hdmi_spec_per_pin *per_pin;
1884 caps = snd_hda_query_pin_caps(codec, pin_nid);
1885 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1889 * For DP MST audio, Configuration Default is the same for
1890 * all device entries on the same pin
1892 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1893 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1894 !spec->force_connect)
1898 * To simplify the implementation, malloc all
1899 * the virtual pins in the initialization statically
1901 if (spec->intel_hsw_fixup) {
1903 * On Intel platforms, device entries count returned
1904 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on
1905 * the type of receiver that is connected. Allocate pin
1906 * structures based on worst case.
1908 dev_num = spec->dev_num;
1909 } else if (codec->dp_mst) {
1910 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1912 * spec->dev_num is the maxinum number of device entries
1913 * among all the pins
1915 spec->dev_num = (spec->dev_num > dev_num) ?
1916 spec->dev_num : dev_num;
1919 * If the platform doesn't support DP MST,
1920 * manually set dev_num to 1. This means
1921 * the pin has only one device entry.
1927 for (i = 0; i < dev_num; i++) {
1928 pin_idx = spec->num_pins;
1929 per_pin = snd_array_new(&spec->pins);
1934 per_pin->pcm = NULL;
1935 per_pin->pcm_idx = -1;
1936 per_pin->prev_pcm_idx = -1;
1937 per_pin->pin_nid = pin_nid;
1938 per_pin->pin_nid_idx = spec->num_nids;
1939 per_pin->dev_id = i;
1940 per_pin->non_pcm = false;
1941 snd_hda_set_dev_select(codec, pin_nid, i);
1942 err = hdmi_read_pin_conn(codec, pin_idx);
1945 if (!is_jack_detectable(codec, pin_nid))
1946 codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid);
1954 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1956 struct hdmi_spec *spec = codec->spec;
1957 struct hdmi_spec_per_cvt *per_cvt;
1961 chans = get_wcaps(codec, cvt_nid);
1962 chans = get_wcaps_channels(chans);
1964 per_cvt = snd_array_new(&spec->cvts);
1968 per_cvt->cvt_nid = cvt_nid;
1969 per_cvt->channels_min = 2;
1971 per_cvt->channels_max = chans;
1972 if (chans > spec->chmap.channels_max)
1973 spec->chmap.channels_max = chans;
1976 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1984 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1985 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1991 static const struct snd_pci_quirk force_connect_list[] = {
1992 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
1993 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
1994 SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1),
1995 SND_PCI_QUIRK(0x103c, 0x8715, "HP", 1),
1996 SND_PCI_QUIRK(0x1043, 0x86ae, "ASUS", 1), /* Z170 PRO */
1997 SND_PCI_QUIRK(0x1043, 0x86c7, "ASUS", 1), /* Z170M PLUS */
1998 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
1999 SND_PCI_QUIRK(0x8086, 0x2060, "Intel NUC5CPYB", 1),
2000 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1),
2004 static int hdmi_parse_codec(struct hda_codec *codec)
2006 struct hdmi_spec *spec = codec->spec;
2007 hda_nid_t start_nid;
2010 const struct snd_pci_quirk *q;
2012 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
2013 if (!start_nid || nodes < 0) {
2014 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
2018 if (enable_all_pins)
2019 spec->force_connect = true;
2021 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
2024 spec->force_connect = true;
2027 * hdmi_add_pin() assumes total amount of converters to
2028 * be known, so first discover all converters
2030 for (i = 0; i < nodes; i++) {
2031 hda_nid_t nid = start_nid + i;
2033 caps = get_wcaps(codec, nid);
2035 if (!(caps & AC_WCAP_DIGITAL))
2038 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
2039 hdmi_add_cvt(codec, nid);
2042 /* discover audio pins */
2043 for (i = 0; i < nodes; i++) {
2044 hda_nid_t nid = start_nid + i;
2046 caps = get_wcaps(codec, nid);
2048 if (!(caps & AC_WCAP_DIGITAL))
2051 if (get_wcaps_type(caps) == AC_WID_PIN)
2052 hdmi_add_pin(codec, nid);
2060 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
2062 struct hda_spdif_out *spdif;
2065 mutex_lock(&codec->spdif_mutex);
2066 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
2067 /* Add sanity check to pass klockwork check.
2068 * This should never happen.
2070 if (WARN_ON(spdif == NULL)) {
2071 mutex_unlock(&codec->spdif_mutex);
2074 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
2075 mutex_unlock(&codec->spdif_mutex);
2083 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2084 struct hda_codec *codec,
2085 unsigned int stream_tag,
2086 unsigned int format,
2087 struct snd_pcm_substream *substream)
2089 hda_nid_t cvt_nid = hinfo->nid;
2090 struct hdmi_spec *spec = codec->spec;
2092 struct hdmi_spec_per_pin *per_pin;
2093 struct snd_pcm_runtime *runtime = substream->runtime;
2098 mutex_lock(&spec->pcm_lock);
2099 pin_idx = hinfo_to_pin_index(codec, hinfo);
2101 /* when pcm is not bound to a pin skip pin setup and return 0
2102 * to make audio playback be ongoing
2104 pin_cvt_fixup(codec, NULL, cvt_nid);
2105 snd_hda_codec_setup_stream(codec, cvt_nid,
2106 stream_tag, 0, format);
2110 per_pin = get_pin(spec, pin_idx);
2112 /* Verify pin:cvt selections to avoid silent audio after S3.
2113 * After S3, the audio driver restores pin:cvt selections
2114 * but this can happen before gfx is ready and such selection
2115 * is overlooked by HW. Thus multiple pins can share a same
2116 * default convertor and mute control will affect each other,
2117 * which can cause a resumed audio playback become silent
2120 pin_cvt_fixup(codec, per_pin, 0);
2122 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2123 /* Todo: add DP1.2 MST audio support later */
2124 if (codec_has_acomp(codec))
2125 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
2126 per_pin->dev_id, runtime->rate);
2128 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
2129 mutex_lock(&per_pin->lock);
2130 per_pin->channels = substream->runtime->channels;
2131 per_pin->setup = true;
2133 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2134 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2136 snd_hda_codec_write(codec, cvt_nid, 0,
2137 AC_VERB_SET_STRIPE_CONTROL,
2141 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2142 mutex_unlock(&per_pin->lock);
2143 if (spec->dyn_pin_out) {
2144 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2146 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2147 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2148 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2149 AC_VERB_SET_PIN_WIDGET_CONTROL,
2153 /* snd_hda_set_dev_select() has been called before */
2154 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2155 per_pin->dev_id, stream_tag, format);
2157 mutex_unlock(&spec->pcm_lock);
2161 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2162 struct hda_codec *codec,
2163 struct snd_pcm_substream *substream)
2165 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2169 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2170 struct hda_codec *codec,
2171 struct snd_pcm_substream *substream)
2173 struct hdmi_spec *spec = codec->spec;
2174 int cvt_idx, pin_idx, pcm_idx;
2175 struct hdmi_spec_per_cvt *per_cvt;
2176 struct hdmi_spec_per_pin *per_pin;
2180 mutex_lock(&spec->pcm_lock);
2182 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2183 if (snd_BUG_ON(pcm_idx < 0)) {
2187 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2188 if (snd_BUG_ON(cvt_idx < 0)) {
2192 per_cvt = get_cvt(spec, cvt_idx);
2193 per_cvt->assigned = false;
2196 azx_stream(get_azx_dev(substream))->stripe = 0;
2198 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2199 clear_bit(pcm_idx, &spec->pcm_in_use);
2200 pin_idx = hinfo_to_pin_index(codec, hinfo);
2202 * In such a case, return 0 to match the behavior in
2208 per_pin = get_pin(spec, pin_idx);
2210 if (spec->dyn_pin_out) {
2211 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2213 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2214 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2215 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2216 AC_VERB_SET_PIN_WIDGET_CONTROL,
2220 mutex_lock(&per_pin->lock);
2221 per_pin->chmap_set = false;
2222 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2224 per_pin->setup = false;
2225 per_pin->channels = 0;
2226 mutex_unlock(&per_pin->lock);
2230 mutex_unlock(&spec->pcm_lock);
2235 static const struct hda_pcm_ops generic_ops = {
2236 .open = hdmi_pcm_open,
2237 .close = hdmi_pcm_close,
2238 .prepare = generic_hdmi_playback_pcm_prepare,
2239 .cleanup = generic_hdmi_playback_pcm_cleanup,
2242 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2244 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2245 struct hdmi_spec *spec = codec->spec;
2246 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2251 return per_pin->sink_eld.info.spk_alloc;
2254 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2255 unsigned char *chmap)
2257 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2258 struct hdmi_spec *spec = codec->spec;
2259 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2261 /* chmap is already set to 0 in caller */
2265 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2268 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2269 unsigned char *chmap, int prepared)
2271 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2272 struct hdmi_spec *spec = codec->spec;
2273 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2277 mutex_lock(&per_pin->lock);
2278 per_pin->chmap_set = true;
2279 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2281 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2282 mutex_unlock(&per_pin->lock);
2285 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2287 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2288 struct hdmi_spec *spec = codec->spec;
2289 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2291 return per_pin ? true:false;
2294 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2296 struct hdmi_spec *spec = codec->spec;
2299 /* limit the PCM devices to the codec converters or available PINs */
2300 pcm_num = min(spec->num_cvts, spec->num_pins);
2301 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2303 for (idx = 0; idx < pcm_num; idx++) {
2304 struct hdmi_spec_per_cvt *per_cvt;
2305 struct hda_pcm *info;
2306 struct hda_pcm_stream *pstr;
2308 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2312 spec->pcm_rec[idx].pcm = info;
2314 info->pcm_type = HDA_PCM_TYPE_HDMI;
2315 info->own_chmap = true;
2317 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2318 pstr->substreams = 1;
2319 pstr->ops = generic_ops;
2321 per_cvt = get_cvt(spec, 0);
2322 pstr->channels_min = per_cvt->channels_min;
2323 pstr->channels_max = per_cvt->channels_max;
2325 /* pcm number is less than pcm_rec array size */
2326 if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec))
2328 /* other pstr fields are set in open */
2334 static void free_hdmi_jack_priv(struct snd_jack *jack)
2336 struct hdmi_pcm *pcm = jack->private_data;
2341 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2343 char hdmi_str[32] = "HDMI/DP";
2344 struct hdmi_spec *spec = codec->spec;
2345 struct snd_jack *jack;
2346 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2350 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2352 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2357 spec->pcm_rec[pcm_idx].jack = jack;
2358 jack->private_data = &spec->pcm_rec[pcm_idx];
2359 jack->private_free = free_hdmi_jack_priv;
2363 static int generic_hdmi_build_controls(struct hda_codec *codec)
2365 struct hdmi_spec *spec = codec->spec;
2367 int pin_idx, pcm_idx;
2369 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2370 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2371 /* no PCM: mark this for skipping permanently */
2372 set_bit(pcm_idx, &spec->pcm_bitmap);
2376 err = generic_hdmi_build_jack(codec, pcm_idx);
2380 /* create the spdif for each pcm
2381 * pin will be bound when monitor is connected
2383 err = snd_hda_create_dig_out_ctls(codec,
2384 0, spec->cvt_nids[0],
2388 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2390 dev = get_pcm_rec(spec, pcm_idx)->device;
2391 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2392 /* add control for ELD Bytes */
2393 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2399 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2400 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2401 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2403 if (spec->static_pcm_mapping) {
2404 hdmi_attach_hda_pcm(spec, per_pin);
2405 hdmi_pcm_setup_pin(spec, per_pin);
2408 pin_eld->eld_valid = false;
2409 hdmi_present_sense(per_pin, 0);
2412 /* add channel maps */
2413 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2414 struct hda_pcm *pcm;
2416 pcm = get_pcm_rec(spec, pcm_idx);
2417 if (!pcm || !pcm->pcm)
2419 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2427 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2429 struct hdmi_spec *spec = codec->spec;
2432 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2433 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2435 per_pin->codec = codec;
2436 mutex_init(&per_pin->lock);
2437 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2438 eld_proc_new(per_pin, pin_idx);
2443 static int generic_hdmi_init(struct hda_codec *codec)
2445 struct hdmi_spec *spec = codec->spec;
2448 mutex_lock(&spec->bind_lock);
2449 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2450 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2451 hda_nid_t pin_nid = per_pin->pin_nid;
2452 int dev_id = per_pin->dev_id;
2454 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2455 hdmi_init_pin(codec, pin_nid);
2456 if (codec_has_acomp(codec))
2458 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2461 mutex_unlock(&spec->bind_lock);
2465 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2467 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2468 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2471 static void hdmi_array_free(struct hdmi_spec *spec)
2473 snd_array_free(&spec->pins);
2474 snd_array_free(&spec->cvts);
2477 static void generic_spec_free(struct hda_codec *codec)
2479 struct hdmi_spec *spec = codec->spec;
2482 hdmi_array_free(spec);
2486 codec->dp_mst = false;
2489 static void generic_hdmi_free(struct hda_codec *codec)
2491 struct hdmi_spec *spec = codec->spec;
2492 int pin_idx, pcm_idx;
2494 if (spec->acomp_registered) {
2495 snd_hdac_acomp_exit(&codec->bus->core);
2496 } else if (codec_has_acomp(codec)) {
2497 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2499 codec->relaxed_resume = 0;
2501 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2502 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2503 cancel_delayed_work_sync(&per_pin->work);
2504 eld_proc_free(per_pin);
2507 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2508 if (spec->pcm_rec[pcm_idx].jack == NULL)
2510 snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack);
2513 generic_spec_free(codec);
2517 static int generic_hdmi_suspend(struct hda_codec *codec)
2519 struct hdmi_spec *spec = codec->spec;
2522 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2523 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2524 cancel_delayed_work_sync(&per_pin->work);
2529 static int generic_hdmi_resume(struct hda_codec *codec)
2531 struct hdmi_spec *spec = codec->spec;
2534 codec->patch_ops.init(codec);
2535 snd_hda_regmap_sync(codec);
2537 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2538 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2539 hdmi_present_sense(per_pin, 1);
2545 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2546 .init = generic_hdmi_init,
2547 .free = generic_hdmi_free,
2548 .build_pcms = generic_hdmi_build_pcms,
2549 .build_controls = generic_hdmi_build_controls,
2550 .unsol_event = hdmi_unsol_event,
2552 .suspend = generic_hdmi_suspend,
2553 .resume = generic_hdmi_resume,
2557 static const struct hdmi_ops generic_standard_hdmi_ops = {
2558 .pin_get_eld = hdmi_pin_get_eld,
2559 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2560 .pin_hbr_setup = hdmi_pin_hbr_setup,
2561 .setup_stream = hdmi_setup_stream,
2564 /* allocate codec->spec and assign/initialize generic parser ops */
2565 static int alloc_generic_hdmi(struct hda_codec *codec)
2567 struct hdmi_spec *spec;
2569 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2573 spec->codec = codec;
2574 spec->ops = generic_standard_hdmi_ops;
2575 spec->dev_num = 1; /* initialize to 1 */
2576 mutex_init(&spec->pcm_lock);
2577 mutex_init(&spec->bind_lock);
2578 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2580 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2581 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2582 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2583 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc;
2586 hdmi_array_init(spec, 4);
2588 codec->patch_ops = generic_hdmi_patch_ops;
2593 /* generic HDMI parser */
2594 static int patch_generic_hdmi(struct hda_codec *codec)
2598 err = alloc_generic_hdmi(codec);
2602 err = hdmi_parse_codec(codec);
2604 generic_spec_free(codec);
2608 generic_hdmi_init_per_pins(codec);
2613 * generic audio component binding
2616 /* turn on / off the unsol event jack detection dynamically */
2617 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2618 int dev_id, bool use_acomp)
2620 struct hda_jack_tbl *tbl;
2622 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2624 /* clear unsol even if component notifier is used, or re-enable
2625 * if notifier is cleared
2627 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2628 snd_hda_codec_write_cache(codec, nid, 0,
2629 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2633 /* set up / clear component notifier dynamically */
2634 static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2637 struct hdmi_spec *spec;
2640 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2641 mutex_lock(&spec->bind_lock);
2642 spec->use_acomp_notifier = use_acomp;
2643 spec->codec->relaxed_resume = use_acomp;
2644 spec->codec->bus->keep_power = 0;
2645 /* reprogram each jack detection logic depending on the notifier */
2646 for (i = 0; i < spec->num_pins; i++)
2647 reprogram_jack_detect(spec->codec,
2648 get_pin(spec, i)->pin_nid,
2649 get_pin(spec, i)->dev_id,
2651 mutex_unlock(&spec->bind_lock);
2654 /* enable / disable the notifier via master bind / unbind */
2655 static int generic_acomp_master_bind(struct device *dev,
2656 struct drm_audio_component *acomp)
2658 generic_acomp_notifier_set(acomp, true);
2662 static void generic_acomp_master_unbind(struct device *dev,
2663 struct drm_audio_component *acomp)
2665 generic_acomp_notifier_set(acomp, false);
2668 /* check whether both HD-audio and DRM PCI devices belong to the same bus */
2669 static int match_bound_vga(struct device *dev, int subtype, void *data)
2671 struct hdac_bus *bus = data;
2672 struct pci_dev *pci, *master;
2674 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2676 master = to_pci_dev(bus->dev);
2677 pci = to_pci_dev(dev);
2678 return master->bus == pci->bus;
2681 /* audio component notifier for AMD/Nvidia HDMI codecs */
2682 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2684 struct hda_codec *codec = audio_ptr;
2685 struct hdmi_spec *spec = codec->spec;
2686 hda_nid_t pin_nid = spec->port2pin(codec, port);
2690 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2692 /* skip notification during system suspend (but not in runtime PM);
2693 * the state will be updated at resume
2695 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2698 check_presence_and_report(codec, pin_nid, dev_id);
2701 /* set up the private drm_audio_ops from the template */
2702 static void setup_drm_audio_ops(struct hda_codec *codec,
2703 const struct drm_audio_component_audio_ops *ops)
2705 struct hdmi_spec *spec = codec->spec;
2707 spec->drm_audio_ops.audio_ptr = codec;
2708 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2709 * will call pin_eld_notify with using audio_ptr pointer
2710 * We need make sure audio_ptr is really setup
2713 spec->drm_audio_ops.pin2port = ops->pin2port;
2714 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2715 spec->drm_audio_ops.master_bind = ops->master_bind;
2716 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2719 /* initialize the generic HDMI audio component */
2720 static void generic_acomp_init(struct hda_codec *codec,
2721 const struct drm_audio_component_audio_ops *ops,
2722 int (*port2pin)(struct hda_codec *, int))
2724 struct hdmi_spec *spec = codec->spec;
2726 if (!enable_acomp) {
2727 codec_info(codec, "audio component disabled by module option\n");
2731 spec->port2pin = port2pin;
2732 setup_drm_audio_ops(codec, ops);
2733 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2734 match_bound_vga, 0)) {
2735 spec->acomp_registered = true;
2740 * Intel codec parsers and helpers
2743 #define INTEL_GET_VENDOR_VERB 0xf81
2744 #define INTEL_SET_VENDOR_VERB 0x781
2745 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2746 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2748 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2751 unsigned int vendor_param;
2752 struct hdmi_spec *spec = codec->spec;
2754 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2755 INTEL_GET_VENDOR_VERB, 0);
2756 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2759 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2760 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2761 INTEL_SET_VENDOR_VERB, vendor_param);
2762 if (vendor_param == -1)
2766 snd_hda_codec_update_widgets(codec);
2769 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2771 unsigned int vendor_param;
2772 struct hdmi_spec *spec = codec->spec;
2774 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2775 INTEL_GET_VENDOR_VERB, 0);
2776 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2779 /* enable DP1.2 mode */
2780 vendor_param |= INTEL_EN_DP12;
2781 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2782 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2783 INTEL_SET_VENDOR_VERB, vendor_param);
2786 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2787 * Otherwise you may get severe h/w communication errors.
2789 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2790 unsigned int power_state)
2792 if (power_state == AC_PWRST_D0) {
2793 intel_haswell_enable_all_pins(codec, false);
2794 intel_haswell_fixup_enable_dp12(codec);
2797 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2798 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2801 /* There is a fixed mapping between audio pin node and display port.
2802 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2803 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2804 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2805 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2808 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2809 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2810 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2812 static int intel_base_nid(struct hda_codec *codec)
2814 switch (codec->core.vendor_id) {
2815 case 0x80860054: /* ILK */
2816 case 0x80862804: /* ILK */
2817 case 0x80862882: /* VLV */
2824 static int intel_pin2port(void *audio_ptr, int pin_nid)
2826 struct hda_codec *codec = audio_ptr;
2827 struct hdmi_spec *spec = codec->spec;
2830 if (!spec->port_num) {
2831 base_nid = intel_base_nid(codec);
2832 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2834 return pin_nid - base_nid + 1;
2838 * looking for the pin number in the mapping table and return
2839 * the index which indicate the port number
2841 for (i = 0; i < spec->port_num; i++) {
2842 if (pin_nid == spec->port_map[i])
2846 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid);
2850 static int intel_port2pin(struct hda_codec *codec, int port)
2852 struct hdmi_spec *spec = codec->spec;
2854 if (!spec->port_num) {
2855 /* we assume only from port-B to port-D */
2856 if (port < 1 || port > 3)
2858 return port + intel_base_nid(codec) - 1;
2861 if (port < 0 || port >= spec->port_num)
2863 return spec->port_map[port];
2866 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2868 struct hda_codec *codec = audio_ptr;
2872 pin_nid = intel_port2pin(codec, port);
2875 /* skip notification during system suspend (but not in runtime PM);
2876 * the state will be updated at resume
2878 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2881 snd_hdac_i915_set_bclk(&codec->bus->core);
2882 check_presence_and_report(codec, pin_nid, dev_id);
2885 static const struct drm_audio_component_audio_ops intel_audio_ops = {
2886 .pin2port = intel_pin2port,
2887 .pin_eld_notify = intel_pin_eld_notify,
2890 /* register i915 component pin_eld_notify callback */
2891 static void register_i915_notifier(struct hda_codec *codec)
2893 struct hdmi_spec *spec = codec->spec;
2895 spec->use_acomp_notifier = true;
2896 spec->port2pin = intel_port2pin;
2897 setup_drm_audio_ops(codec, &intel_audio_ops);
2898 snd_hdac_acomp_register_notifier(&codec->bus->core,
2899 &spec->drm_audio_ops);
2900 /* no need for forcible resume for jack check thanks to notifier */
2901 codec->relaxed_resume = 1;
2904 /* setup_stream ops override for HSW+ */
2905 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2906 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2909 struct hdmi_spec *spec = codec->spec;
2910 int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id);
2911 struct hdmi_spec_per_pin *per_pin;
2917 per_pin = get_pin(spec, pin_idx);
2919 haswell_verify_D0(codec, cvt_nid, pin_nid);
2921 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
2922 silent_stream_set_kae(codec, per_pin, false);
2923 /* wait for pending transfers in codec to clear */
2924 usleep_range(100, 200);
2927 res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2928 stream_tag, format);
2930 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
2931 usleep_range(100, 200);
2932 silent_stream_set_kae(codec, per_pin, true);
2938 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2939 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2940 struct hdmi_spec_per_pin *per_pin,
2944 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2945 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2947 intel_verify_pin_cvt_connect(codec, per_pin);
2948 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2949 per_pin->dev_id, per_pin->mux_idx);
2951 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2956 static int i915_adlp_hdmi_suspend(struct hda_codec *codec)
2958 struct hdmi_spec *spec = codec->spec;
2959 bool silent_streams = false;
2962 res = generic_hdmi_suspend(codec);
2964 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2965 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2967 if (per_pin->silent_stream) {
2968 silent_streams = true;
2973 if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) {
2975 * stream-id should remain programmed when codec goes
2976 * to runtime suspend
2978 codec->no_stream_clean_at_suspend = 1;
2981 * the system might go to S3, in which case keep-alive
2982 * must be reprogrammed upon resume
2984 codec->forced_resume = 1;
2986 codec_dbg(codec, "HDMI: KAE active at suspend\n");
2988 codec->no_stream_clean_at_suspend = 0;
2989 codec->forced_resume = 0;
2995 static int i915_adlp_hdmi_resume(struct hda_codec *codec)
2997 struct hdmi_spec *spec = codec->spec;
3000 res = generic_hdmi_resume(codec);
3002 /* KAE not programmed at suspend, nothing to do here */
3003 if (!codec->no_stream_clean_at_suspend)
3006 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3007 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3010 * If system was in suspend with monitor connected,
3011 * the codec setting may have been lost. Re-enable
3014 if (per_pin->silent_stream) {
3017 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
3018 AC_VERB_GET_CONV, 0);
3020 codec_dbg(codec, "HDMI: KAE: restore stream id\n");
3021 silent_stream_enable_i915(codec, per_pin);
3024 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
3025 AC_VERB_GET_DIGI_CONVERT_1, 0);
3026 if (!(param & (AC_DIG3_KAE << 16))) {
3027 codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n");
3028 silent_stream_set_kae(codec, per_pin, true);
3037 /* precondition and allocation for Intel codecs */
3038 static int alloc_intel_hdmi(struct hda_codec *codec)
3042 /* requires i915 binding */
3043 if (!codec->bus->core.audio_component) {
3044 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
3045 /* set probe_id here to prevent generic fallback binding */
3046 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
3050 err = alloc_generic_hdmi(codec);
3053 /* no need to handle unsol events */
3054 codec->patch_ops.unsol_event = NULL;
3058 /* parse and post-process for Intel codecs */
3059 static int parse_intel_hdmi(struct hda_codec *codec)
3061 int err, retries = 3;
3064 err = hdmi_parse_codec(codec);
3065 } while (err < 0 && retries--);
3068 generic_spec_free(codec);
3072 generic_hdmi_init_per_pins(codec);
3073 register_i915_notifier(codec);
3077 /* Intel Haswell and onwards; audio component with eld notifier */
3078 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
3079 const int *port_map, int port_num, int dev_num,
3080 bool send_silent_stream)
3082 struct hdmi_spec *spec;
3085 err = alloc_intel_hdmi(codec);
3089 codec->dp_mst = true;
3090 spec->vendor_nid = vendor_nid;
3091 spec->port_map = port_map;
3092 spec->port_num = port_num;
3093 spec->intel_hsw_fixup = true;
3094 spec->dev_num = dev_num;
3096 intel_haswell_enable_all_pins(codec, true);
3097 intel_haswell_fixup_enable_dp12(codec);
3099 codec->display_power_control = 1;
3101 codec->patch_ops.set_power_state = haswell_set_power_state;
3102 codec->depop_delay = 0;
3103 codec->auto_runtime_pm = 1;
3105 spec->ops.setup_stream = i915_hsw_setup_stream;
3106 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3109 * Enable silent stream feature, if it is enabled via
3110 * module param or Kconfig option
3112 if (send_silent_stream)
3113 spec->silent_stream_type = SILENT_STREAM_I915;
3115 return parse_intel_hdmi(codec);
3118 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
3120 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
3121 enable_silent_stream);
3124 static int patch_i915_glk_hdmi(struct hda_codec *codec)
3127 * Silent stream calls audio component .get_power() from
3128 * .pin_eld_notify(). On GLK this will deadlock in i915 due
3129 * to the audio vs. CDCLK workaround.
3131 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
3134 static int patch_i915_icl_hdmi(struct hda_codec *codec)
3137 * pin to port mapping table where the value indicate the pin number and
3138 * the index indicate the port number.
3140 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
3142 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
3143 enable_silent_stream);
3146 static int patch_i915_tgl_hdmi(struct hda_codec *codec)
3149 * pin to port mapping table where the value indicate the pin number and
3150 * the index indicate the port number.
3152 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
3154 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
3155 enable_silent_stream);
3158 static int patch_i915_adlp_hdmi(struct hda_codec *codec)
3160 struct hdmi_spec *spec;
3163 res = patch_i915_tgl_hdmi(codec);
3167 if (spec->silent_stream_type) {
3168 spec->silent_stream_type = SILENT_STREAM_KAE;
3171 codec->patch_ops.resume = i915_adlp_hdmi_resume;
3172 codec->patch_ops.suspend = i915_adlp_hdmi_suspend;
3180 /* Intel Baytrail and Braswell; with eld notifier */
3181 static int patch_i915_byt_hdmi(struct hda_codec *codec)
3183 struct hdmi_spec *spec;
3186 err = alloc_intel_hdmi(codec);
3191 /* For Valleyview/Cherryview, only the display codec is in the display
3192 * power well and can use link_power ops to request/release the power.
3194 codec->display_power_control = 1;
3196 codec->depop_delay = 0;
3197 codec->auto_runtime_pm = 1;
3199 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3201 return parse_intel_hdmi(codec);
3204 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
3205 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
3209 err = alloc_intel_hdmi(codec);
3212 return parse_intel_hdmi(codec);
3216 * Shared non-generic implementations
3219 static int simple_playback_build_pcms(struct hda_codec *codec)
3221 struct hdmi_spec *spec = codec->spec;
3222 struct hda_pcm *info;
3224 struct hda_pcm_stream *pstr;
3225 struct hdmi_spec_per_cvt *per_cvt;
3227 per_cvt = get_cvt(spec, 0);
3228 chans = get_wcaps(codec, per_cvt->cvt_nid);
3229 chans = get_wcaps_channels(chans);
3231 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
3234 spec->pcm_rec[0].pcm = info;
3235 info->pcm_type = HDA_PCM_TYPE_HDMI;
3236 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
3237 *pstr = spec->pcm_playback;
3238 pstr->nid = per_cvt->cvt_nid;
3239 if (pstr->channels_max <= 2 && chans && chans <= 16)
3240 pstr->channels_max = chans;
3245 /* unsolicited event for jack sensing */
3246 static void simple_hdmi_unsol_event(struct hda_codec *codec,
3249 snd_hda_jack_set_dirty_all(codec);
3250 snd_hda_jack_report_sync(codec);
3253 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
3254 * as long as spec->pins[] is set correctly
3256 #define simple_hdmi_build_jack generic_hdmi_build_jack
3258 static int simple_playback_build_controls(struct hda_codec *codec)
3260 struct hdmi_spec *spec = codec->spec;
3261 struct hdmi_spec_per_cvt *per_cvt;
3264 per_cvt = get_cvt(spec, 0);
3265 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3270 return simple_hdmi_build_jack(codec, 0);
3273 static int simple_playback_init(struct hda_codec *codec)
3275 struct hdmi_spec *spec = codec->spec;
3276 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3277 hda_nid_t pin = per_pin->pin_nid;
3279 snd_hda_codec_write(codec, pin, 0,
3280 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3281 /* some codecs require to unmute the pin */
3282 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3283 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3285 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3289 static void simple_playback_free(struct hda_codec *codec)
3291 struct hdmi_spec *spec = codec->spec;
3293 hdmi_array_free(spec);
3298 * Nvidia specific implementations
3301 #define Nv_VERB_SET_Channel_Allocation 0xF79
3302 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3303 #define Nv_VERB_SET_Audio_Protection_On 0xF98
3304 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
3306 #define nvhdmi_master_con_nid_7x 0x04
3307 #define nvhdmi_master_pin_nid_7x 0x05
3309 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3310 /*front, rear, clfe, rear_surr */
3314 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3315 /* set audio protect on */
3316 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3317 /* enable digital output on pin widget */
3318 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3322 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3323 /* set audio protect on */
3324 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3325 /* enable digital output on pin widget */
3326 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3327 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3328 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3329 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3330 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3334 #ifdef LIMITED_RATE_FMT_SUPPORT
3335 /* support only the safe format and rate */
3336 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3337 #define SUPPORTED_MAXBPS 16
3338 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3340 /* support all rates and formats */
3341 #define SUPPORTED_RATES \
3342 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3343 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3344 SNDRV_PCM_RATE_192000)
3345 #define SUPPORTED_MAXBPS 24
3346 #define SUPPORTED_FORMATS \
3347 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3350 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3352 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3356 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3358 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3362 static const unsigned int channels_2_6_8[] = {
3366 static const unsigned int channels_2_8[] = {
3370 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3371 .count = ARRAY_SIZE(channels_2_6_8),
3372 .list = channels_2_6_8,
3376 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3377 .count = ARRAY_SIZE(channels_2_8),
3378 .list = channels_2_8,
3382 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3383 struct hda_codec *codec,
3384 struct snd_pcm_substream *substream)
3386 struct hdmi_spec *spec = codec->spec;
3387 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3389 switch (codec->preset->vendor_id) {
3394 hw_constraints_channels = &hw_constraints_2_8_channels;
3397 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3403 if (hw_constraints_channels != NULL) {
3404 snd_pcm_hw_constraint_list(substream->runtime, 0,
3405 SNDRV_PCM_HW_PARAM_CHANNELS,
3406 hw_constraints_channels);
3408 snd_pcm_hw_constraint_step(substream->runtime, 0,
3409 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3412 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3415 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3416 struct hda_codec *codec,
3417 struct snd_pcm_substream *substream)
3419 struct hdmi_spec *spec = codec->spec;
3420 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3423 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3424 struct hda_codec *codec,
3425 unsigned int stream_tag,
3426 unsigned int format,
3427 struct snd_pcm_substream *substream)
3429 struct hdmi_spec *spec = codec->spec;
3430 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3431 stream_tag, format, substream);
3434 static const struct hda_pcm_stream simple_pcm_playback = {
3439 .open = simple_playback_pcm_open,
3440 .close = simple_playback_pcm_close,
3441 .prepare = simple_playback_pcm_prepare
3445 static const struct hda_codec_ops simple_hdmi_patch_ops = {
3446 .build_controls = simple_playback_build_controls,
3447 .build_pcms = simple_playback_build_pcms,
3448 .init = simple_playback_init,
3449 .free = simple_playback_free,
3450 .unsol_event = simple_hdmi_unsol_event,
3453 static int patch_simple_hdmi(struct hda_codec *codec,
3454 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3456 struct hdmi_spec *spec;
3457 struct hdmi_spec_per_cvt *per_cvt;
3458 struct hdmi_spec_per_pin *per_pin;
3460 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3464 spec->codec = codec;
3466 hdmi_array_init(spec, 1);
3468 spec->multiout.num_dacs = 0; /* no analog */
3469 spec->multiout.max_channels = 2;
3470 spec->multiout.dig_out_nid = cvt_nid;
3473 per_pin = snd_array_new(&spec->pins);
3474 per_cvt = snd_array_new(&spec->cvts);
3475 if (!per_pin || !per_cvt) {
3476 simple_playback_free(codec);
3479 per_cvt->cvt_nid = cvt_nid;
3480 per_pin->pin_nid = pin_nid;
3481 spec->pcm_playback = simple_pcm_playback;
3483 codec->patch_ops = simple_hdmi_patch_ops;
3488 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3491 unsigned int chanmask;
3492 int chan = channels ? (channels - 1) : 1;
3511 /* Set the audio infoframe channel allocation and checksum fields. The
3512 * channel count is computed implicitly by the hardware. */
3513 snd_hda_codec_write(codec, 0x1, 0,
3514 Nv_VERB_SET_Channel_Allocation, chanmask);
3516 snd_hda_codec_write(codec, 0x1, 0,
3517 Nv_VERB_SET_Info_Frame_Checksum,
3518 (0x71 - chan - chanmask));
3521 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3522 struct hda_codec *codec,
3523 struct snd_pcm_substream *substream)
3525 struct hdmi_spec *spec = codec->spec;
3528 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3529 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3530 for (i = 0; i < 4; i++) {
3531 /* set the stream id */
3532 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3533 AC_VERB_SET_CHANNEL_STREAMID, 0);
3534 /* set the stream format */
3535 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3536 AC_VERB_SET_STREAM_FORMAT, 0);
3539 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3540 * streams are disabled. */
3541 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3543 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3546 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3547 struct hda_codec *codec,
3548 unsigned int stream_tag,
3549 unsigned int format,
3550 struct snd_pcm_substream *substream)
3553 unsigned int dataDCC2, channel_id;
3555 struct hdmi_spec *spec = codec->spec;
3556 struct hda_spdif_out *spdif;
3557 struct hdmi_spec_per_cvt *per_cvt;
3559 mutex_lock(&codec->spdif_mutex);
3560 per_cvt = get_cvt(spec, 0);
3561 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3563 chs = substream->runtime->channels;
3567 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3568 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3569 snd_hda_codec_write(codec,
3570 nvhdmi_master_con_nid_7x,
3572 AC_VERB_SET_DIGI_CONVERT_1,
3573 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3575 /* set the stream id */
3576 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3577 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3579 /* set the stream format */
3580 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3581 AC_VERB_SET_STREAM_FORMAT, format);
3583 /* turn on again (if needed) */
3584 /* enable and set the channel status audio/data flag */
3585 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3586 snd_hda_codec_write(codec,
3587 nvhdmi_master_con_nid_7x,
3589 AC_VERB_SET_DIGI_CONVERT_1,
3590 spdif->ctls & 0xff);
3591 snd_hda_codec_write(codec,
3592 nvhdmi_master_con_nid_7x,
3594 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3597 for (i = 0; i < 4; i++) {
3603 /* turn off SPDIF once;
3604 *otherwise the IEC958 bits won't be updated
3606 if (codec->spdif_status_reset &&
3607 (spdif->ctls & AC_DIG1_ENABLE))
3608 snd_hda_codec_write(codec,
3609 nvhdmi_con_nids_7x[i],
3611 AC_VERB_SET_DIGI_CONVERT_1,
3612 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3613 /* set the stream id */
3614 snd_hda_codec_write(codec,
3615 nvhdmi_con_nids_7x[i],
3617 AC_VERB_SET_CHANNEL_STREAMID,
3618 (stream_tag << 4) | channel_id);
3619 /* set the stream format */
3620 snd_hda_codec_write(codec,
3621 nvhdmi_con_nids_7x[i],
3623 AC_VERB_SET_STREAM_FORMAT,
3625 /* turn on again (if needed) */
3626 /* enable and set the channel status audio/data flag */
3627 if (codec->spdif_status_reset &&
3628 (spdif->ctls & AC_DIG1_ENABLE)) {
3629 snd_hda_codec_write(codec,
3630 nvhdmi_con_nids_7x[i],
3632 AC_VERB_SET_DIGI_CONVERT_1,
3633 spdif->ctls & 0xff);
3634 snd_hda_codec_write(codec,
3635 nvhdmi_con_nids_7x[i],
3637 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3641 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3643 mutex_unlock(&codec->spdif_mutex);
3647 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3651 .nid = nvhdmi_master_con_nid_7x,
3652 .rates = SUPPORTED_RATES,
3653 .maxbps = SUPPORTED_MAXBPS,
3654 .formats = SUPPORTED_FORMATS,
3656 .open = simple_playback_pcm_open,
3657 .close = nvhdmi_8ch_7x_pcm_close,
3658 .prepare = nvhdmi_8ch_7x_pcm_prepare
3662 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3664 struct hdmi_spec *spec;
3665 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3666 nvhdmi_master_pin_nid_7x);
3670 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3671 /* override the PCM rates, etc, as the codec doesn't give full list */
3673 spec->pcm_playback.rates = SUPPORTED_RATES;
3674 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3675 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3676 spec->nv_dp_workaround = true;
3680 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3682 struct hdmi_spec *spec = codec->spec;
3683 int err = simple_playback_build_pcms(codec);
3685 struct hda_pcm *info = get_pcm_rec(spec, 0);
3686 info->own_chmap = true;
3691 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3693 struct hdmi_spec *spec = codec->spec;
3694 struct hda_pcm *info;
3695 struct snd_pcm_chmap *chmap;
3698 err = simple_playback_build_controls(codec);
3702 /* add channel maps */
3703 info = get_pcm_rec(spec, 0);
3704 err = snd_pcm_add_chmap_ctls(info->pcm,
3705 SNDRV_PCM_STREAM_PLAYBACK,
3706 snd_pcm_alt_chmaps, 8, 0, &chmap);
3709 switch (codec->preset->vendor_id) {
3714 chmap->channel_mask = (1U << 2) | (1U << 8);
3717 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3722 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3724 struct hdmi_spec *spec;
3725 int err = patch_nvhdmi_2ch(codec);
3729 spec->multiout.max_channels = 8;
3730 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3731 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3732 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3733 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3735 /* Initialize the audio infoframe channel mask and checksum to something
3737 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3743 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3747 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3748 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3750 if (cap->ca_index == 0x00 && channels == 2)
3751 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3753 /* If the speaker allocation matches the channel count, it is OK. */
3754 if (cap->channels != channels)
3757 /* all channels are remappable freely */
3758 return SNDRV_CTL_TLVT_CHMAP_VAR;
3761 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3762 int ca, int chs, unsigned char *map)
3764 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3770 /* map from pin NID to port; port is 0-based */
3771 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3772 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3777 /* reverse-map from port to pin NID: see above */
3778 static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3783 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3784 .pin2port = nvhdmi_pin2port,
3785 .pin_eld_notify = generic_acomp_pin_eld_notify,
3786 .master_bind = generic_acomp_master_bind,
3787 .master_unbind = generic_acomp_master_unbind,
3790 static int patch_nvhdmi(struct hda_codec *codec)
3792 struct hdmi_spec *spec;
3795 err = alloc_generic_hdmi(codec);
3798 codec->dp_mst = true;
3802 err = hdmi_parse_codec(codec);
3804 generic_spec_free(codec);
3808 generic_hdmi_init_per_pins(codec);
3810 spec->dyn_pin_out = true;
3812 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3813 nvhdmi_chmap_cea_alloc_validate_get_type;
3814 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3815 spec->nv_dp_workaround = true;
3817 codec->link_down_at_suspend = 1;
3819 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3824 static int patch_nvhdmi_legacy(struct hda_codec *codec)
3826 struct hdmi_spec *spec;
3829 err = patch_generic_hdmi(codec);
3834 spec->dyn_pin_out = true;
3836 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3837 nvhdmi_chmap_cea_alloc_validate_get_type;
3838 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3839 spec->nv_dp_workaround = true;
3841 codec->link_down_at_suspend = 1;
3847 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3848 * accessed using vendor-defined verbs. These registers can be used for
3849 * interoperability between the HDA and HDMI drivers.
3852 /* Audio Function Group node */
3853 #define NVIDIA_AFG_NID 0x01
3856 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3857 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3858 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3859 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3860 * additional bit (at position 30) to signal the validity of the format.
3862 * | 31 | 30 | 29 16 | 15 0 |
3863 * +---------+-------+--------+--------+
3864 * | TRIGGER | VALID | UNUSED | FORMAT |
3865 * +-----------------------------------|
3867 * Note that for the trigger bit to take effect it needs to change value
3868 * (i.e. it needs to be toggled). The trigger bit is not applicable from
3869 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt
3872 #define NVIDIA_SET_HOST_INTR 0xf80
3873 #define NVIDIA_GET_SCRATCH0 0xfa6
3874 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3875 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3876 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3877 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3878 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3879 #define NVIDIA_SCRATCH_VALID (1 << 6)
3881 #define NVIDIA_GET_SCRATCH1 0xfab
3882 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3883 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3884 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3885 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3888 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3889 * the format is invalidated so that the HDMI codec can be disabled.
3891 static void tegra_hdmi_set_format(struct hda_codec *codec,
3893 unsigned int format)
3896 unsigned int nid = NVIDIA_AFG_NID;
3897 struct hdmi_spec *spec = codec->spec;
3900 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST.
3901 * This resulted in moving scratch registers from audio function
3902 * group to converter widget context. So CVT NID should be used for
3903 * scratch register read/write for DP MST supported Tegra HDA codec.
3908 /* bits [31:30] contain the trigger and valid bits */
3909 value = snd_hda_codec_read(codec, nid, 0,
3910 NVIDIA_GET_SCRATCH0, 0);
3911 value = (value >> 24) & 0xff;
3913 /* bits [15:0] are used to store the HDA format */
3914 snd_hda_codec_write(codec, nid, 0,
3915 NVIDIA_SET_SCRATCH0_BYTE0,
3916 (format >> 0) & 0xff);
3917 snd_hda_codec_write(codec, nid, 0,
3918 NVIDIA_SET_SCRATCH0_BYTE1,
3919 (format >> 8) & 0xff);
3921 /* bits [16:24] are unused */
3922 snd_hda_codec_write(codec, nid, 0,
3923 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3926 * Bit 30 signals that the data is valid and hence that HDMI audio can
3930 value &= ~NVIDIA_SCRATCH_VALID;
3932 value |= NVIDIA_SCRATCH_VALID;
3934 if (spec->hdmi_intr_trig_ctrl) {
3936 * For Tegra HDA Codec design from TEGRA234 onwards, the
3937 * Interrupt to hdmi driver is triggered by writing
3938 * non-zero values to verb 0xF80 instead of 31st bit of
3941 snd_hda_codec_write(codec, nid, 0,
3942 NVIDIA_SET_SCRATCH0_BYTE3, value);
3943 snd_hda_codec_write(codec, nid, 0,
3944 NVIDIA_SET_HOST_INTR, 0x1);
3947 * Whenever the 31st trigger bit is toggled, an interrupt is raised
3948 * in the HDMI codec. The HDMI driver will use that as trigger
3949 * to update its configuration.
3951 value ^= NVIDIA_SCRATCH_TRIGGER;
3953 snd_hda_codec_write(codec, nid, 0,
3954 NVIDIA_SET_SCRATCH0_BYTE3, value);
3958 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3959 struct hda_codec *codec,
3960 unsigned int stream_tag,
3961 unsigned int format,
3962 struct snd_pcm_substream *substream)
3966 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3971 /* notify the HDMI codec of the format change */
3972 tegra_hdmi_set_format(codec, hinfo->nid, format);
3977 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3978 struct hda_codec *codec,
3979 struct snd_pcm_substream *substream)
3981 /* invalidate the format in the HDMI codec */
3982 tegra_hdmi_set_format(codec, hinfo->nid, 0);
3984 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3987 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3989 struct hdmi_spec *spec = codec->spec;
3992 for (i = 0; i < spec->num_pins; i++) {
3993 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3995 if (pcm->pcm_type == type)
4002 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
4004 struct hda_pcm_stream *stream;
4005 struct hda_pcm *pcm;
4008 err = generic_hdmi_build_pcms(codec);
4012 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
4017 * Override ->prepare() and ->cleanup() operations to notify the HDMI
4018 * codec about format changes.
4020 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
4021 stream->ops.prepare = tegra_hdmi_pcm_prepare;
4022 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
4027 static int tegra_hdmi_init(struct hda_codec *codec)
4029 struct hdmi_spec *spec = codec->spec;
4032 err = hdmi_parse_codec(codec);
4034 generic_spec_free(codec);
4038 for (i = 0; i < spec->num_cvts; i++)
4039 snd_hda_codec_write(codec, spec->cvt_nids[i], 0,
4040 AC_VERB_SET_DIGI_CONVERT_1,
4043 generic_hdmi_init_per_pins(codec);
4045 codec->depop_delay = 10;
4046 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
4047 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4048 nvhdmi_chmap_cea_alloc_validate_get_type;
4049 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
4051 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4052 nvhdmi_chmap_cea_alloc_validate_get_type;
4053 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
4054 spec->nv_dp_workaround = true;
4059 static int patch_tegra_hdmi(struct hda_codec *codec)
4063 err = alloc_generic_hdmi(codec);
4067 return tegra_hdmi_init(codec);
4070 static int patch_tegra234_hdmi(struct hda_codec *codec)
4072 struct hdmi_spec *spec;
4075 err = alloc_generic_hdmi(codec);
4079 codec->dp_mst = true;
4081 spec->dyn_pin_out = true;
4082 spec->hdmi_intr_trig_ctrl = true;
4084 return tegra_hdmi_init(codec);
4088 * ATI/AMD-specific implementations
4091 #define is_amdhdmi_rev3_or_later(codec) \
4092 ((codec)->core.vendor_id == 0x1002aa01 && \
4093 ((codec)->core.revision_id & 0xff00) >= 0x0300)
4094 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
4096 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
4097 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
4098 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
4099 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
4100 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
4101 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
4102 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
4103 #define ATI_VERB_SET_HBR_CONTROL 0x77c
4104 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
4105 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
4106 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
4107 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
4108 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
4109 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
4110 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
4111 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
4112 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
4113 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
4114 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
4115 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
4116 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
4117 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
4118 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
4119 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
4120 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
4122 /* AMD specific HDA cvt verbs */
4123 #define ATI_VERB_SET_RAMP_RATE 0x770
4124 #define ATI_VERB_GET_RAMP_RATE 0xf70
4126 #define ATI_OUT_ENABLE 0x1
4128 #define ATI_MULTICHANNEL_MODE_PAIRED 0
4129 #define ATI_MULTICHANNEL_MODE_SINGLE 1
4131 #define ATI_HBR_CAPABLE 0x01
4132 #define ATI_HBR_ENABLE 0x10
4134 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
4135 int dev_id, unsigned char *buf, int *eld_size)
4137 WARN_ON(dev_id != 0);
4138 /* call hda_eld.c ATI/AMD-specific function */
4139 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
4140 is_amdhdmi_rev3_or_later(codec));
4143 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
4144 hda_nid_t pin_nid, int dev_id, int ca,
4145 int active_channels, int conn_type)
4147 WARN_ON(dev_id != 0);
4148 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
4151 static int atihdmi_paired_swap_fc_lfe(int pos)
4154 * ATI/AMD have automatic FC/LFE swap built-in
4155 * when in pairwise mapping mode.
4159 /* see channel_allocations[].speakers[] */
4168 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
4169 int ca, int chs, unsigned char *map)
4171 struct hdac_cea_channel_speaker_allocation *cap;
4174 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
4176 cap = snd_hdac_get_ch_alloc_from_ca(ca);
4177 for (i = 0; i < chs; ++i) {
4178 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
4180 bool companion_ok = false;
4185 for (j = 0 + i % 2; j < 8; j += 2) {
4186 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
4187 if (cap->speakers[chan_idx] == mask) {
4188 /* channel is in a supported position */
4191 if (i % 2 == 0 && i + 1 < chs) {
4192 /* even channel, check the odd companion */
4193 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
4194 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
4195 int comp_mask_act = cap->speakers[comp_chan_idx];
4197 if (comp_mask_req == comp_mask_act)
4198 companion_ok = true;
4210 i++; /* companion channel already checked */
4216 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
4217 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
4219 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4221 int ati_channel_setup = 0;
4226 if (!has_amd_full_remap_support(codec)) {
4227 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
4229 /* In case this is an odd slot but without stream channel, do not
4230 * disable the slot since the corresponding even slot could have a
4231 * channel. In case neither have a channel, the slot pair will be
4232 * disabled when this function is called for the even slot. */
4233 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
4236 hdmi_slot -= hdmi_slot % 2;
4238 if (stream_channel != 0xf)
4239 stream_channel -= stream_channel % 2;
4242 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
4244 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
4246 if (stream_channel != 0xf)
4247 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
4249 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
4252 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
4253 hda_nid_t pin_nid, int asp_slot)
4255 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4256 bool was_odd = false;
4257 int ati_asp_slot = asp_slot;
4259 int ati_channel_setup;
4264 if (!has_amd_full_remap_support(codec)) {
4265 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
4266 if (ati_asp_slot % 2 != 0) {
4272 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
4274 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
4276 if (!(ati_channel_setup & ATI_OUT_ENABLE))
4279 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
4282 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
4283 struct hdac_chmap *chmap,
4284 struct hdac_cea_channel_speaker_allocation *cap,
4290 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
4291 * we need to take that into account (a single channel may take 2
4292 * channel slots if we need to carry a silent channel next to it).
4293 * On Rev3+ AMD codecs this function is not used.
4297 /* We only produce even-numbered channel count TLVs */
4298 if ((channels % 2) != 0)
4301 for (c = 0; c < 7; c += 2) {
4302 if (cap->speakers[c] || cap->speakers[c+1])
4306 if (chanpairs * 2 != channels)
4309 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
4312 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
4313 struct hdac_cea_channel_speaker_allocation *cap,
4314 unsigned int *chmap, int channels)
4316 /* produce paired maps for pre-rev3 ATI/AMD codecs */
4320 for (c = 7; c >= 0; c--) {
4321 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
4322 int spk = cap->speakers[chan];
4324 /* add N/A channel if the companion channel is occupied */
4325 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
4326 chmap[count++] = SNDRV_CHMAP_NA;
4331 chmap[count++] = snd_hdac_spk_to_chmap(spk);
4334 WARN_ON(count != channels);
4337 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4338 int dev_id, bool hbr)
4340 int hbr_ctl, hbr_ctl_new;
4342 WARN_ON(dev_id != 0);
4344 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4345 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4347 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4349 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4352 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4354 hbr_ctl == hbr_ctl_new ? "" : "new-",
4357 if (hbr_ctl != hbr_ctl_new)
4358 snd_hda_codec_write(codec, pin_nid, 0,
4359 ATI_VERB_SET_HBR_CONTROL,
4368 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4369 hda_nid_t pin_nid, int dev_id,
4370 u32 stream_tag, int format)
4372 if (is_amdhdmi_rev3_or_later(codec)) {
4373 int ramp_rate = 180; /* default as per AMD spec */
4374 /* disable ramp-up/down for non-pcm as per AMD spec */
4375 if (format & AC_FMT_TYPE_NON_PCM)
4378 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4381 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4382 stream_tag, format);
4386 static int atihdmi_init(struct hda_codec *codec)
4388 struct hdmi_spec *spec = codec->spec;
4391 err = generic_hdmi_init(codec);
4396 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4397 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4399 /* make sure downmix information in infoframe is zero */
4400 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4402 /* enable channel-wise remap mode if supported */
4403 if (has_amd_full_remap_support(codec))
4404 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4405 ATI_VERB_SET_MULTICHANNEL_MODE,
4406 ATI_MULTICHANNEL_MODE_SINGLE);
4408 codec->auto_runtime_pm = 1;
4413 /* map from pin NID to port; port is 0-based */
4414 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4415 static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4417 return pin_nid / 2 - 1;
4420 /* reverse-map from port to pin NID: see above */
4421 static int atihdmi_port2pin(struct hda_codec *codec, int port)
4423 return port * 2 + 3;
4426 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4427 .pin2port = atihdmi_pin2port,
4428 .pin_eld_notify = generic_acomp_pin_eld_notify,
4429 .master_bind = generic_acomp_master_bind,
4430 .master_unbind = generic_acomp_master_unbind,
4433 static int patch_atihdmi(struct hda_codec *codec)
4435 struct hdmi_spec *spec;
4436 struct hdmi_spec_per_cvt *per_cvt;
4439 err = patch_generic_hdmi(codec);
4444 codec->patch_ops.init = atihdmi_init;
4448 spec->static_pcm_mapping = true;
4450 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4451 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4452 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4453 spec->ops.setup_stream = atihdmi_setup_stream;
4455 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4456 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4458 if (!has_amd_full_remap_support(codec)) {
4459 /* override to ATI/AMD-specific versions with pairwise mapping */
4460 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4461 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4462 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4463 atihdmi_paired_cea_alloc_to_tlv_chmap;
4464 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4467 /* ATI/AMD converters do not advertise all of their capabilities */
4468 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4469 per_cvt = get_cvt(spec, cvt_idx);
4470 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4471 per_cvt->rates |= SUPPORTED_RATES;
4472 per_cvt->formats |= SUPPORTED_FORMATS;
4473 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4476 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4478 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4479 * the link-down as is. Tell the core to allow it.
4481 codec->link_down_at_suspend = 1;
4483 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4488 /* VIA HDMI Implementation */
4489 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4490 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4492 static int patch_via_hdmi(struct hda_codec *codec)
4494 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4497 static int patch_gf_hdmi(struct hda_codec *codec)
4501 err = patch_generic_hdmi(codec);
4506 * Glenfly GPUs have two codecs, stream switches from one codec to
4507 * another, need to do actual clean-ups in codec_cleanup_stream
4509 codec->no_sticky_stream = 1;
4516 static const struct hda_device_id snd_hda_id_hdmi[] = {
4517 HDA_CODEC_ENTRY(0x00147a47, "Loongson HDMI", patch_generic_hdmi),
4518 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4519 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4520 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4521 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4522 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4523 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4524 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4525 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4526 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4527 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4528 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4529 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4530 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4531 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4532 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
4533 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
4534 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
4535 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
4536 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
4537 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
4538 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
4539 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
4540 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
4541 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
4542 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
4543 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
4544 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
4545 /* 17 is known to be absent */
4546 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
4547 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
4548 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
4549 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
4550 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
4551 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4552 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4553 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4554 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4555 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4556 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4557 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4558 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4559 HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi),
4560 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4561 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4562 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4563 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4564 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4565 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4566 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4567 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4568 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4569 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4570 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4571 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4572 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4573 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4574 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4575 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4576 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4577 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4578 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4579 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4580 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4581 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4582 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4583 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4584 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4585 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4586 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4587 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4588 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4589 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4590 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4591 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4592 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4593 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4594 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4595 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4596 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4597 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
4598 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
4599 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
4600 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
4601 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
4602 HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP", patch_nvhdmi),
4603 HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP", patch_nvhdmi),
4604 HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP", patch_nvhdmi),
4605 HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP", patch_nvhdmi),
4606 HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP", patch_nvhdmi),
4607 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4608 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4609 HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi),
4610 HDA_CODEC_ENTRY(0x67663d83, "Arise 83 HDMI/DP", patch_gf_hdmi),
4611 HDA_CODEC_ENTRY(0x67663d84, "Arise 84 HDMI/DP", patch_gf_hdmi),
4612 HDA_CODEC_ENTRY(0x67663d85, "Arise 85 HDMI/DP", patch_gf_hdmi),
4613 HDA_CODEC_ENTRY(0x67663d86, "Arise 86 HDMI/DP", patch_gf_hdmi),
4614 HDA_CODEC_ENTRY(0x67663d87, "Arise 87 HDMI/DP", patch_gf_hdmi),
4615 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4616 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4617 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4618 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4619 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4620 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4621 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4622 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4623 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4624 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4625 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4626 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4627 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4628 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4629 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4630 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4631 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4632 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4633 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4634 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4635 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4636 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi),
4637 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi),
4638 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
4639 HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi),
4640 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi),
4641 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4642 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4643 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi),
4644 HDA_CODEC_ENTRY(0x8086281d, "Meteor Lake HDMI", patch_i915_adlp_hdmi),
4645 HDA_CODEC_ENTRY(0x8086281f, "Raptor Lake P HDMI", patch_i915_adlp_hdmi),
4646 HDA_CODEC_ENTRY(0x80862820, "Lunar Lake HDMI", patch_i915_adlp_hdmi),
4647 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4648 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4649 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4650 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4651 /* special ID for generic HDMI */
4652 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4655 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4657 MODULE_LICENSE("GPL");
4658 MODULE_DESCRIPTION("HDMI HD-audio codec");
4659 MODULE_ALIAS("snd-hda-codec-intelhdmi");
4660 MODULE_ALIAS("snd-hda-codec-nvhdmi");
4661 MODULE_ALIAS("snd-hda-codec-atihdmi");
4663 static struct hda_codec_driver hdmi_driver = {
4664 .id = snd_hda_id_hdmi,
4667 module_hda_codec_driver(hdmi_driver);