sound/pci/hda/patch_cs8409.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
   4  *
   5  * Copyright (C) 2021 Cirrus Logic, Inc. and
   6  *                    Cirrus Logic International Semiconductor Ltd.
   7  */
   8
   9 #include <linux/init.h>
  10 #include <linux/slab.h>
  11 #include <linux/module.h>
  12 #include <sound/core.h>
  13 #include <linux/mutex.h>
  14 #include <linux/iopoll.h>
  15
  16 #include "patch_cs8409.h"
  17
  18 /******************************************************************************
  19  *                        CS8409 Specific Functions
  20  ******************************************************************************/
  21
  22 static int cs8409_parse_auto_config(struct hda_codec *codec)
  23 {
  24         struct cs8409_spec *spec = codec->spec;
  25         int err;
  26         int i;
  27
  28         err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0);
  29         if (err < 0)
  30                 return err;
  31
  32         err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
  33         if (err < 0)
  34                 return err;
  35
  36         /* keep the ADCs powered up when it's dynamically switchable */
  37         if (spec->gen.dyn_adc_switch) {
  38                 unsigned int done = 0;
  39
  40                 for (i = 0; i < spec->gen.input_mux.num_items; i++) {
  41                         int idx = spec->gen.dyn_adc_idx[i];
  42
  43                         if (done & (1 << idx))
  44                                 continue;
  45                         snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]);
  46                         done |= 1 << idx;
  47                 }
  48         }
  49
  50         return 0;
  51 }
  52
  53 static void cs8409_disable_i2c_clock_worker(struct work_struct *work);
  54
  55 static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec)
  56 {
  57         struct cs8409_spec *spec;
  58
  59         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  60         if (!spec)
  61                 return NULL;
  62         codec->spec = spec;
  63         spec->codec = codec;
  64         codec->power_save_node = 1;
  65         mutex_init(&spec->i2c_mux);
  66         INIT_DELAYED_WORK(&spec->i2c_clk_work, cs8409_disable_i2c_clock_worker);
  67         snd_hda_gen_spec_init(&spec->gen);
  68
  69         return spec;
  70 }
  71
  72 static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx)
  73 {
  74         snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
  75         return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0);
  76 }
  77
  78 static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx,
  79                                           unsigned int coef)
  80 {
  81         snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
  82         snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef);
  83 }
  84
  85 /*
  86  * cs8409_enable_i2c_clock - Disable I2C clocks
  87  * @codec: the codec instance
  88  * Disable I2C clocks.
  89  * This must be called when the i2c mutex is unlocked.
  90  */
  91 static void cs8409_disable_i2c_clock(struct hda_codec *codec)
  92 {
  93         struct cs8409_spec *spec = codec->spec;
  94
  95         mutex_lock(&spec->i2c_mux);
  96         if (spec->i2c_clck_enabled) {
  97                 cs8409_vendor_coef_set(spec->codec, 0x0,
  98                                cs8409_vendor_coef_get(spec->codec, 0x0) & 0xfffffff7);
  99                 spec->i2c_clck_enabled = 0;
 100         }
 101         mutex_unlock(&spec->i2c_mux);
 102 }
 103
 104 /*
 105  * cs8409_disable_i2c_clock_worker - Worker that disable the I2C Clock after 25ms without use
 106  */
 107 static void cs8409_disable_i2c_clock_worker(struct work_struct *work)
 108 {
 109         struct cs8409_spec *spec = container_of(work, struct cs8409_spec, i2c_clk_work.work);
 110
 111         cs8409_disable_i2c_clock(spec->codec);
 112 }
 113
 114 /*
 115  * cs8409_enable_i2c_clock - Enable I2C clocks
 116  * @codec: the codec instance
 117  * Enable I2C clocks.
 118  * This must be called when the i2c mutex is locked.
 119  */
 120 static void cs8409_enable_i2c_clock(struct hda_codec *codec)
 121 {
 122         struct cs8409_spec *spec = codec->spec;
 123
 124         /* Cancel the disable timer, but do not wait for any running disable functions to finish.
 125          * If the disable timer runs out before cancel, the delayed work thread will be blocked,
 126          * waiting for the mutex to become unlocked. This mutex will be locked for the duration of
 127          * any i2c transaction, so the disable function will run to completion immediately
 128          * afterwards in the scenario. The next enable call will re-enable the clock, regardless.
 129          */
 130         cancel_delayed_work(&spec->i2c_clk_work);
 131
 132         if (!spec->i2c_clck_enabled) {
 133                 cs8409_vendor_coef_set(codec, 0x0, cs8409_vendor_coef_get(codec, 0x0) | 0x8);
 134                 spec->i2c_clck_enabled = 1;
 135         }
 136         queue_delayed_work(system_power_efficient_wq, &spec->i2c_clk_work, msecs_to_jiffies(25));
 137 }
 138
 139 /**
 140  * cs8409_i2c_wait_complete - Wait for I2C transaction
 141  * @codec: the codec instance
 142  *
 143  * Wait for I2C transaction to complete.
 144  * Return -ETIMEDOUT if transaction wait times out.
 145  */
 146 static int cs8409_i2c_wait_complete(struct hda_codec *codec)
 147 {
 148         unsigned int retval;
 149
 150         return read_poll_timeout(cs8409_vendor_coef_get, retval, retval & 0x18,
 151                 CS42L42_I2C_SLEEP_US, CS42L42_I2C_TIMEOUT_US, false, codec, CS8409_I2C_STS);
 152 }
 153
 154 /**
 155  * cs8409_set_i2c_dev_addr - Set i2c address for transaction
 156  * @codec: the codec instance
 157  * @addr: I2C Address
 158  */
 159 static void cs8409_set_i2c_dev_addr(struct hda_codec *codec, unsigned int addr)
 160 {
 161         struct cs8409_spec *spec = codec->spec;
 162
 163         if (spec->dev_addr != addr) {
 164                 cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, addr);
 165                 spec->dev_addr = addr;
 166         }
 167 }
 168
 169 /**
 170  * cs8409_i2c_set_page - CS8409 I2C set page register.
 171  * @scodec: the codec instance
 172  * @i2c_reg: Page register
 173  *
 174  * Returns negative on error.
 175  */
 176 static int cs8409_i2c_set_page(struct sub_codec *scodec, unsigned int i2c_reg)
 177 {
 178         struct hda_codec *codec = scodec->codec;
 179
 180         if (scodec->paged && (scodec->last_page != (i2c_reg >> 8))) {
 181                 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8);
 182                 if (cs8409_i2c_wait_complete(codec) < 0)
 183                         return -EIO;
 184                 scodec->last_page = i2c_reg >> 8;
 185         }
 186
 187         return 0;
 188 }
 189
 190 /**
 191  * cs8409_i2c_read - CS8409 I2C Read.
 192  * @scodec: the codec instance
 193  * @addr: Register to read
 194  *
 195  * Returns negative on error, otherwise returns read value in bits 0-7.
 196  */
 197 static int cs8409_i2c_read(struct sub_codec *scodec, unsigned int addr)
 198 {
 199         struct hda_codec *codec = scodec->codec;
 200         struct cs8409_spec *spec = codec->spec;
 201         unsigned int i2c_reg_data;
 202         unsigned int read_data;
 203
 204         if (scodec->suspended)
 205                 return -EPERM;
 206
 207         mutex_lock(&spec->i2c_mux);
 208         cs8409_enable_i2c_clock(codec);
 209         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 210
 211         if (cs8409_i2c_set_page(scodec, addr))
 212                 goto error;
 213
 214         i2c_reg_data = (addr << 8) & 0x0ffff;
 215         cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
 216         if (cs8409_i2c_wait_complete(codec) < 0)
 217                 goto error;
 218
 219         /* Register in bits 15-8 and the data in 7-0 */
 220         read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD);
 221
 222         mutex_unlock(&spec->i2c_mux);
 223
 224         return read_data & 0x0ff;
 225
 226 error:
 227         mutex_unlock(&spec->i2c_mux);
 228         codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
 229         return -EIO;
 230 }
 231
 232 /**
 233  * cs8409_i2c_bulk_read - CS8409 I2C Read Sequence.
 234  * @scodec: the codec instance
 235  * @seq: Register Sequence to read
 236  * @count: Number of registeres to read
 237  *
 238  * Returns negative on error, values are read into value element of cs8409_i2c_param sequence.
 239  */
 240 static int cs8409_i2c_bulk_read(struct sub_codec *scodec, struct cs8409_i2c_param *seq, int count)
 241 {
 242         struct hda_codec *codec = scodec->codec;
 243         struct cs8409_spec *spec = codec->spec;
 244         unsigned int i2c_reg_data;
 245         int i;
 246
 247         if (scodec->suspended)
 248                 return -EPERM;
 249
 250         mutex_lock(&spec->i2c_mux);
 251         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 252
 253         for (i = 0; i < count; i++) {
 254                 cs8409_enable_i2c_clock(codec);
 255                 if (cs8409_i2c_set_page(scodec, seq[i].addr))
 256                         goto error;
 257
 258                 i2c_reg_data = (seq[i].addr << 8) & 0x0ffff;
 259                 cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
 260
 261                 if (cs8409_i2c_wait_complete(codec) < 0)
 262                         goto error;
 263
 264                 seq[i].value = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD) & 0xff;
 265         }
 266
 267         mutex_unlock(&spec->i2c_mux);
 268
 269         return 0;
 270
 271 error:
 272         mutex_unlock(&spec->i2c_mux);
 273         codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
 274         return -EIO;
 275 }
 276
 277 /**
 278  * cs8409_i2c_write - CS8409 I2C Write.
 279  * @scodec: the codec instance
 280  * @addr: Register to write to
 281  * @value: Data to write
 282  *
 283  * Returns negative on error, otherwise returns 0.
 284  */
 285 static int cs8409_i2c_write(struct sub_codec *scodec, unsigned int addr, unsigned int value)
 286 {
 287         struct hda_codec *codec = scodec->codec;
 288         struct cs8409_spec *spec = codec->spec;
 289         unsigned int i2c_reg_data;
 290
 291         if (scodec->suspended)
 292                 return -EPERM;
 293
 294         mutex_lock(&spec->i2c_mux);
 295
 296         cs8409_enable_i2c_clock(codec);
 297         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 298
 299         if (cs8409_i2c_set_page(scodec, addr))
 300                 goto error;
 301
 302         i2c_reg_data = ((addr << 8) & 0x0ff00) | (value & 0x0ff);
 303         cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
 304
 305         if (cs8409_i2c_wait_complete(codec) < 0)
 306                 goto error;
 307
 308         mutex_unlock(&spec->i2c_mux);
 309         return 0;
 310
 311 error:
 312         mutex_unlock(&spec->i2c_mux);
 313         codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
 314         return -EIO;
 315 }
 316
 317 /**
 318  * cs8409_i2c_bulk_write - CS8409 I2C Write Sequence.
 319  * @scodec: the codec instance
 320  * @seq: Register Sequence to write
 321  * @count: Number of registeres to write
 322  *
 323  * Returns negative on error.
 324  */
 325 static int cs8409_i2c_bulk_write(struct sub_codec *scodec, const struct cs8409_i2c_param *seq,
 326                                  int count)
 327 {
 328         struct hda_codec *codec = scodec->codec;
 329         struct cs8409_spec *spec = codec->spec;
 330         unsigned int i2c_reg_data;
 331         int i;
 332
 333         if (scodec->suspended)
 334                 return -EPERM;
 335
 336         mutex_lock(&spec->i2c_mux);
 337         cs8409_set_i2c_dev_addr(codec, scodec->addr);
 338
 339         for (i = 0; i < count; i++) {
 340                 cs8409_enable_i2c_clock(codec);
 341                 if (cs8409_i2c_set_page(scodec, seq[i].addr))
 342                         goto error;
 343
 344                 i2c_reg_data = ((seq[i].addr << 8) & 0x0ff00) | (seq[i].value & 0x0ff);
 345                 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
 346
 347                 if (cs8409_i2c_wait_complete(codec) < 0)
 348                         goto error;
 349         }
 350
 351         mutex_unlock(&spec->i2c_mux);
 352
 353         return 0;
 354
 355 error:
 356         mutex_unlock(&spec->i2c_mux);
 357         codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
 358         return -EIO;
 359 }
 360
 361 static int cs8409_init(struct hda_codec *codec)
 362 {
 363         int ret = snd_hda_gen_init(codec);
 364
 365         if (!ret)
 366                 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT);
 367
 368         return ret;
 369 }
 370
 371 static int cs8409_build_controls(struct hda_codec *codec)
 372 {
 373         int err;
 374
 375         err = snd_hda_gen_build_controls(codec);
 376         if (err < 0)
 377                 return err;
 378         snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD);
 379
 380         return 0;
 381 }
 382
 383 /* Enable/Disable Unsolicited Response */
 384 static void cs8409_enable_ur(struct hda_codec *codec, int flag)
 385 {
 386         struct cs8409_spec *spec = codec->spec;
 387         unsigned int ur_gpios = 0;
 388         int i;
 389
 390         for (i = 0; i < spec->num_scodecs; i++)
 391                 ur_gpios |= spec->scodecs[i]->irq_mask;
 392
 393         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK,
 394                             flag ? ur_gpios : 0);
 395
 396         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE,
 397                             flag ? AC_UNSOL_ENABLED : 0);
 398 }
 399
 400 static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid)
 401 {
 402         int caps;
 403
 404         /* CS8409 is simple HDA bridge and intended to be used with a remote
 405          * companion codec. Most of input/output PIN(s) have only basic
 406          * capabilities. Receive and Transmit NID(s) have only OUTC and INC
 407          * capabilities and no presence detect capable (PDC) and call to
 408          * snd_hda_gen_build_controls() will mark them as non detectable
 409          * phantom jacks. However, a companion codec may be
 410          * connected to these pins which supports jack detect
 411          * capabilities. We have to override pin capabilities,
 412          * otherwise they will not be created as input devices.
 413          */
 414         caps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP);
 415         if (caps >= 0)
 416                 snd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP,
 417                                        (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT)));
 418
 419         snd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP));
 420 }
 421
 422 static int cs8409_spk_sw_gpio_get(struct snd_kcontrol *kcontrol,
 423                                  struct snd_ctl_elem_value *ucontrol)
 424 {
 425         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 426         struct cs8409_spec *spec = codec->spec;
 427
 428         ucontrol->value.integer.value[0] = !!(spec->gpio_data & spec->speaker_pdn_gpio);
 429         return 0;
 430 }
 431
 432 static int cs8409_spk_sw_gpio_put(struct snd_kcontrol *kcontrol,
 433                                  struct snd_ctl_elem_value *ucontrol)
 434 {
 435         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 436         struct cs8409_spec *spec = codec->spec;
 437         unsigned int gpio_data;
 438
 439         gpio_data = (spec->gpio_data & ~spec->speaker_pdn_gpio) |
 440                 (ucontrol->value.integer.value[0] ? spec->speaker_pdn_gpio : 0);
 441         if (gpio_data == spec->gpio_data)
 442                 return 0;
 443         spec->gpio_data = gpio_data;
 444         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
 445         return 1;
 446 }
 447
 448 static const struct snd_kcontrol_new cs8409_spk_sw_ctrl = {
 449         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
 450         .info = snd_ctl_boolean_mono_info,
 451         .get = cs8409_spk_sw_gpio_get,
 452         .put = cs8409_spk_sw_gpio_put,
 453 };
 454
 455 /******************************************************************************
 456  *                        CS42L42 Specific Functions
 457  ******************************************************************************/
 458
 459 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo)
 460 {
 461         unsigned int ofs = get_amp_offset(kctrl);
 462         u8 chs = get_amp_channels(kctrl);
 463
 464         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 465         uinfo->value.integer.step = 1;
 466         uinfo->count = chs == 3 ? 2 : 1;
 467
 468         switch (ofs) {
 469         case CS42L42_VOL_DAC:
 470                 uinfo->value.integer.min = CS42L42_HP_VOL_REAL_MIN;
 471                 uinfo->value.integer.max = CS42L42_HP_VOL_REAL_MAX;
 472                 break;
 473         case CS42L42_VOL_ADC:
 474                 uinfo->value.integer.min = CS42L42_AMIC_VOL_REAL_MIN;
 475                 uinfo->value.integer.max = CS42L42_AMIC_VOL_REAL_MAX;
 476                 break;
 477         default:
 478                 break;
 479         }
 480
 481         return 0;
 482 }
 483
 484 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
 485 {
 486         struct hda_codec *codec = snd_kcontrol_chip(kctrl);
 487         struct cs8409_spec *spec = codec->spec;
 488         struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
 489         int chs = get_amp_channels(kctrl);
 490         unsigned int ofs = get_amp_offset(kctrl);
 491         long *valp = uctrl->value.integer.value;
 492
 493         switch (ofs) {
 494         case CS42L42_VOL_DAC:
 495                 if (chs & BIT(0))
 496                         *valp++ = cs42l42->vol[ofs];
 497                 if (chs & BIT(1))
 498                         *valp = cs42l42->vol[ofs+1];
 499                 break;
 500         case CS42L42_VOL_ADC:
 501                 if (chs & BIT(0))
 502                         *valp = cs42l42->vol[ofs];
 503                 break;
 504         default:
 505                 break;
 506         }
 507
 508         return 0;
 509 }
 510
 511 static void cs42l42_mute(struct sub_codec *cs42l42, int vol_type,
 512         unsigned int chs, bool mute)
 513 {
 514         if (mute) {
 515                 if (vol_type == CS42L42_VOL_DAC) {
 516                         if (chs & BIT(0))
 517                                 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, 0x3f);
 518                         if (chs & BIT(1))
 519                                 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, 0x3f);
 520                 } else if (vol_type == CS42L42_VOL_ADC) {
 521                         if (chs & BIT(0))
 522                                 cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, 0x9f);
 523                 }
 524         } else {
 525                 if (vol_type == CS42L42_VOL_DAC) {
 526                         if (chs & BIT(0))
 527                                 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL,
 528                                         -(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET])
 529                                         & CS42L42_MIXER_CH_VOL_MASK);
 530                         if (chs & BIT(1))
 531                                 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL,
 532                                         -(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET])
 533                                         & CS42L42_MIXER_CH_VOL_MASK);
 534                 } else if (vol_type == CS42L42_VOL_ADC) {
 535                         if (chs & BIT(0))
 536                                 cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME,
 537                                         cs42l42->vol[CS42L42_ADC_VOL_OFFSET]
 538                                         & CS42L42_REG_AMIC_VOL_MASK);
 539                 }
 540         }
 541 }
 542
 543 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
 544 {
 545         struct hda_codec *codec = snd_kcontrol_chip(kctrl);
 546         struct cs8409_spec *spec = codec->spec;
 547         struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
 548         int chs = get_amp_channels(kctrl);
 549         unsigned int ofs = get_amp_offset(kctrl);
 550         long *valp = uctrl->value.integer.value;
 551
 552         switch (ofs) {
 553         case CS42L42_VOL_DAC:
 554                 if (chs & BIT(0))
 555                         cs42l42->vol[ofs] = *valp;
 556                 if (chs & BIT(1)) {
 557                         valp++;
 558                         cs42l42->vol[ofs + 1] = *valp;
 559                 }
 560                 if (spec->playback_started)
 561                         cs42l42_mute(cs42l42, CS42L42_VOL_DAC, chs, false);
 562                 break;
 563         case CS42L42_VOL_ADC:
 564                 if (chs & BIT(0))
 565                         cs42l42->vol[ofs] = *valp;
 566                 if (spec->capture_started)
 567                         cs42l42_mute(cs42l42, CS42L42_VOL_ADC, chs, false);
 568                 break;
 569         default:
 570                 break;
 571         }
 572
 573         return 0;
 574 }
 575
 576 static void cs42l42_playback_pcm_hook(struct hda_pcm_stream *hinfo,
 577                                    struct hda_codec *codec,
 578                                    struct snd_pcm_substream *substream,
 579                                    int action)
 580 {
 581         struct cs8409_spec *spec = codec->spec;
 582         struct sub_codec *cs42l42;
 583         int i;
 584         bool mute;
 585
 586         switch (action) {
 587         case HDA_GEN_PCM_ACT_PREPARE:
 588                 mute = false;
 589                 spec->playback_started = 1;
 590                 break;
 591         case HDA_GEN_PCM_ACT_CLEANUP:
 592                 mute = true;
 593                 spec->playback_started = 0;
 594                 break;
 595         default:
 596                 return;
 597         }
 598
 599         for (i = 0; i < spec->num_scodecs; i++) {
 600                 cs42l42 = spec->scodecs[i];
 601                 cs42l42_mute(cs42l42, CS42L42_VOL_DAC, 0x3, mute);
 602         }
 603 }
 604
 605 static void cs42l42_capture_pcm_hook(struct hda_pcm_stream *hinfo,
 606                                    struct hda_codec *codec,
 607                                    struct snd_pcm_substream *substream,
 608                                    int action)
 609 {
 610         struct cs8409_spec *spec = codec->spec;
 611         struct sub_codec *cs42l42;
 612         int i;
 613         bool mute;
 614
 615         switch (action) {
 616         case HDA_GEN_PCM_ACT_PREPARE:
 617                 mute = false;
 618                 spec->capture_started = 1;
 619                 break;
 620         case HDA_GEN_PCM_ACT_CLEANUP:
 621                 mute = true;
 622                 spec->capture_started = 0;
 623                 break;
 624         default:
 625                 return;
 626         }
 627
 628         for (i = 0; i < spec->num_scodecs; i++) {
 629                 cs42l42 = spec->scodecs[i];
 630                 cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute);
 631         }
 632 }
 633
 634 /* Configure CS42L42 slave codec for jack autodetect */
 635 static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42)
 636 {
 637         cs8409_i2c_write(cs42l42, CS42L42_HSBIAS_SC_AUTOCTL, cs42l42->hsbias_hiz);
 638         /* Clear WAKE# */
 639         cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C1);
 640         /* Wait ~2.5ms */
 641         usleep_range(2500, 3000);
 642         /* Set mode WAKE# output follows the combination logic directly */
 643         cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C0);
 644         /* Clear interrupts status */
 645         cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
 646         /* Enable interrupt */
 647         cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
 648 }
 649
 650 /* Enable and run CS42L42 slave codec jack auto detect */
 651 static void cs42l42_run_jack_detect(struct sub_codec *cs42l42)
 652 {
 653         /* Clear interrupts */
 654         cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS);
 655         cs8409_i2c_read(cs42l42, CS42L42_DET_STATUS1);
 656         cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xFF);
 657         cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
 658
 659         cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x87);
 660         cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x86);
 661         cs8409_i2c_write(cs42l42, CS42L42_MISC_DET_CTL, 0x07);
 662         cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFD);
 663         cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
 664         /* Wait ~20ms*/
 665         usleep_range(20000, 25000);
 666         cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 0x77);
 667         cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0xc0);
 668 }
 669
 670 static int cs42l42_manual_hs_det(struct sub_codec *cs42l42)
 671 {
 672         unsigned int hs_det_status;
 673         unsigned int hs_det_comp1;
 674         unsigned int hs_det_comp2;
 675         unsigned int hs_det_sw;
 676         unsigned int hs_type;
 677
 678         /* Set hs detect to manual, active mode */
 679         cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2,
 680                          (1 << CS42L42_HSDET_CTRL_SHIFT) |
 681                          (0 << CS42L42_HSDET_SET_SHIFT) |
 682                          (0 << CS42L42_HSBIAS_REF_SHIFT) |
 683                          (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
 684
 685         /* Configure HS DET comparator reference levels. */
 686         cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1,
 687                          (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
 688                          (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
 689
 690         /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
 691         cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
 692
 693         msleep(100);
 694
 695         hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
 696
 697         hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
 698                         CS42L42_HSDET_COMP1_OUT_SHIFT;
 699         hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
 700                         CS42L42_HSDET_COMP2_OUT_SHIFT;
 701
 702         /* Close the SW_HSB_HS3 switch for a Type 2 headset. */
 703         cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
 704
 705         msleep(100);
 706
 707         hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
 708
 709         hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
 710                         CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
 711         hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
 712                         CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
 713
 714         /* Use Comparator 1 with 1.25V Threshold. */
 715         switch (hs_det_comp1) {
 716         case CS42L42_HSDET_COMP_TYPE1:
 717                 hs_type = CS42L42_PLUG_CTIA;
 718                 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
 719                 break;
 720         case CS42L42_HSDET_COMP_TYPE2:
 721                 hs_type = CS42L42_PLUG_OMTP;
 722                 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
 723                 break;
 724         default:
 725                 /* Fallback to Comparator 2 with 1.75V Threshold. */
 726                 switch (hs_det_comp2) {
 727                 case CS42L42_HSDET_COMP_TYPE1:
 728                         hs_type = CS42L42_PLUG_CTIA;
 729                         hs_det_sw = CS42L42_HSDET_SW_TYPE1;
 730                         break;
 731                 case CS42L42_HSDET_COMP_TYPE2:
 732                         hs_type = CS42L42_PLUG_OMTP;
 733                         hs_det_sw = CS42L42_HSDET_SW_TYPE2;
 734                         break;
 735                 case CS42L42_HSDET_COMP_TYPE3:
 736                         hs_type = CS42L42_PLUG_HEADPHONE;
 737                         hs_det_sw = CS42L42_HSDET_SW_TYPE3;
 738                         break;
 739                 default:
 740                         hs_type = CS42L42_PLUG_INVALID;
 741                         hs_det_sw = CS42L42_HSDET_SW_TYPE4;
 742                         break;
 743                 }
 744         }
 745
 746         /* Set Switches */
 747         cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, hs_det_sw);
 748
 749         /* Set HSDET mode to Manual—Disabled */
 750         cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2,
 751                          (0 << CS42L42_HSDET_CTRL_SHIFT) |
 752                          (0 << CS42L42_HSDET_SET_SHIFT) |
 753                          (0 << CS42L42_HSBIAS_REF_SHIFT) |
 754                          (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
 755
 756         /* Configure HS DET comparator reference levels. */
 757         cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1,
 758                          (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
 759                          (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
 760
 761         return hs_type;
 762 }
 763
 764 static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status)
 765 {
 766         int status_changed = 0;
 767
 768         /* TIP_SENSE INSERT/REMOVE */
 769         switch (reg_ts_status) {
 770         case CS42L42_TS_PLUG:
 771                 if (cs42l42->no_type_dect) {
 772                         status_changed = 1;
 773                         cs42l42->hp_jack_in = 1;
 774                         cs42l42->mic_jack_in = 0;
 775                 } else {
 776                         cs42l42_run_jack_detect(cs42l42);
 777                 }
 778                 break;
 779
 780         case CS42L42_TS_UNPLUG:
 781                 status_changed = 1;
 782                 cs42l42->hp_jack_in = 0;
 783                 cs42l42->mic_jack_in = 0;
 784                 break;
 785         default:
 786                 /* jack in transition */
 787                 break;
 788         }
 789
 790         codec_dbg(cs42l42->codec, "Tip Sense Detection: (%d)\n", reg_ts_status);
 791
 792         return status_changed;
 793 }
 794
 795 static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42)
 796 {
 797         int current_plug_status;
 798         int status_changed = 0;
 799         int reg_cdc_status;
 800         int reg_hs_status;
 801         int reg_ts_status;
 802         int type;
 803
 804         /* Read jack detect status registers */
 805         reg_cdc_status = cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS);
 806         reg_hs_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
 807         reg_ts_status = cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
 808
 809         /* If status values are < 0, read error has occurred. */
 810         if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0)
 811                 return -EIO;
 812
 813         current_plug_status = (reg_ts_status & (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK))
 814                                 >> CS42L42_TS_PLUG_SHIFT;
 815
 816         /* HSDET_AUTO_DONE */
 817         if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE_MASK) {
 818
 819                 /* Disable HSDET_AUTO_DONE */
 820                 cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFF);
 821
 822                 type = (reg_hs_status & CS42L42_HSDET_TYPE_MASK) >> CS42L42_HSDET_TYPE_SHIFT;
 823
 824                 /* Configure the HSDET mode. */
 825                 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
 826
 827                 if (cs42l42->no_type_dect) {
 828                         status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);
 829                 } else {
 830                         if (type == CS42L42_PLUG_INVALID || type == CS42L42_PLUG_HEADPHONE) {
 831                                 codec_dbg(cs42l42->codec,
 832                                           "Auto detect value not valid (%d), running manual det\n",
 833                                           type);
 834                                 type = cs42l42_manual_hs_det(cs42l42);
 835                         }
 836
 837                         switch (type) {
 838                         case CS42L42_PLUG_CTIA:
 839                         case CS42L42_PLUG_OMTP:
 840                                 status_changed = 1;
 841                                 cs42l42->hp_jack_in = 1;
 842                                 cs42l42->mic_jack_in = 1;
 843                                 break;
 844                         case CS42L42_PLUG_HEADPHONE:
 845                                 status_changed = 1;
 846                                 cs42l42->hp_jack_in = 1;
 847                                 cs42l42->mic_jack_in = 0;
 848                                 break;
 849                         default:
 850                                 status_changed = 1;
 851                                 cs42l42->hp_jack_in = 0;
 852                                 cs42l42->mic_jack_in = 0;
 853                                 break;
 854                         }
 855                         codec_dbg(cs42l42->codec, "Detection done (%d)\n", type);
 856                 }
 857
 858                 /* Enable the HPOUT ground clamp and configure the HP pull-down */
 859                 cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x02);
 860                 /* Re-Enable Tip Sense Interrupt */
 861                 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
 862         } else {
 863                 status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);
 864         }
 865
 866         return status_changed;
 867 }
 868
 869 static void cs42l42_resume(struct sub_codec *cs42l42)
 870 {
 871         struct hda_codec *codec = cs42l42->codec;
 872         struct cs8409_spec *spec = codec->spec;
 873         struct cs8409_i2c_param irq_regs[] = {
 874                 { CS42L42_CODEC_STATUS, 0x00 },
 875                 { CS42L42_DET_INT_STATUS1, 0x00 },
 876                 { CS42L42_DET_INT_STATUS2, 0x00 },
 877                 { CS42L42_TSRS_PLUG_STATUS, 0x00 },
 878         };
 879         int fsv_old, fsv_new;
 880
 881         /* Bring CS42L42 out of Reset */
 882         spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
 883         spec->gpio_data |= cs42l42->reset_gpio;
 884         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
 885         usleep_range(10000, 15000);
 886
 887         cs42l42->suspended = 0;
 888
 889         /* Initialize CS42L42 companion codec */
 890         cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num);
 891         msleep(CS42L42_INIT_TIMEOUT_MS);
 892
 893         /* Clear interrupts, by reading interrupt status registers */
 894         cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs));
 895
 896         fsv_old = cs8409_i2c_read(cs42l42, CS42L42_HP_CTL);
 897         if (cs42l42->full_scale_vol == CS42L42_FULL_SCALE_VOL_0DB)
 898                 fsv_new = fsv_old & ~CS42L42_FULL_SCALE_VOL_MASK;
 899         else
 900                 fsv_new = fsv_old & CS42L42_FULL_SCALE_VOL_MASK;
 901         if (fsv_new != fsv_old)
 902                 cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv_new);
 903
 904         /* we have to explicitly allow unsol event handling even during the
 905          * resume phase so that the jack event is processed properly
 906          */
 907         snd_hda_codec_allow_unsol_events(cs42l42->codec);
 908
 909         cs42l42_enable_jack_detect(cs42l42);
 910 }
 911
 912 #ifdef CONFIG_PM
 913 static void cs42l42_suspend(struct sub_codec *cs42l42)
 914 {
 915         struct hda_codec *codec = cs42l42->codec;
 916         struct cs8409_spec *spec = codec->spec;
 917         int reg_cdc_status = 0;
 918         const struct cs8409_i2c_param cs42l42_pwr_down_seq[] = {
 919                 { CS42L42_DAC_CTL2, 0x02 },
 920                 { CS42L42_HS_CLAMP_DISABLE, 0x00 },
 921                 { CS42L42_MIXER_CHA_VOL, 0x3F },
 922                 { CS42L42_MIXER_ADC_VOL, 0x3F },
 923                 { CS42L42_MIXER_CHB_VOL, 0x3F },
 924                 { CS42L42_HP_CTL, 0x0F },
 925                 { CS42L42_ASP_RX_DAI0_EN, 0x00 },
 926                 { CS42L42_ASP_CLK_CFG, 0x00 },
 927                 { CS42L42_PWR_CTL1, 0xFE },
 928                 { CS42L42_PWR_CTL2, 0x8C },
 929                 { CS42L42_PWR_CTL1, 0xFF },
 930         };
 931
 932         cs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq));
 933
 934         if (read_poll_timeout(cs8409_i2c_read, reg_cdc_status,
 935                         (reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US,
 936                         true, cs42l42, CS42L42_CODEC_STATUS) < 0)
 937                 codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n");
 938
 939         /* Power down CS42L42 ASP/EQ/MIX/HP */
 940         cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x9C);
 941         cs42l42->suspended = 1;
 942         cs42l42->last_page = 0;
 943         cs42l42->hp_jack_in = 0;
 944         cs42l42->mic_jack_in = 0;
 945
 946         /* Put CS42L42 into Reset */
 947         spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
 948         spec->gpio_data &= ~cs42l42->reset_gpio;
 949         snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
 950 }
 951 #endif
 952
 953 static void cs8409_free(struct hda_codec *codec)
 954 {
 955         struct cs8409_spec *spec = codec->spec;
 956
 957         /* Cancel i2c clock disable timer, and disable clock if left enabled */
 958         cancel_delayed_work_sync(&spec->i2c_clk_work);
 959         cs8409_disable_i2c_clock(codec);
 960
 961         snd_hda_gen_free(codec);
 962 }
 963
 964 /******************************************************************************
 965  *                   BULLSEYE / WARLOCK / CYBORG Specific Functions
 966  *                               CS8409/CS42L42
 967  ******************************************************************************/
 968
 969 /*
 970  * In the case of CS8409 we do not have unsolicited events from NID's 0x24
 971  * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will
 972  * generate interrupt via gpio 4 to notify jack events. We have to overwrite
 973  * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
 974  * and then notify status via generic snd_hda_jack_unsol_event() call.
 975  */
 976 static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res)
 977 {
 978         struct cs8409_spec *spec = codec->spec;
 979         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
 980         struct hda_jack_tbl *jk;
 981
 982         /* jack_unsol_event() will be called every time gpio line changing state.
 983          * In this case gpio4 line goes up as a result of reading interrupt status
 984          * registers in previous cs8409_jack_unsol_event() call.
 985          * We don't need to handle this event, ignoring...
 986          */
 987         if (res & cs42l42->irq_mask)
 988                 return;
 989
 990         if (cs42l42_jack_unsol_event(cs42l42)) {
 991                 snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID,
 992                                     cs42l42->hp_jack_in ? 0 : PIN_OUT);
 993                 /* Report jack*/
 994                 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0);
 995                 if (jk)
 996                         snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
 997                                                         AC_UNSOL_RES_TAG);
 998                 /* Report jack*/
 999                 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0);
1000                 if (jk)
1001                         snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1002                                                          AC_UNSOL_RES_TAG);
1003         }
1004 }
1005
1006 #ifdef CONFIG_PM
1007 /* Manage PDREF, when transition to D3hot */
1008 static int cs8409_cs42l42_suspend(struct hda_codec *codec)
1009 {
1010         struct cs8409_spec *spec = codec->spec;
1011         int i;
1012
1013         spec->init_done = 0;
1014
1015         cs8409_enable_ur(codec, 0);
1016
1017         for (i = 0; i < spec->num_scodecs; i++)
1018                 cs42l42_suspend(spec->scodecs[i]);
1019
1020         /* Cancel i2c clock disable timer, and disable clock if left enabled */
1021         cancel_delayed_work_sync(&spec->i2c_clk_work);
1022         cs8409_disable_i2c_clock(codec);
1023
1024         snd_hda_shutup_pins(codec);
1025
1026         return 0;
1027 }
1028 #endif
1029
1030 /* Vendor specific HW configuration
1031  * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
1032  */
1033 static void cs8409_cs42l42_hw_init(struct hda_codec *codec)
1034 {
1035         const struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg;
1036         const struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn;
1037         struct cs8409_spec *spec = codec->spec;
1038         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1039
1040         if (spec->gpio_mask) {
1041                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1042                         spec->gpio_mask);
1043                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1044                         spec->gpio_dir);
1045                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1046                         spec->gpio_data);
1047         }
1048
1049         for (; seq->nid; seq++)
1050                 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1051
1052         if (codec->fixup_id == CS8409_BULLSEYE) {
1053                 for (; seq_bullseye->nid; seq_bullseye++)
1054                         cs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff);
1055         }
1056
1057         switch (codec->fixup_id) {
1058         case CS8409_CYBORG:
1059         case CS8409_WARLOCK_MLK_DUAL_MIC:
1060                 /* DMIC1_MO=00b, DMIC1/2_SR=1 */
1061                 cs8409_vendor_coef_set(codec, CS8409_DMIC_CFG, 0x0003);
1062                 break;
1063         case CS8409_ODIN:
1064                 /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=0 */
1065                 cs8409_vendor_coef_set(codec, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc00);
1066                 break;
1067         default:
1068                 break;
1069         }
1070
1071         cs42l42_resume(cs42l42);
1072
1073         /* Enable Unsolicited Response */
1074         cs8409_enable_ur(codec, 1);
1075 }
1076
1077 static const struct hda_codec_ops cs8409_cs42l42_patch_ops = {
1078         .build_controls = cs8409_build_controls,
1079         .build_pcms = snd_hda_gen_build_pcms,
1080         .init = cs8409_init,
1081         .free = cs8409_free,
1082         .unsol_event = cs8409_cs42l42_jack_unsol_event,
1083 #ifdef CONFIG_PM
1084         .suspend = cs8409_cs42l42_suspend,
1085 #endif
1086 };
1087
1088 static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
1089                                     unsigned int *res)
1090 {
1091         struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1092         struct cs8409_spec *spec = codec->spec;
1093         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1094
1095         unsigned int nid = ((cmd >> 20) & 0x07f);
1096         unsigned int verb = ((cmd >> 8) & 0x0fff);
1097
1098         /* CS8409 pins have no AC_PINSENSE_PRESENCE
1099          * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34
1100          * and return correct pin sense values for read_pin_sense() call from
1101          * hda_jack based on CS42L42 jack detect status.
1102          */
1103         switch (nid) {
1104         case CS8409_CS42L42_HP_PIN_NID:
1105                 if (verb == AC_VERB_GET_PIN_SENSE) {
1106                         *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1107                         return 0;
1108                 }
1109                 break;
1110         case CS8409_CS42L42_AMIC_PIN_NID:
1111                 if (verb == AC_VERB_GET_PIN_SENSE) {
1112                         *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1113                         return 0;
1114                 }
1115                 break;
1116         default:
1117                 break;
1118         }
1119
1120         return spec->exec_verb(dev, cmd, flags, res);
1121 }
1122
1123 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1124 {
1125         struct cs8409_spec *spec = codec->spec;
1126
1127         switch (action) {
1128         case HDA_FIXUP_ACT_PRE_PROBE:
1129                 snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs);
1130                 /* verb exec op override */
1131                 spec->exec_verb = codec->core.exec_verb;
1132                 codec->core.exec_verb = cs8409_cs42l42_exec_verb;
1133
1134                 spec->scodecs[CS8409_CODEC0] = &cs8409_cs42l42_codec;
1135                 spec->num_scodecs = 1;
1136                 spec->scodecs[CS8409_CODEC0]->codec = codec;
1137                 codec->patch_ops = cs8409_cs42l42_patch_ops;
1138
1139                 spec->gen.suppress_auto_mute = 1;
1140                 spec->gen.no_primary_hp = 1;
1141                 spec->gen.suppress_vmaster = 1;
1142
1143                 spec->speaker_pdn_gpio = 0;
1144
1145                 /* GPIO 5 out, 3,4 in */
1146                 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio;
1147                 spec->gpio_data = 0;
1148                 spec->gpio_mask = 0x03f;
1149
1150                 /* Basic initial sequence for specific hw configuration */
1151                 snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs);
1152
1153                 cs8409_fix_caps(codec, CS8409_CS42L42_HP_PIN_NID);
1154                 cs8409_fix_caps(codec, CS8409_CS42L42_AMIC_PIN_NID);
1155
1156                 spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020;
1157
1158                 switch (codec->fixup_id) {
1159                 case CS8409_CYBORG:
1160                         spec->scodecs[CS8409_CODEC0]->full_scale_vol =
1161                                 CS42L42_FULL_SCALE_VOL_MINUS6DB;
1162                         spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN;
1163                         break;
1164                 case CS8409_ODIN:
1165                         spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB;
1166                         spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN;
1167                         break;
1168                 case CS8409_WARLOCK_MLK:
1169                 case CS8409_WARLOCK_MLK_DUAL_MIC:
1170                         spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB;
1171                         spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN;
1172                         break;
1173                 default:
1174                         spec->scodecs[CS8409_CODEC0]->full_scale_vol =
1175                                 CS42L42_FULL_SCALE_VOL_MINUS6DB;
1176                         spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN;
1177                         break;
1178                 }
1179
1180                 if (spec->speaker_pdn_gpio > 0) {
1181                         spec->gpio_dir |= spec->speaker_pdn_gpio;
1182                         spec->gpio_data |= spec->speaker_pdn_gpio;
1183                 }
1184
1185                 break;
1186         case HDA_FIXUP_ACT_PROBE:
1187                 /* Fix Sample Rate to 48kHz */
1188                 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1189                 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1190                 /* add hooks */
1191                 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1192                 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1193                 if (codec->fixup_id != CS8409_ODIN)
1194                         /* Set initial DMIC volume to -26 dB */
1195                         snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID,
1196                                                       HDA_INPUT, 0, 0xff, 0x19);
1197                 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1198                                 &cs42l42_dac_volume_mixer);
1199                 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume",
1200                                 &cs42l42_adc_volume_mixer);
1201                 if (spec->speaker_pdn_gpio > 0)
1202                         snd_hda_gen_add_kctl(&spec->gen, "Speaker Playback Switch",
1203                                              &cs8409_spk_sw_ctrl);
1204                 /* Disable Unsolicited Response during boot */
1205                 cs8409_enable_ur(codec, 0);
1206                 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1207                 break;
1208         case HDA_FIXUP_ACT_INIT:
1209                 cs8409_cs42l42_hw_init(codec);
1210                 spec->init_done = 1;
1211                 if (spec->init_done && spec->build_ctrl_done
1212                         && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1213                         cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1214                 break;
1215         case HDA_FIXUP_ACT_BUILD:
1216                 spec->build_ctrl_done = 1;
1217                 /* Run jack auto detect first time on boot
1218                  * after controls have been added, to check if jack has
1219                  * been already plugged in.
1220                  * Run immediately after init.
1221                  */
1222                 if (spec->init_done && spec->build_ctrl_done
1223                         && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1224                         cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1225                 break;
1226         default:
1227                 break;
1228         }
1229 }
1230
1231 /******************************************************************************
1232  *                          Dolphin Specific Functions
1233  *                               CS8409/ 2 X CS42L42
1234  ******************************************************************************/
1235
1236 /*
1237  * In the case of CS8409 we do not have unsolicited events when
1238  * hs mic and hp are connected. Companion codec CS42L42 will
1239  * generate interrupt via irq_mask to notify jack events. We have to overwrite
1240  * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
1241  * and then notify status via generic snd_hda_jack_unsol_event() call.
1242  */
1243 static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res)
1244 {
1245         struct cs8409_spec *spec = codec->spec;
1246         struct sub_codec *cs42l42;
1247         struct hda_jack_tbl *jk;
1248
1249         cs42l42 = spec->scodecs[CS8409_CODEC0];
1250         if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1251             cs42l42_jack_unsol_event(cs42l42)) {
1252                 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0);
1253                 if (jk)
1254                         snd_hda_jack_unsol_event(codec,
1255                                                  (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1256                                                   AC_UNSOL_RES_TAG);
1257
1258                 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0);
1259                 if (jk)
1260                         snd_hda_jack_unsol_event(codec,
1261                                                  (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1262                                                   AC_UNSOL_RES_TAG);
1263         }
1264
1265         cs42l42 = spec->scodecs[CS8409_CODEC1];
1266         if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1267             cs42l42_jack_unsol_event(cs42l42)) {
1268                 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0);
1269                 if (jk)
1270                         snd_hda_jack_unsol_event(codec,
1271                                                  (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1272                                                   AC_UNSOL_RES_TAG);
1273         }
1274 }
1275
1276 /* Vendor specific HW configuration
1277  * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
1278  */
1279 static void dolphin_hw_init(struct hda_codec *codec)
1280 {
1281         const struct cs8409_cir_param *seq = dolphin_hw_cfg;
1282         struct cs8409_spec *spec = codec->spec;
1283         struct sub_codec *cs42l42;
1284         int i;
1285
1286         if (spec->gpio_mask) {
1287                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1288                                     spec->gpio_mask);
1289                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1290                                     spec->gpio_dir);
1291                 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1292                                     spec->gpio_data);
1293         }
1294
1295         for (; seq->nid; seq++)
1296                 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1297
1298         for (i = 0; i < spec->num_scodecs; i++) {
1299                 cs42l42 = spec->scodecs[i];
1300                 cs42l42_resume(cs42l42);
1301         }
1302
1303         /* Enable Unsolicited Response */
1304         cs8409_enable_ur(codec, 1);
1305 }
1306
1307 static const struct hda_codec_ops cs8409_dolphin_patch_ops = {
1308         .build_controls = cs8409_build_controls,
1309         .build_pcms = snd_hda_gen_build_pcms,
1310         .init = cs8409_init,
1311         .free = cs8409_free,
1312         .unsol_event = dolphin_jack_unsol_event,
1313 #ifdef CONFIG_PM
1314         .suspend = cs8409_cs42l42_suspend,
1315 #endif
1316 };
1317
1318 static int dolphin_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
1319                              unsigned int *res)
1320 {
1321         struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1322         struct cs8409_spec *spec = codec->spec;
1323         struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1324
1325         unsigned int nid = ((cmd >> 20) & 0x07f);
1326         unsigned int verb = ((cmd >> 8) & 0x0fff);
1327
1328         /* CS8409 pins have no AC_PINSENSE_PRESENCE
1329          * capabilities. We have to intercept calls for CS42L42 pins
1330          * and return correct pin sense values for read_pin_sense() call from
1331          * hda_jack based on CS42L42 jack detect status.
1332          */
1333         switch (nid) {
1334         case DOLPHIN_HP_PIN_NID:
1335         case DOLPHIN_LO_PIN_NID:
1336                 if (nid == DOLPHIN_LO_PIN_NID)
1337                         cs42l42 = spec->scodecs[CS8409_CODEC1];
1338                 if (verb == AC_VERB_GET_PIN_SENSE) {
1339                         *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1340                         return 0;
1341                 }
1342                 break;
1343         case DOLPHIN_AMIC_PIN_NID:
1344                 if (verb == AC_VERB_GET_PIN_SENSE) {
1345                         *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1346                         return 0;
1347                 }
1348                 break;
1349         default:
1350                 break;
1351         }
1352
1353         return spec->exec_verb(dev, cmd, flags, res);
1354 }
1355
1356 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1357 {
1358         struct cs8409_spec *spec = codec->spec;
1359         struct snd_kcontrol_new *kctrl;
1360         int i;
1361
1362         switch (action) {
1363         case HDA_FIXUP_ACT_PRE_PROBE:
1364                 snd_hda_add_verbs(codec, dolphin_init_verbs);
1365                 /* verb exec op override */
1366                 spec->exec_verb = codec->core.exec_verb;
1367                 codec->core.exec_verb = dolphin_exec_verb;
1368
1369                 spec->scodecs[CS8409_CODEC0] = &dolphin_cs42l42_0;
1370                 spec->scodecs[CS8409_CODEC0]->codec = codec;
1371                 spec->scodecs[CS8409_CODEC1] = &dolphin_cs42l42_1;
1372                 spec->scodecs[CS8409_CODEC1]->codec = codec;
1373                 spec->num_scodecs = 2;
1374                 spec->gen.suppress_vmaster = 1;
1375
1376                 codec->patch_ops = cs8409_dolphin_patch_ops;
1377
1378                 /* GPIO 1,5 out, 0,4 in */
1379                 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio |
1380                                  spec->scodecs[CS8409_CODEC1]->reset_gpio;
1381                 spec->gpio_data = 0;
1382                 spec->gpio_mask = 0x03f;
1383
1384                 /* Basic initial sequence for specific hw configuration */
1385                 snd_hda_sequence_write(codec, dolphin_init_verbs);
1386
1387                 snd_hda_jack_add_kctl(codec, DOLPHIN_LO_PIN_NID, "Line Out", true,
1388                                       SND_JACK_HEADPHONE, NULL);
1389
1390                 snd_hda_jack_add_kctl(codec, DOLPHIN_AMIC_PIN_NID, "Microphone", true,
1391                                       SND_JACK_MICROPHONE, NULL);
1392
1393                 cs8409_fix_caps(codec, DOLPHIN_HP_PIN_NID);
1394                 cs8409_fix_caps(codec, DOLPHIN_LO_PIN_NID);
1395                 cs8409_fix_caps(codec, DOLPHIN_AMIC_PIN_NID);
1396
1397                 spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB;
1398                 spec->scodecs[CS8409_CODEC1]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB;
1399
1400                 break;
1401         case HDA_FIXUP_ACT_PROBE:
1402                 /* Fix Sample Rate to 48kHz */
1403                 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1404                 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1405                 /* add hooks */
1406                 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1407                 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1408                 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1409                                      &cs42l42_dac_volume_mixer);
1410                 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer);
1411                 kctrl = snd_hda_gen_add_kctl(&spec->gen, "Line Out Playback Volume",
1412                                              &cs42l42_dac_volume_mixer);
1413                 /* Update Line Out kcontrol template */
1414                 kctrl->private_value = HDA_COMPOSE_AMP_VAL_OFS(DOLPHIN_HP_PIN_NID, 3, CS8409_CODEC1,
1415                                        HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE;
1416                 cs8409_enable_ur(codec, 0);
1417                 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1418                 break;
1419         case HDA_FIXUP_ACT_INIT:
1420                 dolphin_hw_init(codec);
1421                 spec->init_done = 1;
1422                 if (spec->init_done && spec->build_ctrl_done) {
1423                         for (i = 0; i < spec->num_scodecs; i++) {
1424                                 if (!spec->scodecs[i]->hp_jack_in)
1425                                         cs42l42_run_jack_detect(spec->scodecs[i]);
1426                         }
1427                 }
1428                 break;
1429         case HDA_FIXUP_ACT_BUILD:
1430                 spec->build_ctrl_done = 1;
1431                 /* Run jack auto detect first time on boot
1432                  * after controls have been added, to check if jack has
1433                  * been already plugged in.
1434                  * Run immediately after init.
1435                  */
1436                 if (spec->init_done && spec->build_ctrl_done) {
1437                         for (i = 0; i < spec->num_scodecs; i++) {
1438                                 if (!spec->scodecs[i]->hp_jack_in)
1439                                         cs42l42_run_jack_detect(spec->scodecs[i]);
1440                         }
1441                 }
1442                 break;
1443         default:
1444                 break;
1445         }
1446 }
1447
1448 static int patch_cs8409(struct hda_codec *codec)
1449 {
1450         int err;
1451
1452         if (!cs8409_alloc_spec(codec))
1453                 return -ENOMEM;
1454
1455         snd_hda_pick_fixup(codec, cs8409_models, cs8409_fixup_tbl, cs8409_fixups);
1456
1457         codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", codec->fixup_id,
1458                          codec->bus->pci->subsystem_vendor,
1459                          codec->bus->pci->subsystem_device);
1460
1461         snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
1462
1463         err = cs8409_parse_auto_config(codec);
1464         if (err < 0) {
1465                 cs8409_free(codec);
1466                 return err;
1467         }
1468
1469         snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE);
1470         return 0;
1471 }
1472
1473 static const struct hda_device_id snd_hda_id_cs8409[] = {
1474         HDA_CODEC_ENTRY(0x10138409, "CS8409", patch_cs8409),
1475         {} /* terminator */
1476 };
1477 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cs8409);
1478
1479 static struct hda_codec_driver cs8409_driver = {
1480         .id = snd_hda_id_cs8409,
1481 };
1482 module_hda_codec_driver(cs8409_driver);
1483
1484 MODULE_LICENSE("GPL");
1485 MODULE_DESCRIPTION("Cirrus Logic HDA bridge");