1 // SPDX-License-Identifier: GPL-2.0-only
3 * patch_cs8409-tables.c -- HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
5 * Copyright (C) 2021 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
8 * Author: Lucas Tanure <tanureal@opensource.cirrus.com>
11 #include "patch_cs8409.h"
13 /******************************************************************************
14 * CS42L42 Specific Data
16 ******************************************************************************/
18 static const DECLARE_TLV_DB_SCALE(cs42l42_dac_db_scale, CS42L42_HP_VOL_REAL_MIN * 100, 100, 1);
20 static const DECLARE_TLV_DB_SCALE(cs42l42_adc_db_scale, CS42L42_AMIC_VOL_REAL_MIN * 100, 100, 1);
22 const struct snd_kcontrol_new cs42l42_dac_volume_mixer = {
23 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
25 .subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG),
26 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ),
27 .info = cs42l42_volume_info,
28 .get = cs42l42_volume_get,
29 .put = cs42l42_volume_put,
30 .tlv = { .p = cs42l42_dac_db_scale },
31 .private_value = HDA_COMPOSE_AMP_VAL_OFS(CS8409_PIN_ASP1_TRANSMITTER_A, 3, CS8409_CODEC0,
32 HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE
35 const struct snd_kcontrol_new cs42l42_adc_volume_mixer = {
36 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
38 .subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG),
39 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ),
40 .info = cs42l42_volume_info,
41 .get = cs42l42_volume_get,
42 .put = cs42l42_volume_put,
43 .tlv = { .p = cs42l42_adc_db_scale },
44 .private_value = HDA_COMPOSE_AMP_VAL_OFS(CS8409_PIN_ASP1_RECEIVER_A, 1, CS8409_CODEC0,
45 HDA_INPUT, CS42L42_VOL_ADC) | HDA_AMP_VAL_MIN_MUTE
48 /******************************************************************************
49 * BULLSEYE / WARLOCK / CYBORG Specific Arrays
51 ******************************************************************************/
53 const struct hda_verb cs8409_cs42l42_init_verbs[] = {
54 { CS8409_PIN_AFG, AC_VERB_SET_GPIO_WAKE_MASK, 0x0018 }, /* WAKE from GPIO 3,4 */
55 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing */
56 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */
57 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0080 }, /* I2C mode */
58 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */
59 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0200 }, /* 100kHz I2C_STO = 2 */
63 const struct hda_pintbl cs8409_cs42l42_pincfgs[] = {
64 { CS8409_PIN_ASP1_TRANSMITTER_A, 0x042120f0 }, /* ASP-1-TX */
65 { CS8409_PIN_ASP1_RECEIVER_A, 0x04a12050 }, /* ASP-1-RX */
66 { CS8409_PIN_ASP2_TRANSMITTER_A, 0x901000f0 }, /* ASP-2-TX */
67 { CS8409_PIN_DMIC1_IN, 0x90a00090 }, /* DMIC-1 */
71 /* Vendor specific HW configuration for CS42L42 */
72 static const struct cs8409_i2c_param cs42l42_init_reg_seq[] = {
134 /* Vendor specific hw configuration for CS8409 */
135 const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[] = {
136 /* +PLL1/2_EN, +I2C_EN */
137 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0xb008 },
138 /* ASP1/2_EN=0, ASP1_STP=1 */
139 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0002 },
140 /* ASP1/2_BUS_IDLE=10, +GPIO_I2C */
141 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG3, 0x0a80 },
142 /* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
143 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL1, 0x0800 },
144 /* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */
145 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL2, 0x0820 },
146 /* ASP2.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
147 { CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL1, 0x0800 },
148 /* ASP2.A: TX.RAP=1, TX.RSZ=24 bits, TX.RCS=0 */
149 { CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL2, 0x2800 },
150 /* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */
151 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL1, 0x0800 },
152 /* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */
153 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL2, 0x0800 },
154 /* ASP1: LCHI = 00h */
155 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL1, 0x8000 },
156 /* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */
157 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL2, 0x28ff },
158 /* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */
159 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL3, 0x0062 },
161 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL1, 0x801f },
162 /* ASP2: MC/SC_SRCSEL=PLL1, LCPR=3Fh */
163 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL2, 0x283f },
164 /* ASP2: 5050=1, MCEN=0, FSD=010, SCPOL_IN/OUT=1, SCDIV=1:16 */
165 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL3, 0x805c },
166 /* DMIC1_MO=10b, DMIC1/2_SR=1 */
167 { CS8409_PIN_VENDOR_WIDGET, CS8409_DMIC_CFG, 0x0023 },
169 { CS8409_PIN_VENDOR_WIDGET, CS8409_BEEP_CFG, 0x0000 },
170 /* ASP1/2_EN=1, ASP1_STP=1 */
171 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0062 },
173 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0x9008 },
174 /* TX2.A: pre-scale att.=0 dB */
175 { CS8409_PIN_VENDOR_WIDGET, CS8409_PRE_SCALE_ATTN2, 0x0000 },
176 /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=1 */
177 { CS8409_PIN_VENDOR_WIDGET, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc03 },
179 { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x9999 },
180 /* GPIO hysteresis = 30 us */
181 { CS8409_PIN_VENDOR_WIDGET, 0xc5, 0x0000 },
183 { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x0000 },
187 const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[] = {
188 /* EQ_SEL=1, EQ1/2_EN=0 */
189 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4000 },
191 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x4000 },
193 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4010 },
194 /* EQ_DATA_HI=0x0647 */
195 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 },
196 /* +EQ_WRT, +EQ_ACC, EQ_ADR=0, EQ_DATA_LO=0x67 */
197 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc0c7 },
198 /* EQ_DATA_HI=0x0647 */
199 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 },
200 /* +EQ_WRT, +EQ_ACC, EQ_ADR=1, EQ_DATA_LO=0x67 */
201 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc1c7 },
202 /* EQ_DATA_HI=0xf370 */
203 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xf370 },
204 /* +EQ_WRT, +EQ_ACC, EQ_ADR=2, EQ_DATA_LO=0x71 */
205 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc271 },
206 /* EQ_DATA_HI=0x1ef8 */
207 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ef8 },
208 /* +EQ_WRT, +EQ_ACC, EQ_ADR=3, EQ_DATA_LO=0x48 */
209 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc348 },
210 /* EQ_DATA_HI=0xc110 */
211 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc110 },
212 /* +EQ_WRT, +EQ_ACC, EQ_ADR=4, EQ_DATA_LO=0x5a */
213 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc45a },
214 /* EQ_DATA_HI=0x1f29 */
215 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1f29 },
216 /* +EQ_WRT, +EQ_ACC, EQ_ADR=5, EQ_DATA_LO=0x74 */
217 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc574 },
218 /* EQ_DATA_HI=0x1d7a */
219 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1d7a },
220 /* +EQ_WRT, +EQ_ACC, EQ_ADR=6, EQ_DATA_LO=0x53 */
221 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc653 },
222 /* EQ_DATA_HI=0xc38c */
223 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c },
224 /* +EQ_WRT, +EQ_ACC, EQ_ADR=7, EQ_DATA_LO=0x14 */
225 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc714 },
226 /* EQ_DATA_HI=0x1ca3 */
227 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ca3 },
228 /* +EQ_WRT, +EQ_ACC, EQ_ADR=8, EQ_DATA_LO=0xc7 */
229 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc8c7 },
230 /* EQ_DATA_HI=0xc38c */
231 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c },
232 /* +EQ_WRT, +EQ_ACC, EQ_ADR=9, EQ_DATA_LO=0x14 */
233 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc914 },
234 /* -EQ_ACC, -EQ_WRT */
235 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x0000 },
239 struct sub_codec cs8409_cs42l42_codec = {
240 .addr = CS42L42_I2C_ADDR,
241 .reset_gpio = CS8409_CS42L42_RESET,
242 .irq_mask = CS8409_CS42L42_INT,
243 .init_seq = cs42l42_init_reg_seq,
244 .init_seq_num = ARRAY_SIZE(cs42l42_init_reg_seq),
252 /******************************************************************************
253 * CS8409 Patch Driver Structs
254 * Arrays Used for all projects using CS8409
255 ******************************************************************************/
257 const struct snd_pci_quirk cs8409_fixup_tbl[] = {
258 SND_PCI_QUIRK(0x1028, 0x0A11, "Bullseye", CS8409_BULLSEYE),
259 SND_PCI_QUIRK(0x1028, 0x0A12, "Bullseye", CS8409_BULLSEYE),
260 SND_PCI_QUIRK(0x1028, 0x0A23, "Bullseye", CS8409_BULLSEYE),
261 SND_PCI_QUIRK(0x1028, 0x0A24, "Bullseye", CS8409_BULLSEYE),
262 SND_PCI_QUIRK(0x1028, 0x0A25, "Bullseye", CS8409_BULLSEYE),
263 SND_PCI_QUIRK(0x1028, 0x0A29, "Bullseye", CS8409_BULLSEYE),
264 SND_PCI_QUIRK(0x1028, 0x0A2A, "Bullseye", CS8409_BULLSEYE),
265 SND_PCI_QUIRK(0x1028, 0x0A2B, "Bullseye", CS8409_BULLSEYE),
266 SND_PCI_QUIRK(0x1028, 0x0AB0, "Warlock", CS8409_WARLOCK),
267 SND_PCI_QUIRK(0x1028, 0x0AB2, "Warlock", CS8409_WARLOCK),
268 SND_PCI_QUIRK(0x1028, 0x0AB1, "Warlock", CS8409_WARLOCK),
269 SND_PCI_QUIRK(0x1028, 0x0AB3, "Warlock", CS8409_WARLOCK),
270 SND_PCI_QUIRK(0x1028, 0x0AB4, "Warlock", CS8409_WARLOCK),
271 SND_PCI_QUIRK(0x1028, 0x0AB5, "Warlock", CS8409_WARLOCK),
272 SND_PCI_QUIRK(0x1028, 0x0AD9, "Warlock", CS8409_WARLOCK),
273 SND_PCI_QUIRK(0x1028, 0x0ADA, "Warlock", CS8409_WARLOCK),
274 SND_PCI_QUIRK(0x1028, 0x0ADB, "Warlock", CS8409_WARLOCK),
275 SND_PCI_QUIRK(0x1028, 0x0ADC, "Warlock", CS8409_WARLOCK),
276 SND_PCI_QUIRK(0x1028, 0x0AF4, "Warlock", CS8409_WARLOCK),
277 SND_PCI_QUIRK(0x1028, 0x0AF5, "Warlock", CS8409_WARLOCK),
278 SND_PCI_QUIRK(0x1028, 0x0A77, "Cyborg", CS8409_CYBORG),
279 SND_PCI_QUIRK(0x1028, 0x0A78, "Cyborg", CS8409_CYBORG),
280 SND_PCI_QUIRK(0x1028, 0x0A79, "Cyborg", CS8409_CYBORG),
281 SND_PCI_QUIRK(0x1028, 0x0A7A, "Cyborg", CS8409_CYBORG),
282 SND_PCI_QUIRK(0x1028, 0x0A7D, "Cyborg", CS8409_CYBORG),
283 SND_PCI_QUIRK(0x1028, 0x0A7E, "Cyborg", CS8409_CYBORG),
284 SND_PCI_QUIRK(0x1028, 0x0A7F, "Cyborg", CS8409_CYBORG),
285 SND_PCI_QUIRK(0x1028, 0x0A80, "Cyborg", CS8409_CYBORG),
286 SND_PCI_QUIRK(0x1028, 0x0ADF, "Cyborg", CS8409_CYBORG),
287 SND_PCI_QUIRK(0x1028, 0x0AE0, "Cyborg", CS8409_CYBORG),
288 SND_PCI_QUIRK(0x1028, 0x0AE1, "Cyborg", CS8409_CYBORG),
289 SND_PCI_QUIRK(0x1028, 0x0AE2, "Cyborg", CS8409_CYBORG),
290 SND_PCI_QUIRK(0x1028, 0x0AE9, "Cyborg", CS8409_CYBORG),
291 SND_PCI_QUIRK(0x1028, 0x0AEA, "Cyborg", CS8409_CYBORG),
292 SND_PCI_QUIRK(0x1028, 0x0AEB, "Cyborg", CS8409_CYBORG),
293 SND_PCI_QUIRK(0x1028, 0x0AEC, "Cyborg", CS8409_CYBORG),
294 SND_PCI_QUIRK(0x1028, 0x0AED, "Cyborg", CS8409_CYBORG),
295 SND_PCI_QUIRK(0x1028, 0x0AEE, "Cyborg", CS8409_CYBORG),
296 SND_PCI_QUIRK(0x1028, 0x0AEF, "Cyborg", CS8409_CYBORG),
297 SND_PCI_QUIRK(0x1028, 0x0AF0, "Cyborg", CS8409_CYBORG),
301 /* Dell Inspiron models with cs8409/cs42l42 */
302 const struct hda_model_fixup cs8409_models[] = {
303 { .id = CS8409_BULLSEYE, .name = "bullseye" },
304 { .id = CS8409_WARLOCK, .name = "warlock" },
305 { .id = CS8409_CYBORG, .name = "cyborg" },
309 const struct hda_fixup cs8409_fixups[] = {
310 [CS8409_BULLSEYE] = {
311 .type = HDA_FIXUP_PINS,
312 .v.pins = cs8409_cs42l42_pincfgs,
314 .chain_id = CS8409_FIXUPS,
317 .type = HDA_FIXUP_PINS,
318 .v.pins = cs8409_cs42l42_pincfgs,
320 .chain_id = CS8409_FIXUPS,
323 .type = HDA_FIXUP_PINS,
324 .v.pins = cs8409_cs42l42_pincfgs,
326 .chain_id = CS8409_FIXUPS,
329 .type = HDA_FIXUP_FUNC,
330 .v.func = cs8409_cs42l42_fixups,