sound/pci/hda/patch_cs8409-tables.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * patch_cs8409-tables.c  --  HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
   4  *
   5  * Copyright (C) 2021 Cirrus Logic, Inc. and
   6  *                    Cirrus Logic International Semiconductor Ltd.
   7  *
   8  * Author: Lucas Tanure <tanureal@opensource.cirrus.com>
   9  */
  10
  11 #include "patch_cs8409.h"
  12
  13 /******************************************************************************
  14  *                          CS42L42 Specific Data
  15  *
  16  ******************************************************************************/
  17
  18 static const DECLARE_TLV_DB_SCALE(cs42l42_dac_db_scale, CS42L42_HP_VOL_REAL_MIN * 100, 100, 1);
  19
  20 static const DECLARE_TLV_DB_SCALE(cs42l42_adc_db_scale, CS42L42_AMIC_VOL_REAL_MIN * 100, 100, 1);
  21
  22 const struct snd_kcontrol_new cs42l42_dac_volume_mixer = {
  23         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  24         .index = 0,
  25         .subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG),
  26         .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  27         .info = cs42l42_volume_info,
  28         .get = cs42l42_volume_get,
  29         .put = cs42l42_volume_put,
  30         .tlv = { .p = cs42l42_dac_db_scale },
  31         .private_value = HDA_COMPOSE_AMP_VAL_OFS(CS8409_PIN_ASP1_TRANSMITTER_A, 3, CS8409_CODEC0,
  32                          HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE
  33 };
  34
  35 const struct snd_kcontrol_new cs42l42_adc_volume_mixer = {
  36         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  37         .index = 0,
  38         .subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG),
  39         .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  40         .info = cs42l42_volume_info,
  41         .get = cs42l42_volume_get,
  42         .put = cs42l42_volume_put,
  43         .tlv = { .p = cs42l42_adc_db_scale },
  44         .private_value = HDA_COMPOSE_AMP_VAL_OFS(CS8409_PIN_ASP1_RECEIVER_A, 1, CS8409_CODEC0,
  45                          HDA_INPUT, CS42L42_VOL_ADC) | HDA_AMP_VAL_MIN_MUTE
  46 };
  47
  48 const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback = {
  49         .rates = SNDRV_PCM_RATE_48000, /* fixed rate */
  50 };
  51
  52 const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture = {
  53         .rates = SNDRV_PCM_RATE_48000, /* fixed rate */
  54 };
  55
  56 /******************************************************************************
  57  *                   BULLSEYE / WARLOCK / CYBORG Specific Arrays
  58  *                               CS8409/CS42L42
  59  ******************************************************************************/
  60
  61 const struct hda_verb cs8409_cs42l42_init_verbs[] = {
  62         { CS8409_PIN_AFG, AC_VERB_SET_GPIO_WAKE_MASK, 0x0018 },         /* WAKE from GPIO 3,4 */
  63         { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 },   /* Enable VPW processing */
  64         { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 },   /* Configure GPIO 6,7 */
  65         { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0080 },   /* I2C mode */
  66         { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b },   /* Set I2C bus speed */
  67         { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0200 },   /* 100kHz I2C_STO = 2 */
  68         {} /* terminator */
  69 };
  70
  71 const struct hda_pintbl cs8409_cs42l42_pincfgs[] = {
  72         { CS8409_PIN_ASP1_TRANSMITTER_A, 0x042120f0 },  /* ASP-1-TX */
  73         { CS8409_PIN_ASP1_RECEIVER_A, 0x04a12050 },     /* ASP-1-RX */
  74         { CS8409_PIN_ASP2_TRANSMITTER_A, 0x901000f0 },  /* ASP-2-TX */
  75         { CS8409_PIN_DMIC1_IN, 0x90a00090 },            /* DMIC-1 */
  76         {} /* terminator */
  77 };
  78
  79 const struct hda_pintbl cs8409_cs42l42_pincfgs_no_dmic[] = {
  80         { CS8409_PIN_ASP1_TRANSMITTER_A, 0x042120f0 },  /* ASP-1-TX */
  81         { CS8409_PIN_ASP1_RECEIVER_A, 0x04a12050 },     /* ASP-1-RX */
  82         { CS8409_PIN_ASP2_TRANSMITTER_A, 0x901000f0 },  /* ASP-2-TX */
  83         {} /* terminator */
  84 };
  85
  86 /* Vendor specific HW configuration for CS42L42 */
  87 static const struct cs8409_i2c_param cs42l42_init_reg_seq[] = {
  88         { CS42L42_I2C_TIMEOUT, 0xB0 },
  89         { CS42L42_ADC_CTL, 0x00 },
  90         { 0x1D02, 0x06 },
  91         { CS42L42_ADC_VOLUME, 0x9F },
  92         { CS42L42_OSC_SWITCH, 0x01 },
  93         { CS42L42_MCLK_CTL, 0x02 },
  94         { CS42L42_SRC_CTL, 0x03 },
  95         { CS42L42_MCLK_SRC_SEL, 0x00 },
  96         { CS42L42_ASP_FRM_CFG, 0x13 },
  97         { CS42L42_FSYNC_P_LOWER, 0xFF },
  98         { CS42L42_FSYNC_P_UPPER, 0x00 },
  99         { CS42L42_ASP_CLK_CFG, 0x20 },
 100         { CS42L42_SPDIF_CLK_CFG, 0x0D },
 101         { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
 102         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
 103         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
 104         { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
 105         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
 106         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x20 },
 107         { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x02 },
 108         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
 109         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x80 },
 110         { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x02 },
 111         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
 112         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0xA0 },
 113         { CS42L42_ASP_RX_DAI0_EN, 0x0C },
 114         { CS42L42_ASP_TX_CH_EN, 0x01 },
 115         { CS42L42_ASP_TX_CH_AP_RES, 0x02 },
 116         { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
 117         { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
 118         { CS42L42_ASP_TX_SZ_EN, 0x01 },
 119         { CS42L42_PWR_CTL1, 0x0A },
 120         { CS42L42_PWR_CTL2, 0x84 },
 121         { CS42L42_MIXER_CHA_VOL, 0x3F },
 122         { CS42L42_MIXER_CHB_VOL, 0x3F },
 123         { CS42L42_MIXER_ADC_VOL, 0x3f },
 124         { CS42L42_HP_CTL, 0x03 },
 125         { CS42L42_MIC_DET_CTL1, 0xB6 },
 126         { CS42L42_TIPSENSE_CTL, 0xC2 },
 127         { CS42L42_HS_CLAMP_DISABLE, 0x01 },
 128         { CS42L42_HS_SWITCH_CTL, 0xF3 },
 129         { CS42L42_PWR_CTL3, 0x20 },
 130         { CS42L42_RSENSE_CTL2, 0x00 },
 131         { CS42L42_RSENSE_CTL3, 0x00 },
 132         { CS42L42_TSENSE_CTL, 0x80 },
 133         { CS42L42_HS_BIAS_CTL, 0xC0 },
 134         { CS42L42_PWR_CTL1, 0x02 },
 135         { CS42L42_ADC_OVFL_INT_MASK, 0xff },
 136         { CS42L42_MIXER_INT_MASK, 0xff },
 137         { CS42L42_SRC_INT_MASK, 0xff },
 138         { CS42L42_ASP_RX_INT_MASK, 0xff },
 139         { CS42L42_ASP_TX_INT_MASK, 0xff },
 140         { CS42L42_CODEC_INT_MASK, 0xff },
 141         { CS42L42_SRCPL_INT_MASK, 0xff },
 142         { CS42L42_VPMON_INT_MASK, 0xff },
 143         { CS42L42_PLL_LOCK_INT_MASK, 0xff },
 144         { CS42L42_TSRS_PLUG_INT_MASK, 0xff },
 145         { CS42L42_DET_INT1_MASK, 0xff },
 146         { CS42L42_DET_INT2_MASK, 0xff },
 147 };
 148
 149 /* Vendor specific hw configuration for CS8409 */
 150 const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[] = {
 151         /* +PLL1/2_EN, +I2C_EN */
 152         { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0xb008 },
 153         /* ASP1/2_EN=0, ASP1_STP=1 */
 154         { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0002 },
 155         /* ASP1/2_BUS_IDLE=10, +GPIO_I2C */
 156         { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG3, 0x0a80 },
 157         /* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
 158         { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL1, 0x0800 },
 159         /* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */
 160         { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL2, 0x0820 },
 161         /* ASP2.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
 162         { CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL1, 0x0800 },
 163         /* ASP2.A: TX.RAP=1, TX.RSZ=24 bits, TX.RCS=0 */
 164         { CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL2, 0x2800 },
 165         /* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */
 166         { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL1, 0x0800 },
 167         /* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */
 168         { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL2, 0x0800 },
 169         /* ASP1: LCHI = 00h */
 170         { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL1, 0x8000 },
 171         /* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */
 172         { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL2, 0x28ff },
 173         /* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */
 174         { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL3, 0x0062 },
 175         /* ASP2: LCHI=1Fh */
 176         { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL1, 0x801f },
 177         /* ASP2: MC/SC_SRCSEL=PLL1, LCPR=3Fh */
 178         { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL2, 0x283f },
 179         /* ASP2: 5050=1, MCEN=0, FSD=010, SCPOL_IN/OUT=1, SCDIV=1:16 */
 180         { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL3, 0x805c },
 181         /* DMIC1_MO=10b, DMIC1/2_SR=1 */
 182         { CS8409_PIN_VENDOR_WIDGET, CS8409_DMIC_CFG, 0x0023 },
 183         /* ASP1/2_BEEP=0 */
 184         { CS8409_PIN_VENDOR_WIDGET, CS8409_BEEP_CFG, 0x0000 },
 185         /* ASP1/2_EN=1, ASP1_STP=1 */
 186         { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0062 },
 187         /* -PLL2_EN */
 188         { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0x9008 },
 189         /* TX2.A: pre-scale att.=0 dB */
 190         { CS8409_PIN_VENDOR_WIDGET, CS8409_PRE_SCALE_ATTN2, 0x0000 },
 191         /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=1 */
 192         { CS8409_PIN_VENDOR_WIDGET, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc03 },
 193         /* test mode on */
 194         { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x9999 },
 195         /* GPIO hysteresis = 30 us */
 196         { CS8409_PIN_VENDOR_WIDGET, 0xc5, 0x0000 },
 197         /* test mode off */
 198         { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x0000 },
 199         {} /* Terminator */
 200 };
 201
 202 const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[] = {
 203         /* EQ_SEL=1, EQ1/2_EN=0 */
 204         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4000 },
 205         /* +EQ_ACC */
 206         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x4000 },
 207         /* +EQ2_EN */
 208         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4010 },
 209         /* EQ_DATA_HI=0x0647 */
 210         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 },
 211         /* +EQ_WRT, +EQ_ACC, EQ_ADR=0, EQ_DATA_LO=0x67 */
 212         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc0c7 },
 213         /* EQ_DATA_HI=0x0647 */
 214         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 },
 215         /* +EQ_WRT, +EQ_ACC, EQ_ADR=1, EQ_DATA_LO=0x67 */
 216         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc1c7 },
 217         /* EQ_DATA_HI=0xf370 */
 218         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xf370 },
 219         /* +EQ_WRT, +EQ_ACC, EQ_ADR=2, EQ_DATA_LO=0x71 */
 220         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc271 },
 221         /* EQ_DATA_HI=0x1ef8 */
 222         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ef8 },
 223         /* +EQ_WRT, +EQ_ACC, EQ_ADR=3, EQ_DATA_LO=0x48 */
 224         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc348 },
 225         /* EQ_DATA_HI=0xc110 */
 226         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc110 },
 227         /* +EQ_WRT, +EQ_ACC, EQ_ADR=4, EQ_DATA_LO=0x5a */
 228         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc45a },
 229         /* EQ_DATA_HI=0x1f29 */
 230         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1f29 },
 231         /* +EQ_WRT, +EQ_ACC, EQ_ADR=5, EQ_DATA_LO=0x74 */
 232         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc574 },
 233         /* EQ_DATA_HI=0x1d7a */
 234         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1d7a },
 235         /* +EQ_WRT, +EQ_ACC, EQ_ADR=6, EQ_DATA_LO=0x53 */
 236         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc653 },
 237         /* EQ_DATA_HI=0xc38c */
 238         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c },
 239         /* +EQ_WRT, +EQ_ACC, EQ_ADR=7, EQ_DATA_LO=0x14 */
 240         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc714 },
 241         /* EQ_DATA_HI=0x1ca3 */
 242         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ca3 },
 243         /* +EQ_WRT, +EQ_ACC, EQ_ADR=8, EQ_DATA_LO=0xc7 */
 244         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc8c7 },
 245         /* EQ_DATA_HI=0xc38c */
 246         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c },
 247         /* +EQ_WRT, +EQ_ACC, EQ_ADR=9, EQ_DATA_LO=0x14 */
 248         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc914 },
 249         /* -EQ_ACC, -EQ_WRT */
 250         { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x0000 },
 251         {} /* Terminator */
 252 };
 253
 254 struct sub_codec cs8409_cs42l42_codec = {
 255         .addr = CS42L42_I2C_ADDR,
 256         .reset_gpio = CS8409_CS42L42_RESET,
 257         .irq_mask = CS8409_CS42L42_INT,
 258         .init_seq = cs42l42_init_reg_seq,
 259         .init_seq_num = ARRAY_SIZE(cs42l42_init_reg_seq),
 260         .hp_jack_in = 0,
 261         .mic_jack_in = 0,
 262         .paged = 1,
 263         .suspended = 1,
 264         .no_type_dect = 0,
 265 };
 266
 267 /******************************************************************************
 268  *                          Dolphin Specific Arrays
 269  *                            CS8409/ 2 X CS42L42
 270  ******************************************************************************/
 271
 272 const struct hda_verb dolphin_init_verbs[] = {
 273         { 0x01, AC_VERB_SET_GPIO_WAKE_MASK, DOLPHIN_WAKE }, /* WAKE from GPIO 0,4 */
 274         { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing  */
 275         { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */
 276         { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0080 }, /* I2C mode */
 277         { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */
 278         { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0200 }, /* 100kHz I2C_STO = 2 */
 279         {} /* terminator */
 280 };
 281
 282 const struct hda_pintbl dolphin_pincfgs[] = {
 283         { 0x24, 0x022210f0 }, /* ASP-1-TX-A */
 284         { 0x25, 0x010240f0 }, /* ASP-1-TX-B */
 285         { 0x34, 0x02a21050 }, /* ASP-1-RX */
 286         {} /* terminator */
 287 };
 288
 289 /* Vendor specific HW configuration for CS42L42 */
 290 static const struct cs8409_i2c_param dolphin_c0_init_reg_seq[] = {
 291         { CS42L42_I2C_TIMEOUT, 0xB0 },
 292         { CS42L42_ADC_CTL, 0x00 },
 293         { 0x1D02, 0x06 },
 294         { CS42L42_ADC_VOLUME, 0x9F },
 295         { CS42L42_OSC_SWITCH, 0x01 },
 296         { CS42L42_MCLK_CTL, 0x02 },
 297         { CS42L42_SRC_CTL, 0x03 },
 298         { CS42L42_MCLK_SRC_SEL, 0x00 },
 299         { CS42L42_ASP_FRM_CFG, 0x13 },
 300         { CS42L42_FSYNC_P_LOWER, 0xFF },
 301         { CS42L42_FSYNC_P_UPPER, 0x00 },
 302         { CS42L42_ASP_CLK_CFG, 0x20 },
 303         { CS42L42_SPDIF_CLK_CFG, 0x0D },
 304         { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
 305         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
 306         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
 307         { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
 308         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
 309         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x20 },
 310         { CS42L42_ASP_RX_DAI0_EN, 0x0C },
 311         { CS42L42_ASP_TX_CH_EN, 0x01 },
 312         { CS42L42_ASP_TX_CH_AP_RES, 0x02 },
 313         { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
 314         { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
 315         { CS42L42_ASP_TX_SZ_EN, 0x01 },
 316         { CS42L42_PWR_CTL1, 0x0A },
 317         { CS42L42_PWR_CTL2, 0x84 },
 318         { CS42L42_HP_CTL, 0x03 },
 319         { CS42L42_MIXER_CHA_VOL, 0x3F },
 320         { CS42L42_MIXER_CHB_VOL, 0x3F },
 321         { CS42L42_MIXER_ADC_VOL, 0x3f },
 322         { CS42L42_MIC_DET_CTL1, 0xB6 },
 323         { CS42L42_TIPSENSE_CTL, 0xC2 },
 324         { CS42L42_HS_CLAMP_DISABLE, 0x01 },
 325         { CS42L42_HS_SWITCH_CTL, 0xF3 },
 326         { CS42L42_PWR_CTL3, 0x20 },
 327         { CS42L42_RSENSE_CTL2, 0x00 },
 328         { CS42L42_RSENSE_CTL3, 0x00 },
 329         { CS42L42_TSENSE_CTL, 0x80 },
 330         { CS42L42_HS_BIAS_CTL, 0xC0 },
 331         { CS42L42_PWR_CTL1, 0x02 },
 332         { CS42L42_ADC_OVFL_INT_MASK, 0xff },
 333         { CS42L42_MIXER_INT_MASK, 0xff },
 334         { CS42L42_SRC_INT_MASK, 0xff },
 335         { CS42L42_ASP_RX_INT_MASK, 0xff },
 336         { CS42L42_ASP_TX_INT_MASK, 0xff },
 337         { CS42L42_CODEC_INT_MASK, 0xff },
 338         { CS42L42_SRCPL_INT_MASK, 0xff },
 339         { CS42L42_VPMON_INT_MASK, 0xff },
 340         { CS42L42_PLL_LOCK_INT_MASK, 0xff },
 341         { CS42L42_TSRS_PLUG_INT_MASK, 0xff },
 342         { CS42L42_DET_INT1_MASK, 0xff },
 343         { CS42L42_DET_INT2_MASK, 0xff }
 344 };
 345
 346 static const struct cs8409_i2c_param dolphin_c1_init_reg_seq[] = {
 347         { CS42L42_I2C_TIMEOUT, 0xB0 },
 348         { CS42L42_ADC_CTL, 0x00 },
 349         { 0x1D02, 0x06 },
 350         { CS42L42_ADC_VOLUME, 0x9F },
 351         { CS42L42_OSC_SWITCH, 0x01 },
 352         { CS42L42_MCLK_CTL, 0x02 },
 353         { CS42L42_SRC_CTL, 0x03 },
 354         { CS42L42_MCLK_SRC_SEL, 0x00 },
 355         { CS42L42_ASP_FRM_CFG, 0x13 },
 356         { CS42L42_FSYNC_P_LOWER, 0xFF },
 357         { CS42L42_FSYNC_P_UPPER, 0x00 },
 358         { CS42L42_ASP_CLK_CFG, 0x20 },
 359         { CS42L42_SPDIF_CLK_CFG, 0x0D },
 360         { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
 361         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
 362         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x80 },
 363         { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
 364         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
 365         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0xA0 },
 366         { CS42L42_ASP_RX_DAI0_EN, 0x0C },
 367         { CS42L42_ASP_TX_CH_EN, 0x00 },
 368         { CS42L42_ASP_TX_CH_AP_RES, 0x02 },
 369         { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
 370         { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
 371         { CS42L42_ASP_TX_SZ_EN, 0x00 },
 372         { CS42L42_PWR_CTL1, 0x0E },
 373         { CS42L42_PWR_CTL2, 0x84 },
 374         { CS42L42_HP_CTL, 0x01 },
 375         { CS42L42_MIXER_CHA_VOL, 0x3F },
 376         { CS42L42_MIXER_CHB_VOL, 0x3F },
 377         { CS42L42_MIXER_ADC_VOL, 0x3f },
 378         { CS42L42_MIC_DET_CTL1, 0xB6 },
 379         { CS42L42_TIPSENSE_CTL, 0xC2 },
 380         { CS42L42_HS_CLAMP_DISABLE, 0x01 },
 381         { CS42L42_HS_SWITCH_CTL, 0xF3 },
 382         { CS42L42_PWR_CTL3, 0x20 },
 383         { CS42L42_RSENSE_CTL2, 0x00 },
 384         { CS42L42_RSENSE_CTL3, 0x00 },
 385         { CS42L42_TSENSE_CTL, 0x80 },
 386         { CS42L42_HS_BIAS_CTL, 0xC0 },
 387         { CS42L42_PWR_CTL1, 0x06 },
 388         { CS42L42_ADC_OVFL_INT_MASK, 0xff },
 389         { CS42L42_MIXER_INT_MASK, 0xff },
 390         { CS42L42_SRC_INT_MASK, 0xff },
 391         { CS42L42_ASP_RX_INT_MASK, 0xff },
 392         { CS42L42_ASP_TX_INT_MASK, 0xff },
 393         { CS42L42_CODEC_INT_MASK, 0xff },
 394         { CS42L42_SRCPL_INT_MASK, 0xff },
 395         { CS42L42_VPMON_INT_MASK, 0xff },
 396         { CS42L42_PLL_LOCK_INT_MASK, 0xff },
 397         { CS42L42_TSRS_PLUG_INT_MASK, 0xff },
 398         { CS42L42_DET_INT1_MASK, 0xff },
 399         { CS42L42_DET_INT2_MASK, 0xff }
 400 };
 401
 402 /* Vendor specific hw configuration for CS8409 */
 403 const struct cs8409_cir_param dolphin_hw_cfg[] = {
 404         /* +PLL1/2_EN, +I2C_EN */
 405         { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0xb008 },
 406         /* ASP1_EN=0, ASP1_STP=1 */
 407         { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0002 },
 408         /* ASP1/2_BUS_IDLE=10, +GPIO_I2C */
 409         { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG3, 0x0a80 },
 410         /* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
 411         { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL1, 0x0800 },
 412         /* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */
 413         { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL2, 0x0820 },
 414         /* ASP1.B: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=128 */
 415         { CS8409_PIN_VENDOR_WIDGET, ASP1_B_TX_CTRL1, 0x0880 },
 416         /* ASP1.B: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=160 */
 417         { CS8409_PIN_VENDOR_WIDGET, ASP1_B_TX_CTRL2, 0x08a0 },
 418         /* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */
 419         { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL1, 0x0800 },
 420         /* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */
 421         { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL2, 0x0800 },
 422         /* ASP1: LCHI = 00h */
 423         { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL1, 0x8000 },
 424         /* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */
 425         { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL2, 0x28ff },
 426         /* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */
 427         { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL3, 0x0062 },
 428         /* ASP1/2_BEEP=0 */
 429         { CS8409_PIN_VENDOR_WIDGET, CS8409_BEEP_CFG, 0x0000 },
 430         /* ASP1_EN=1, ASP1_STP=1 */
 431         { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0022 },
 432         /* -PLL2_EN */
 433         { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0x9008 },
 434         /* ASP1_xxx_EN=1, ASP1_MCLK_EN=0 */
 435         { CS8409_PIN_VENDOR_WIDGET, CS8409_PAD_CFG_SLW_RATE_CTRL, 0x5400 },
 436         /* test mode on */
 437         { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x9999 },
 438         /* GPIO hysteresis = 30 us */
 439         { CS8409_PIN_VENDOR_WIDGET, 0xc5, 0x0000 },
 440         /* test mode off */
 441         { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x0000 },
 442         {} /* Terminator */
 443 };
 444
 445 struct sub_codec dolphin_cs42l42_0 = {
 446         .addr = DOLPHIN_C0_I2C_ADDR,
 447         .reset_gpio = DOLPHIN_C0_RESET,
 448         .irq_mask = DOLPHIN_C0_INT,
 449         .init_seq = dolphin_c0_init_reg_seq,
 450         .init_seq_num = ARRAY_SIZE(dolphin_c0_init_reg_seq),
 451         .hp_jack_in = 0,
 452         .mic_jack_in = 0,
 453         .paged = 1,
 454         .suspended = 1,
 455         .no_type_dect = 0,
 456 };
 457
 458 struct sub_codec dolphin_cs42l42_1 = {
 459         .addr = DOLPHIN_C1_I2C_ADDR,
 460         .reset_gpio = DOLPHIN_C1_RESET,
 461         .irq_mask = DOLPHIN_C1_INT,
 462         .init_seq = dolphin_c1_init_reg_seq,
 463         .init_seq_num = ARRAY_SIZE(dolphin_c1_init_reg_seq),
 464         .hp_jack_in = 0,
 465         .mic_jack_in = 0,
 466         .paged = 1,
 467         .suspended = 1,
 468         .no_type_dect = 1,
 469 };
 470
 471 /******************************************************************************
 472  *                         CS8409 Patch Driver Structs
 473  *                    Arrays Used for all projects using CS8409
 474  ******************************************************************************/
 475
 476 const struct snd_pci_quirk cs8409_fixup_tbl[] = {
 477         SND_PCI_QUIRK(0x1028, 0x0A11, "Bullseye", CS8409_BULLSEYE),
 478         SND_PCI_QUIRK(0x1028, 0x0A12, "Bullseye", CS8409_BULLSEYE),
 479         SND_PCI_QUIRK(0x1028, 0x0A23, "Bullseye", CS8409_BULLSEYE),
 480         SND_PCI_QUIRK(0x1028, 0x0A24, "Bullseye", CS8409_BULLSEYE),
 481         SND_PCI_QUIRK(0x1028, 0x0A25, "Bullseye", CS8409_BULLSEYE),
 482         SND_PCI_QUIRK(0x1028, 0x0A29, "Bullseye", CS8409_BULLSEYE),
 483         SND_PCI_QUIRK(0x1028, 0x0A2A, "Bullseye", CS8409_BULLSEYE),
 484         SND_PCI_QUIRK(0x1028, 0x0A2B, "Bullseye", CS8409_BULLSEYE),
 485         SND_PCI_QUIRK(0x1028, 0x0A77, "Cyborg", CS8409_CYBORG),
 486         SND_PCI_QUIRK(0x1028, 0x0A78, "Cyborg", CS8409_CYBORG),
 487         SND_PCI_QUIRK(0x1028, 0x0A79, "Cyborg", CS8409_CYBORG),
 488         SND_PCI_QUIRK(0x1028, 0x0A7A, "Cyborg", CS8409_CYBORG),
 489         SND_PCI_QUIRK(0x1028, 0x0A7D, "Cyborg", CS8409_CYBORG),
 490         SND_PCI_QUIRK(0x1028, 0x0A7E, "Cyborg", CS8409_CYBORG),
 491         SND_PCI_QUIRK(0x1028, 0x0A7F, "Cyborg", CS8409_CYBORG),
 492         SND_PCI_QUIRK(0x1028, 0x0A80, "Cyborg", CS8409_CYBORG),
 493         SND_PCI_QUIRK(0x1028, 0x0AB0, "Warlock", CS8409_WARLOCK),
 494         SND_PCI_QUIRK(0x1028, 0x0AB2, "Warlock", CS8409_WARLOCK),
 495         SND_PCI_QUIRK(0x1028, 0x0AB1, "Warlock", CS8409_WARLOCK),
 496         SND_PCI_QUIRK(0x1028, 0x0AB3, "Warlock", CS8409_WARLOCK),
 497         SND_PCI_QUIRK(0x1028, 0x0AB4, "Warlock", CS8409_WARLOCK),
 498         SND_PCI_QUIRK(0x1028, 0x0AB5, "Warlock", CS8409_WARLOCK),
 499         SND_PCI_QUIRK(0x1028, 0x0ACF, "Dolphin", CS8409_DOLPHIN),
 500         SND_PCI_QUIRK(0x1028, 0x0AD0, "Dolphin", CS8409_DOLPHIN),
 501         SND_PCI_QUIRK(0x1028, 0x0AD1, "Dolphin", CS8409_DOLPHIN),
 502         SND_PCI_QUIRK(0x1028, 0x0AD2, "Dolphin", CS8409_DOLPHIN),
 503         SND_PCI_QUIRK(0x1028, 0x0AD3, "Dolphin", CS8409_DOLPHIN),
 504         SND_PCI_QUIRK(0x1028, 0x0AD9, "Warlock", CS8409_WARLOCK),
 505         SND_PCI_QUIRK(0x1028, 0x0ADA, "Warlock", CS8409_WARLOCK),
 506         SND_PCI_QUIRK(0x1028, 0x0ADB, "Warlock", CS8409_WARLOCK),
 507         SND_PCI_QUIRK(0x1028, 0x0ADC, "Warlock", CS8409_WARLOCK),
 508         SND_PCI_QUIRK(0x1028, 0x0ADF, "Cyborg", CS8409_CYBORG),
 509         SND_PCI_QUIRK(0x1028, 0x0AE0, "Cyborg", CS8409_CYBORG),
 510         SND_PCI_QUIRK(0x1028, 0x0AE1, "Cyborg", CS8409_CYBORG),
 511         SND_PCI_QUIRK(0x1028, 0x0AE2, "Cyborg", CS8409_CYBORG),
 512         SND_PCI_QUIRK(0x1028, 0x0AE9, "Cyborg", CS8409_CYBORG),
 513         SND_PCI_QUIRK(0x1028, 0x0AEA, "Cyborg", CS8409_CYBORG),
 514         SND_PCI_QUIRK(0x1028, 0x0AEB, "Cyborg", CS8409_CYBORG),
 515         SND_PCI_QUIRK(0x1028, 0x0AEC, "Cyborg", CS8409_CYBORG),
 516         SND_PCI_QUIRK(0x1028, 0x0AED, "Cyborg", CS8409_CYBORG),
 517         SND_PCI_QUIRK(0x1028, 0x0AEE, "Cyborg", CS8409_CYBORG),
 518         SND_PCI_QUIRK(0x1028, 0x0AEF, "Cyborg", CS8409_CYBORG),
 519         SND_PCI_QUIRK(0x1028, 0x0AF0, "Cyborg", CS8409_CYBORG),
 520         SND_PCI_QUIRK(0x1028, 0x0AF4, "Warlock", CS8409_WARLOCK),
 521         SND_PCI_QUIRK(0x1028, 0x0AF5, "Warlock", CS8409_WARLOCK),
 522         SND_PCI_QUIRK(0x1028, 0x0B92, "Warlock MLK", CS8409_WARLOCK_MLK),
 523         SND_PCI_QUIRK(0x1028, 0x0B93, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
 524         SND_PCI_QUIRK(0x1028, 0x0B94, "Warlock MLK", CS8409_WARLOCK_MLK),
 525         SND_PCI_QUIRK(0x1028, 0x0B95, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
 526         SND_PCI_QUIRK(0x1028, 0x0B96, "Warlock MLK", CS8409_WARLOCK_MLK),
 527         SND_PCI_QUIRK(0x1028, 0x0B97, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
 528         SND_PCI_QUIRK(0x1028, 0x0BA5, "Odin", CS8409_ODIN),
 529         SND_PCI_QUIRK(0x1028, 0x0BA6, "Odin", CS8409_ODIN),
 530         SND_PCI_QUIRK(0x1028, 0x0BA8, "Odin", CS8409_ODIN),
 531         SND_PCI_QUIRK(0x1028, 0x0BAA, "Odin", CS8409_ODIN),
 532         SND_PCI_QUIRK(0x1028, 0x0BAE, "Odin", CS8409_ODIN),
 533         SND_PCI_QUIRK(0x1028, 0x0BB2, "Warlock MLK", CS8409_WARLOCK_MLK),
 534         SND_PCI_QUIRK(0x1028, 0x0BB3, "Warlock MLK", CS8409_WARLOCK_MLK),
 535         SND_PCI_QUIRK(0x1028, 0x0BB4, "Warlock MLK", CS8409_WARLOCK_MLK),
 536         SND_PCI_QUIRK(0x1028, 0x0BB5, "Warlock N3 15 TGL-U Nuvoton EC", CS8409_WARLOCK),
 537         SND_PCI_QUIRK(0x1028, 0x0BB6, "Warlock V3 15 TGL-U Nuvoton EC", CS8409_WARLOCK),
 538         SND_PCI_QUIRK(0x1028, 0x0BB8, "Warlock MLK", CS8409_WARLOCK_MLK),
 539         SND_PCI_QUIRK(0x1028, 0x0BB9, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
 540         SND_PCI_QUIRK(0x1028, 0x0BBA, "Warlock MLK", CS8409_WARLOCK_MLK),
 541         SND_PCI_QUIRK(0x1028, 0x0BBB, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
 542         SND_PCI_QUIRK(0x1028, 0x0BBC, "Warlock MLK", CS8409_WARLOCK_MLK),
 543         SND_PCI_QUIRK(0x1028, 0x0BBD, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
 544         SND_PCI_QUIRK(0x1028, 0x0BD4, "Dolphin", CS8409_DOLPHIN),
 545         SND_PCI_QUIRK(0x1028, 0x0BD5, "Dolphin", CS8409_DOLPHIN),
 546         SND_PCI_QUIRK(0x1028, 0x0BD6, "Dolphin", CS8409_DOLPHIN),
 547         SND_PCI_QUIRK(0x1028, 0x0BD7, "Dolphin", CS8409_DOLPHIN),
 548         SND_PCI_QUIRK(0x1028, 0x0BD8, "Dolphin", CS8409_DOLPHIN),
 549         {} /* terminator */
 550 };
 551
 552 /* Dell Inspiron models with cs8409/cs42l42 */
 553 const struct hda_model_fixup cs8409_models[] = {
 554         { .id = CS8409_BULLSEYE, .name = "bullseye" },
 555         { .id = CS8409_WARLOCK, .name = "warlock" },
 556         { .id = CS8409_WARLOCK_MLK, .name = "warlock mlk" },
 557         { .id = CS8409_WARLOCK_MLK_DUAL_MIC, .name = "warlock mlk dual mic" },
 558         { .id = CS8409_CYBORG, .name = "cyborg" },
 559         { .id = CS8409_DOLPHIN, .name = "dolphin" },
 560         { .id = CS8409_ODIN, .name = "odin" },
 561         {}
 562 };
 563
 564 const struct hda_fixup cs8409_fixups[] = {
 565         [CS8409_BULLSEYE] = {
 566                 .type = HDA_FIXUP_PINS,
 567                 .v.pins = cs8409_cs42l42_pincfgs,
 568                 .chained = true,
 569                 .chain_id = CS8409_FIXUPS,
 570         },
 571         [CS8409_WARLOCK] = {
 572                 .type = HDA_FIXUP_PINS,
 573                 .v.pins = cs8409_cs42l42_pincfgs,
 574                 .chained = true,
 575                 .chain_id = CS8409_FIXUPS,
 576         },
 577         [CS8409_WARLOCK_MLK] = {
 578                 .type = HDA_FIXUP_PINS,
 579                 .v.pins = cs8409_cs42l42_pincfgs,
 580                 .chained = true,
 581                 .chain_id = CS8409_FIXUPS,
 582         },
 583         [CS8409_WARLOCK_MLK_DUAL_MIC] = {
 584                 .type = HDA_FIXUP_PINS,
 585                 .v.pins = cs8409_cs42l42_pincfgs,
 586                 .chained = true,
 587                 .chain_id = CS8409_FIXUPS,
 588         },
 589         [CS8409_CYBORG] = {
 590                 .type = HDA_FIXUP_PINS,
 591                 .v.pins = cs8409_cs42l42_pincfgs,
 592                 .chained = true,
 593                 .chain_id = CS8409_FIXUPS,
 594         },
 595         [CS8409_FIXUPS] = {
 596                 .type = HDA_FIXUP_FUNC,
 597                 .v.func = cs8409_cs42l42_fixups,
 598         },
 599         [CS8409_DOLPHIN] = {
 600                 .type = HDA_FIXUP_PINS,
 601                 .v.pins = dolphin_pincfgs,
 602                 .chained = true,
 603                 .chain_id = CS8409_DOLPHIN_FIXUPS,
 604         },
 605         [CS8409_DOLPHIN_FIXUPS] = {
 606                 .type = HDA_FIXUP_FUNC,
 607                 .v.func = dolphin_fixups,
 608         },
 609         [CS8409_ODIN] = {
 610                 .type = HDA_FIXUP_PINS,
 611                 .v.pins = cs8409_cs42l42_pincfgs_no_dmic,
 612                 .chained = true,
 613                 .chain_id = CS8409_FIXUPS,
 614         },
 615 };