1 // SPDX-License-Identifier: GPL-2.0-only
3 * patch_cs8409-tables.c -- HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
5 * Copyright (C) 2021 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
8 * Author: Lucas Tanure <tanureal@opensource.cirrus.com>
11 #include "patch_cs8409.h"
13 /* Dell Inspiron platforms
14 * with cs8409 bridge and cs42l42 codec
16 const struct snd_pci_quirk cs8409_fixup_tbl[] = {
17 SND_PCI_QUIRK(0x1028, 0x0A11, "Bullseye", CS8409_BULLSEYE),
18 SND_PCI_QUIRK(0x1028, 0x0A12, "Bullseye", CS8409_BULLSEYE),
19 SND_PCI_QUIRK(0x1028, 0x0A23, "Bullseye", CS8409_BULLSEYE),
20 SND_PCI_QUIRK(0x1028, 0x0A24, "Bullseye", CS8409_BULLSEYE),
21 SND_PCI_QUIRK(0x1028, 0x0A25, "Bullseye", CS8409_BULLSEYE),
22 SND_PCI_QUIRK(0x1028, 0x0A29, "Bullseye", CS8409_BULLSEYE),
23 SND_PCI_QUIRK(0x1028, 0x0A2A, "Bullseye", CS8409_BULLSEYE),
24 SND_PCI_QUIRK(0x1028, 0x0A2B, "Bullseye", CS8409_BULLSEYE),
25 SND_PCI_QUIRK(0x1028, 0x0AB0, "Warlock", CS8409_WARLOCK),
26 SND_PCI_QUIRK(0x1028, 0x0AB2, "Warlock", CS8409_WARLOCK),
27 SND_PCI_QUIRK(0x1028, 0x0AB1, "Warlock", CS8409_WARLOCK),
28 SND_PCI_QUIRK(0x1028, 0x0AB3, "Warlock", CS8409_WARLOCK),
29 SND_PCI_QUIRK(0x1028, 0x0AB4, "Warlock", CS8409_WARLOCK),
30 SND_PCI_QUIRK(0x1028, 0x0AB5, "Warlock", CS8409_WARLOCK),
31 SND_PCI_QUIRK(0x1028, 0x0AD9, "Warlock", CS8409_WARLOCK),
32 SND_PCI_QUIRK(0x1028, 0x0ADA, "Warlock", CS8409_WARLOCK),
33 SND_PCI_QUIRK(0x1028, 0x0ADB, "Warlock", CS8409_WARLOCK),
34 SND_PCI_QUIRK(0x1028, 0x0ADC, "Warlock", CS8409_WARLOCK),
35 SND_PCI_QUIRK(0x1028, 0x0AF4, "Warlock", CS8409_WARLOCK),
36 SND_PCI_QUIRK(0x1028, 0x0AF5, "Warlock", CS8409_WARLOCK),
37 SND_PCI_QUIRK(0x1028, 0x0A77, "Cyborg", CS8409_CYBORG),
38 SND_PCI_QUIRK(0x1028, 0x0A78, "Cyborg", CS8409_CYBORG),
39 SND_PCI_QUIRK(0x1028, 0x0A79, "Cyborg", CS8409_CYBORG),
40 SND_PCI_QUIRK(0x1028, 0x0A7A, "Cyborg", CS8409_CYBORG),
41 SND_PCI_QUIRK(0x1028, 0x0A7D, "Cyborg", CS8409_CYBORG),
42 SND_PCI_QUIRK(0x1028, 0x0A7E, "Cyborg", CS8409_CYBORG),
43 SND_PCI_QUIRK(0x1028, 0x0A7F, "Cyborg", CS8409_CYBORG),
44 SND_PCI_QUIRK(0x1028, 0x0A80, "Cyborg", CS8409_CYBORG),
45 SND_PCI_QUIRK(0x1028, 0x0ADF, "Cyborg", CS8409_CYBORG),
46 SND_PCI_QUIRK(0x1028, 0x0AE0, "Cyborg", CS8409_CYBORG),
47 SND_PCI_QUIRK(0x1028, 0x0AE1, "Cyborg", CS8409_CYBORG),
48 SND_PCI_QUIRK(0x1028, 0x0AE2, "Cyborg", CS8409_CYBORG),
49 SND_PCI_QUIRK(0x1028, 0x0AE9, "Cyborg", CS8409_CYBORG),
50 SND_PCI_QUIRK(0x1028, 0x0AEA, "Cyborg", CS8409_CYBORG),
51 SND_PCI_QUIRK(0x1028, 0x0AEB, "Cyborg", CS8409_CYBORG),
52 SND_PCI_QUIRK(0x1028, 0x0AEC, "Cyborg", CS8409_CYBORG),
53 SND_PCI_QUIRK(0x1028, 0x0AED, "Cyborg", CS8409_CYBORG),
54 SND_PCI_QUIRK(0x1028, 0x0AEE, "Cyborg", CS8409_CYBORG),
55 SND_PCI_QUIRK(0x1028, 0x0AEF, "Cyborg", CS8409_CYBORG),
56 SND_PCI_QUIRK(0x1028, 0x0AF0, "Cyborg", CS8409_CYBORG),
60 /* Dell Inspiron models with cs8409/cs42l42 */
61 const struct hda_model_fixup cs8409_models[] = {
62 { .id = CS8409_BULLSEYE, .name = "bullseye" },
63 { .id = CS8409_WARLOCK, .name = "warlock" },
64 { .id = CS8409_CYBORG, .name = "cyborg" },
68 const struct hda_fixup cs8409_fixups[] = {
70 .type = HDA_FIXUP_PINS,
71 .v.pins = cs8409_cs42l42_pincfgs,
73 .chain_id = CS8409_FIXUPS,
76 .type = HDA_FIXUP_PINS,
77 .v.pins = cs8409_cs42l42_pincfgs,
79 .chain_id = CS8409_FIXUPS,
82 .type = HDA_FIXUP_PINS,
83 .v.pins = cs8409_cs42l42_pincfgs,
85 .chain_id = CS8409_FIXUPS,
88 .type = HDA_FIXUP_FUNC,
89 .v.func = cs8409_cs42l42_fixups,
93 const struct hda_verb cs8409_cs42l42_init_verbs[] = {
94 { 0x01, AC_VERB_SET_GPIO_WAKE_MASK, 0x0018 }, /* WAKE from GPIO 3,4 */
95 { 0x47, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing */
96 { 0x47, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */
97 { 0x47, AC_VERB_SET_PROC_COEF, 0x0080 }, /* I2C mode */
98 { 0x47, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */
99 { 0x47, AC_VERB_SET_PROC_COEF, 0x0200 }, /* 100kHz I2C_STO = 2 */
103 const struct hda_pintbl cs8409_cs42l42_pincfgs[] = {
104 { 0x24, 0x042120f0 }, /* ASP-1-TX */
105 { 0x34, 0x04a12050 }, /* ASP-1-RX */
106 { 0x2c, 0x901000f0 }, /* ASP-2-TX */
107 { 0x44, 0x90a00090 }, /* DMIC-1 */
111 /* Vendor specific HW configuration for CS42L42 */
112 const struct cs8409_i2c_param cs42l42_init_reg_seq[] = {
165 /* Vendor specific hw configuration for CS8409 */
166 const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[] = {
167 { 0x47, 0x00, 0xb008 }, /* +PLL1/2_EN, +I2C_EN */
168 { 0x47, 0x01, 0x0002 }, /* ASP1/2_EN=0, ASP1_STP=1 */
169 { 0x47, 0x02, 0x0a80 }, /* ASP1/2_BUS_IDLE=10, +GPIO_I2C */
170 { 0x47, 0x19, 0x0800 }, /* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
171 { 0x47, 0x1a, 0x0820 }, /* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */
172 { 0x47, 0x29, 0x0800 }, /* ASP2.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
173 { 0x47, 0x2a, 0x2800 }, /* ASP2.A: TX.RAP=1, TX.RSZ=24 bits, TX.RCS=0 */
174 { 0x47, 0x39, 0x0800 }, /* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */
175 { 0x47, 0x3a, 0x0800 }, /* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */
176 { 0x47, 0x03, 0x8000 }, /* ASP1: LCHI = 00h */
177 { 0x47, 0x04, 0x28ff }, /* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */
178 { 0x47, 0x05, 0x0062 }, /* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */
179 { 0x47, 0x06, 0x801f }, /* ASP2: LCHI=1Fh */
180 { 0x47, 0x07, 0x283f }, /* ASP2: MC/SC_SRCSEL=PLL1, LCPR=3Fh */
181 { 0x47, 0x08, 0x805c }, /* ASP2: 5050=1, MCEN=0, FSD=010, SCPOL_IN/OUT=1, SCDIV=1:16 */
182 { 0x47, 0x09, 0x0023 }, /* DMIC1_MO=10b, DMIC1/2_SR=1 */
183 { 0x47, 0x0a, 0x0000 }, /* ASP1/2_BEEP=0 */
184 { 0x47, 0x01, 0x0062 }, /* ASP1/2_EN=1, ASP1_STP=1 */
185 { 0x47, 0x00, 0x9008 }, /* -PLL2_EN */
186 { 0x47, 0x68, 0x0000 }, /* TX2.A: pre-scale att.=0 dB */
187 { 0x47, 0x82, 0xfc03 }, /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=1 */
188 { 0x47, 0xc0, 0x9999 }, /* test mode on */
189 { 0x47, 0xc5, 0x0000 }, /* GPIO hysteresis = 30 us */
190 { 0x47, 0xc0, 0x0000 }, /* test mode off */
194 const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[] = {
195 { 0x47, 0x65, 0x4000 }, /* EQ_SEL=1, EQ1/2_EN=0 */
196 { 0x47, 0x64, 0x4000 }, /* +EQ_ACC */
197 { 0x47, 0x65, 0x4010 }, /* +EQ2_EN */
198 { 0x47, 0x63, 0x0647 }, /* EQ_DATA_HI=0x0647 */
199 { 0x47, 0x64, 0xc0c7 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=0, EQ_DATA_LO=0x67 */
200 { 0x47, 0x63, 0x0647 }, /* EQ_DATA_HI=0x0647 */
201 { 0x47, 0x64, 0xc1c7 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=1, EQ_DATA_LO=0x67 */
202 { 0x47, 0x63, 0xf370 }, /* EQ_DATA_HI=0xf370 */
203 { 0x47, 0x64, 0xc271 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=2, EQ_DATA_LO=0x71 */
204 { 0x47, 0x63, 0x1ef8 }, /* EQ_DATA_HI=0x1ef8 */
205 { 0x47, 0x64, 0xc348 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=3, EQ_DATA_LO=0x48 */
206 { 0x47, 0x63, 0xc110 }, /* EQ_DATA_HI=0xc110 */
207 { 0x47, 0x64, 0xc45a }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=4, EQ_DATA_LO=0x5a */
208 { 0x47, 0x63, 0x1f29 }, /* EQ_DATA_HI=0x1f29 */
209 { 0x47, 0x64, 0xc574 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=5, EQ_DATA_LO=0x74 */
210 { 0x47, 0x63, 0x1d7a }, /* EQ_DATA_HI=0x1d7a */
211 { 0x47, 0x64, 0xc653 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=6, EQ_DATA_LO=0x53 */
212 { 0x47, 0x63, 0xc38c }, /* EQ_DATA_HI=0xc38c */
213 { 0x47, 0x64, 0xc714 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=7, EQ_DATA_LO=0x14 */
214 { 0x47, 0x63, 0x1ca3 }, /* EQ_DATA_HI=0x1ca3 */
215 { 0x47, 0x64, 0xc8c7 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=8, EQ_DATA_LO=0xc7 */
216 { 0x47, 0x63, 0xc38c }, /* EQ_DATA_HI=0xc38c */
217 { 0x47, 0x64, 0xc914 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=9, EQ_DATA_LO=0x14 */
218 { 0x47, 0x64, 0x0000 }, /* -EQ_ACC, -EQ_WRT */