sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38 #include <linux/acpi.h>
  39 #include <linux/pgtable.h>
  40
  41 #ifdef CONFIG_X86
  42 /* for snoop control */
  43 #include <asm/set_memory.h>
  44 #include <asm/cpufeature.h>
  45 #endif
  46 #include <sound/core.h>
  47 #include <sound/initval.h>
  48 #include <sound/hdaudio.h>
  49 #include <sound/hda_i915.h>
  50 #include <sound/intel-dsp-config.h>
  51 #include <linux/vgaarb.h>
  52 #include <linux/vga_switcheroo.h>
  53 #include <linux/apple-gmux.h>
  54 #include <linux/firmware.h>
  55 #include <sound/hda_codec.h>
  56 #include "hda_controller.h"
  57 #include "hda_intel.h"
  58
  59 #define CREATE_TRACE_POINTS
  60 #include "hda_intel_trace.h"
  61
  62 /* position fix mode */
  63 enum {
  64         POS_FIX_AUTO,
  65         POS_FIX_LPIB,
  66         POS_FIX_POSBUF,
  67         POS_FIX_VIACOMBO,
  68         POS_FIX_COMBO,
  69         POS_FIX_SKL,
  70         POS_FIX_FIFO,
  71 };
  72
  73 /* Defines for ATI HD Audio support in SB450 south bridge */
  74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  76
  77 /* Defines for Nvidia HDA support */
  78 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  79 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  80 #define NVIDIA_HDA_ISTRM_COH          0x4d
  81 #define NVIDIA_HDA_OSTRM_COH          0x4c
  82 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  83
  84 /* Defines for Intel SCH HDA snoop control */
  85 #define INTEL_HDA_CGCTL  0x48
  86 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  87 #define INTEL_SCH_HDA_DEVC      0x78
  88 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  89
  90 /* max number of SDs */
  91 /* ICH, ATI and VIA have 4 playback and 4 capture */
  92 #define ICH6_NUM_CAPTURE        4
  93 #define ICH6_NUM_PLAYBACK       4
  94
  95 /* ULI has 6 playback and 5 capture */
  96 #define ULI_NUM_CAPTURE         5
  97 #define ULI_NUM_PLAYBACK        6
  98
  99 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 100 #define ATIHDMI_NUM_CAPTURE     0
 101 #define ATIHDMI_NUM_PLAYBACK    8
 102
 103
 104 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 105 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 106 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 107 static char *model[SNDRV_CARDS];
 108 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 109 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 110 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 111 static int probe_only[SNDRV_CARDS];
 112 static int jackpoll_ms[SNDRV_CARDS];
 113 static int single_cmd = -1;
 114 static int enable_msi = -1;
 115 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 116 static char *patch[SNDRV_CARDS];
 117 #endif
 118 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 119 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 120                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 121 #endif
 122 static bool dmic_detect = 1;
 123 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
 124
 125 module_param_array(index, int, NULL, 0444);
 126 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 127 module_param_array(id, charp, NULL, 0444);
 128 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 129 module_param_array(enable, bool, NULL, 0444);
 130 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 131 module_param_array(model, charp, NULL, 0444);
 132 MODULE_PARM_DESC(model, "Use the given board model.");
 133 module_param_array(position_fix, int, NULL, 0444);
 134 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 135                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 136 module_param_array(bdl_pos_adj, int, NULL, 0644);
 137 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 138 module_param_array(probe_mask, int, NULL, 0444);
 139 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 140 module_param_array(probe_only, int, NULL, 0444);
 141 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 142 module_param_array(jackpoll_ms, int, NULL, 0444);
 143 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 144 module_param(single_cmd, bint, 0444);
 145 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 146                  "(for debugging only).");
 147 module_param(enable_msi, bint, 0444);
 148 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 149 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 150 module_param_array(patch, charp, NULL, 0444);
 151 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 152 #endif
 153 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 154 module_param_array(beep_mode, bool, NULL, 0444);
 155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 156                             "(0=off, 1=on) (default=1).");
 157 #endif
 158 module_param(dmic_detect, bool, 0444);
 159 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
 160                              "(0=off, 1=on) (default=1); "
 161                  "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
 162 module_param(ctl_dev_id, bool, 0444);
 163 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
 164
 165 #ifdef CONFIG_PM
 166 static int param_set_xint(const char *val, const struct kernel_param *kp);
 167 static const struct kernel_param_ops param_ops_xint = {
 168         .set = param_set_xint,
 169         .get = param_get_int,
 170 };
 171 #define param_check_xint param_check_int
 172
 173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 174 module_param(power_save, xint, 0644);
 175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 176                  "(in second, 0 = disable).");
 177
 178 static bool pm_blacklist = true;
 179 module_param(pm_blacklist, bool, 0644);
 180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
 181
 182 /* reset the HD-audio controller in power save mode.
 183  * this may give more power-saving, but will take longer time to
 184  * wake up.
 185  */
 186 static bool power_save_controller = 1;
 187 module_param(power_save_controller, bool, 0644);
 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 189 #else
 190 #define power_save      0
 191 #endif /* CONFIG_PM */
 192
 193 static int align_buffer_size = -1;
 194 module_param(align_buffer_size, bint, 0644);
 195 MODULE_PARM_DESC(align_buffer_size,
 196                 "Force buffer and period sizes to be multiple of 128 bytes.");
 197
 198 #ifdef CONFIG_X86
 199 static int hda_snoop = -1;
 200 module_param_named(snoop, hda_snoop, bint, 0444);
 201 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 202 #else
 203 #define hda_snoop               true
 204 #endif
 205
 206
 207 MODULE_LICENSE("GPL");
 208 MODULE_DESCRIPTION("Intel HDA driver");
 209
 210 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 211 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 212 #define SUPPORT_VGA_SWITCHEROO
 213 #endif
 214 #endif
 215
 216
 217 /*
 218  */
 219
 220 /* driver types */
 221 enum {
 222         AZX_DRIVER_ICH,
 223         AZX_DRIVER_PCH,
 224         AZX_DRIVER_SCH,
 225         AZX_DRIVER_SKL,
 226         AZX_DRIVER_HDMI,
 227         AZX_DRIVER_ATI,
 228         AZX_DRIVER_ATIHDMI,
 229         AZX_DRIVER_ATIHDMI_NS,
 230         AZX_DRIVER_GFHDMI,
 231         AZX_DRIVER_VIA,
 232         AZX_DRIVER_SIS,
 233         AZX_DRIVER_ULI,
 234         AZX_DRIVER_NVIDIA,
 235         AZX_DRIVER_TERA,
 236         AZX_DRIVER_CTX,
 237         AZX_DRIVER_CTHDA,
 238         AZX_DRIVER_CMEDIA,
 239         AZX_DRIVER_ZHAOXIN,
 240         AZX_DRIVER_LOONGSON,
 241         AZX_DRIVER_GENERIC,
 242         AZX_NUM_DRIVERS, /* keep this as last entry */
 243 };
 244
 245 #define azx_get_snoop_type(chip) \
 246         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 247 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 248
 249 /* quirks for old Intel chipsets */
 250 #define AZX_DCAPS_INTEL_ICH \
 251         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 252
 253 /* quirks for Intel PCH */
 254 #define AZX_DCAPS_INTEL_PCH_BASE \
 255         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 256          AZX_DCAPS_SNOOP_TYPE(SCH))
 257
 258 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 259 #define AZX_DCAPS_INTEL_PCH_NOPM \
 260         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 261
 262 /* PCH for HSW/BDW; with runtime PM */
 263 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 264 #define AZX_DCAPS_INTEL_PCH \
 265         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 266
 267 /* HSW HDMI */
 268 #define AZX_DCAPS_INTEL_HASWELL \
 269         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 270          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 271          AZX_DCAPS_SNOOP_TYPE(SCH))
 272
 273 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 274 #define AZX_DCAPS_INTEL_BROADWELL \
 275         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 276          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 277          AZX_DCAPS_SNOOP_TYPE(SCH))
 278
 279 #define AZX_DCAPS_INTEL_BAYTRAIL \
 280         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 281
 282 #define AZX_DCAPS_INTEL_BRASWELL \
 283         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 284          AZX_DCAPS_I915_COMPONENT)
 285
 286 #define AZX_DCAPS_INTEL_SKYLAKE \
 287         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 288          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 289
 290 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 291
 292 /* quirks for ATI SB / AMD Hudson */
 293 #define AZX_DCAPS_PRESET_ATI_SB \
 294         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
 295          AZX_DCAPS_SNOOP_TYPE(ATI))
 296
 297 /* quirks for ATI/AMD HDMI */
 298 #define AZX_DCAPS_PRESET_ATI_HDMI \
 299         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
 300          AZX_DCAPS_NO_MSI64)
 301
 302 /* quirks for ATI HDMI with snoop off */
 303 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 304         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 305
 306 /* quirks for AMD SB */
 307 #define AZX_DCAPS_PRESET_AMD_SB \
 308         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
 309          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
 310          AZX_DCAPS_RETRY_PROBE)
 311
 312 /* quirks for Nvidia */
 313 #define AZX_DCAPS_PRESET_NVIDIA \
 314         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 315          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 316
 317 #define AZX_DCAPS_PRESET_CTHDA \
 318         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 319          AZX_DCAPS_NO_64BIT |\
 320          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 321
 322 /*
 323  * vga_switcheroo support
 324  */
 325 #ifdef SUPPORT_VGA_SWITCHEROO
 326 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 327 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 328 #else
 329 #define use_vga_switcheroo(chip)        0
 330 #define needs_eld_notify_link(chip)     false
 331 #endif
 332
 333 #define CONTROLLER_IN_GPU(pci) (((pci)->vendor == 0x8086) &&         \
 334                                        (((pci)->device == 0x0a0c) || \
 335                                         ((pci)->device == 0x0c0c) || \
 336                                         ((pci)->device == 0x0d0c) || \
 337                                         ((pci)->device == 0x160c) || \
 338                                         ((pci)->device == 0x490d) || \
 339                                         ((pci)->device == 0x4f90) || \
 340                                         ((pci)->device == 0x4f91) || \
 341                                         ((pci)->device == 0x4f92)))
 342
 343 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 344
 345 static const char * const driver_short_names[] = {
 346         [AZX_DRIVER_ICH] = "HDA Intel",
 347         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 348         [AZX_DRIVER_SCH] = "HDA Intel MID",
 349         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 350         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 351         [AZX_DRIVER_ATI] = "HDA ATI SB",
 352         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 353         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 354         [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
 355         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 356         [AZX_DRIVER_SIS] = "HDA SIS966",
 357         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 358         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 359         [AZX_DRIVER_TERA] = "HDA Teradici",
 360         [AZX_DRIVER_CTX] = "HDA Creative",
 361         [AZX_DRIVER_CTHDA] = "HDA Creative",
 362         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 363         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 364         [AZX_DRIVER_LOONGSON] = "HDA Loongson",
 365         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 366 };
 367
 368 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 369 static void set_default_power_save(struct azx *chip);
 370
 371 /*
 372  * initialize the PCI registers
 373  */
 374 /* update bits in a PCI register byte */
 375 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 376                             unsigned char mask, unsigned char val)
 377 {
 378         unsigned char data;
 379
 380         pci_read_config_byte(pci, reg, &data);
 381         data &= ~mask;
 382         data |= (val & mask);
 383         pci_write_config_byte(pci, reg, data);
 384 }
 385
 386 static void azx_init_pci(struct azx *chip)
 387 {
 388         int snoop_type = azx_get_snoop_type(chip);
 389
 390         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 391          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 392          * Ensuring these bits are 0 clears playback static on some HD Audio
 393          * codecs.
 394          * The PCI register TCSEL is defined in the Intel manuals.
 395          */
 396         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 397                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 398                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 399         }
 400
 401         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 402          * we need to enable snoop.
 403          */
 404         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 405                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 406                         azx_snoop(chip));
 407                 update_pci_byte(chip->pci,
 408                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 409                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 410         }
 411
 412         /* For NVIDIA HDA, enable snoop */
 413         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 414                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 415                         azx_snoop(chip));
 416                 update_pci_byte(chip->pci,
 417                                 NVIDIA_HDA_TRANSREG_ADDR,
 418                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 419                 update_pci_byte(chip->pci,
 420                                 NVIDIA_HDA_ISTRM_COH,
 421                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 422                 update_pci_byte(chip->pci,
 423                                 NVIDIA_HDA_OSTRM_COH,
 424                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 425         }
 426
 427         /* Enable SCH/PCH snoop if needed */
 428         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 429                 unsigned short snoop;
 430                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 431                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 432                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 433                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 434                         if (!azx_snoop(chip))
 435                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 436                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 437                         pci_read_config_word(chip->pci,
 438                                 INTEL_SCH_HDA_DEVC, &snoop);
 439                 }
 440                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 441                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 442                         "Disabled" : "Enabled");
 443         }
 444 }
 445
 446 /*
 447  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 448  * and makes an audio stream sensitive to system latencies when
 449  * 24/32 bits are playing.
 450  * Adjusting threshold of DMA fifo to force the DMA request
 451  * sooner to improve latency tolerance at the expense of power.
 452  */
 453 static void bxt_reduce_dma_latency(struct azx *chip)
 454 {
 455         u32 val;
 456
 457         val = azx_readl(chip, VS_EM4L);
 458         val &= (0x3 << 20);
 459         azx_writel(chip, VS_EM4L, val);
 460 }
 461
 462 /*
 463  * ML_LCAP bits:
 464  *  bit 0: 6 MHz Supported
 465  *  bit 1: 12 MHz Supported
 466  *  bit 2: 24 MHz Supported
 467  *  bit 3: 48 MHz Supported
 468  *  bit 4: 96 MHz Supported
 469  *  bit 5: 192 MHz Supported
 470  */
 471 static int intel_get_lctl_scf(struct azx *chip)
 472 {
 473         struct hdac_bus *bus = azx_bus(chip);
 474         static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
 475         u32 val, t;
 476         int i;
 477
 478         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 479
 480         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 481                 t = preferred_bits[i];
 482                 if (val & (1 << t))
 483                         return t;
 484         }
 485
 486         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 487         return 0;
 488 }
 489
 490 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 491 {
 492         struct hdac_bus *bus = azx_bus(chip);
 493         u32 val;
 494         int timeout;
 495
 496         /*
 497          * Changes to LCTL.SCF are only needed for the first multi-link dealing
 498          * with external codecs
 499          */
 500         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 501         val &= ~AZX_ML_LCTL_SPA;
 502         val |= state << AZX_ML_LCTL_SPA_SHIFT;
 503         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 504         /* wait for CPA */
 505         timeout = 50;
 506         while (timeout) {
 507                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 508                     AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
 509                         return 0;
 510                 timeout--;
 511                 udelay(10);
 512         }
 513
 514         return -1;
 515 }
 516
 517 static void intel_init_lctl(struct azx *chip)
 518 {
 519         struct hdac_bus *bus = azx_bus(chip);
 520         u32 val;
 521         int ret;
 522
 523         /* 0. check lctl register value is correct or not */
 524         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 525         /* only perform additional configurations if the SCF is initially based on 6MHz */
 526         if ((val & AZX_ML_LCTL_SCF) != 0)
 527                 return;
 528
 529         /*
 530          * Before operating on SPA, CPA must match SPA.
 531          * Any deviation may result in undefined behavior.
 532          */
 533         if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
 534                 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
 535                 return;
 536
 537         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 538         ret = intel_ml_lctl_set_power(chip, 0);
 539         udelay(100);
 540         if (ret)
 541                 goto set_spa;
 542
 543         /* 2. update SCF to select an audio clock different from 6MHz */
 544         val &= ~AZX_ML_LCTL_SCF;
 545         val |= intel_get_lctl_scf(chip);
 546         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 547
 548 set_spa:
 549         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 550         intel_ml_lctl_set_power(chip, 1);
 551         udelay(100);
 552 }
 553
 554 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 555 {
 556         struct hdac_bus *bus = azx_bus(chip);
 557         struct pci_dev *pci = chip->pci;
 558         u32 val;
 559
 560         snd_hdac_set_codec_wakeup(bus, true);
 561         if (chip->driver_type == AZX_DRIVER_SKL) {
 562                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 563                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 564                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 565         }
 566         azx_init_chip(chip, full_reset);
 567         if (chip->driver_type == AZX_DRIVER_SKL) {
 568                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 569                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 570                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 571         }
 572
 573         snd_hdac_set_codec_wakeup(bus, false);
 574
 575         /* reduce dma latency to avoid noise */
 576         if (IS_BXT(pci))
 577                 bxt_reduce_dma_latency(chip);
 578
 579         if (bus->mlcap != NULL)
 580                 intel_init_lctl(chip);
 581 }
 582
 583 /* calculate runtime delay from LPIB */
 584 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 585                                    unsigned int pos)
 586 {
 587         struct snd_pcm_substream *substream = azx_dev->core.substream;
 588         int stream = substream->stream;
 589         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 590         int delay;
 591
 592         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 593                 delay = pos - lpib_pos;
 594         else
 595                 delay = lpib_pos - pos;
 596         if (delay < 0) {
 597                 if (delay >= azx_dev->core.delay_negative_threshold)
 598                         delay = 0;
 599                 else
 600                         delay += azx_dev->core.bufsize;
 601         }
 602
 603         if (delay >= azx_dev->core.period_bytes) {
 604                 dev_info(chip->card->dev,
 605                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 606                          delay, azx_dev->core.period_bytes);
 607                 delay = 0;
 608                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 609                 chip->get_delay[stream] = NULL;
 610         }
 611
 612         return bytes_to_frames(substream->runtime, delay);
 613 }
 614
 615 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 616
 617 /* called from IRQ */
 618 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 619 {
 620         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 621         int ok;
 622
 623         ok = azx_position_ok(chip, azx_dev);
 624         if (ok == 1) {
 625                 azx_dev->irq_pending = 0;
 626                 return ok;
 627         } else if (ok == 0) {
 628                 /* bogus IRQ, process it later */
 629                 azx_dev->irq_pending = 1;
 630                 schedule_work(&hda->irq_pending_work);
 631         }
 632         return 0;
 633 }
 634
 635 #define display_power(chip, enable) \
 636         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 637
 638 /*
 639  * Check whether the current DMA position is acceptable for updating
 640  * periods.  Returns non-zero if it's OK.
 641  *
 642  * Many HD-audio controllers appear pretty inaccurate about
 643  * the update-IRQ timing.  The IRQ is issued before actually the
 644  * data is processed.  So, we need to process it afterwords in a
 645  * workqueue.
 646  *
 647  * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
 648  */
 649 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 650 {
 651         struct snd_pcm_substream *substream = azx_dev->core.substream;
 652         struct snd_pcm_runtime *runtime = substream->runtime;
 653         int stream = substream->stream;
 654         u32 wallclk;
 655         unsigned int pos;
 656         snd_pcm_uframes_t hwptr, target;
 657
 658         /*
 659          * The value of the WALLCLK register is always 0
 660          * on the Loongson controller, so we return directly.
 661          */
 662         if (chip->driver_type == AZX_DRIVER_LOONGSON)
 663                 return 1;
 664
 665         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 666         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 667                 return -1;      /* bogus (too early) interrupt */
 668
 669         if (chip->get_position[stream])
 670                 pos = chip->get_position[stream](chip, azx_dev);
 671         else { /* use the position buffer as default */
 672                 pos = azx_get_pos_posbuf(chip, azx_dev);
 673                 if (!pos || pos == (u32)-1) {
 674                         dev_info(chip->card->dev,
 675                                  "Invalid position buffer, using LPIB read method instead.\n");
 676                         chip->get_position[stream] = azx_get_pos_lpib;
 677                         if (chip->get_position[0] == azx_get_pos_lpib &&
 678                             chip->get_position[1] == azx_get_pos_lpib)
 679                                 azx_bus(chip)->use_posbuf = false;
 680                         pos = azx_get_pos_lpib(chip, azx_dev);
 681                         chip->get_delay[stream] = NULL;
 682                 } else {
 683                         chip->get_position[stream] = azx_get_pos_posbuf;
 684                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 685                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 686                 }
 687         }
 688
 689         if (pos >= azx_dev->core.bufsize)
 690                 pos = 0;
 691
 692         if (WARN_ONCE(!azx_dev->core.period_bytes,
 693                       "hda-intel: zero azx_dev->period_bytes"))
 694                 return -1; /* this shouldn't happen! */
 695         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 696             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 697                 /* NG - it's below the first next period boundary */
 698                 return chip->bdl_pos_adj ? 0 : -1;
 699         azx_dev->core.start_wallclk += wallclk;
 700
 701         if (azx_dev->core.no_period_wakeup)
 702                 return 1; /* OK, no need to check period boundary */
 703
 704         if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
 705                 return 1; /* OK, already in hwptr updating process */
 706
 707         /* check whether the period gets really elapsed */
 708         pos = bytes_to_frames(runtime, pos);
 709         hwptr = runtime->hw_ptr_base + pos;
 710         if (hwptr < runtime->status->hw_ptr)
 711                 hwptr += runtime->buffer_size;
 712         target = runtime->hw_ptr_interrupt + runtime->period_size;
 713         if (hwptr < target) {
 714                 /* too early wakeup, process it later */
 715                 return chip->bdl_pos_adj ? 0 : -1;
 716         }
 717
 718         return 1; /* OK, it's fine */
 719 }
 720
 721 /*
 722  * The work for pending PCM period updates.
 723  */
 724 static void azx_irq_pending_work(struct work_struct *work)
 725 {
 726         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 727         struct azx *chip = &hda->chip;
 728         struct hdac_bus *bus = azx_bus(chip);
 729         struct hdac_stream *s;
 730         int pending, ok;
 731
 732         if (!hda->irq_pending_warned) {
 733                 dev_info(chip->card->dev,
 734                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 735                          chip->card->number);
 736                 hda->irq_pending_warned = 1;
 737         }
 738
 739         for (;;) {
 740                 pending = 0;
 741                 spin_lock_irq(&bus->reg_lock);
 742                 list_for_each_entry(s, &bus->stream_list, list) {
 743                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 744                         if (!azx_dev->irq_pending ||
 745                             !s->substream ||
 746                             !s->running)
 747                                 continue;
 748                         ok = azx_position_ok(chip, azx_dev);
 749                         if (ok > 0) {
 750                                 azx_dev->irq_pending = 0;
 751                                 spin_unlock(&bus->reg_lock);
 752                                 snd_pcm_period_elapsed(s->substream);
 753                                 spin_lock(&bus->reg_lock);
 754                         } else if (ok < 0) {
 755                                 pending = 0;    /* too early */
 756                         } else
 757                                 pending++;
 758                 }
 759                 spin_unlock_irq(&bus->reg_lock);
 760                 if (!pending)
 761                         return;
 762                 msleep(1);
 763         }
 764 }
 765
 766 /* clear irq_pending flags and assure no on-going workq */
 767 static void azx_clear_irq_pending(struct azx *chip)
 768 {
 769         struct hdac_bus *bus = azx_bus(chip);
 770         struct hdac_stream *s;
 771
 772         spin_lock_irq(&bus->reg_lock);
 773         list_for_each_entry(s, &bus->stream_list, list) {
 774                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 775                 azx_dev->irq_pending = 0;
 776         }
 777         spin_unlock_irq(&bus->reg_lock);
 778 }
 779
 780 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 781 {
 782         struct hdac_bus *bus = azx_bus(chip);
 783
 784         if (request_irq(chip->pci->irq, azx_interrupt,
 785                         chip->msi ? 0 : IRQF_SHARED,
 786                         chip->card->irq_descr, chip)) {
 787                 dev_err(chip->card->dev,
 788                         "unable to grab IRQ %d, disabling device\n",
 789                         chip->pci->irq);
 790                 if (do_disconnect)
 791                         snd_card_disconnect(chip->card);
 792                 return -1;
 793         }
 794         bus->irq = chip->pci->irq;
 795         chip->card->sync_irq = bus->irq;
 796         pci_intx(chip->pci, !chip->msi);
 797         return 0;
 798 }
 799
 800 /* get the current DMA position with correction on VIA chips */
 801 static unsigned int azx_via_get_position(struct azx *chip,
 802                                          struct azx_dev *azx_dev)
 803 {
 804         unsigned int link_pos, mini_pos, bound_pos;
 805         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 806         unsigned int fifo_size;
 807
 808         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 809         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 810                 /* Playback, no problem using link position */
 811                 return link_pos;
 812         }
 813
 814         /* Capture */
 815         /* For new chipset,
 816          * use mod to get the DMA position just like old chipset
 817          */
 818         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 819         mod_dma_pos %= azx_dev->core.period_bytes;
 820
 821         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 822
 823         if (azx_dev->insufficient) {
 824                 /* Link position never gather than FIFO size */
 825                 if (link_pos <= fifo_size)
 826                         return 0;
 827
 828                 azx_dev->insufficient = 0;
 829         }
 830
 831         if (link_pos <= fifo_size)
 832                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 833         else
 834                 mini_pos = link_pos - fifo_size;
 835
 836         /* Find nearest previous boudary */
 837         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 838         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 839         if (mod_link_pos >= fifo_size)
 840                 bound_pos = link_pos - mod_link_pos;
 841         else if (mod_dma_pos >= mod_mini_pos)
 842                 bound_pos = mini_pos - mod_mini_pos;
 843         else {
 844                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 845                 if (bound_pos >= azx_dev->core.bufsize)
 846                         bound_pos = 0;
 847         }
 848
 849         /* Calculate real DMA position we want */
 850         return bound_pos + mod_dma_pos;
 851 }
 852
 853 #define AMD_FIFO_SIZE   32
 854
 855 /* get the current DMA position with FIFO size correction */
 856 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 857 {
 858         struct snd_pcm_substream *substream = azx_dev->core.substream;
 859         struct snd_pcm_runtime *runtime = substream->runtime;
 860         unsigned int pos, delay;
 861
 862         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 863         if (!runtime)
 864                 return pos;
 865
 866         runtime->delay = AMD_FIFO_SIZE;
 867         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 868         if (azx_dev->insufficient) {
 869                 if (pos < delay) {
 870                         delay = pos;
 871                         runtime->delay = bytes_to_frames(runtime, pos);
 872                 } else {
 873                         azx_dev->insufficient = 0;
 874                 }
 875         }
 876
 877         /* correct the DMA position for capture stream */
 878         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 879                 if (pos < delay)
 880                         pos += azx_dev->core.bufsize;
 881                 pos -= delay;
 882         }
 883
 884         return pos;
 885 }
 886
 887 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 888                                    unsigned int pos)
 889 {
 890         struct snd_pcm_substream *substream = azx_dev->core.substream;
 891
 892         /* just read back the calculated value in the above */
 893         return substream->runtime->delay;
 894 }
 895
 896 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
 897 {
 898         azx_stop_chip(chip);
 899         if (!skip_link_reset)
 900                 azx_enter_link_reset(chip);
 901         azx_clear_irq_pending(chip);
 902         display_power(chip, false);
 903 }
 904
 905 #ifdef CONFIG_PM
 906 static DEFINE_MUTEX(card_list_lock);
 907 static LIST_HEAD(card_list);
 908
 909 static void azx_shutdown_chip(struct azx *chip)
 910 {
 911         __azx_shutdown_chip(chip, false);
 912 }
 913
 914 static void azx_add_card_list(struct azx *chip)
 915 {
 916         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 917         mutex_lock(&card_list_lock);
 918         list_add(&hda->list, &card_list);
 919         mutex_unlock(&card_list_lock);
 920 }
 921
 922 static void azx_del_card_list(struct azx *chip)
 923 {
 924         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 925         mutex_lock(&card_list_lock);
 926         list_del_init(&hda->list);
 927         mutex_unlock(&card_list_lock);
 928 }
 929
 930 /* trigger power-save check at writing parameter */
 931 static int param_set_xint(const char *val, const struct kernel_param *kp)
 932 {
 933         struct hda_intel *hda;
 934         struct azx *chip;
 935         int prev = power_save;
 936         int ret = param_set_int(val, kp);
 937
 938         if (ret || prev == power_save)
 939                 return ret;
 940
 941         mutex_lock(&card_list_lock);
 942         list_for_each_entry(hda, &card_list, list) {
 943                 chip = &hda->chip;
 944                 if (!hda->probe_continued || chip->disabled)
 945                         continue;
 946                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 947         }
 948         mutex_unlock(&card_list_lock);
 949         return 0;
 950 }
 951
 952 /*
 953  * power management
 954  */
 955 static bool azx_is_pm_ready(struct snd_card *card)
 956 {
 957         struct azx *chip;
 958         struct hda_intel *hda;
 959
 960         if (!card)
 961                 return false;
 962         chip = card->private_data;
 963         hda = container_of(chip, struct hda_intel, chip);
 964         if (chip->disabled || hda->init_failed || !chip->running)
 965                 return false;
 966         return true;
 967 }
 968
 969 static void __azx_runtime_resume(struct azx *chip)
 970 {
 971         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 972         struct hdac_bus *bus = azx_bus(chip);
 973         struct hda_codec *codec;
 974         int status;
 975
 976         display_power(chip, true);
 977         if (hda->need_i915_power)
 978                 snd_hdac_i915_set_bclk(bus);
 979
 980         /* Read STATESTS before controller reset */
 981         status = azx_readw(chip, STATESTS);
 982
 983         azx_init_pci(chip);
 984         hda_intel_init_chip(chip, true);
 985
 986         /* Avoid codec resume if runtime resume is for system suspend */
 987         if (!chip->pm_prepared) {
 988                 list_for_each_codec(codec, &chip->bus) {
 989                         if (codec->relaxed_resume)
 990                                 continue;
 991
 992                         if (codec->forced_resume || (status & (1 << codec->addr)))
 993                                 pm_request_resume(hda_codec_dev(codec));
 994                 }
 995         }
 996
 997         /* power down again for link-controlled chips */
 998         if (!hda->need_i915_power)
 999                 display_power(chip, false);
1000 }
1001
1002 #ifdef CONFIG_PM_SLEEP
1003 static int azx_prepare(struct device *dev)
1004 {
1005         struct snd_card *card = dev_get_drvdata(dev);
1006         struct azx *chip;
1007
1008         if (!azx_is_pm_ready(card))
1009                 return 0;
1010
1011         chip = card->private_data;
1012         chip->pm_prepared = 1;
1013         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1014
1015         flush_work(&azx_bus(chip)->unsol_work);
1016
1017         /* HDA controller always requires different WAKEEN for runtime suspend
1018          * and system suspend, so don't use direct-complete here.
1019          */
1020         return 0;
1021 }
1022
1023 static void azx_complete(struct device *dev)
1024 {
1025         struct snd_card *card = dev_get_drvdata(dev);
1026         struct azx *chip;
1027
1028         if (!azx_is_pm_ready(card))
1029                 return;
1030
1031         chip = card->private_data;
1032         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1033         chip->pm_prepared = 0;
1034 }
1035
1036 static int azx_suspend(struct device *dev)
1037 {
1038         struct snd_card *card = dev_get_drvdata(dev);
1039         struct azx *chip;
1040         struct hdac_bus *bus;
1041
1042         if (!azx_is_pm_ready(card))
1043                 return 0;
1044
1045         chip = card->private_data;
1046         bus = azx_bus(chip);
1047         azx_shutdown_chip(chip);
1048         if (bus->irq >= 0) {
1049                 free_irq(bus->irq, chip);
1050                 bus->irq = -1;
1051                 chip->card->sync_irq = -1;
1052         }
1053
1054         if (chip->msi)
1055                 pci_disable_msi(chip->pci);
1056
1057         trace_azx_suspend(chip);
1058         return 0;
1059 }
1060
1061 static int azx_resume(struct device *dev)
1062 {
1063         struct snd_card *card = dev_get_drvdata(dev);
1064         struct azx *chip;
1065
1066         if (!azx_is_pm_ready(card))
1067                 return 0;
1068
1069         chip = card->private_data;
1070         if (chip->msi)
1071                 if (pci_enable_msi(chip->pci) < 0)
1072                         chip->msi = 0;
1073         if (azx_acquire_irq(chip, 1) < 0)
1074                 return -EIO;
1075
1076         __azx_runtime_resume(chip);
1077
1078         trace_azx_resume(chip);
1079         return 0;
1080 }
1081
1082 /* put codec down to D3 at hibernation for Intel SKL+;
1083  * otherwise BIOS may still access the codec and screw up the driver
1084  */
1085 static int azx_freeze_noirq(struct device *dev)
1086 {
1087         struct snd_card *card = dev_get_drvdata(dev);
1088         struct azx *chip = card->private_data;
1089         struct pci_dev *pci = to_pci_dev(dev);
1090
1091         if (!azx_is_pm_ready(card))
1092                 return 0;
1093         if (chip->driver_type == AZX_DRIVER_SKL)
1094                 pci_set_power_state(pci, PCI_D3hot);
1095
1096         return 0;
1097 }
1098
1099 static int azx_thaw_noirq(struct device *dev)
1100 {
1101         struct snd_card *card = dev_get_drvdata(dev);
1102         struct azx *chip = card->private_data;
1103         struct pci_dev *pci = to_pci_dev(dev);
1104
1105         if (!azx_is_pm_ready(card))
1106                 return 0;
1107         if (chip->driver_type == AZX_DRIVER_SKL)
1108                 pci_set_power_state(pci, PCI_D0);
1109
1110         return 0;
1111 }
1112 #endif /* CONFIG_PM_SLEEP */
1113
1114 static int azx_runtime_suspend(struct device *dev)
1115 {
1116         struct snd_card *card = dev_get_drvdata(dev);
1117         struct azx *chip;
1118
1119         if (!azx_is_pm_ready(card))
1120                 return 0;
1121         chip = card->private_data;
1122
1123         /* enable controller wake up event */
1124         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1125
1126         azx_shutdown_chip(chip);
1127         trace_azx_runtime_suspend(chip);
1128         return 0;
1129 }
1130
1131 static int azx_runtime_resume(struct device *dev)
1132 {
1133         struct snd_card *card = dev_get_drvdata(dev);
1134         struct azx *chip;
1135
1136         if (!azx_is_pm_ready(card))
1137                 return 0;
1138         chip = card->private_data;
1139         __azx_runtime_resume(chip);
1140
1141         /* disable controller Wake Up event*/
1142         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1143
1144         trace_azx_runtime_resume(chip);
1145         return 0;
1146 }
1147
1148 static int azx_runtime_idle(struct device *dev)
1149 {
1150         struct snd_card *card = dev_get_drvdata(dev);
1151         struct azx *chip;
1152         struct hda_intel *hda;
1153
1154         if (!card)
1155                 return 0;
1156
1157         chip = card->private_data;
1158         hda = container_of(chip, struct hda_intel, chip);
1159         if (chip->disabled || hda->init_failed)
1160                 return 0;
1161
1162         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1163             azx_bus(chip)->codec_powered || !chip->running)
1164                 return -EBUSY;
1165
1166         /* ELD notification gets broken when HD-audio bus is off */
1167         if (needs_eld_notify_link(chip))
1168                 return -EBUSY;
1169
1170         return 0;
1171 }
1172
1173 static const struct dev_pm_ops azx_pm = {
1174         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1175 #ifdef CONFIG_PM_SLEEP
1176         .prepare = azx_prepare,
1177         .complete = azx_complete,
1178         .freeze_noirq = azx_freeze_noirq,
1179         .thaw_noirq = azx_thaw_noirq,
1180 #endif
1181         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1182 };
1183
1184 #define AZX_PM_OPS      &azx_pm
1185 #else
1186 #define azx_add_card_list(chip) /* NOP */
1187 #define azx_del_card_list(chip) /* NOP */
1188 #define AZX_PM_OPS      NULL
1189 #endif /* CONFIG_PM */
1190
1191
1192 static int azx_probe_continue(struct azx *chip);
1193
1194 #ifdef SUPPORT_VGA_SWITCHEROO
1195 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1196
1197 static void azx_vs_set_state(struct pci_dev *pci,
1198                              enum vga_switcheroo_state state)
1199 {
1200         struct snd_card *card = pci_get_drvdata(pci);
1201         struct azx *chip = card->private_data;
1202         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1203         struct hda_codec *codec;
1204         bool disabled;
1205
1206         wait_for_completion(&hda->probe_wait);
1207         if (hda->init_failed)
1208                 return;
1209
1210         disabled = (state == VGA_SWITCHEROO_OFF);
1211         if (chip->disabled == disabled)
1212                 return;
1213
1214         if (!hda->probe_continued) {
1215                 chip->disabled = disabled;
1216                 if (!disabled) {
1217                         dev_info(chip->card->dev,
1218                                  "Start delayed initialization\n");
1219                         if (azx_probe_continue(chip) < 0)
1220                                 dev_err(chip->card->dev, "initialization error\n");
1221                 }
1222         } else {
1223                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1224                          disabled ? "Disabling" : "Enabling");
1225                 if (disabled) {
1226                         list_for_each_codec(codec, &chip->bus) {
1227                                 pm_runtime_suspend(hda_codec_dev(codec));
1228                                 pm_runtime_disable(hda_codec_dev(codec));
1229                         }
1230                         pm_runtime_suspend(card->dev);
1231                         pm_runtime_disable(card->dev);
1232                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1233                          * however we have no ACPI handle, so pci/acpi can't put us there,
1234                          * put ourselves there */
1235                         pci->current_state = PCI_D3cold;
1236                         chip->disabled = true;
1237                         if (snd_hda_lock_devices(&chip->bus))
1238                                 dev_warn(chip->card->dev,
1239                                          "Cannot lock devices!\n");
1240                 } else {
1241                         snd_hda_unlock_devices(&chip->bus);
1242                         chip->disabled = false;
1243                         pm_runtime_enable(card->dev);
1244                         list_for_each_codec(codec, &chip->bus) {
1245                                 pm_runtime_enable(hda_codec_dev(codec));
1246                                 pm_runtime_resume(hda_codec_dev(codec));
1247                         }
1248                 }
1249         }
1250 }
1251
1252 static bool azx_vs_can_switch(struct pci_dev *pci)
1253 {
1254         struct snd_card *card = pci_get_drvdata(pci);
1255         struct azx *chip = card->private_data;
1256         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1257
1258         wait_for_completion(&hda->probe_wait);
1259         if (hda->init_failed)
1260                 return false;
1261         if (chip->disabled || !hda->probe_continued)
1262                 return true;
1263         if (snd_hda_lock_devices(&chip->bus))
1264                 return false;
1265         snd_hda_unlock_devices(&chip->bus);
1266         return true;
1267 }
1268
1269 /*
1270  * The discrete GPU cannot power down unless the HDA controller runtime
1271  * suspends, so activate runtime PM on codecs even if power_save == 0.
1272  */
1273 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1274 {
1275         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1276         struct hda_codec *codec;
1277
1278         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1279                 list_for_each_codec(codec, &chip->bus)
1280                         codec->auto_runtime_pm = 1;
1281                 /* reset the power save setup */
1282                 if (chip->running)
1283                         set_default_power_save(chip);
1284         }
1285 }
1286
1287 static void azx_vs_gpu_bound(struct pci_dev *pci,
1288                              enum vga_switcheroo_client_id client_id)
1289 {
1290         struct snd_card *card = pci_get_drvdata(pci);
1291         struct azx *chip = card->private_data;
1292
1293         if (client_id == VGA_SWITCHEROO_DIS)
1294                 chip->bus.keep_power = 0;
1295         setup_vga_switcheroo_runtime_pm(chip);
1296 }
1297
1298 static void init_vga_switcheroo(struct azx *chip)
1299 {
1300         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1301         struct pci_dev *p = get_bound_vga(chip->pci);
1302         struct pci_dev *parent;
1303         if (p) {
1304                 dev_info(chip->card->dev,
1305                          "Handle vga_switcheroo audio client\n");
1306                 hda->use_vga_switcheroo = 1;
1307
1308                 /* cleared in either gpu_bound op or codec probe, or when its
1309                  * upstream port has _PR3 (i.e. dGPU).
1310                  */
1311                 parent = pci_upstream_bridge(p);
1312                 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1313                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1314                 pci_dev_put(p);
1315         }
1316 }
1317
1318 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1319         .set_gpu_state = azx_vs_set_state,
1320         .can_switch = azx_vs_can_switch,
1321         .gpu_bound = azx_vs_gpu_bound,
1322 };
1323
1324 static int register_vga_switcheroo(struct azx *chip)
1325 {
1326         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1327         struct pci_dev *p;
1328         int err;
1329
1330         if (!hda->use_vga_switcheroo)
1331                 return 0;
1332
1333         p = get_bound_vga(chip->pci);
1334         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1335         pci_dev_put(p);
1336
1337         if (err < 0)
1338                 return err;
1339         hda->vga_switcheroo_registered = 1;
1340
1341         return 0;
1342 }
1343 #else
1344 #define init_vga_switcheroo(chip)               /* NOP */
1345 #define register_vga_switcheroo(chip)           0
1346 #define check_hdmi_disabled(pci)        false
1347 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1348 #endif /* SUPPORT_VGA_SWITCHER */
1349
1350 /*
1351  * destructor
1352  */
1353 static void azx_free(struct azx *chip)
1354 {
1355         struct pci_dev *pci = chip->pci;
1356         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1357         struct hdac_bus *bus = azx_bus(chip);
1358
1359         if (hda->freed)
1360                 return;
1361
1362         if (azx_has_pm_runtime(chip) && chip->running) {
1363                 pm_runtime_get_noresume(&pci->dev);
1364                 pm_runtime_forbid(&pci->dev);
1365                 pm_runtime_dont_use_autosuspend(&pci->dev);
1366         }
1367
1368         chip->running = 0;
1369
1370         azx_del_card_list(chip);
1371
1372         hda->init_failed = 1; /* to be sure */
1373         complete_all(&hda->probe_wait);
1374
1375         if (use_vga_switcheroo(hda)) {
1376                 if (chip->disabled && hda->probe_continued)
1377                         snd_hda_unlock_devices(&chip->bus);
1378                 if (hda->vga_switcheroo_registered)
1379                         vga_switcheroo_unregister_client(chip->pci);
1380         }
1381
1382         if (bus->chip_init) {
1383                 azx_clear_irq_pending(chip);
1384                 azx_stop_all_streams(chip);
1385                 azx_stop_chip(chip);
1386         }
1387
1388         if (bus->irq >= 0)
1389                 free_irq(bus->irq, (void*)chip);
1390
1391         azx_free_stream_pages(chip);
1392         azx_free_streams(chip);
1393         snd_hdac_bus_exit(bus);
1394
1395 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1396         release_firmware(chip->fw);
1397 #endif
1398         display_power(chip, false);
1399
1400         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1401                 snd_hdac_i915_exit(bus);
1402
1403         hda->freed = 1;
1404 }
1405
1406 static int azx_dev_disconnect(struct snd_device *device)
1407 {
1408         struct azx *chip = device->device_data;
1409         struct hdac_bus *bus = azx_bus(chip);
1410
1411         chip->bus.shutdown = 1;
1412         cancel_work_sync(&bus->unsol_work);
1413
1414         return 0;
1415 }
1416
1417 static int azx_dev_free(struct snd_device *device)
1418 {
1419         azx_free(device->device_data);
1420         return 0;
1421 }
1422
1423 #ifdef SUPPORT_VGA_SWITCHEROO
1424 #ifdef CONFIG_ACPI
1425 /* ATPX is in the integrated GPU's namespace */
1426 static bool atpx_present(void)
1427 {
1428         struct pci_dev *pdev = NULL;
1429         acpi_handle dhandle, atpx_handle;
1430         acpi_status status;
1431
1432         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1433                 dhandle = ACPI_HANDLE(&pdev->dev);
1434                 if (dhandle) {
1435                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1436                         if (ACPI_SUCCESS(status)) {
1437                                 pci_dev_put(pdev);
1438                                 return true;
1439                         }
1440                 }
1441         }
1442         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1443                 dhandle = ACPI_HANDLE(&pdev->dev);
1444                 if (dhandle) {
1445                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1446                         if (ACPI_SUCCESS(status)) {
1447                                 pci_dev_put(pdev);
1448                                 return true;
1449                         }
1450                 }
1451         }
1452         return false;
1453 }
1454 #else
1455 static bool atpx_present(void)
1456 {
1457         return false;
1458 }
1459 #endif
1460
1461 /*
1462  * Check of disabled HDMI controller by vga_switcheroo
1463  */
1464 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1465 {
1466         struct pci_dev *p;
1467
1468         /* check only discrete GPU */
1469         switch (pci->vendor) {
1470         case PCI_VENDOR_ID_ATI:
1471         case PCI_VENDOR_ID_AMD:
1472                 if (pci->devfn == 1) {
1473                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1474                                                         pci->bus->number, 0);
1475                         if (p) {
1476                                 /* ATPX is in the integrated GPU's ACPI namespace
1477                                  * rather than the dGPU's namespace. However,
1478                                  * the dGPU is the one who is involved in
1479                                  * vgaswitcheroo.
1480                                  */
1481                                 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1482                                     (atpx_present() || apple_gmux_detect(NULL, NULL)))
1483                                         return p;
1484                                 pci_dev_put(p);
1485                         }
1486                 }
1487                 break;
1488         case PCI_VENDOR_ID_NVIDIA:
1489                 if (pci->devfn == 1) {
1490                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1491                                                         pci->bus->number, 0);
1492                         if (p) {
1493                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1494                                         return p;
1495                                 pci_dev_put(p);
1496                         }
1497                 }
1498                 break;
1499         }
1500         return NULL;
1501 }
1502
1503 static bool check_hdmi_disabled(struct pci_dev *pci)
1504 {
1505         bool vga_inactive = false;
1506         struct pci_dev *p = get_bound_vga(pci);
1507
1508         if (p) {
1509                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1510                         vga_inactive = true;
1511                 pci_dev_put(p);
1512         }
1513         return vga_inactive;
1514 }
1515 #endif /* SUPPORT_VGA_SWITCHEROO */
1516
1517 /*
1518  * allow/deny-listing for position_fix
1519  */
1520 static const struct snd_pci_quirk position_fix_list[] = {
1521         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1522         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1523         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1524         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1525         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1526         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1527         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1528         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1529         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1530         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1531         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1532         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1533         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1534         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1535         {}
1536 };
1537
1538 static int check_position_fix(struct azx *chip, int fix)
1539 {
1540         const struct snd_pci_quirk *q;
1541
1542         switch (fix) {
1543         case POS_FIX_AUTO:
1544         case POS_FIX_LPIB:
1545         case POS_FIX_POSBUF:
1546         case POS_FIX_VIACOMBO:
1547         case POS_FIX_COMBO:
1548         case POS_FIX_SKL:
1549         case POS_FIX_FIFO:
1550                 return fix;
1551         }
1552
1553         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1554         if (q) {
1555                 dev_info(chip->card->dev,
1556                          "position_fix set to %d for device %04x:%04x\n",
1557                          q->value, q->subvendor, q->subdevice);
1558                 return q->value;
1559         }
1560
1561         /* Check VIA/ATI HD Audio Controller exist */
1562         if (chip->driver_type == AZX_DRIVER_VIA) {
1563                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1564                 return POS_FIX_VIACOMBO;
1565         }
1566         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1567                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1568                 return POS_FIX_FIFO;
1569         }
1570         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1571                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1572                 return POS_FIX_LPIB;
1573         }
1574         if (chip->driver_type == AZX_DRIVER_SKL) {
1575                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1576                 return POS_FIX_SKL;
1577         }
1578         return POS_FIX_AUTO;
1579 }
1580
1581 static void assign_position_fix(struct azx *chip, int fix)
1582 {
1583         static const azx_get_pos_callback_t callbacks[] = {
1584                 [POS_FIX_AUTO] = NULL,
1585                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1586                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1587                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1588                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1589                 [POS_FIX_SKL] = azx_get_pos_posbuf,
1590                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1591         };
1592
1593         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1594
1595         /* combo mode uses LPIB only for playback */
1596         if (fix == POS_FIX_COMBO)
1597                 chip->get_position[1] = NULL;
1598
1599         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1600             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1601                 chip->get_delay[0] = chip->get_delay[1] =
1602                         azx_get_delay_from_lpib;
1603         }
1604
1605         if (fix == POS_FIX_FIFO)
1606                 chip->get_delay[0] = chip->get_delay[1] =
1607                         azx_get_delay_from_fifo;
1608 }
1609
1610 /*
1611  * deny-lists for probe_mask
1612  */
1613 static const struct snd_pci_quirk probe_mask_list[] = {
1614         /* Thinkpad often breaks the controller communication when accessing
1615          * to the non-working (or non-existing) modem codec slot.
1616          */
1617         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1618         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1619         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1620         /* broken BIOS */
1621         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1622         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1623         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1624         /* forced codec slots */
1625         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1626         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1627         SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1628         /* WinFast VP200 H (Teradici) user reported broken communication */
1629         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1630         {}
1631 };
1632
1633 #define AZX_FORCE_CODEC_MASK    0x100
1634
1635 static void check_probe_mask(struct azx *chip, int dev)
1636 {
1637         const struct snd_pci_quirk *q;
1638
1639         chip->codec_probe_mask = probe_mask[dev];
1640         if (chip->codec_probe_mask == -1) {
1641                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1642                 if (q) {
1643                         dev_info(chip->card->dev,
1644                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1645                                  q->value, q->subvendor, q->subdevice);
1646                         chip->codec_probe_mask = q->value;
1647                 }
1648         }
1649
1650         /* check forced option */
1651         if (chip->codec_probe_mask != -1 &&
1652             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1653                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1654                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1655                          (int)azx_bus(chip)->codec_mask);
1656         }
1657 }
1658
1659 /*
1660  * allow/deny-list for enable_msi
1661  */
1662 static const struct snd_pci_quirk msi_deny_list[] = {
1663         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1664         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1665         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1666         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1667         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1668         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1669         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1670         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1671         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1672         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1673         {}
1674 };
1675
1676 static void check_msi(struct azx *chip)
1677 {
1678         const struct snd_pci_quirk *q;
1679
1680         if (enable_msi >= 0) {
1681                 chip->msi = !!enable_msi;
1682                 return;
1683         }
1684         chip->msi = 1;  /* enable MSI as default */
1685         q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1686         if (q) {
1687                 dev_info(chip->card->dev,
1688                          "msi for device %04x:%04x set to %d\n",
1689                          q->subvendor, q->subdevice, q->value);
1690                 chip->msi = q->value;
1691                 return;
1692         }
1693
1694         /* NVidia chipsets seem to cause troubles with MSI */
1695         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1696                 dev_info(chip->card->dev, "Disabling MSI\n");
1697                 chip->msi = 0;
1698         }
1699 }
1700
1701 /* check the snoop mode availability */
1702 static void azx_check_snoop_available(struct azx *chip)
1703 {
1704         int snoop = hda_snoop;
1705
1706         if (snoop >= 0) {
1707                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1708                          snoop ? "snoop" : "non-snoop");
1709                 chip->snoop = snoop;
1710                 chip->uc_buffer = !snoop;
1711                 return;
1712         }
1713
1714         snoop = true;
1715         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1716             chip->driver_type == AZX_DRIVER_VIA) {
1717                 /* force to non-snoop mode for a new VIA controller
1718                  * when BIOS is set
1719                  */
1720                 u8 val;
1721                 pci_read_config_byte(chip->pci, 0x42, &val);
1722                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1723                                       chip->pci->revision == 0x20))
1724                         snoop = false;
1725         }
1726
1727         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1728                 snoop = false;
1729
1730         chip->snoop = snoop;
1731         if (!snoop) {
1732                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1733                 /* C-Media requires non-cached pages only for CORB/RIRB */
1734                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1735                         chip->uc_buffer = true;
1736         }
1737 }
1738
1739 static void azx_probe_work(struct work_struct *work)
1740 {
1741         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1742         azx_probe_continue(&hda->chip);
1743 }
1744
1745 static int default_bdl_pos_adj(struct azx *chip)
1746 {
1747         /* some exceptions: Atoms seem problematic with value 1 */
1748         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1749                 switch (chip->pci->device) {
1750                 case 0x0f04: /* Baytrail */
1751                 case 0x2284: /* Braswell */
1752                         return 32;
1753                 }
1754         }
1755
1756         switch (chip->driver_type) {
1757         /*
1758          * increase the bdl size for Glenfly Gpus for hardware
1759          * limitation on hdac interrupt interval
1760          */
1761         case AZX_DRIVER_GFHDMI:
1762                 return 128;
1763         case AZX_DRIVER_ICH:
1764         case AZX_DRIVER_PCH:
1765                 return 1;
1766         default:
1767                 return 32;
1768         }
1769 }
1770
1771 /*
1772  * constructor
1773  */
1774 static const struct hda_controller_ops pci_hda_ops;
1775
1776 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1777                       int dev, unsigned int driver_caps,
1778                       struct azx **rchip)
1779 {
1780         static const struct snd_device_ops ops = {
1781                 .dev_disconnect = azx_dev_disconnect,
1782                 .dev_free = azx_dev_free,
1783         };
1784         struct hda_intel *hda;
1785         struct azx *chip;
1786         int err;
1787
1788         *rchip = NULL;
1789
1790         err = pcim_enable_device(pci);
1791         if (err < 0)
1792                 return err;
1793
1794         hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1795         if (!hda)
1796                 return -ENOMEM;
1797
1798         chip = &hda->chip;
1799         mutex_init(&chip->open_mutex);
1800         chip->card = card;
1801         chip->pci = pci;
1802         chip->ops = &pci_hda_ops;
1803         chip->driver_caps = driver_caps;
1804         chip->driver_type = driver_caps & 0xff;
1805         check_msi(chip);
1806         chip->dev_index = dev;
1807         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1808                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1809         INIT_LIST_HEAD(&chip->pcm_list);
1810         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1811         INIT_LIST_HEAD(&hda->list);
1812         init_vga_switcheroo(chip);
1813         init_completion(&hda->probe_wait);
1814
1815         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1816
1817         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1818                 chip->fallback_to_single_cmd = 1;
1819         else /* explicitly set to single_cmd or not */
1820                 chip->single_cmd = single_cmd;
1821
1822         azx_check_snoop_available(chip);
1823
1824         if (bdl_pos_adj[dev] < 0)
1825                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1826         else
1827                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1828
1829         err = azx_bus_init(chip, model[dev]);
1830         if (err < 0)
1831                 return err;
1832
1833         /* use the non-cached pages in non-snoop mode */
1834         if (!azx_snoop(chip))
1835                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG;
1836
1837         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1838                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1839                 chip->bus.core.needs_damn_long_delay = 1;
1840         }
1841
1842         check_probe_mask(chip, dev);
1843
1844         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1845         if (err < 0) {
1846                 dev_err(card->dev, "Error creating device [card]!\n");
1847                 azx_free(chip);
1848                 return err;
1849         }
1850
1851         /* continue probing in work context as may trigger request module */
1852         INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1853
1854         *rchip = chip;
1855
1856         return 0;
1857 }
1858
1859 static int azx_first_init(struct azx *chip)
1860 {
1861         int dev = chip->dev_index;
1862         struct pci_dev *pci = chip->pci;
1863         struct snd_card *card = chip->card;
1864         struct hdac_bus *bus = azx_bus(chip);
1865         int err;
1866         unsigned short gcap;
1867         unsigned int dma_bits = 64;
1868
1869 #if BITS_PER_LONG != 64
1870         /* Fix up base address on ULI M5461 */
1871         if (chip->driver_type == AZX_DRIVER_ULI) {
1872                 u16 tmp3;
1873                 pci_read_config_word(pci, 0x40, &tmp3);
1874                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1875                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1876         }
1877 #endif
1878         /*
1879          * Fix response write request not synced to memory when handle
1880          * hdac interrupt on Glenfly Gpus
1881          */
1882         if (chip->driver_type == AZX_DRIVER_GFHDMI)
1883                 bus->polling_mode = 1;
1884
1885         if (chip->driver_type == AZX_DRIVER_LOONGSON) {
1886                 bus->polling_mode = 1;
1887                 bus->not_use_interrupts = 1;
1888                 bus->access_sdnctl_in_dword = 1;
1889         }
1890
1891         err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
1892         if (err < 0)
1893                 return err;
1894
1895         bus->addr = pci_resource_start(pci, 0);
1896         bus->remap_addr = pcim_iomap_table(pci)[0];
1897
1898         if (chip->driver_type == AZX_DRIVER_SKL)
1899                 snd_hdac_bus_parse_capabilities(bus);
1900
1901         /*
1902          * Some Intel CPUs has always running timer (ART) feature and
1903          * controller may have Global time sync reporting capability, so
1904          * check both of these before declaring synchronized time reporting
1905          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1906          */
1907         chip->gts_present = false;
1908
1909 #ifdef CONFIG_X86
1910         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1911                 chip->gts_present = true;
1912 #endif
1913
1914         if (chip->msi) {
1915                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1916                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1917                         pci->no_64bit_msi = true;
1918                 }
1919                 if (pci_enable_msi(pci) < 0)
1920                         chip->msi = 0;
1921         }
1922
1923         pci_set_master(pci);
1924
1925         gcap = azx_readw(chip, GCAP);
1926         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1927
1928         /* AMD devices support 40 or 48bit DMA, take the safe one */
1929         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1930                 dma_bits = 40;
1931
1932         /* disable SB600 64bit support for safety */
1933         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1934                 struct pci_dev *p_smbus;
1935                 dma_bits = 40;
1936                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1937                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1938                                          NULL);
1939                 if (p_smbus) {
1940                         if (p_smbus->revision < 0x30)
1941                                 gcap &= ~AZX_GCAP_64OK;
1942                         pci_dev_put(p_smbus);
1943                 }
1944         }
1945
1946         /* NVidia hardware normally only supports up to 40 bits of DMA */
1947         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1948                 dma_bits = 40;
1949
1950         /* disable 64bit DMA address on some devices */
1951         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1952                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1953                 gcap &= ~AZX_GCAP_64OK;
1954         }
1955
1956         /* disable buffer size rounding to 128-byte multiples if supported */
1957         if (align_buffer_size >= 0)
1958                 chip->align_buffer_size = !!align_buffer_size;
1959         else {
1960                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1961                         chip->align_buffer_size = 0;
1962                 else
1963                         chip->align_buffer_size = 1;
1964         }
1965
1966         /* allow 64bit DMA address if supported by H/W */
1967         if (!(gcap & AZX_GCAP_64OK))
1968                 dma_bits = 32;
1969         if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1970                 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1971         dma_set_max_seg_size(&pci->dev, UINT_MAX);
1972
1973         /* read number of streams from GCAP register instead of using
1974          * hardcoded value
1975          */
1976         chip->capture_streams = (gcap >> 8) & 0x0f;
1977         chip->playback_streams = (gcap >> 12) & 0x0f;
1978         if (!chip->playback_streams && !chip->capture_streams) {
1979                 /* gcap didn't give any info, switching to old method */
1980
1981                 switch (chip->driver_type) {
1982                 case AZX_DRIVER_ULI:
1983                         chip->playback_streams = ULI_NUM_PLAYBACK;
1984                         chip->capture_streams = ULI_NUM_CAPTURE;
1985                         break;
1986                 case AZX_DRIVER_ATIHDMI:
1987                 case AZX_DRIVER_ATIHDMI_NS:
1988                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1989                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1990                         break;
1991                 case AZX_DRIVER_GFHDMI:
1992                 case AZX_DRIVER_GENERIC:
1993                 default:
1994                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1995                         chip->capture_streams = ICH6_NUM_CAPTURE;
1996                         break;
1997                 }
1998         }
1999         chip->capture_index_offset = 0;
2000         chip->playback_index_offset = chip->capture_streams;
2001         chip->num_streams = chip->playback_streams + chip->capture_streams;
2002
2003         /* sanity check for the SDxCTL.STRM field overflow */
2004         if (chip->num_streams > 15 &&
2005             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
2006                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
2007                          "forcing separate stream tags", chip->num_streams);
2008                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
2009         }
2010
2011         /* initialize streams */
2012         err = azx_init_streams(chip);
2013         if (err < 0)
2014                 return err;
2015
2016         err = azx_alloc_stream_pages(chip);
2017         if (err < 0)
2018                 return err;
2019
2020         /* initialize chip */
2021         azx_init_pci(chip);
2022
2023         snd_hdac_i915_set_bclk(bus);
2024
2025         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2026
2027         /* codec detection */
2028         if (!azx_bus(chip)->codec_mask) {
2029                 dev_err(card->dev, "no codecs found!\n");
2030                 /* keep running the rest for the runtime PM */
2031         }
2032
2033         if (azx_acquire_irq(chip, 0) < 0)
2034                 return -EBUSY;
2035
2036         strcpy(card->driver, "HDA-Intel");
2037         strscpy(card->shortname, driver_short_names[chip->driver_type],
2038                 sizeof(card->shortname));
2039         snprintf(card->longname, sizeof(card->longname),
2040                  "%s at 0x%lx irq %i",
2041                  card->shortname, bus->addr, bus->irq);
2042
2043         return 0;
2044 }
2045
2046 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2047 /* callback from request_firmware_nowait() */
2048 static void azx_firmware_cb(const struct firmware *fw, void *context)
2049 {
2050         struct snd_card *card = context;
2051         struct azx *chip = card->private_data;
2052
2053         if (fw)
2054                 chip->fw = fw;
2055         else
2056                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2057         if (!chip->disabled) {
2058                 /* continue probing */
2059                 azx_probe_continue(chip);
2060         }
2061 }
2062 #endif
2063
2064 static int disable_msi_reset_irq(struct azx *chip)
2065 {
2066         struct hdac_bus *bus = azx_bus(chip);
2067         int err;
2068
2069         free_irq(bus->irq, chip);
2070         bus->irq = -1;
2071         chip->card->sync_irq = -1;
2072         pci_disable_msi(chip->pci);
2073         chip->msi = 0;
2074         err = azx_acquire_irq(chip, 1);
2075         if (err < 0)
2076                 return err;
2077
2078         return 0;
2079 }
2080
2081 /* Denylist for skipping the whole probe:
2082  * some HD-audio PCI entries are exposed without any codecs, and such devices
2083  * should be ignored from the beginning.
2084  */
2085 static const struct pci_device_id driver_denylist[] = {
2086         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2087         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2088         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2089         {}
2090 };
2091
2092 static const struct hda_controller_ops pci_hda_ops = {
2093         .disable_msi_reset_irq = disable_msi_reset_irq,
2094         .position_check = azx_position_check,
2095 };
2096
2097 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2098
2099 static int azx_probe(struct pci_dev *pci,
2100                      const struct pci_device_id *pci_id)
2101 {
2102         struct snd_card *card;
2103         struct hda_intel *hda;
2104         struct azx *chip;
2105         bool schedule_probe;
2106         int dev;
2107         int err;
2108
2109         if (pci_match_id(driver_denylist, pci)) {
2110                 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2111                 return -ENODEV;
2112         }
2113
2114         dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
2115         if (dev >= SNDRV_CARDS)
2116                 return -ENODEV;
2117         if (!enable[dev]) {
2118                 set_bit(dev, probed_devs);
2119                 return -ENOENT;
2120         }
2121
2122         /*
2123          * stop probe if another Intel's DSP driver should be activated
2124          */
2125         if (dmic_detect) {
2126                 err = snd_intel_dsp_driver_probe(pci);
2127                 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2128                         dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2129                         return -ENODEV;
2130                 }
2131         } else {
2132                 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2133         }
2134
2135         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2136                            0, &card);
2137         if (err < 0) {
2138                 dev_err(&pci->dev, "Error creating card!\n");
2139                 return err;
2140         }
2141
2142         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2143         if (err < 0)
2144                 goto out_free;
2145         card->private_data = chip;
2146         hda = container_of(chip, struct hda_intel, chip);
2147
2148         pci_set_drvdata(pci, card);
2149
2150         err = register_vga_switcheroo(chip);
2151         if (err < 0) {
2152                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2153                 goto out_free;
2154         }
2155
2156         if (check_hdmi_disabled(pci)) {
2157                 dev_info(card->dev, "VGA controller is disabled\n");
2158                 dev_info(card->dev, "Delaying initialization\n");
2159                 chip->disabled = true;
2160         }
2161
2162         schedule_probe = !chip->disabled;
2163
2164 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2165         if (patch[dev] && *patch[dev]) {
2166                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2167                          patch[dev]);
2168                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2169                                               &pci->dev, GFP_KERNEL, card,
2170                                               azx_firmware_cb);
2171                 if (err < 0)
2172                         goto out_free;
2173                 schedule_probe = false; /* continued in azx_firmware_cb() */
2174         }
2175 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2176
2177 #ifndef CONFIG_SND_HDA_I915
2178         if (CONTROLLER_IN_GPU(pci))
2179                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2180 #endif
2181
2182         if (schedule_probe)
2183                 schedule_delayed_work(&hda->probe_work, 0);
2184
2185         set_bit(dev, probed_devs);
2186         if (chip->disabled)
2187                 complete_all(&hda->probe_wait);
2188         return 0;
2189
2190 out_free:
2191         snd_card_free(card);
2192         return err;
2193 }
2194
2195 #ifdef CONFIG_PM
2196 /* On some boards setting power_save to a non 0 value leads to clicking /
2197  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2198  * figure out how to avoid these sounds, but that is not always feasible.
2199  * So we keep a list of devices where we disable powersaving as its known
2200  * to causes problems on these devices.
2201  */
2202 static const struct snd_pci_quirk power_save_denylist[] = {
2203         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2204         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2205         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2206         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2207         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2208         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2209         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2210         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2211         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2212         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2213         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2214         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2215         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2216         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2217         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2218         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2219         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2220         /* https://bugs.launchpad.net/bugs/1821663 */
2221         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2222         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2223         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2224         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2225         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2226         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2227         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2228         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2229         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2230         /* https://bugs.launchpad.net/bugs/1821663 */
2231         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2232         {}
2233 };
2234 #endif /* CONFIG_PM */
2235
2236 static void set_default_power_save(struct azx *chip)
2237 {
2238         int val = power_save;
2239
2240 #ifdef CONFIG_PM
2241         if (pm_blacklist) {
2242                 const struct snd_pci_quirk *q;
2243
2244                 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2245                 if (q && val) {
2246                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2247                                  q->subvendor, q->subdevice);
2248                         val = 0;
2249                 }
2250         }
2251 #endif /* CONFIG_PM */
2252         snd_hda_set_power_save(&chip->bus, val * 1000);
2253 }
2254
2255 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2256 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2257         [AZX_DRIVER_NVIDIA] = 8,
2258         [AZX_DRIVER_TERA] = 1,
2259 };
2260
2261 static int azx_probe_continue(struct azx *chip)
2262 {
2263         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2264         struct hdac_bus *bus = azx_bus(chip);
2265         struct pci_dev *pci = chip->pci;
2266         int dev = chip->dev_index;
2267         int err;
2268
2269         if (chip->disabled || hda->init_failed)
2270                 return -EIO;
2271         if (hda->probe_retry)
2272                 goto probe_retry;
2273
2274         to_hda_bus(bus)->bus_probing = 1;
2275         hda->probe_continued = 1;
2276
2277         /* bind with i915 if needed */
2278         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2279                 err = snd_hdac_i915_init(bus);
2280                 if (err < 0) {
2281                         /* if the controller is bound only with HDMI/DP
2282                          * (for HSW and BDW), we need to abort the probe;
2283                          * for other chips, still continue probing as other
2284                          * codecs can be on the same link.
2285                          */
2286                         if (CONTROLLER_IN_GPU(pci)) {
2287                                 dev_err(chip->card->dev,
2288                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2289                                 goto out_free;
2290                         } else {
2291                                 /* don't bother any longer */
2292                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2293                         }
2294                 }
2295
2296                 /* HSW/BDW controllers need this power */
2297                 if (CONTROLLER_IN_GPU(pci))
2298                         hda->need_i915_power = true;
2299         }
2300
2301         /* Request display power well for the HDA controller or codec. For
2302          * Haswell/Broadwell, both the display HDA controller and codec need
2303          * this power. For other platforms, like Baytrail/Braswell, only the
2304          * display codec needs the power and it can be released after probe.
2305          */
2306         display_power(chip, true);
2307
2308         err = azx_first_init(chip);
2309         if (err < 0)
2310                 goto out_free;
2311
2312 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2313         chip->beep_mode = beep_mode[dev];
2314 #endif
2315
2316         chip->ctl_dev_id = ctl_dev_id;
2317
2318         /* create codec instances */
2319         if (bus->codec_mask) {
2320                 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2321                 if (err < 0)
2322                         goto out_free;
2323         }
2324
2325 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2326         if (chip->fw) {
2327                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2328                                          chip->fw->data);
2329                 if (err < 0)
2330                         goto out_free;
2331 #ifndef CONFIG_PM
2332                 release_firmware(chip->fw); /* no longer needed */
2333                 chip->fw = NULL;
2334 #endif
2335         }
2336 #endif
2337
2338  probe_retry:
2339         if (bus->codec_mask && !(probe_only[dev] & 1)) {
2340                 err = azx_codec_configure(chip);
2341                 if (err) {
2342                         if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2343                             ++hda->probe_retry < 60) {
2344                                 schedule_delayed_work(&hda->probe_work,
2345                                                       msecs_to_jiffies(1000));
2346                                 return 0; /* keep things up */
2347                         }
2348                         dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2349                         goto out_free;
2350                 }
2351         }
2352
2353         err = snd_card_register(chip->card);
2354         if (err < 0)
2355                 goto out_free;
2356
2357         setup_vga_switcheroo_runtime_pm(chip);
2358
2359         chip->running = 1;
2360         azx_add_card_list(chip);
2361
2362         set_default_power_save(chip);
2363
2364         if (azx_has_pm_runtime(chip)) {
2365                 pm_runtime_use_autosuspend(&pci->dev);
2366                 pm_runtime_allow(&pci->dev);
2367                 pm_runtime_put_autosuspend(&pci->dev);
2368         }
2369
2370 out_free:
2371         if (err < 0) {
2372                 pci_set_drvdata(pci, NULL);
2373                 snd_card_free(chip->card);
2374                 return err;
2375         }
2376
2377         if (!hda->need_i915_power)
2378                 display_power(chip, false);
2379         complete_all(&hda->probe_wait);
2380         to_hda_bus(bus)->bus_probing = 0;
2381         hda->probe_retry = 0;
2382         return 0;
2383 }
2384
2385 static void azx_remove(struct pci_dev *pci)
2386 {
2387         struct snd_card *card = pci_get_drvdata(pci);
2388         struct azx *chip;
2389         struct hda_intel *hda;
2390
2391         if (card) {
2392                 /* cancel the pending probing work */
2393                 chip = card->private_data;
2394                 hda = container_of(chip, struct hda_intel, chip);
2395                 /* FIXME: below is an ugly workaround.
2396                  * Both device_release_driver() and driver_probe_device()
2397                  * take *both* the device's and its parent's lock before
2398                  * calling the remove() and probe() callbacks.  The codec
2399                  * probe takes the locks of both the codec itself and its
2400                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2401                  * the PCI controller is unbound, it takes its lock, too
2402                  * ==> ouch, a deadlock!
2403                  * As a workaround, we unlock temporarily here the controller
2404                  * device during cancel_work_sync() call.
2405                  */
2406                 device_unlock(&pci->dev);
2407                 cancel_delayed_work_sync(&hda->probe_work);
2408                 device_lock(&pci->dev);
2409
2410                 clear_bit(chip->dev_index, probed_devs);
2411                 pci_set_drvdata(pci, NULL);
2412                 snd_card_free(card);
2413         }
2414 }
2415
2416 static void azx_shutdown(struct pci_dev *pci)
2417 {
2418         struct snd_card *card = pci_get_drvdata(pci);
2419         struct azx *chip;
2420
2421         if (!card)
2422                 return;
2423         chip = card->private_data;
2424         if (chip && chip->running)
2425                 __azx_shutdown_chip(chip, true);
2426 }
2427
2428 /* PCI IDs */
2429 static const struct pci_device_id azx_ids[] = {
2430         /* CPT */
2431         { PCI_DEVICE(0x8086, 0x1c20),
2432           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2433         /* PBG */
2434         { PCI_DEVICE(0x8086, 0x1d20),
2435           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2436         /* Panther Point */
2437         { PCI_DEVICE(0x8086, 0x1e20),
2438           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2439         /* Lynx Point */
2440         { PCI_DEVICE(0x8086, 0x8c20),
2441           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2442         /* 9 Series */
2443         { PCI_DEVICE(0x8086, 0x8ca0),
2444           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2445         /* Wellsburg */
2446         { PCI_DEVICE(0x8086, 0x8d20),
2447           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2448         { PCI_DEVICE(0x8086, 0x8d21),
2449           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2450         /* Lewisburg */
2451         { PCI_DEVICE(0x8086, 0xa1f0),
2452           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2453         { PCI_DEVICE(0x8086, 0xa270),
2454           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2455         /* Lynx Point-LP */
2456         { PCI_DEVICE(0x8086, 0x9c20),
2457           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2458         /* Lynx Point-LP */
2459         { PCI_DEVICE(0x8086, 0x9c21),
2460           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2461         /* Wildcat Point-LP */
2462         { PCI_DEVICE(0x8086, 0x9ca0),
2463           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2464         /* Sunrise Point */
2465         { PCI_DEVICE(0x8086, 0xa170),
2466           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2467         /* Sunrise Point-LP */
2468         { PCI_DEVICE(0x8086, 0x9d70),
2469           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2470         /* Kabylake */
2471         { PCI_DEVICE(0x8086, 0xa171),
2472           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2473         /* Kabylake-LP */
2474         { PCI_DEVICE(0x8086, 0x9d71),
2475           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2476         /* Kabylake-H */
2477         { PCI_DEVICE(0x8086, 0xa2f0),
2478           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2479         /* Coffelake */
2480         { PCI_DEVICE(0x8086, 0xa348),
2481           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2482         /* Cannonlake */
2483         { PCI_DEVICE(0x8086, 0x9dc8),
2484           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2485         /* CometLake-LP */
2486         { PCI_DEVICE(0x8086, 0x02C8),
2487           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2488         /* CometLake-H */
2489         { PCI_DEVICE(0x8086, 0x06C8),
2490           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2491         { PCI_DEVICE(0x8086, 0xf1c8),
2492           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2493         /* CometLake-S */
2494         { PCI_DEVICE(0x8086, 0xa3f0),
2495           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2496         /* CometLake-R */
2497         { PCI_DEVICE(0x8086, 0xf0c8),
2498           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2499         /* Icelake */
2500         { PCI_DEVICE(0x8086, 0x34c8),
2501           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2502         /* Icelake-H */
2503         { PCI_DEVICE(0x8086, 0x3dc8),
2504           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2505         /* Jasperlake */
2506         { PCI_DEVICE(0x8086, 0x38c8),
2507           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2508         { PCI_DEVICE(0x8086, 0x4dc8),
2509           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2510         /* Tigerlake */
2511         { PCI_DEVICE(0x8086, 0xa0c8),
2512           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2513         /* Tigerlake-H */
2514         { PCI_DEVICE(0x8086, 0x43c8),
2515           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2516         /* DG1 */
2517         { PCI_DEVICE(0x8086, 0x490d),
2518           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2519         /* DG2 */
2520         { PCI_DEVICE(0x8086, 0x4f90),
2521           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2522         { PCI_DEVICE(0x8086, 0x4f91),
2523           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2524         { PCI_DEVICE(0x8086, 0x4f92),
2525           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2526         /* Alderlake-S */
2527         { PCI_DEVICE(0x8086, 0x7ad0),
2528           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2529         /* Alderlake-P */
2530         { PCI_DEVICE(0x8086, 0x51c8),
2531           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2532         { PCI_DEVICE(0x8086, 0x51c9),
2533           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2534         { PCI_DEVICE(0x8086, 0x51cd),
2535           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2536         /* Alderlake-M */
2537         { PCI_DEVICE(0x8086, 0x51cc),
2538           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2539         /* Alderlake-N */
2540         { PCI_DEVICE(0x8086, 0x54c8),
2541           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2542         /* Elkhart Lake */
2543         { PCI_DEVICE(0x8086, 0x4b55),
2544           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2545         { PCI_DEVICE(0x8086, 0x4b58),
2546           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2547         /* Raptor Lake */
2548         { PCI_DEVICE(0x8086, 0x7a50),
2549           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2550         { PCI_DEVICE(0x8086, 0x51ca),
2551           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2552         { PCI_DEVICE(0x8086, 0x51cb),
2553           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2554         { PCI_DEVICE(0x8086, 0x51ce),
2555           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2556         { PCI_DEVICE(0x8086, 0x51cf),
2557           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2558         /* Meteorlake-P */
2559         { PCI_DEVICE(0x8086, 0x7e28),
2560           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2561         /* Lunarlake-P */
2562         { PCI_DEVICE(0x8086, 0xa828),
2563           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2564         /* Broxton-P(Apollolake) */
2565         { PCI_DEVICE(0x8086, 0x5a98),
2566           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2567         /* Broxton-T */
2568         { PCI_DEVICE(0x8086, 0x1a98),
2569           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2570         /* Gemini-Lake */
2571         { PCI_DEVICE(0x8086, 0x3198),
2572           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2573         /* Haswell */
2574         { PCI_DEVICE(0x8086, 0x0a0c),
2575           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2576         { PCI_DEVICE(0x8086, 0x0c0c),
2577           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2578         { PCI_DEVICE(0x8086, 0x0d0c),
2579           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2580         /* Broadwell */
2581         { PCI_DEVICE(0x8086, 0x160c),
2582           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2583         /* 5 Series/3400 */
2584         { PCI_DEVICE(0x8086, 0x3b56),
2585           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2586         { PCI_DEVICE(0x8086, 0x3b57),
2587           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2588         /* Poulsbo */
2589         { PCI_DEVICE(0x8086, 0x811b),
2590           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2591           AZX_DCAPS_POSFIX_LPIB },
2592         /* Oaktrail */
2593         { PCI_DEVICE(0x8086, 0x080a),
2594           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2595         /* BayTrail */
2596         { PCI_DEVICE(0x8086, 0x0f04),
2597           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2598         /* Braswell */
2599         { PCI_DEVICE(0x8086, 0x2284),
2600           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2601         /* ICH6 */
2602         { PCI_DEVICE(0x8086, 0x2668),
2603           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2604         /* ICH7 */
2605         { PCI_DEVICE(0x8086, 0x27d8),
2606           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2607         /* ESB2 */
2608         { PCI_DEVICE(0x8086, 0x269a),
2609           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2610         /* ICH8 */
2611         { PCI_DEVICE(0x8086, 0x284b),
2612           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2613         /* ICH9 */
2614         { PCI_DEVICE(0x8086, 0x293e),
2615           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2616         /* ICH9 */
2617         { PCI_DEVICE(0x8086, 0x293f),
2618           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2619         /* ICH10 */
2620         { PCI_DEVICE(0x8086, 0x3a3e),
2621           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2622         /* ICH10 */
2623         { PCI_DEVICE(0x8086, 0x3a6e),
2624           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2625         /* Generic Intel */
2626         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2627           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2628           .class_mask = 0xffffff,
2629           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2630         /* ATI SB 450/600/700/800/900 */
2631         { PCI_DEVICE(0x1002, 0x437b),
2632           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2633         { PCI_DEVICE(0x1002, 0x4383),
2634           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2635         /* AMD Hudson */
2636         { PCI_DEVICE(0x1022, 0x780d),
2637           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2638         /* AMD, X370 & co */
2639         { PCI_DEVICE(0x1022, 0x1457),
2640           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2641         /* AMD, X570 & co */
2642         { PCI_DEVICE(0x1022, 0x1487),
2643           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2644         /* AMD Stoney */
2645         { PCI_DEVICE(0x1022, 0x157a),
2646           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2647                          AZX_DCAPS_PM_RUNTIME },
2648         /* AMD Raven */
2649         { PCI_DEVICE(0x1022, 0x15e3),
2650           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2651         /* ATI HDMI */
2652         { PCI_DEVICE(0x1002, 0x0002),
2653           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2654           AZX_DCAPS_PM_RUNTIME },
2655         { PCI_DEVICE(0x1002, 0x1308),
2656           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2657         { PCI_DEVICE(0x1002, 0x157a),
2658           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2659         { PCI_DEVICE(0x1002, 0x15b3),
2660           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2661         { PCI_DEVICE(0x1002, 0x793b),
2662           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2663         { PCI_DEVICE(0x1002, 0x7919),
2664           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2665         { PCI_DEVICE(0x1002, 0x960f),
2666           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2667         { PCI_DEVICE(0x1002, 0x970f),
2668           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2669         { PCI_DEVICE(0x1002, 0x9840),
2670           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2671         { PCI_DEVICE(0x1002, 0xaa00),
2672           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2673         { PCI_DEVICE(0x1002, 0xaa08),
2674           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2675         { PCI_DEVICE(0x1002, 0xaa10),
2676           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2677         { PCI_DEVICE(0x1002, 0xaa18),
2678           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2679         { PCI_DEVICE(0x1002, 0xaa20),
2680           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2681         { PCI_DEVICE(0x1002, 0xaa28),
2682           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2683         { PCI_DEVICE(0x1002, 0xaa30),
2684           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2685         { PCI_DEVICE(0x1002, 0xaa38),
2686           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2687         { PCI_DEVICE(0x1002, 0xaa40),
2688           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2689         { PCI_DEVICE(0x1002, 0xaa48),
2690           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2691         { PCI_DEVICE(0x1002, 0xaa50),
2692           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2693         { PCI_DEVICE(0x1002, 0xaa58),
2694           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2695         { PCI_DEVICE(0x1002, 0xaa60),
2696           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2697         { PCI_DEVICE(0x1002, 0xaa68),
2698           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2699         { PCI_DEVICE(0x1002, 0xaa80),
2700           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2701         { PCI_DEVICE(0x1002, 0xaa88),
2702           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2703         { PCI_DEVICE(0x1002, 0xaa90),
2704           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2705         { PCI_DEVICE(0x1002, 0xaa98),
2706           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2707         { PCI_DEVICE(0x1002, 0x9902),
2708           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2709         { PCI_DEVICE(0x1002, 0xaaa0),
2710           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2711         { PCI_DEVICE(0x1002, 0xaaa8),
2712           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2713         { PCI_DEVICE(0x1002, 0xaab0),
2714           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2715         { PCI_DEVICE(0x1002, 0xaac0),
2716           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2717           AZX_DCAPS_PM_RUNTIME },
2718         { PCI_DEVICE(0x1002, 0xaac8),
2719           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2720           AZX_DCAPS_PM_RUNTIME },
2721         { PCI_DEVICE(0x1002, 0xaad8),
2722           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2723           AZX_DCAPS_PM_RUNTIME },
2724         { PCI_DEVICE(0x1002, 0xaae0),
2725           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2726           AZX_DCAPS_PM_RUNTIME },
2727         { PCI_DEVICE(0x1002, 0xaae8),
2728           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2729           AZX_DCAPS_PM_RUNTIME },
2730         { PCI_DEVICE(0x1002, 0xaaf0),
2731           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2732           AZX_DCAPS_PM_RUNTIME },
2733         { PCI_DEVICE(0x1002, 0xaaf8),
2734           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2735           AZX_DCAPS_PM_RUNTIME },
2736         { PCI_DEVICE(0x1002, 0xab00),
2737           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2738           AZX_DCAPS_PM_RUNTIME },
2739         { PCI_DEVICE(0x1002, 0xab08),
2740           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2741           AZX_DCAPS_PM_RUNTIME },
2742         { PCI_DEVICE(0x1002, 0xab10),
2743           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2744           AZX_DCAPS_PM_RUNTIME },
2745         { PCI_DEVICE(0x1002, 0xab18),
2746           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2747           AZX_DCAPS_PM_RUNTIME },
2748         { PCI_DEVICE(0x1002, 0xab20),
2749           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2750           AZX_DCAPS_PM_RUNTIME },
2751         { PCI_DEVICE(0x1002, 0xab28),
2752           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2753           AZX_DCAPS_PM_RUNTIME },
2754         { PCI_DEVICE(0x1002, 0xab30),
2755           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2756           AZX_DCAPS_PM_RUNTIME },
2757         { PCI_DEVICE(0x1002, 0xab38),
2758           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2759           AZX_DCAPS_PM_RUNTIME },
2760         /* GLENFLY */
2761         { PCI_DEVICE(0x6766, PCI_ANY_ID),
2762           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2763           .class_mask = 0xffffff,
2764           .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
2765           AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2766         /* VIA VT8251/VT8237A */
2767         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2768         /* VIA GFX VT7122/VX900 */
2769         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2770         /* VIA GFX VT6122/VX11 */
2771         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2772         /* SIS966 */
2773         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2774         /* ULI M5461 */
2775         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2776         /* NVIDIA MCP */
2777         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2778           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2779           .class_mask = 0xffffff,
2780           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2781         /* Teradici */
2782         { PCI_DEVICE(0x6549, 0x1200),
2783           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2784         { PCI_DEVICE(0x6549, 0x2200),
2785           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2786         /* Creative X-Fi (CA0110-IBG) */
2787         /* CTHDA chips */
2788         { PCI_DEVICE(0x1102, 0x0010),
2789           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2790         { PCI_DEVICE(0x1102, 0x0012),
2791           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2792 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2793         /* the following entry conflicts with snd-ctxfi driver,
2794          * as ctxfi driver mutates from HD-audio to native mode with
2795          * a special command sequence.
2796          */
2797         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2798           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2799           .class_mask = 0xffffff,
2800           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2801           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2802 #else
2803         /* this entry seems still valid -- i.e. without emu20kx chip */
2804         { PCI_DEVICE(0x1102, 0x0009),
2805           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2806           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2807 #endif
2808         /* CM8888 */
2809         { PCI_DEVICE(0x13f6, 0x5011),
2810           .driver_data = AZX_DRIVER_CMEDIA |
2811           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2812         /* Vortex86MX */
2813         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2814         /* VMware HDAudio */
2815         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2816         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2817         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2818           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2819           .class_mask = 0xffffff,
2820           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2821         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2822           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2823           .class_mask = 0xffffff,
2824           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2825         /* Zhaoxin */
2826         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2827         /* Loongson HDAudio*/
2828         {PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA),
2829           .driver_data = AZX_DRIVER_LOONGSON },
2830         {PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI),
2831           .driver_data = AZX_DRIVER_LOONGSON },
2832         { 0, }
2833 };
2834 MODULE_DEVICE_TABLE(pci, azx_ids);
2835
2836 /* pci_driver definition */
2837 static struct pci_driver azx_driver = {
2838         .name = KBUILD_MODNAME,
2839         .id_table = azx_ids,
2840         .probe = azx_probe,
2841         .remove = azx_remove,
2842         .shutdown = azx_shutdown,
2843         .driver = {
2844                 .pm = AZX_PM_OPS,
2845         },
2846 };
2847
2848 module_pci_driver(azx_driver);