1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * hda_intel.c - Implementation of primary alsa driver code base
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
42 /* for snoop control */
43 #include <asm/set_memory.h>
44 #include <asm/cpufeature.h>
46 #include <sound/core.h>
47 #include <sound/initval.h>
48 #include <sound/hdaudio.h>
49 #include <sound/hda_i915.h>
50 #include <sound/intel-dsp-config.h>
51 #include <linux/vgaarb.h>
52 #include <linux/vga_switcheroo.h>
53 #include <linux/apple-gmux.h>
54 #include <linux/firmware.h>
55 #include <sound/hda_codec.h>
56 #include "hda_controller.h"
57 #include "hda_intel.h"
59 #define CREATE_TRACE_POINTS
60 #include "hda_intel_trace.h"
62 /* position fix mode */
73 /* Defines for ATI HD Audio support in SB450 south bridge */
74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
77 /* Defines for Nvidia HDA support */
78 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
79 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
80 #define NVIDIA_HDA_ISTRM_COH 0x4d
81 #define NVIDIA_HDA_OSTRM_COH 0x4c
82 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
84 /* Defines for Intel SCH HDA snoop control */
85 #define INTEL_HDA_CGCTL 0x48
86 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
87 #define INTEL_SCH_HDA_DEVC 0x78
88 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
90 /* max number of SDs */
91 /* ICH, ATI and VIA have 4 playback and 4 capture */
92 #define ICH6_NUM_CAPTURE 4
93 #define ICH6_NUM_PLAYBACK 4
95 /* ULI has 6 playback and 5 capture */
96 #define ULI_NUM_CAPTURE 5
97 #define ULI_NUM_PLAYBACK 6
99 /* ATI HDMI may have up to 8 playbacks and 0 capture */
100 #define ATIHDMI_NUM_CAPTURE 0
101 #define ATIHDMI_NUM_PLAYBACK 8
104 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
105 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
106 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
107 static char *model[SNDRV_CARDS];
108 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
109 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
110 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
111 static int probe_only[SNDRV_CARDS];
112 static int jackpoll_ms[SNDRV_CARDS];
113 static int single_cmd = -1;
114 static int enable_msi = -1;
115 #ifdef CONFIG_SND_HDA_PATCH_LOADER
116 static char *patch[SNDRV_CARDS];
118 #ifdef CONFIG_SND_HDA_INPUT_BEEP
119 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
120 CONFIG_SND_HDA_INPUT_BEEP_MODE};
122 static bool dmic_detect = 1;
123 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
125 module_param_array(index, int, NULL, 0444);
126 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
127 module_param_array(id, charp, NULL, 0444);
128 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
129 module_param_array(enable, bool, NULL, 0444);
130 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
131 module_param_array(model, charp, NULL, 0444);
132 MODULE_PARM_DESC(model, "Use the given board model.");
133 module_param_array(position_fix, int, NULL, 0444);
134 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
136 module_param_array(bdl_pos_adj, int, NULL, 0644);
137 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
138 module_param_array(probe_mask, int, NULL, 0444);
139 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
140 module_param_array(probe_only, int, NULL, 0444);
141 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
142 module_param_array(jackpoll_ms, int, NULL, 0444);
143 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
144 module_param(single_cmd, bint, 0444);
145 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
146 "(for debugging only).");
147 module_param(enable_msi, bint, 0444);
148 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
149 #ifdef CONFIG_SND_HDA_PATCH_LOADER
150 module_param_array(patch, charp, NULL, 0444);
151 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
153 #ifdef CONFIG_SND_HDA_INPUT_BEEP
154 module_param_array(beep_mode, bool, NULL, 0444);
155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
156 "(0=off, 1=on) (default=1).");
158 module_param(dmic_detect, bool, 0444);
159 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
160 "(0=off, 1=on) (default=1); "
161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
162 module_param(ctl_dev_id, bool, 0444);
163 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
166 static int param_set_xint(const char *val, const struct kernel_param *kp);
167 static const struct kernel_param_ops param_ops_xint = {
168 .set = param_set_xint,
169 .get = param_get_int,
171 #define param_check_xint param_check_int
173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
174 module_param(power_save, xint, 0644);
175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
176 "(in second, 0 = disable).");
178 static bool pm_blacklist = true;
179 module_param(pm_blacklist, bool, 0644);
180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
182 /* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
186 static bool power_save_controller = 1;
187 module_param(power_save_controller, bool, 0644);
188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
191 #endif /* CONFIG_PM */
193 static int align_buffer_size = -1;
194 module_param(align_buffer_size, bint, 0644);
195 MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
199 static int hda_snoop = -1;
200 module_param_named(snoop, hda_snoop, bint, 0444);
201 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
203 #define hda_snoop true
207 MODULE_LICENSE("GPL");
208 MODULE_DESCRIPTION("Intel HDA driver");
210 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
211 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
212 #define SUPPORT_VGA_SWITCHEROO
229 AZX_DRIVER_ATIHDMI_NS,
242 AZX_NUM_DRIVERS, /* keep this as last entry */
245 #define azx_get_snoop_type(chip) \
246 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
247 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
249 /* quirks for old Intel chipsets */
250 #define AZX_DCAPS_INTEL_ICH \
251 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
253 /* quirks for Intel PCH */
254 #define AZX_DCAPS_INTEL_PCH_BASE \
255 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
256 AZX_DCAPS_SNOOP_TYPE(SCH))
258 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
259 #define AZX_DCAPS_INTEL_PCH_NOPM \
260 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
262 /* PCH for HSW/BDW; with runtime PM */
263 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
264 #define AZX_DCAPS_INTEL_PCH \
265 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
268 #define AZX_DCAPS_INTEL_HASWELL \
269 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
270 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
271 AZX_DCAPS_SNOOP_TYPE(SCH))
273 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
274 #define AZX_DCAPS_INTEL_BROADWELL \
275 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
276 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
277 AZX_DCAPS_SNOOP_TYPE(SCH))
279 #define AZX_DCAPS_INTEL_BAYTRAIL \
280 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
282 #define AZX_DCAPS_INTEL_BRASWELL \
283 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
284 AZX_DCAPS_I915_COMPONENT)
286 #define AZX_DCAPS_INTEL_SKYLAKE \
287 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
288 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
290 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
292 /* quirks for ATI SB / AMD Hudson */
293 #define AZX_DCAPS_PRESET_ATI_SB \
294 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
295 AZX_DCAPS_SNOOP_TYPE(ATI))
297 /* quirks for ATI/AMD HDMI */
298 #define AZX_DCAPS_PRESET_ATI_HDMI \
299 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
302 /* quirks for ATI HDMI with snoop off */
303 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
304 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
306 /* quirks for AMD SB */
307 #define AZX_DCAPS_PRESET_AMD_SB \
308 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
309 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
310 AZX_DCAPS_RETRY_PROBE)
312 /* quirks for Nvidia */
313 #define AZX_DCAPS_PRESET_NVIDIA \
314 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
315 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
317 #define AZX_DCAPS_PRESET_CTHDA \
318 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
319 AZX_DCAPS_NO_64BIT |\
320 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
323 * vga_switcheroo support
325 #ifdef SUPPORT_VGA_SWITCHEROO
326 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
327 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
329 #define use_vga_switcheroo(chip) 0
330 #define needs_eld_notify_link(chip) false
333 static const char * const driver_short_names[] = {
334 [AZX_DRIVER_ICH] = "HDA Intel",
335 [AZX_DRIVER_PCH] = "HDA Intel PCH",
336 [AZX_DRIVER_SCH] = "HDA Intel MID",
337 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
338 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
339 [AZX_DRIVER_ATI] = "HDA ATI SB",
340 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
341 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
342 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI",
343 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
344 [AZX_DRIVER_SIS] = "HDA SIS966",
345 [AZX_DRIVER_ULI] = "HDA ULI M5461",
346 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
347 [AZX_DRIVER_TERA] = "HDA Teradici",
348 [AZX_DRIVER_CTX] = "HDA Creative",
349 [AZX_DRIVER_CTHDA] = "HDA Creative",
350 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
351 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
352 [AZX_DRIVER_LOONGSON] = "HDA Loongson",
353 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
356 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
357 static void set_default_power_save(struct azx *chip);
360 * initialize the PCI registers
362 /* update bits in a PCI register byte */
363 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
364 unsigned char mask, unsigned char val)
368 pci_read_config_byte(pci, reg, &data);
370 data |= (val & mask);
371 pci_write_config_byte(pci, reg, data);
374 static void azx_init_pci(struct azx *chip)
376 int snoop_type = azx_get_snoop_type(chip);
378 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
379 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
380 * Ensuring these bits are 0 clears playback static on some HD Audio
382 * The PCI register TCSEL is defined in the Intel manuals.
384 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
385 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
386 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
389 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
390 * we need to enable snoop.
392 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
393 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
395 update_pci_byte(chip->pci,
396 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
397 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
400 /* For NVIDIA HDA, enable snoop */
401 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
402 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
404 update_pci_byte(chip->pci,
405 NVIDIA_HDA_TRANSREG_ADDR,
406 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
407 update_pci_byte(chip->pci,
408 NVIDIA_HDA_ISTRM_COH,
409 0x01, NVIDIA_HDA_ENABLE_COHBIT);
410 update_pci_byte(chip->pci,
411 NVIDIA_HDA_OSTRM_COH,
412 0x01, NVIDIA_HDA_ENABLE_COHBIT);
415 /* Enable SCH/PCH snoop if needed */
416 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
417 unsigned short snoop;
418 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
419 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
420 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
421 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
422 if (!azx_snoop(chip))
423 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
424 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
425 pci_read_config_word(chip->pci,
426 INTEL_SCH_HDA_DEVC, &snoop);
428 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
429 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
430 "Disabled" : "Enabled");
435 * In BXT-P A0, HD-Audio DMA requests is later than expected,
436 * and makes an audio stream sensitive to system latencies when
437 * 24/32 bits are playing.
438 * Adjusting threshold of DMA fifo to force the DMA request
439 * sooner to improve latency tolerance at the expense of power.
441 static void bxt_reduce_dma_latency(struct azx *chip)
445 val = azx_readl(chip, VS_EM4L);
447 azx_writel(chip, VS_EM4L, val);
452 * bit 0: 6 MHz Supported
453 * bit 1: 12 MHz Supported
454 * bit 2: 24 MHz Supported
455 * bit 3: 48 MHz Supported
456 * bit 4: 96 MHz Supported
457 * bit 5: 192 MHz Supported
459 static int intel_get_lctl_scf(struct azx *chip)
461 struct hdac_bus *bus = azx_bus(chip);
462 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
466 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
468 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
469 t = preferred_bits[i];
474 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
478 static int intel_ml_lctl_set_power(struct azx *chip, int state)
480 struct hdac_bus *bus = azx_bus(chip);
485 * Changes to LCTL.SCF are only needed for the first multi-link dealing
486 * with external codecs
488 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
489 val &= ~AZX_ML_LCTL_SPA;
490 val |= state << AZX_ML_LCTL_SPA_SHIFT;
491 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
495 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
496 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
505 static void intel_init_lctl(struct azx *chip)
507 struct hdac_bus *bus = azx_bus(chip);
511 /* 0. check lctl register value is correct or not */
512 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
513 /* only perform additional configurations if the SCF is initially based on 6MHz */
514 if ((val & AZX_ML_LCTL_SCF) != 0)
518 * Before operating on SPA, CPA must match SPA.
519 * Any deviation may result in undefined behavior.
521 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
522 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
525 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
526 ret = intel_ml_lctl_set_power(chip, 0);
531 /* 2. update SCF to select an audio clock different from 6MHz */
532 val &= ~AZX_ML_LCTL_SCF;
533 val |= intel_get_lctl_scf(chip);
534 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
537 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
538 intel_ml_lctl_set_power(chip, 1);
542 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
544 struct hdac_bus *bus = azx_bus(chip);
545 struct pci_dev *pci = chip->pci;
548 snd_hdac_set_codec_wakeup(bus, true);
549 if (chip->driver_type == AZX_DRIVER_SKL) {
550 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
551 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
552 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
554 azx_init_chip(chip, full_reset);
555 if (chip->driver_type == AZX_DRIVER_SKL) {
556 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
557 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
558 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
561 snd_hdac_set_codec_wakeup(bus, false);
563 /* reduce dma latency to avoid noise */
564 if (HDA_CONTROLLER_IS_APL(pci))
565 bxt_reduce_dma_latency(chip);
567 if (bus->mlcap != NULL)
568 intel_init_lctl(chip);
571 /* calculate runtime delay from LPIB */
572 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
575 struct snd_pcm_substream *substream = azx_dev->core.substream;
576 int stream = substream->stream;
577 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
580 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
581 delay = pos - lpib_pos;
583 delay = lpib_pos - pos;
585 if (delay >= azx_dev->core.delay_negative_threshold)
588 delay += azx_dev->core.bufsize;
591 if (delay >= azx_dev->core.period_bytes) {
592 dev_info(chip->card->dev,
593 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
594 delay, azx_dev->core.period_bytes);
596 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
597 chip->get_delay[stream] = NULL;
600 return bytes_to_frames(substream->runtime, delay);
603 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
605 /* called from IRQ */
606 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
608 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
611 ok = azx_position_ok(chip, azx_dev);
613 azx_dev->irq_pending = 0;
615 } else if (ok == 0) {
616 /* bogus IRQ, process it later */
617 azx_dev->irq_pending = 1;
618 schedule_work(&hda->irq_pending_work);
623 #define display_power(chip, enable) \
624 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
627 * Check whether the current DMA position is acceptable for updating
628 * periods. Returns non-zero if it's OK.
630 * Many HD-audio controllers appear pretty inaccurate about
631 * the update-IRQ timing. The IRQ is issued before actually the
632 * data is processed. So, we need to process it afterwords in a
635 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
637 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
639 struct snd_pcm_substream *substream = azx_dev->core.substream;
640 struct snd_pcm_runtime *runtime = substream->runtime;
641 int stream = substream->stream;
644 snd_pcm_uframes_t hwptr, target;
647 * The value of the WALLCLK register is always 0
648 * on the Loongson controller, so we return directly.
650 if (chip->driver_type == AZX_DRIVER_LOONGSON)
653 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
654 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
655 return -1; /* bogus (too early) interrupt */
657 if (chip->get_position[stream])
658 pos = chip->get_position[stream](chip, azx_dev);
659 else { /* use the position buffer as default */
660 pos = azx_get_pos_posbuf(chip, azx_dev);
661 if (!pos || pos == (u32)-1) {
662 dev_info(chip->card->dev,
663 "Invalid position buffer, using LPIB read method instead.\n");
664 chip->get_position[stream] = azx_get_pos_lpib;
665 if (chip->get_position[0] == azx_get_pos_lpib &&
666 chip->get_position[1] == azx_get_pos_lpib)
667 azx_bus(chip)->use_posbuf = false;
668 pos = azx_get_pos_lpib(chip, azx_dev);
669 chip->get_delay[stream] = NULL;
671 chip->get_position[stream] = azx_get_pos_posbuf;
672 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
673 chip->get_delay[stream] = azx_get_delay_from_lpib;
677 if (pos >= azx_dev->core.bufsize)
680 if (WARN_ONCE(!azx_dev->core.period_bytes,
681 "hda-intel: zero azx_dev->period_bytes"))
682 return -1; /* this shouldn't happen! */
683 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
684 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
685 /* NG - it's below the first next period boundary */
686 return chip->bdl_pos_adj ? 0 : -1;
687 azx_dev->core.start_wallclk += wallclk;
689 if (azx_dev->core.no_period_wakeup)
690 return 1; /* OK, no need to check period boundary */
692 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
693 return 1; /* OK, already in hwptr updating process */
695 /* check whether the period gets really elapsed */
696 pos = bytes_to_frames(runtime, pos);
697 hwptr = runtime->hw_ptr_base + pos;
698 if (hwptr < runtime->status->hw_ptr)
699 hwptr += runtime->buffer_size;
700 target = runtime->hw_ptr_interrupt + runtime->period_size;
701 if (hwptr < target) {
702 /* too early wakeup, process it later */
703 return chip->bdl_pos_adj ? 0 : -1;
706 return 1; /* OK, it's fine */
710 * The work for pending PCM period updates.
712 static void azx_irq_pending_work(struct work_struct *work)
714 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
715 struct azx *chip = &hda->chip;
716 struct hdac_bus *bus = azx_bus(chip);
717 struct hdac_stream *s;
720 if (!hda->irq_pending_warned) {
721 dev_info(chip->card->dev,
722 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
724 hda->irq_pending_warned = 1;
729 spin_lock_irq(&bus->reg_lock);
730 list_for_each_entry(s, &bus->stream_list, list) {
731 struct azx_dev *azx_dev = stream_to_azx_dev(s);
732 if (!azx_dev->irq_pending ||
736 ok = azx_position_ok(chip, azx_dev);
738 azx_dev->irq_pending = 0;
739 spin_unlock(&bus->reg_lock);
740 snd_pcm_period_elapsed(s->substream);
741 spin_lock(&bus->reg_lock);
743 pending = 0; /* too early */
747 spin_unlock_irq(&bus->reg_lock);
754 /* clear irq_pending flags and assure no on-going workq */
755 static void azx_clear_irq_pending(struct azx *chip)
757 struct hdac_bus *bus = azx_bus(chip);
758 struct hdac_stream *s;
760 spin_lock_irq(&bus->reg_lock);
761 list_for_each_entry(s, &bus->stream_list, list) {
762 struct azx_dev *azx_dev = stream_to_azx_dev(s);
763 azx_dev->irq_pending = 0;
765 spin_unlock_irq(&bus->reg_lock);
768 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
770 struct hdac_bus *bus = azx_bus(chip);
772 if (request_irq(chip->pci->irq, azx_interrupt,
773 chip->msi ? 0 : IRQF_SHARED,
774 chip->card->irq_descr, chip)) {
775 dev_err(chip->card->dev,
776 "unable to grab IRQ %d, disabling device\n",
779 snd_card_disconnect(chip->card);
782 bus->irq = chip->pci->irq;
783 chip->card->sync_irq = bus->irq;
784 pci_intx(chip->pci, !chip->msi);
788 /* get the current DMA position with correction on VIA chips */
789 static unsigned int azx_via_get_position(struct azx *chip,
790 struct azx_dev *azx_dev)
792 unsigned int link_pos, mini_pos, bound_pos;
793 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
794 unsigned int fifo_size;
796 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
797 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
798 /* Playback, no problem using link position */
804 * use mod to get the DMA position just like old chipset
806 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
807 mod_dma_pos %= azx_dev->core.period_bytes;
809 fifo_size = azx_stream(azx_dev)->fifo_size;
811 if (azx_dev->insufficient) {
812 /* Link position never gather than FIFO size */
813 if (link_pos <= fifo_size)
816 azx_dev->insufficient = 0;
819 if (link_pos <= fifo_size)
820 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
822 mini_pos = link_pos - fifo_size;
824 /* Find nearest previous boudary */
825 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
826 mod_link_pos = link_pos % azx_dev->core.period_bytes;
827 if (mod_link_pos >= fifo_size)
828 bound_pos = link_pos - mod_link_pos;
829 else if (mod_dma_pos >= mod_mini_pos)
830 bound_pos = mini_pos - mod_mini_pos;
832 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
833 if (bound_pos >= azx_dev->core.bufsize)
837 /* Calculate real DMA position we want */
838 return bound_pos + mod_dma_pos;
841 #define AMD_FIFO_SIZE 32
843 /* get the current DMA position with FIFO size correction */
844 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
846 struct snd_pcm_substream *substream = azx_dev->core.substream;
847 struct snd_pcm_runtime *runtime = substream->runtime;
848 unsigned int pos, delay;
850 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
854 runtime->delay = AMD_FIFO_SIZE;
855 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
856 if (azx_dev->insufficient) {
859 runtime->delay = bytes_to_frames(runtime, pos);
861 azx_dev->insufficient = 0;
865 /* correct the DMA position for capture stream */
866 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
868 pos += azx_dev->core.bufsize;
875 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
878 struct snd_pcm_substream *substream = azx_dev->core.substream;
880 /* just read back the calculated value in the above */
881 return substream->runtime->delay;
884 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
887 if (!skip_link_reset)
888 azx_enter_link_reset(chip);
889 azx_clear_irq_pending(chip);
890 display_power(chip, false);
894 static DEFINE_MUTEX(card_list_lock);
895 static LIST_HEAD(card_list);
897 static void azx_shutdown_chip(struct azx *chip)
899 __azx_shutdown_chip(chip, false);
902 static void azx_add_card_list(struct azx *chip)
904 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
905 mutex_lock(&card_list_lock);
906 list_add(&hda->list, &card_list);
907 mutex_unlock(&card_list_lock);
910 static void azx_del_card_list(struct azx *chip)
912 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
913 mutex_lock(&card_list_lock);
914 list_del_init(&hda->list);
915 mutex_unlock(&card_list_lock);
918 /* trigger power-save check at writing parameter */
919 static int param_set_xint(const char *val, const struct kernel_param *kp)
921 struct hda_intel *hda;
923 int prev = power_save;
924 int ret = param_set_int(val, kp);
926 if (ret || prev == power_save)
929 mutex_lock(&card_list_lock);
930 list_for_each_entry(hda, &card_list, list) {
932 if (!hda->probe_continued || chip->disabled)
934 snd_hda_set_power_save(&chip->bus, power_save * 1000);
936 mutex_unlock(&card_list_lock);
943 static bool azx_is_pm_ready(struct snd_card *card)
946 struct hda_intel *hda;
950 chip = card->private_data;
951 hda = container_of(chip, struct hda_intel, chip);
952 if (chip->disabled || hda->init_failed || !chip->running)
957 static void __azx_runtime_resume(struct azx *chip)
959 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
960 struct hdac_bus *bus = azx_bus(chip);
961 struct hda_codec *codec;
964 display_power(chip, true);
965 if (hda->need_i915_power)
966 snd_hdac_i915_set_bclk(bus);
968 /* Read STATESTS before controller reset */
969 status = azx_readw(chip, STATESTS);
972 hda_intel_init_chip(chip, true);
974 /* Avoid codec resume if runtime resume is for system suspend */
975 if (!chip->pm_prepared) {
976 list_for_each_codec(codec, &chip->bus) {
977 if (codec->relaxed_resume)
980 if (codec->forced_resume || (status & (1 << codec->addr)))
981 pm_request_resume(hda_codec_dev(codec));
985 /* power down again for link-controlled chips */
986 if (!hda->need_i915_power)
987 display_power(chip, false);
990 #ifdef CONFIG_PM_SLEEP
991 static int azx_prepare(struct device *dev)
993 struct snd_card *card = dev_get_drvdata(dev);
996 if (!azx_is_pm_ready(card))
999 chip = card->private_data;
1000 chip->pm_prepared = 1;
1001 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1003 flush_work(&azx_bus(chip)->unsol_work);
1005 /* HDA controller always requires different WAKEEN for runtime suspend
1006 * and system suspend, so don't use direct-complete here.
1011 static void azx_complete(struct device *dev)
1013 struct snd_card *card = dev_get_drvdata(dev);
1016 if (!azx_is_pm_ready(card))
1019 chip = card->private_data;
1020 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1021 chip->pm_prepared = 0;
1024 static int azx_suspend(struct device *dev)
1026 struct snd_card *card = dev_get_drvdata(dev);
1028 struct hdac_bus *bus;
1030 if (!azx_is_pm_ready(card))
1033 chip = card->private_data;
1034 bus = azx_bus(chip);
1035 azx_shutdown_chip(chip);
1036 if (bus->irq >= 0) {
1037 free_irq(bus->irq, chip);
1039 chip->card->sync_irq = -1;
1043 pci_disable_msi(chip->pci);
1045 trace_azx_suspend(chip);
1049 static int azx_resume(struct device *dev)
1051 struct snd_card *card = dev_get_drvdata(dev);
1054 if (!azx_is_pm_ready(card))
1057 chip = card->private_data;
1059 if (pci_enable_msi(chip->pci) < 0)
1061 if (azx_acquire_irq(chip, 1) < 0)
1064 __azx_runtime_resume(chip);
1066 trace_azx_resume(chip);
1070 /* put codec down to D3 at hibernation for Intel SKL+;
1071 * otherwise BIOS may still access the codec and screw up the driver
1073 static int azx_freeze_noirq(struct device *dev)
1075 struct snd_card *card = dev_get_drvdata(dev);
1076 struct azx *chip = card->private_data;
1077 struct pci_dev *pci = to_pci_dev(dev);
1079 if (!azx_is_pm_ready(card))
1081 if (chip->driver_type == AZX_DRIVER_SKL)
1082 pci_set_power_state(pci, PCI_D3hot);
1087 static int azx_thaw_noirq(struct device *dev)
1089 struct snd_card *card = dev_get_drvdata(dev);
1090 struct azx *chip = card->private_data;
1091 struct pci_dev *pci = to_pci_dev(dev);
1093 if (!azx_is_pm_ready(card))
1095 if (chip->driver_type == AZX_DRIVER_SKL)
1096 pci_set_power_state(pci, PCI_D0);
1100 #endif /* CONFIG_PM_SLEEP */
1102 static int azx_runtime_suspend(struct device *dev)
1104 struct snd_card *card = dev_get_drvdata(dev);
1107 if (!azx_is_pm_ready(card))
1109 chip = card->private_data;
1111 /* enable controller wake up event */
1112 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1114 azx_shutdown_chip(chip);
1115 trace_azx_runtime_suspend(chip);
1119 static int azx_runtime_resume(struct device *dev)
1121 struct snd_card *card = dev_get_drvdata(dev);
1124 if (!azx_is_pm_ready(card))
1126 chip = card->private_data;
1127 __azx_runtime_resume(chip);
1129 /* disable controller Wake Up event*/
1130 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1132 trace_azx_runtime_resume(chip);
1136 static int azx_runtime_idle(struct device *dev)
1138 struct snd_card *card = dev_get_drvdata(dev);
1140 struct hda_intel *hda;
1145 chip = card->private_data;
1146 hda = container_of(chip, struct hda_intel, chip);
1147 if (chip->disabled || hda->init_failed)
1150 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1151 azx_bus(chip)->codec_powered || !chip->running)
1154 /* ELD notification gets broken when HD-audio bus is off */
1155 if (needs_eld_notify_link(chip))
1161 static const struct dev_pm_ops azx_pm = {
1162 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1163 #ifdef CONFIG_PM_SLEEP
1164 .prepare = azx_prepare,
1165 .complete = azx_complete,
1166 .freeze_noirq = azx_freeze_noirq,
1167 .thaw_noirq = azx_thaw_noirq,
1169 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1172 #define AZX_PM_OPS &azx_pm
1174 #define azx_add_card_list(chip) /* NOP */
1175 #define azx_del_card_list(chip) /* NOP */
1176 #define AZX_PM_OPS NULL
1177 #endif /* CONFIG_PM */
1180 static int azx_probe_continue(struct azx *chip);
1182 #ifdef SUPPORT_VGA_SWITCHEROO
1183 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1185 static void azx_vs_set_state(struct pci_dev *pci,
1186 enum vga_switcheroo_state state)
1188 struct snd_card *card = pci_get_drvdata(pci);
1189 struct azx *chip = card->private_data;
1190 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1191 struct hda_codec *codec;
1194 wait_for_completion(&hda->probe_wait);
1195 if (hda->init_failed)
1198 disabled = (state == VGA_SWITCHEROO_OFF);
1199 if (chip->disabled == disabled)
1202 if (!hda->probe_continued) {
1203 chip->disabled = disabled;
1205 dev_info(chip->card->dev,
1206 "Start delayed initialization\n");
1207 if (azx_probe_continue(chip) < 0)
1208 dev_err(chip->card->dev, "initialization error\n");
1211 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1212 disabled ? "Disabling" : "Enabling");
1214 list_for_each_codec(codec, &chip->bus) {
1215 pm_runtime_suspend(hda_codec_dev(codec));
1216 pm_runtime_disable(hda_codec_dev(codec));
1218 pm_runtime_suspend(card->dev);
1219 pm_runtime_disable(card->dev);
1220 /* when we get suspended by vga_switcheroo we end up in D3cold,
1221 * however we have no ACPI handle, so pci/acpi can't put us there,
1222 * put ourselves there */
1223 pci->current_state = PCI_D3cold;
1224 chip->disabled = true;
1225 if (snd_hda_lock_devices(&chip->bus))
1226 dev_warn(chip->card->dev,
1227 "Cannot lock devices!\n");
1229 snd_hda_unlock_devices(&chip->bus);
1230 chip->disabled = false;
1231 pm_runtime_enable(card->dev);
1232 list_for_each_codec(codec, &chip->bus) {
1233 pm_runtime_enable(hda_codec_dev(codec));
1234 pm_runtime_resume(hda_codec_dev(codec));
1240 static bool azx_vs_can_switch(struct pci_dev *pci)
1242 struct snd_card *card = pci_get_drvdata(pci);
1243 struct azx *chip = card->private_data;
1244 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1246 wait_for_completion(&hda->probe_wait);
1247 if (hda->init_failed)
1249 if (chip->disabled || !hda->probe_continued)
1251 if (snd_hda_lock_devices(&chip->bus))
1253 snd_hda_unlock_devices(&chip->bus);
1258 * The discrete GPU cannot power down unless the HDA controller runtime
1259 * suspends, so activate runtime PM on codecs even if power_save == 0.
1261 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1263 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1264 struct hda_codec *codec;
1266 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1267 list_for_each_codec(codec, &chip->bus)
1268 codec->auto_runtime_pm = 1;
1269 /* reset the power save setup */
1271 set_default_power_save(chip);
1275 static void azx_vs_gpu_bound(struct pci_dev *pci,
1276 enum vga_switcheroo_client_id client_id)
1278 struct snd_card *card = pci_get_drvdata(pci);
1279 struct azx *chip = card->private_data;
1281 if (client_id == VGA_SWITCHEROO_DIS)
1282 chip->bus.keep_power = 0;
1283 setup_vga_switcheroo_runtime_pm(chip);
1286 static void init_vga_switcheroo(struct azx *chip)
1288 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1289 struct pci_dev *p = get_bound_vga(chip->pci);
1290 struct pci_dev *parent;
1292 dev_info(chip->card->dev,
1293 "Handle vga_switcheroo audio client\n");
1294 hda->use_vga_switcheroo = 1;
1296 /* cleared in either gpu_bound op or codec probe, or when its
1297 * upstream port has _PR3 (i.e. dGPU).
1299 parent = pci_upstream_bridge(p);
1300 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1301 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1306 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1307 .set_gpu_state = azx_vs_set_state,
1308 .can_switch = azx_vs_can_switch,
1309 .gpu_bound = azx_vs_gpu_bound,
1312 static int register_vga_switcheroo(struct azx *chip)
1314 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1318 if (!hda->use_vga_switcheroo)
1321 p = get_bound_vga(chip->pci);
1322 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1327 hda->vga_switcheroo_registered = 1;
1332 #define init_vga_switcheroo(chip) /* NOP */
1333 #define register_vga_switcheroo(chip) 0
1334 #define check_hdmi_disabled(pci) false
1335 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1336 #endif /* SUPPORT_VGA_SWITCHER */
1341 static void azx_free(struct azx *chip)
1343 struct pci_dev *pci = chip->pci;
1344 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1345 struct hdac_bus *bus = azx_bus(chip);
1350 if (azx_has_pm_runtime(chip) && chip->running) {
1351 pm_runtime_get_noresume(&pci->dev);
1352 pm_runtime_forbid(&pci->dev);
1353 pm_runtime_dont_use_autosuspend(&pci->dev);
1358 azx_del_card_list(chip);
1360 hda->init_failed = 1; /* to be sure */
1361 complete_all(&hda->probe_wait);
1363 if (use_vga_switcheroo(hda)) {
1364 if (chip->disabled && hda->probe_continued)
1365 snd_hda_unlock_devices(&chip->bus);
1366 if (hda->vga_switcheroo_registered)
1367 vga_switcheroo_unregister_client(chip->pci);
1370 if (bus->chip_init) {
1371 azx_clear_irq_pending(chip);
1372 azx_stop_all_streams(chip);
1373 azx_stop_chip(chip);
1377 free_irq(bus->irq, (void*)chip);
1379 azx_free_stream_pages(chip);
1380 azx_free_streams(chip);
1381 snd_hdac_bus_exit(bus);
1383 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1384 release_firmware(chip->fw);
1386 display_power(chip, false);
1388 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1389 snd_hdac_i915_exit(bus);
1394 static int azx_dev_disconnect(struct snd_device *device)
1396 struct azx *chip = device->device_data;
1397 struct hdac_bus *bus = azx_bus(chip);
1399 chip->bus.shutdown = 1;
1400 cancel_work_sync(&bus->unsol_work);
1405 static int azx_dev_free(struct snd_device *device)
1407 azx_free(device->device_data);
1411 #ifdef SUPPORT_VGA_SWITCHEROO
1413 /* ATPX is in the integrated GPU's namespace */
1414 static bool atpx_present(void)
1416 struct pci_dev *pdev = NULL;
1417 acpi_handle dhandle, atpx_handle;
1420 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
1421 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
1422 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
1425 dhandle = ACPI_HANDLE(&pdev->dev);
1427 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1428 if (ACPI_SUCCESS(status)) {
1437 static bool atpx_present(void)
1444 * Check of disabled HDMI controller by vga_switcheroo
1446 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1450 /* check only discrete GPU */
1451 switch (pci->vendor) {
1452 case PCI_VENDOR_ID_ATI:
1453 case PCI_VENDOR_ID_AMD:
1454 if (pci->devfn == 1) {
1455 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1456 pci->bus->number, 0);
1458 /* ATPX is in the integrated GPU's ACPI namespace
1459 * rather than the dGPU's namespace. However,
1460 * the dGPU is the one who is involved in
1463 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1464 (atpx_present() || apple_gmux_detect(NULL, NULL)))
1470 case PCI_VENDOR_ID_NVIDIA:
1471 if (pci->devfn == 1) {
1472 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1473 pci->bus->number, 0);
1475 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1485 static bool check_hdmi_disabled(struct pci_dev *pci)
1487 bool vga_inactive = false;
1488 struct pci_dev *p = get_bound_vga(pci);
1491 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1492 vga_inactive = true;
1495 return vga_inactive;
1497 #endif /* SUPPORT_VGA_SWITCHEROO */
1500 * allow/deny-listing for position_fix
1502 static const struct snd_pci_quirk position_fix_list[] = {
1503 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1504 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1505 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1506 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1507 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1508 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1509 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1510 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1511 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1512 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1516 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1520 static int check_position_fix(struct azx *chip, int fix)
1522 const struct snd_pci_quirk *q;
1527 case POS_FIX_POSBUF:
1528 case POS_FIX_VIACOMBO:
1535 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1537 dev_info(chip->card->dev,
1538 "position_fix set to %d for device %04x:%04x\n",
1539 q->value, q->subvendor, q->subdevice);
1543 /* Check VIA/ATI HD Audio Controller exist */
1544 if (chip->driver_type == AZX_DRIVER_VIA) {
1545 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1546 return POS_FIX_VIACOMBO;
1548 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1549 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1550 return POS_FIX_FIFO;
1552 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1553 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1554 return POS_FIX_LPIB;
1556 if (chip->driver_type == AZX_DRIVER_SKL) {
1557 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1560 return POS_FIX_AUTO;
1563 static void assign_position_fix(struct azx *chip, int fix)
1565 static const azx_get_pos_callback_t callbacks[] = {
1566 [POS_FIX_AUTO] = NULL,
1567 [POS_FIX_LPIB] = azx_get_pos_lpib,
1568 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1569 [POS_FIX_VIACOMBO] = azx_via_get_position,
1570 [POS_FIX_COMBO] = azx_get_pos_lpib,
1571 [POS_FIX_SKL] = azx_get_pos_posbuf,
1572 [POS_FIX_FIFO] = azx_get_pos_fifo,
1575 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1577 /* combo mode uses LPIB only for playback */
1578 if (fix == POS_FIX_COMBO)
1579 chip->get_position[1] = NULL;
1581 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1582 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1583 chip->get_delay[0] = chip->get_delay[1] =
1584 azx_get_delay_from_lpib;
1587 if (fix == POS_FIX_FIFO)
1588 chip->get_delay[0] = chip->get_delay[1] =
1589 azx_get_delay_from_fifo;
1593 * deny-lists for probe_mask
1595 static const struct snd_pci_quirk probe_mask_list[] = {
1596 /* Thinkpad often breaks the controller communication when accessing
1597 * to the non-working (or non-existing) modem codec slot.
1599 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1600 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1601 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1603 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1604 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1605 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1606 /* forced codec slots */
1607 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1608 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1609 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1610 /* WinFast VP200 H (Teradici) user reported broken communication */
1611 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1615 #define AZX_FORCE_CODEC_MASK 0x100
1617 static void check_probe_mask(struct azx *chip, int dev)
1619 const struct snd_pci_quirk *q;
1621 chip->codec_probe_mask = probe_mask[dev];
1622 if (chip->codec_probe_mask == -1) {
1623 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1625 dev_info(chip->card->dev,
1626 "probe_mask set to 0x%x for device %04x:%04x\n",
1627 q->value, q->subvendor, q->subdevice);
1628 chip->codec_probe_mask = q->value;
1632 /* check forced option */
1633 if (chip->codec_probe_mask != -1 &&
1634 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1635 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1636 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1637 (int)azx_bus(chip)->codec_mask);
1642 * allow/deny-list for enable_msi
1644 static const struct snd_pci_quirk msi_deny_list[] = {
1645 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1646 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1647 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1648 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1649 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1650 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1651 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1652 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1653 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1654 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1658 static void check_msi(struct azx *chip)
1660 const struct snd_pci_quirk *q;
1662 if (enable_msi >= 0) {
1663 chip->msi = !!enable_msi;
1666 chip->msi = 1; /* enable MSI as default */
1667 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1669 dev_info(chip->card->dev,
1670 "msi for device %04x:%04x set to %d\n",
1671 q->subvendor, q->subdevice, q->value);
1672 chip->msi = q->value;
1676 /* NVidia chipsets seem to cause troubles with MSI */
1677 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1678 dev_info(chip->card->dev, "Disabling MSI\n");
1683 /* check the snoop mode availability */
1684 static void azx_check_snoop_available(struct azx *chip)
1686 int snoop = hda_snoop;
1689 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1690 snoop ? "snoop" : "non-snoop");
1691 chip->snoop = snoop;
1692 chip->uc_buffer = !snoop;
1697 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1698 chip->driver_type == AZX_DRIVER_VIA) {
1699 /* force to non-snoop mode for a new VIA controller
1703 pci_read_config_byte(chip->pci, 0x42, &val);
1704 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1705 chip->pci->revision == 0x20))
1709 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1712 chip->snoop = snoop;
1714 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1715 /* C-Media requires non-cached pages only for CORB/RIRB */
1716 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1717 chip->uc_buffer = true;
1721 static void azx_probe_work(struct work_struct *work)
1723 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1724 azx_probe_continue(&hda->chip);
1727 static int default_bdl_pos_adj(struct azx *chip)
1729 /* some exceptions: Atoms seem problematic with value 1 */
1730 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1731 switch (chip->pci->device) {
1732 case 0x0f04: /* Baytrail */
1733 case 0x2284: /* Braswell */
1738 switch (chip->driver_type) {
1740 * increase the bdl size for Glenfly Gpus for hardware
1741 * limitation on hdac interrupt interval
1743 case AZX_DRIVER_GFHDMI:
1745 case AZX_DRIVER_ICH:
1746 case AZX_DRIVER_PCH:
1756 static const struct hda_controller_ops pci_hda_ops;
1758 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1759 int dev, unsigned int driver_caps,
1762 static const struct snd_device_ops ops = {
1763 .dev_disconnect = azx_dev_disconnect,
1764 .dev_free = azx_dev_free,
1766 struct hda_intel *hda;
1772 err = pcim_enable_device(pci);
1776 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1781 mutex_init(&chip->open_mutex);
1784 chip->ops = &pci_hda_ops;
1785 chip->driver_caps = driver_caps;
1786 chip->driver_type = driver_caps & 0xff;
1788 chip->dev_index = dev;
1789 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1790 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1791 INIT_LIST_HEAD(&chip->pcm_list);
1792 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1793 INIT_LIST_HEAD(&hda->list);
1794 init_vga_switcheroo(chip);
1795 init_completion(&hda->probe_wait);
1797 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1799 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1800 chip->fallback_to_single_cmd = 1;
1801 else /* explicitly set to single_cmd or not */
1802 chip->single_cmd = single_cmd;
1804 azx_check_snoop_available(chip);
1806 if (bdl_pos_adj[dev] < 0)
1807 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1809 chip->bdl_pos_adj = bdl_pos_adj[dev];
1811 err = azx_bus_init(chip, model[dev]);
1815 /* use the non-cached pages in non-snoop mode */
1816 if (!azx_snoop(chip))
1817 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG;
1819 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1820 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1821 chip->bus.core.needs_damn_long_delay = 1;
1824 check_probe_mask(chip, dev);
1826 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1828 dev_err(card->dev, "Error creating device [card]!\n");
1833 /* continue probing in work context as may trigger request module */
1834 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1841 static int azx_first_init(struct azx *chip)
1843 int dev = chip->dev_index;
1844 struct pci_dev *pci = chip->pci;
1845 struct snd_card *card = chip->card;
1846 struct hdac_bus *bus = azx_bus(chip);
1848 unsigned short gcap;
1849 unsigned int dma_bits = 64;
1851 #if BITS_PER_LONG != 64
1852 /* Fix up base address on ULI M5461 */
1853 if (chip->driver_type == AZX_DRIVER_ULI) {
1855 pci_read_config_word(pci, 0x40, &tmp3);
1856 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1857 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1861 * Fix response write request not synced to memory when handle
1862 * hdac interrupt on Glenfly Gpus
1864 if (chip->driver_type == AZX_DRIVER_GFHDMI)
1865 bus->polling_mode = 1;
1867 if (chip->driver_type == AZX_DRIVER_LOONGSON) {
1868 bus->polling_mode = 1;
1869 bus->not_use_interrupts = 1;
1870 bus->access_sdnctl_in_dword = 1;
1873 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
1877 bus->addr = pci_resource_start(pci, 0);
1878 bus->remap_addr = pcim_iomap_table(pci)[0];
1880 if (chip->driver_type == AZX_DRIVER_SKL)
1881 snd_hdac_bus_parse_capabilities(bus);
1884 * Some Intel CPUs has always running timer (ART) feature and
1885 * controller may have Global time sync reporting capability, so
1886 * check both of these before declaring synchronized time reporting
1887 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1889 chip->gts_present = false;
1892 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1893 chip->gts_present = true;
1897 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1898 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1899 pci->no_64bit_msi = true;
1901 if (pci_enable_msi(pci) < 0)
1905 pci_set_master(pci);
1907 gcap = azx_readw(chip, GCAP);
1908 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1910 /* AMD devices support 40 or 48bit DMA, take the safe one */
1911 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1914 /* disable SB600 64bit support for safety */
1915 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1916 struct pci_dev *p_smbus;
1918 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1919 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1922 if (p_smbus->revision < 0x30)
1923 gcap &= ~AZX_GCAP_64OK;
1924 pci_dev_put(p_smbus);
1928 /* NVidia hardware normally only supports up to 40 bits of DMA */
1929 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1932 /* disable 64bit DMA address on some devices */
1933 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1934 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1935 gcap &= ~AZX_GCAP_64OK;
1938 /* disable buffer size rounding to 128-byte multiples if supported */
1939 if (align_buffer_size >= 0)
1940 chip->align_buffer_size = !!align_buffer_size;
1942 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1943 chip->align_buffer_size = 0;
1945 chip->align_buffer_size = 1;
1948 /* allow 64bit DMA address if supported by H/W */
1949 if (!(gcap & AZX_GCAP_64OK))
1951 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1952 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1953 dma_set_max_seg_size(&pci->dev, UINT_MAX);
1955 /* read number of streams from GCAP register instead of using
1958 chip->capture_streams = (gcap >> 8) & 0x0f;
1959 chip->playback_streams = (gcap >> 12) & 0x0f;
1960 if (!chip->playback_streams && !chip->capture_streams) {
1961 /* gcap didn't give any info, switching to old method */
1963 switch (chip->driver_type) {
1964 case AZX_DRIVER_ULI:
1965 chip->playback_streams = ULI_NUM_PLAYBACK;
1966 chip->capture_streams = ULI_NUM_CAPTURE;
1968 case AZX_DRIVER_ATIHDMI:
1969 case AZX_DRIVER_ATIHDMI_NS:
1970 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1971 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1973 case AZX_DRIVER_GFHDMI:
1974 case AZX_DRIVER_GENERIC:
1976 chip->playback_streams = ICH6_NUM_PLAYBACK;
1977 chip->capture_streams = ICH6_NUM_CAPTURE;
1981 chip->capture_index_offset = 0;
1982 chip->playback_index_offset = chip->capture_streams;
1983 chip->num_streams = chip->playback_streams + chip->capture_streams;
1985 /* sanity check for the SDxCTL.STRM field overflow */
1986 if (chip->num_streams > 15 &&
1987 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1988 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1989 "forcing separate stream tags", chip->num_streams);
1990 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1993 /* initialize streams */
1994 err = azx_init_streams(chip);
1998 err = azx_alloc_stream_pages(chip);
2002 /* initialize chip */
2005 snd_hdac_i915_set_bclk(bus);
2007 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
2009 /* codec detection */
2010 if (!azx_bus(chip)->codec_mask) {
2011 dev_err(card->dev, "no codecs found!\n");
2012 /* keep running the rest for the runtime PM */
2015 if (azx_acquire_irq(chip, 0) < 0)
2018 strcpy(card->driver, "HDA-Intel");
2019 strscpy(card->shortname, driver_short_names[chip->driver_type],
2020 sizeof(card->shortname));
2021 snprintf(card->longname, sizeof(card->longname),
2022 "%s at 0x%lx irq %i",
2023 card->shortname, bus->addr, bus->irq);
2028 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2029 /* callback from request_firmware_nowait() */
2030 static void azx_firmware_cb(const struct firmware *fw, void *context)
2032 struct snd_card *card = context;
2033 struct azx *chip = card->private_data;
2038 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2039 if (!chip->disabled) {
2040 /* continue probing */
2041 azx_probe_continue(chip);
2046 static int disable_msi_reset_irq(struct azx *chip)
2048 struct hdac_bus *bus = azx_bus(chip);
2051 free_irq(bus->irq, chip);
2053 chip->card->sync_irq = -1;
2054 pci_disable_msi(chip->pci);
2056 err = azx_acquire_irq(chip, 1);
2063 /* Denylist for skipping the whole probe:
2064 * some HD-audio PCI entries are exposed without any codecs, and such devices
2065 * should be ignored from the beginning.
2067 static const struct pci_device_id driver_denylist[] = {
2068 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2069 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2070 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2071 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */
2075 static const struct hda_controller_ops pci_hda_ops = {
2076 .disable_msi_reset_irq = disable_msi_reset_irq,
2077 .position_check = azx_position_check,
2080 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2082 static int azx_probe(struct pci_dev *pci,
2083 const struct pci_device_id *pci_id)
2085 struct snd_card *card;
2086 struct hda_intel *hda;
2088 bool schedule_probe;
2092 if (pci_match_id(driver_denylist, pci)) {
2093 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2097 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
2098 if (dev >= SNDRV_CARDS)
2101 set_bit(dev, probed_devs);
2106 * stop probe if another Intel's DSP driver should be activated
2109 err = snd_intel_dsp_driver_probe(pci);
2110 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2111 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2115 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2118 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2121 dev_err(&pci->dev, "Error creating card!\n");
2125 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2128 card->private_data = chip;
2129 hda = container_of(chip, struct hda_intel, chip);
2131 pci_set_drvdata(pci, card);
2133 #ifdef CONFIG_SND_HDA_I915
2134 /* bind with i915 if needed */
2135 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2136 err = snd_hdac_i915_init(azx_bus(chip));
2138 /* if the controller is bound only with HDMI/DP
2139 * (for HSW and BDW), we need to abort the probe;
2140 * for other chips, still continue probing as other
2141 * codecs can be on the same link.
2143 if (HDA_CONTROLLER_IN_GPU(pci)) {
2144 dev_err_probe(card->dev, err,
2145 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2149 /* don't bother any longer */
2150 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2154 /* HSW/BDW controllers need this power */
2155 if (HDA_CONTROLLER_IN_GPU(pci))
2156 hda->need_i915_power = true;
2159 if (HDA_CONTROLLER_IN_GPU(pci))
2160 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2163 err = register_vga_switcheroo(chip);
2165 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2169 if (check_hdmi_disabled(pci)) {
2170 dev_info(card->dev, "VGA controller is disabled\n");
2171 dev_info(card->dev, "Delaying initialization\n");
2172 chip->disabled = true;
2175 schedule_probe = !chip->disabled;
2177 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2178 if (patch[dev] && *patch[dev]) {
2179 dev_info(card->dev, "Applying patch firmware '%s'\n",
2181 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2182 &pci->dev, GFP_KERNEL, card,
2186 schedule_probe = false; /* continued in azx_firmware_cb() */
2188 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2191 schedule_delayed_work(&hda->probe_work, 0);
2193 set_bit(dev, probed_devs);
2195 complete_all(&hda->probe_wait);
2199 pci_set_drvdata(pci, NULL);
2200 snd_card_free(card);
2205 /* On some boards setting power_save to a non 0 value leads to clicking /
2206 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2207 * figure out how to avoid these sounds, but that is not always feasible.
2208 * So we keep a list of devices where we disable powersaving as its known
2209 * to causes problems on these devices.
2211 static const struct snd_pci_quirk power_save_denylist[] = {
2212 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2213 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2214 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2215 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2216 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2217 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2218 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2219 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2220 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2221 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2222 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2223 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2224 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2225 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2226 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2227 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2228 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2229 /* https://bugs.launchpad.net/bugs/1821663 */
2230 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2231 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2232 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2233 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2234 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2235 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
2236 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2237 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2238 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2239 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2240 /* https://bugs.launchpad.net/bugs/1821663 */
2241 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2244 #endif /* CONFIG_PM */
2246 static void set_default_power_save(struct azx *chip)
2248 int val = power_save;
2252 const struct snd_pci_quirk *q;
2254 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2256 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2257 q->subvendor, q->subdevice);
2261 #endif /* CONFIG_PM */
2262 snd_hda_set_power_save(&chip->bus, val * 1000);
2265 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2266 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2267 [AZX_DRIVER_NVIDIA] = 8,
2268 [AZX_DRIVER_TERA] = 1,
2271 static int azx_probe_continue(struct azx *chip)
2273 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2274 struct hdac_bus *bus = azx_bus(chip);
2275 struct pci_dev *pci = chip->pci;
2276 int dev = chip->dev_index;
2279 if (chip->disabled || hda->init_failed)
2281 if (hda->probe_retry)
2284 to_hda_bus(bus)->bus_probing = 1;
2285 hda->probe_continued = 1;
2287 /* Request display power well for the HDA controller or codec. For
2288 * Haswell/Broadwell, both the display HDA controller and codec need
2289 * this power. For other platforms, like Baytrail/Braswell, only the
2290 * display codec needs the power and it can be released after probe.
2292 display_power(chip, true);
2294 err = azx_first_init(chip);
2298 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2299 chip->beep_mode = beep_mode[dev];
2302 chip->ctl_dev_id = ctl_dev_id;
2304 /* create codec instances */
2305 if (bus->codec_mask) {
2306 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2311 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2313 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2318 release_firmware(chip->fw); /* no longer needed */
2325 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2326 err = azx_codec_configure(chip);
2328 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2329 ++hda->probe_retry < 60) {
2330 schedule_delayed_work(&hda->probe_work,
2331 msecs_to_jiffies(1000));
2332 return 0; /* keep things up */
2334 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2339 err = snd_card_register(chip->card);
2343 setup_vga_switcheroo_runtime_pm(chip);
2346 azx_add_card_list(chip);
2348 set_default_power_save(chip);
2350 if (azx_has_pm_runtime(chip)) {
2351 pm_runtime_use_autosuspend(&pci->dev);
2352 pm_runtime_allow(&pci->dev);
2353 pm_runtime_put_autosuspend(&pci->dev);
2358 pci_set_drvdata(pci, NULL);
2359 snd_card_free(chip->card);
2363 if (!hda->need_i915_power)
2364 display_power(chip, false);
2365 complete_all(&hda->probe_wait);
2366 to_hda_bus(bus)->bus_probing = 0;
2367 hda->probe_retry = 0;
2371 static void azx_remove(struct pci_dev *pci)
2373 struct snd_card *card = pci_get_drvdata(pci);
2375 struct hda_intel *hda;
2378 /* cancel the pending probing work */
2379 chip = card->private_data;
2380 hda = container_of(chip, struct hda_intel, chip);
2381 /* FIXME: below is an ugly workaround.
2382 * Both device_release_driver() and driver_probe_device()
2383 * take *both* the device's and its parent's lock before
2384 * calling the remove() and probe() callbacks. The codec
2385 * probe takes the locks of both the codec itself and its
2386 * parent, i.e. the PCI controller dev. Meanwhile, when
2387 * the PCI controller is unbound, it takes its lock, too
2388 * ==> ouch, a deadlock!
2389 * As a workaround, we unlock temporarily here the controller
2390 * device during cancel_work_sync() call.
2392 device_unlock(&pci->dev);
2393 cancel_delayed_work_sync(&hda->probe_work);
2394 device_lock(&pci->dev);
2396 clear_bit(chip->dev_index, probed_devs);
2397 pci_set_drvdata(pci, NULL);
2398 snd_card_free(card);
2402 static void azx_shutdown(struct pci_dev *pci)
2404 struct snd_card *card = pci_get_drvdata(pci);
2409 chip = card->private_data;
2410 if (chip && chip->running)
2411 __azx_shutdown_chip(chip, true);
2415 static const struct pci_device_id azx_ids[] = {
2417 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2419 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2421 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2423 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2425 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2427 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2428 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2430 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2431 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) },
2433 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2435 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2436 /* Wildcat Point-LP */
2437 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) },
2438 /* Skylake (Sunrise Point) */
2439 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2440 /* Skylake-LP (Sunrise Point-LP) */
2441 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2443 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2445 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2447 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2449 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2451 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2453 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2455 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2456 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2458 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2460 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2462 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2464 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2466 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2467 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2469 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2471 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2473 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2475 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2476 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2477 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2479 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2481 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2482 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2483 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2485 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2487 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2489 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2490 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2492 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2493 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2494 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2495 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2496 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2497 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2499 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2501 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) },
2502 /* Apollolake (Broxton-P) */
2503 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2505 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) },
2507 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2508 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2509 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) },
2511 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) },
2513 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2514 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) },
2516 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2517 AZX_DCAPS_POSFIX_LPIB) },
2519 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) },
2521 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) },
2523 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) },
2525 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2527 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2529 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2531 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2533 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2535 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2537 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2539 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) },
2541 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2542 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2543 .class_mask = 0xffffff,
2544 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2545 /* ATI SB 450/600/700/800/900 */
2546 { PCI_VDEVICE(ATI, 0x437b),
2547 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2548 { PCI_VDEVICE(ATI, 0x4383),
2549 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2551 { PCI_VDEVICE(AMD, 0x780d),
2552 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2553 /* AMD, X370 & co */
2554 { PCI_VDEVICE(AMD, 0x1457),
2555 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2556 /* AMD, X570 & co */
2557 { PCI_VDEVICE(AMD, 0x1487),
2558 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2560 { PCI_VDEVICE(AMD, 0x157a),
2561 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2562 AZX_DCAPS_PM_RUNTIME },
2564 { PCI_VDEVICE(AMD, 0x15e3),
2565 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2567 { PCI_VDEVICE(ATI, 0x0002),
2568 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2569 AZX_DCAPS_PM_RUNTIME },
2570 { PCI_VDEVICE(ATI, 0x1308),
2571 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2572 { PCI_VDEVICE(ATI, 0x157a),
2573 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2574 { PCI_VDEVICE(ATI, 0x15b3),
2575 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2576 { PCI_VDEVICE(ATI, 0x793b),
2577 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2578 { PCI_VDEVICE(ATI, 0x7919),
2579 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2580 { PCI_VDEVICE(ATI, 0x960f),
2581 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2582 { PCI_VDEVICE(ATI, 0x970f),
2583 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2584 { PCI_VDEVICE(ATI, 0x9840),
2585 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2586 { PCI_VDEVICE(ATI, 0xaa00),
2587 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2588 { PCI_VDEVICE(ATI, 0xaa08),
2589 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2590 { PCI_VDEVICE(ATI, 0xaa10),
2591 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2592 { PCI_VDEVICE(ATI, 0xaa18),
2593 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2594 { PCI_VDEVICE(ATI, 0xaa20),
2595 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2596 { PCI_VDEVICE(ATI, 0xaa28),
2597 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2598 { PCI_VDEVICE(ATI, 0xaa30),
2599 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2600 { PCI_VDEVICE(ATI, 0xaa38),
2601 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2602 { PCI_VDEVICE(ATI, 0xaa40),
2603 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2604 { PCI_VDEVICE(ATI, 0xaa48),
2605 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2606 { PCI_VDEVICE(ATI, 0xaa50),
2607 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2608 { PCI_VDEVICE(ATI, 0xaa58),
2609 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2610 { PCI_VDEVICE(ATI, 0xaa60),
2611 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2612 { PCI_VDEVICE(ATI, 0xaa68),
2613 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2614 { PCI_VDEVICE(ATI, 0xaa80),
2615 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2616 { PCI_VDEVICE(ATI, 0xaa88),
2617 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2618 { PCI_VDEVICE(ATI, 0xaa90),
2619 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2620 { PCI_VDEVICE(ATI, 0xaa98),
2621 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2622 { PCI_VDEVICE(ATI, 0x9902),
2623 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2624 { PCI_VDEVICE(ATI, 0xaaa0),
2625 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2626 { PCI_VDEVICE(ATI, 0xaaa8),
2627 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2628 { PCI_VDEVICE(ATI, 0xaab0),
2629 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2630 { PCI_VDEVICE(ATI, 0xaac0),
2631 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2632 AZX_DCAPS_PM_RUNTIME },
2633 { PCI_VDEVICE(ATI, 0xaac8),
2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2635 AZX_DCAPS_PM_RUNTIME },
2636 { PCI_VDEVICE(ATI, 0xaad8),
2637 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2638 AZX_DCAPS_PM_RUNTIME },
2639 { PCI_VDEVICE(ATI, 0xaae0),
2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2641 AZX_DCAPS_PM_RUNTIME },
2642 { PCI_VDEVICE(ATI, 0xaae8),
2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2644 AZX_DCAPS_PM_RUNTIME },
2645 { PCI_VDEVICE(ATI, 0xaaf0),
2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2647 AZX_DCAPS_PM_RUNTIME },
2648 { PCI_VDEVICE(ATI, 0xaaf8),
2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2650 AZX_DCAPS_PM_RUNTIME },
2651 { PCI_VDEVICE(ATI, 0xab00),
2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2653 AZX_DCAPS_PM_RUNTIME },
2654 { PCI_VDEVICE(ATI, 0xab08),
2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2656 AZX_DCAPS_PM_RUNTIME },
2657 { PCI_VDEVICE(ATI, 0xab10),
2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2659 AZX_DCAPS_PM_RUNTIME },
2660 { PCI_VDEVICE(ATI, 0xab18),
2661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2662 AZX_DCAPS_PM_RUNTIME },
2663 { PCI_VDEVICE(ATI, 0xab20),
2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2665 AZX_DCAPS_PM_RUNTIME },
2666 { PCI_VDEVICE(ATI, 0xab28),
2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2668 AZX_DCAPS_PM_RUNTIME },
2669 { PCI_VDEVICE(ATI, 0xab30),
2670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2671 AZX_DCAPS_PM_RUNTIME },
2672 { PCI_VDEVICE(ATI, 0xab38),
2673 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2674 AZX_DCAPS_PM_RUNTIME },
2676 { PCI_DEVICE(0x6766, PCI_ANY_ID),
2677 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2678 .class_mask = 0xffffff,
2679 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB |
2680 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT },
2681 /* VIA VT8251/VT8237A */
2682 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA },
2683 /* VIA GFX VT7122/VX900 */
2684 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2685 /* VIA GFX VT6122/VX11 */
2686 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2688 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS },
2690 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI },
2692 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2693 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2694 .class_mask = 0xffffff,
2695 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2697 { PCI_DEVICE(0x6549, 0x1200),
2698 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2699 { PCI_DEVICE(0x6549, 0x2200),
2700 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2701 /* Creative X-Fi (CA0110-IBG) */
2703 { PCI_VDEVICE(CREATIVE, 0x0010),
2704 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2705 { PCI_VDEVICE(CREATIVE, 0x0012),
2706 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2707 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2708 /* the following entry conflicts with snd-ctxfi driver,
2709 * as ctxfi driver mutates from HD-audio to native mode with
2710 * a special command sequence.
2712 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2713 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2714 .class_mask = 0xffffff,
2715 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2716 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2718 /* this entry seems still valid -- i.e. without emu20kx chip */
2719 { PCI_VDEVICE(CREATIVE, 0x0009),
2720 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2721 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2724 { PCI_VDEVICE(CMEDIA, 0x5011),
2725 .driver_data = AZX_DRIVER_CMEDIA |
2726 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2728 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2729 /* VMware HDAudio */
2730 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2731 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2732 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2733 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2734 .class_mask = 0xffffff,
2735 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2736 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2737 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2738 .class_mask = 0xffffff,
2739 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2741 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2742 /* Loongson HDAudio*/
2743 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA),
2744 .driver_data = AZX_DRIVER_LOONGSON },
2745 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI),
2746 .driver_data = AZX_DRIVER_LOONGSON },
2749 MODULE_DEVICE_TABLE(pci, azx_ids);
2751 /* pci_driver definition */
2752 static struct pci_driver azx_driver = {
2753 .name = KBUILD_MODNAME,
2754 .id_table = azx_ids,
2756 .remove = azx_remove,
2757 .shutdown = azx_shutdown,
2763 module_pci_driver(azx_driver);