1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Abramo Bagnara <abramo@alsa-project.org>
6 * Routines for control of Cirrus Logic CS461x chips
9 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
10 * and the SPDIF get somewhat "distorcionated", or/and left right channel
11 * are swapped. To get around this problem when it happens, mute and unmute
12 * the SPDIF input mixer control.
13 * - On the Hercules Game Theater XP the amplifier are sometimes turned
14 * off on inadecuate moments which causes distorcions on sound.
17 * - Secondary CODEC on some soundcards
18 * - SPDIF input support for other sample rates then 48khz
19 * - Posibility to mix the SPDIF output with analog sources.
20 * - PCM channels for Center and LFE on secondary codec
22 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
23 * is default configuration), no SPDIF, no secondary codec, no
24 * multi channel PCM. But known to work.
26 * FINALLY: A credit to the developers Tom and Jordan
27 * at Cirrus for have helping me out with the DSP, however we
28 * still don't have sufficient documentation and technical
29 * references to be able to implement all fancy feutures
30 * supported by the cs46xx DSP's.
31 * Benny <benny@hostmobility.com>
34 #include <linux/delay.h>
35 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/interrupt.h>
39 #include <linux/slab.h>
40 #include <linux/gameport.h>
41 #include <linux/mutex.h>
42 #include <linux/export.h>
43 #include <linux/module.h>
44 #include <linux/firmware.h>
45 #include <linux/vmalloc.h>
48 #include <sound/core.h>
49 #include <sound/control.h>
50 #include <sound/info.h>
51 #include <sound/pcm.h>
52 #include <sound/pcm_params.h>
55 #include "cs46xx_lib.h"
58 static void amp_voyetra(struct snd_cs46xx *chip, int change);
60 #ifdef CONFIG_SND_CS46XX_NEW_DSP
61 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
62 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
63 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
64 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
65 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
66 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
69 static const struct snd_pcm_ops snd_cs46xx_playback_ops;
70 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
71 static const struct snd_pcm_ops snd_cs46xx_capture_ops;
72 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
74 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
79 unsigned short result,tmp;
82 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
83 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
86 chip->active_ctrl(chip, 1);
88 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
89 offset = CS46XX_SECONDARY_CODEC_OFFSET;
92 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
93 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
94 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
95 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
96 * 5. if DCV not cleared, break and return error
97 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
103 if ((tmp & ACCTL_VFRM) == 0) {
104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
113 * Setup the AC97 control registers on the CS461x to send the
114 * appropriate command to the AC97 to perform the read.
115 * ACCAD = Command Address Register = 46Ch
116 * ACCDA = Command Data Register = 470h
117 * ACCTL = Control Register = 460h
118 * set DCV - will clear when process completed
119 * set CRW - Read command
120 * set VFRM - valid frame enabled
121 * set ESYN - ASYNC generation enabled
122 * set RSTN - ARST# inactive, AC97 codec not reset
125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
127 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
129 ACCTL_VFRM | ACCTL_ESYN |
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
132 ACCTL_VFRM | ACCTL_ESYN |
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
136 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
141 * Wait for the read to occur.
143 for (count = 0; count < 1000; count++) {
145 * First, we want to wait for a short time.
149 * Now, check to see if the read has completed.
150 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
156 dev_err(chip->card->dev,
157 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
163 * Wait for the valid status bit to go active.
165 for (count = 0; count < 100; count++) {
167 * Read the AC97 status register.
168 * ACSTS = Status Register = 464h
169 * VSTS - Valid Status
171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
176 dev_err(chip->card->dev,
177 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
184 * Read the data returned from the AC97 register.
185 * ACSDA = Status Data Register = 474h
188 dev_dbg(chip->card->dev,
189 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
190 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
191 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
197 chip->active_ctrl(chip, -1);
201 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
204 struct snd_cs46xx *chip = ac97->private_data;
206 int codec_index = ac97->num;
208 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
209 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
212 val = snd_cs46xx_codec_read(chip, reg, codec_index);
218 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
225 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
226 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
229 chip->active_ctrl(chip, 1);
232 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
233 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
234 * 3. Write ACCTL = Control Register = 460h for initiating the write
235 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
236 * 5. if DCV not cleared, break and return error
240 * Setup the AC97 control registers on the CS461x to send the
241 * appropriate command to the AC97 to perform the read.
242 * ACCAD = Command Address Register = 46Ch
243 * ACCDA = Command Data Register = 470h
244 * ACCTL = Control Register = 460h
245 * set DCV - will clear when process completed
246 * reset CRW - Write command
247 * set VFRM - valid frame enabled
248 * set ESYN - ASYNC generation enabled
249 * set RSTN - ARST# inactive, AC97 codec not reset
251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
253 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
255 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
257 ACCTL_ESYN | ACCTL_RSTN);
258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
259 ACCTL_ESYN | ACCTL_RSTN);
261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
262 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
265 for (count = 0; count < 4000; count++) {
267 * First, we want to wait for a short time.
271 * Now, check to see if the write has completed.
272 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
278 dev_err(chip->card->dev,
279 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
280 codec_index, reg, val);
282 chip->active_ctrl(chip, -1);
285 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
289 struct snd_cs46xx *chip = ac97->private_data;
290 int codec_index = ac97->num;
292 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
293 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
296 snd_cs46xx_codec_write(chip, reg, val, codec_index);
301 * Chip initialization
304 int snd_cs46xx_download(struct snd_cs46xx *chip,
306 unsigned long offset,
310 unsigned int bank = offset >> 16;
311 offset = offset & 0xffff;
313 if (snd_BUG_ON((offset & 3) || (len & 3)))
315 dst = chip->region.idx[bank+1].remap_addr + offset;
318 /* writel already converts 32-bit value to right endianess */
326 static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
328 #ifdef __LITTLE_ENDIAN
329 memcpy(dst, src, len);
332 const __le32 *_src = src;
335 *_dst++ = le32_to_cpu(*_src++);
339 #ifdef CONFIG_SND_CS46XX_NEW_DSP
341 static const char *module_names[CS46XX_DSP_MODULES] = {
342 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
345 MODULE_FIRMWARE("cs46xx/cwc4630");
346 MODULE_FIRMWARE("cs46xx/cwcasync");
347 MODULE_FIRMWARE("cs46xx/cwcsnoop");
348 MODULE_FIRMWARE("cs46xx/cwcbinhack");
349 MODULE_FIRMWARE("cs46xx/cwcdma");
351 static void free_module_desc(struct dsp_module_desc *module)
355 kfree(module->module_name);
356 kfree(module->symbol_table.symbols);
357 if (module->segments) {
359 for (i = 0; i < module->nsegments; i++)
360 kfree(module->segments[i].data);
361 kfree(module->segments);
366 /* firmware binary format:
370 * char symbol_name[DSP_MAX_SYMBOL_NAME];
372 * } symbols[nsymbols];
379 * } segments[nsegments];
382 static int load_firmware(struct snd_cs46xx *chip,
383 struct dsp_module_desc **module_ret,
387 unsigned int nums, fwlen, fwsize;
389 struct dsp_module_desc *module = NULL;
390 const struct firmware *fw;
393 sprintf(fw_path, "cs46xx/%s", fw_name);
394 err = request_firmware(&fw, fw_path, &chip->pci->dev);
397 fwsize = fw->size / 4;
404 module = kzalloc(sizeof(*module), GFP_KERNEL);
407 module->module_name = kstrdup(fw_name, GFP_KERNEL);
408 if (!module->module_name)
412 fwdat = (const __le32 *)fw->data;
413 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
416 module->symbol_table.symbols =
417 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
418 if (!module->symbol_table.symbols)
420 for (i = 0; i < nums; i++) {
421 struct dsp_symbol_entry *entry =
422 &module->symbol_table.symbols[i];
423 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
425 entry->address = le32_to_cpu(fwdat[fwlen++]);
426 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
427 fwlen += DSP_MAX_SYMBOL_NAME / 4;
428 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
433 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
437 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
438 if (!module->segments)
440 for (i = 0; i < nums; i++) {
441 struct dsp_segment_desc *entry = &module->segments[i];
442 if (fwlen + 3 > fwsize)
444 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
445 entry->offset = le32_to_cpu(fwdat[fwlen++]);
446 entry->size = le32_to_cpu(fwdat[fwlen++]);
447 if (fwlen + entry->size > fwsize)
449 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
452 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
453 fwlen += entry->size;
456 *module_ret = module;
457 release_firmware(fw);
463 free_module_desc(module);
464 release_firmware(fw);
468 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
469 unsigned long offset,
473 unsigned int bank = offset >> 16;
474 offset = offset & 0xffff;
476 if (snd_BUG_ON((offset & 3) || (len & 3)))
478 dst = chip->region.idx[bank+1].remap_addr + offset;
481 /* writel already converts 32-bit value to right endianess */
489 #else /* old DSP image */
495 } memory[BA1_MEMORY_COUNT];
496 u32 map[BA1_DWORD_SIZE];
499 MODULE_FIRMWARE("cs46xx/ba1");
501 static int load_firmware(struct snd_cs46xx *chip)
503 const struct firmware *fw;
506 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
509 if (fw->size != sizeof(*chip->ba1)) {
514 chip->ba1 = vmalloc(sizeof(*chip->ba1));
520 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
524 for (i = 0; i < BA1_MEMORY_COUNT; i++)
525 size += chip->ba1->memory[i].size;
526 if (size > BA1_DWORD_SIZE * 4)
530 release_firmware(fw);
534 int snd_cs46xx_download_image(struct snd_cs46xx *chip)
537 unsigned int offset = 0;
538 struct ba1_struct *ba1 = chip->ba1;
540 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
541 err = snd_cs46xx_download(chip,
543 ba1->memory[idx].offset,
544 ba1->memory[idx].size);
547 offset += ba1->memory[idx].size >> 2;
551 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
557 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
562 * Write the reset bit of the SP control register.
564 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
567 * Write the control register.
569 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
572 * Clear the trap registers.
574 for (idx = 0; idx < 8; idx++) {
575 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
576 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
578 snd_cs46xx_poke(chip, BA1_DREG, 0);
581 * Set the frame timer to reflect the number of cycles per frame.
583 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
586 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
590 * Make sure the previous FIFO write operation has completed.
592 for(i = 0; i < 50; i++){
593 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
595 if( !(status & SERBST_WBSY) )
598 mdelay(retry_timeout);
601 if(status & SERBST_WBSY) {
602 dev_err(chip->card->dev,
603 "failure waiting for FIFO command to complete\n");
610 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
612 int idx, powerdown = 0;
616 * See if the devices are powered down. If so, we must power them up first
617 * or they will not respond.
619 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
620 if (!(tmp & CLKCR1_SWCE)) {
621 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
626 * We want to clear out the serial port FIFOs so we don't end up playing
627 * whatever random garbage happens to be in them. We fill the sample FIFOS
628 * with zero (silence).
630 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
633 * Fill all 256 sample FIFO locations.
635 for (idx = 0; idx < 0xFF; idx++) {
637 * Make sure the previous FIFO write operation has completed.
639 if (cs46xx_wait_for_fifo(chip,1)) {
640 dev_dbg(chip->card->dev,
641 "failed waiting for FIFO at addr (%02X)\n",
645 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
650 * Write the serial port FIFO index.
652 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
654 * Tell the serial port to load the new value into the FIFO location.
656 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
659 * Now, if we powered up the devices, then power them back down again.
660 * This is kinda ugly, but should never happen.
663 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
666 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
671 * Set the frame timer to reflect the number of cycles per frame.
673 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
675 * Turn on the run, run at frame, and DMA enable bits in the local copy of
676 * the SP control register.
678 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
680 * Wait until the run at frame bit resets itself in the SP control
683 for (cnt = 0; cnt < 25; cnt++) {
685 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
689 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
690 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
693 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
696 * Turn off the run, run at frame, and DMA enable bits in the local copy of
697 * the SP control register.
699 snd_cs46xx_poke(chip, BA1_SPCR, 0);
703 * Sample rate routines
706 #define GOF_PER_SEC 200
708 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
711 unsigned int tmp1, tmp2;
712 unsigned int phiIncr;
713 unsigned int correctionPerGOF, correctionPerSec;
716 * Compute the values used to drive the actual sample rate conversion.
717 * The following formulas are being computed, using inline assembly
718 * since we need to use 64 bit arithmetic to compute the values:
720 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
721 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
723 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
724 * GOF_PER_SEC * correctionPerGOF
728 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
729 * correctionPerGOF:correctionPerSec =
730 * dividend:remainder(ulOther / GOF_PER_SEC)
733 phiIncr = tmp1 / 48000;
734 tmp1 -= phiIncr * 48000;
739 tmp1 -= tmp2 * 48000;
740 correctionPerGOF = tmp1 / GOF_PER_SEC;
741 tmp1 -= correctionPerGOF * GOF_PER_SEC;
742 correctionPerSec = tmp1;
745 * Fill in the SampleRateConverter control block.
747 spin_lock_irqsave(&chip->reg_lock, flags);
748 snd_cs46xx_poke(chip, BA1_PSRC,
749 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
750 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
751 spin_unlock_irqrestore(&chip->reg_lock, flags);
754 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
757 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
758 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
759 unsigned int frameGroupLength, cnt;
762 * We can only decimate by up to a factor of 1/9th the hardware rate.
763 * Correct the value if an attempt is made to stray outside that limit.
765 if ((rate * 9) < 48000)
769 * We can not capture at at rate greater than the Input Rate (48000).
770 * Return an error if an attempt is made to stray outside that limit.
776 * Compute the values used to drive the actual sample rate conversion.
777 * The following formulas are being computed, using inline assembly
778 * since we need to use 64 bit arithmetic to compute the values:
780 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
781 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
782 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
784 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
785 * GOF_PER_SEC * correctionPerGOF
786 * initialDelay = ceil((24 * Fs,in) / Fs,out)
790 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
791 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
792 * correctionPerGOF:correctionPerSec =
793 * dividend:remainder(ulOther / GOF_PER_SEC)
794 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
798 coeffIncr = tmp1 / 48000;
799 tmp1 -= coeffIncr * 48000;
802 coeffIncr += tmp1 / 48000;
803 coeffIncr ^= 0xFFFFFFFF;
806 phiIncr = tmp1 / rate;
807 tmp1 -= phiIncr * rate;
813 correctionPerGOF = tmp1 / GOF_PER_SEC;
814 tmp1 -= correctionPerGOF * GOF_PER_SEC;
815 correctionPerSec = tmp1;
816 initialDelay = ((48000 * 24) + rate - 1) / rate;
819 * Fill in the VariDecimate control block.
821 spin_lock_irqsave(&chip->reg_lock, flags);
822 snd_cs46xx_poke(chip, BA1_CSRC,
823 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
824 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
825 snd_cs46xx_poke(chip, BA1_CD,
826 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
827 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
828 spin_unlock_irqrestore(&chip->reg_lock, flags);
831 * Figure out the frame group length for the write back task. Basically,
832 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
833 * the output sample rate.
835 frameGroupLength = 1;
836 for (cnt = 2; cnt <= 64; cnt *= 2) {
837 if (((rate / cnt) * cnt) != rate)
838 frameGroupLength *= 2;
840 if (((rate / 3) * 3) != rate) {
841 frameGroupLength *= 3;
843 for (cnt = 5; cnt <= 125; cnt *= 5) {
844 if (((rate / cnt) * cnt) != rate)
845 frameGroupLength *= 5;
849 * Fill in the WriteBack control block.
851 spin_lock_irqsave(&chip->reg_lock, flags);
852 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
853 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
854 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
855 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
856 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
857 spin_unlock_irqrestore(&chip->reg_lock, flags);
864 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
865 struct snd_pcm_indirect *rec, size_t bytes)
867 struct snd_pcm_runtime *runtime = substream->runtime;
868 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
869 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
872 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
874 struct snd_pcm_runtime *runtime = substream->runtime;
875 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
876 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
877 snd_cs46xx_pb_trans_copy);
880 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
881 struct snd_pcm_indirect *rec, size_t bytes)
883 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
884 struct snd_pcm_runtime *runtime = substream->runtime;
885 memcpy(runtime->dma_area + rec->sw_data,
886 chip->capt.hw_buf.area + rec->hw_data, bytes);
889 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
891 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
892 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
893 snd_cs46xx_cp_trans_copy);
896 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
898 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
900 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
902 if (snd_BUG_ON(!cpcm->pcm_channel))
905 #ifdef CONFIG_SND_CS46XX_NEW_DSP
906 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
908 ptr = snd_cs46xx_peek(chip, BA1_PBA);
910 ptr -= cpcm->hw_buf.addr;
911 return ptr >> cpcm->shift;
914 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
916 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
918 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
920 #ifdef CONFIG_SND_CS46XX_NEW_DSP
921 if (snd_BUG_ON(!cpcm->pcm_channel))
923 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
925 ptr = snd_cs46xx_peek(chip, BA1_PBA);
927 ptr -= cpcm->hw_buf.addr;
928 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
931 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
933 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
934 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
935 return ptr >> chip->capt.shift;
938 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
940 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
941 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
942 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
945 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
948 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
949 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
952 #ifdef CONFIG_SND_CS46XX_NEW_DSP
953 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
954 if (! cpcm->pcm_channel) {
959 case SNDRV_PCM_TRIGGER_START:
960 case SNDRV_PCM_TRIGGER_RESUME:
961 #ifdef CONFIG_SND_CS46XX_NEW_DSP
962 /* magic value to unmute PCM stream playback volume */
963 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
964 SCBVolumeCtrl) << 2, 0x80008000);
966 if (cpcm->pcm_channel->unlinked)
967 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
969 if (substream->runtime->periods != CS46XX_FRAGS)
970 snd_cs46xx_playback_transfer(substream);
972 spin_lock(&chip->reg_lock);
973 if (substream->runtime->periods != CS46XX_FRAGS)
974 snd_cs46xx_playback_transfer(substream);
976 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
978 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
980 spin_unlock(&chip->reg_lock);
983 case SNDRV_PCM_TRIGGER_STOP:
984 case SNDRV_PCM_TRIGGER_SUSPEND:
985 #ifdef CONFIG_SND_CS46XX_NEW_DSP
986 /* magic mute channel */
987 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
988 SCBVolumeCtrl) << 2, 0xffffffff);
990 if (!cpcm->pcm_channel->unlinked)
991 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
993 spin_lock(&chip->reg_lock);
995 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
997 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
999 spin_unlock(&chip->reg_lock);
1010 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1013 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1017 spin_lock(&chip->reg_lock);
1019 case SNDRV_PCM_TRIGGER_START:
1020 case SNDRV_PCM_TRIGGER_RESUME:
1021 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1023 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1025 case SNDRV_PCM_TRIGGER_STOP:
1026 case SNDRV_PCM_TRIGGER_SUSPEND:
1027 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1029 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1035 spin_unlock(&chip->reg_lock);
1040 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1041 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1045 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1046 if ( cpcm->pcm_channel == NULL) {
1047 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1048 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1049 if (cpcm->pcm_channel == NULL) {
1050 dev_err(chip->card->dev,
1051 "failed to create virtual PCM channel\n");
1054 cpcm->pcm_channel->sample_rate = sample_rate;
1056 /* if sample rate is changed */
1057 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1058 int unlinked = cpcm->pcm_channel->unlinked;
1059 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1061 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
1063 cpcm->pcm_channel_id)) == NULL) {
1064 dev_err(chip->card->dev,
1065 "failed to re-create virtual PCM channel\n");
1069 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1070 cpcm->pcm_channel->sample_rate = sample_rate;
1078 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1079 struct snd_pcm_hw_params *hw_params)
1081 struct snd_pcm_runtime *runtime = substream->runtime;
1082 struct snd_cs46xx_pcm *cpcm;
1084 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1085 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1086 int sample_rate = params_rate(hw_params);
1087 int period_size = params_period_bytes(hw_params);
1089 cpcm = runtime->private_data;
1091 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1092 if (snd_BUG_ON(!sample_rate))
1095 mutex_lock(&chip->spos_mutex);
1097 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1098 mutex_unlock(&chip->spos_mutex);
1102 snd_BUG_ON(!cpcm->pcm_channel);
1103 if (!cpcm->pcm_channel) {
1104 mutex_unlock(&chip->spos_mutex);
1109 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1110 mutex_unlock(&chip->spos_mutex);
1114 dev_dbg(chip->card->dev,
1115 "period_size (%d), periods (%d) buffer_size(%d)\n",
1116 period_size, params_periods(hw_params),
1117 params_buffer_bytes(hw_params));
1120 if (params_periods(hw_params) == CS46XX_FRAGS) {
1121 if (runtime->dma_area != cpcm->hw_buf.area)
1122 snd_pcm_lib_free_pages(substream);
1123 runtime->dma_area = cpcm->hw_buf.area;
1124 runtime->dma_addr = cpcm->hw_buf.addr;
1125 runtime->dma_bytes = cpcm->hw_buf.bytes;
1128 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1129 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1130 substream->ops = &snd_cs46xx_playback_ops;
1131 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1132 substream->ops = &snd_cs46xx_playback_rear_ops;
1133 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1134 substream->ops = &snd_cs46xx_playback_clfe_ops;
1135 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1136 substream->ops = &snd_cs46xx_playback_iec958_ops;
1141 substream->ops = &snd_cs46xx_playback_ops;
1145 if (runtime->dma_area == cpcm->hw_buf.area) {
1146 runtime->dma_area = NULL;
1147 runtime->dma_addr = 0;
1148 runtime->dma_bytes = 0;
1150 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
1151 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1152 mutex_unlock(&chip->spos_mutex);
1157 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1158 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1159 substream->ops = &snd_cs46xx_playback_indirect_ops;
1160 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1161 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1162 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1163 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1164 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1165 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1170 substream->ops = &snd_cs46xx_playback_indirect_ops;
1175 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1176 mutex_unlock(&chip->spos_mutex);
1182 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1184 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1185 struct snd_pcm_runtime *runtime = substream->runtime;
1186 struct snd_cs46xx_pcm *cpcm;
1188 cpcm = runtime->private_data;
1190 /* if play_back open fails, then this function
1191 is called and cpcm can actually be NULL here */
1192 if (!cpcm) return -ENXIO;
1194 if (runtime->dma_area != cpcm->hw_buf.area)
1195 snd_pcm_lib_free_pages(substream);
1197 runtime->dma_area = NULL;
1198 runtime->dma_addr = 0;
1199 runtime->dma_bytes = 0;
1204 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1208 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1209 struct snd_pcm_runtime *runtime = substream->runtime;
1210 struct snd_cs46xx_pcm *cpcm;
1212 cpcm = runtime->private_data;
1214 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1215 if (snd_BUG_ON(!cpcm->pcm_channel))
1218 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1219 pfie &= ~0x0000f03f;
1222 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1223 pfie &= ~0x0000f03f;
1227 /* if to convert from stereo to mono */
1228 if (runtime->channels == 1) {
1232 /* if to convert from 8 bit to 16 bit */
1233 if (snd_pcm_format_width(runtime->format) == 8) {
1237 /* if to convert to unsigned */
1238 if (snd_pcm_format_unsigned(runtime->format))
1241 /* Never convert byte order when sample stream is 8 bit */
1242 if (snd_pcm_format_width(runtime->format) != 8) {
1243 /* convert from big endian to little endian */
1244 if (snd_pcm_format_big_endian(runtime->format))
1248 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1249 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1250 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1252 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1254 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1256 tmp |= (4 << cpcm->shift) - 1;
1257 /* playback transaction count register */
1258 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1260 /* playback format && interrupt enable */
1261 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1263 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1264 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1266 tmp |= (4 << cpcm->shift) - 1;
1267 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1268 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1269 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1275 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1276 struct snd_pcm_hw_params *hw_params)
1278 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1279 struct snd_pcm_runtime *runtime = substream->runtime;
1282 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1283 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1285 if (runtime->periods == CS46XX_FRAGS) {
1286 if (runtime->dma_area != chip->capt.hw_buf.area)
1287 snd_pcm_lib_free_pages(substream);
1288 runtime->dma_area = chip->capt.hw_buf.area;
1289 runtime->dma_addr = chip->capt.hw_buf.addr;
1290 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1291 substream->ops = &snd_cs46xx_capture_ops;
1293 if (runtime->dma_area == chip->capt.hw_buf.area) {
1294 runtime->dma_area = NULL;
1295 runtime->dma_addr = 0;
1296 runtime->dma_bytes = 0;
1298 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1300 substream->ops = &snd_cs46xx_capture_indirect_ops;
1306 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1308 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1309 struct snd_pcm_runtime *runtime = substream->runtime;
1311 if (runtime->dma_area != chip->capt.hw_buf.area)
1312 snd_pcm_lib_free_pages(substream);
1313 runtime->dma_area = NULL;
1314 runtime->dma_addr = 0;
1315 runtime->dma_bytes = 0;
1320 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1322 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1323 struct snd_pcm_runtime *runtime = substream->runtime;
1325 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1326 chip->capt.shift = 2;
1327 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1328 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1329 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1330 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1335 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1337 struct snd_cs46xx *chip = dev_id;
1339 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1340 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1343 struct snd_cs46xx_pcm *cpcm = NULL;
1347 * Read the Interrupt Status Register to clear the interrupt
1349 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1350 if ((status1 & 0x7fffffff) == 0) {
1351 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1355 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1356 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1358 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1360 if ( status1 & (1 << i) ) {
1361 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1362 if (chip->capt.substream)
1363 snd_pcm_period_elapsed(chip->capt.substream);
1365 if (ins->pcm_channels[i].active &&
1366 ins->pcm_channels[i].private_data &&
1367 !ins->pcm_channels[i].unlinked) {
1368 cpcm = ins->pcm_channels[i].private_data;
1369 snd_pcm_period_elapsed(cpcm->substream);
1374 if ( status2 & (1 << (i - 16))) {
1375 if (ins->pcm_channels[i].active &&
1376 ins->pcm_channels[i].private_data &&
1377 !ins->pcm_channels[i].unlinked) {
1378 cpcm = ins->pcm_channels[i].private_data;
1379 snd_pcm_period_elapsed(cpcm->substream);
1387 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1388 if (chip->playback_pcm->substream)
1389 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1391 if ((status1 & HISR_VC1) && chip->pcm) {
1392 if (chip->capt.substream)
1393 snd_pcm_period_elapsed(chip->capt.substream);
1397 if ((status1 & HISR_MIDI) && chip->rmidi) {
1400 spin_lock(&chip->reg_lock);
1401 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1402 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1403 if ((chip->midcr & MIDCR_RIE) == 0)
1405 snd_rawmidi_receive(chip->midi_input, &c, 1);
1407 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1408 if ((chip->midcr & MIDCR_TIE) == 0)
1410 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1411 chip->midcr &= ~MIDCR_TIE;
1412 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1415 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1417 spin_unlock(&chip->reg_lock);
1420 * EOI to the PCI part....reenables interrupts
1422 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1427 static const struct snd_pcm_hardware snd_cs46xx_playback =
1429 .info = (SNDRV_PCM_INFO_MMAP |
1430 SNDRV_PCM_INFO_INTERLEAVED |
1431 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1432 /*SNDRV_PCM_INFO_RESUME*/ |
1433 SNDRV_PCM_INFO_SYNC_APPLPTR),
1434 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1435 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1436 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1437 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1442 .buffer_bytes_max = (256 * 1024),
1443 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1444 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1445 .periods_min = CS46XX_FRAGS,
1446 .periods_max = 1024,
1450 static const struct snd_pcm_hardware snd_cs46xx_capture =
1452 .info = (SNDRV_PCM_INFO_MMAP |
1453 SNDRV_PCM_INFO_INTERLEAVED |
1454 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1455 /*SNDRV_PCM_INFO_RESUME*/ |
1456 SNDRV_PCM_INFO_SYNC_APPLPTR),
1457 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1458 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1463 .buffer_bytes_max = (256 * 1024),
1464 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1465 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1466 .periods_min = CS46XX_FRAGS,
1467 .periods_max = 1024,
1471 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1473 static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1475 static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1476 .count = ARRAY_SIZE(period_sizes),
1477 .list = period_sizes,
1483 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1485 kfree(runtime->private_data);
1488 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1490 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1491 struct snd_cs46xx_pcm * cpcm;
1492 struct snd_pcm_runtime *runtime = substream->runtime;
1494 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1497 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1498 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1503 runtime->hw = snd_cs46xx_playback;
1504 runtime->private_data = cpcm;
1505 runtime->private_free = snd_cs46xx_pcm_free_substream;
1507 cpcm->substream = substream;
1508 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1509 mutex_lock(&chip->spos_mutex);
1510 cpcm->pcm_channel = NULL;
1511 cpcm->pcm_channel_id = pcm_channel_id;
1514 snd_pcm_hw_constraint_list(runtime, 0,
1515 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1516 &hw_constraints_period_sizes);
1518 mutex_unlock(&chip->spos_mutex);
1520 chip->playback_pcm = cpcm; /* HACK */
1523 if (chip->accept_valid)
1524 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1525 chip->active_ctrl(chip, 1);
1530 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1532 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1533 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1536 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1537 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1539 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1540 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1543 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1545 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1546 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1549 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1551 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1553 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1555 mutex_lock(&chip->spos_mutex);
1556 cs46xx_iec958_pre_open (chip);
1557 mutex_unlock(&chip->spos_mutex);
1559 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1562 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1564 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1567 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1569 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1571 err = snd_cs46xx_playback_close(substream);
1573 mutex_lock(&chip->spos_mutex);
1574 cs46xx_iec958_post_close (chip);
1575 mutex_unlock(&chip->spos_mutex);
1581 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1583 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1585 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1586 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1588 chip->capt.substream = substream;
1589 substream->runtime->hw = snd_cs46xx_capture;
1591 if (chip->accept_valid)
1592 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1594 chip->active_ctrl(chip, 1);
1596 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1597 snd_pcm_hw_constraint_list(substream->runtime, 0,
1598 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1599 &hw_constraints_period_sizes);
1604 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1606 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1607 struct snd_pcm_runtime *runtime = substream->runtime;
1608 struct snd_cs46xx_pcm * cpcm;
1610 cpcm = runtime->private_data;
1612 /* when playback_open fails, then cpcm can be NULL */
1613 if (!cpcm) return -ENXIO;
1615 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1616 mutex_lock(&chip->spos_mutex);
1617 if (cpcm->pcm_channel) {
1618 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1619 cpcm->pcm_channel = NULL;
1621 mutex_unlock(&chip->spos_mutex);
1623 chip->playback_pcm = NULL;
1626 cpcm->substream = NULL;
1627 snd_dma_free_pages(&cpcm->hw_buf);
1628 chip->active_ctrl(chip, -1);
1633 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1635 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1637 chip->capt.substream = NULL;
1638 snd_dma_free_pages(&chip->capt.hw_buf);
1639 chip->active_ctrl(chip, -1);
1644 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1645 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1646 .open = snd_cs46xx_playback_open_rear,
1647 .close = snd_cs46xx_playback_close,
1648 .ioctl = snd_pcm_lib_ioctl,
1649 .hw_params = snd_cs46xx_playback_hw_params,
1650 .hw_free = snd_cs46xx_playback_hw_free,
1651 .prepare = snd_cs46xx_playback_prepare,
1652 .trigger = snd_cs46xx_playback_trigger,
1653 .pointer = snd_cs46xx_playback_direct_pointer,
1656 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1657 .open = snd_cs46xx_playback_open_rear,
1658 .close = snd_cs46xx_playback_close,
1659 .ioctl = snd_pcm_lib_ioctl,
1660 .hw_params = snd_cs46xx_playback_hw_params,
1661 .hw_free = snd_cs46xx_playback_hw_free,
1662 .prepare = snd_cs46xx_playback_prepare,
1663 .trigger = snd_cs46xx_playback_trigger,
1664 .pointer = snd_cs46xx_playback_indirect_pointer,
1665 .ack = snd_cs46xx_playback_transfer,
1668 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1669 .open = snd_cs46xx_playback_open_clfe,
1670 .close = snd_cs46xx_playback_close,
1671 .ioctl = snd_pcm_lib_ioctl,
1672 .hw_params = snd_cs46xx_playback_hw_params,
1673 .hw_free = snd_cs46xx_playback_hw_free,
1674 .prepare = snd_cs46xx_playback_prepare,
1675 .trigger = snd_cs46xx_playback_trigger,
1676 .pointer = snd_cs46xx_playback_direct_pointer,
1679 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1680 .open = snd_cs46xx_playback_open_clfe,
1681 .close = snd_cs46xx_playback_close,
1682 .ioctl = snd_pcm_lib_ioctl,
1683 .hw_params = snd_cs46xx_playback_hw_params,
1684 .hw_free = snd_cs46xx_playback_hw_free,
1685 .prepare = snd_cs46xx_playback_prepare,
1686 .trigger = snd_cs46xx_playback_trigger,
1687 .pointer = snd_cs46xx_playback_indirect_pointer,
1688 .ack = snd_cs46xx_playback_transfer,
1691 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1692 .open = snd_cs46xx_playback_open_iec958,
1693 .close = snd_cs46xx_playback_close_iec958,
1694 .ioctl = snd_pcm_lib_ioctl,
1695 .hw_params = snd_cs46xx_playback_hw_params,
1696 .hw_free = snd_cs46xx_playback_hw_free,
1697 .prepare = snd_cs46xx_playback_prepare,
1698 .trigger = snd_cs46xx_playback_trigger,
1699 .pointer = snd_cs46xx_playback_direct_pointer,
1702 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1703 .open = snd_cs46xx_playback_open_iec958,
1704 .close = snd_cs46xx_playback_close_iec958,
1705 .ioctl = snd_pcm_lib_ioctl,
1706 .hw_params = snd_cs46xx_playback_hw_params,
1707 .hw_free = snd_cs46xx_playback_hw_free,
1708 .prepare = snd_cs46xx_playback_prepare,
1709 .trigger = snd_cs46xx_playback_trigger,
1710 .pointer = snd_cs46xx_playback_indirect_pointer,
1711 .ack = snd_cs46xx_playback_transfer,
1716 static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1717 .open = snd_cs46xx_playback_open,
1718 .close = snd_cs46xx_playback_close,
1719 .ioctl = snd_pcm_lib_ioctl,
1720 .hw_params = snd_cs46xx_playback_hw_params,
1721 .hw_free = snd_cs46xx_playback_hw_free,
1722 .prepare = snd_cs46xx_playback_prepare,
1723 .trigger = snd_cs46xx_playback_trigger,
1724 .pointer = snd_cs46xx_playback_direct_pointer,
1727 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1728 .open = snd_cs46xx_playback_open,
1729 .close = snd_cs46xx_playback_close,
1730 .ioctl = snd_pcm_lib_ioctl,
1731 .hw_params = snd_cs46xx_playback_hw_params,
1732 .hw_free = snd_cs46xx_playback_hw_free,
1733 .prepare = snd_cs46xx_playback_prepare,
1734 .trigger = snd_cs46xx_playback_trigger,
1735 .pointer = snd_cs46xx_playback_indirect_pointer,
1736 .ack = snd_cs46xx_playback_transfer,
1739 static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1740 .open = snd_cs46xx_capture_open,
1741 .close = snd_cs46xx_capture_close,
1742 .ioctl = snd_pcm_lib_ioctl,
1743 .hw_params = snd_cs46xx_capture_hw_params,
1744 .hw_free = snd_cs46xx_capture_hw_free,
1745 .prepare = snd_cs46xx_capture_prepare,
1746 .trigger = snd_cs46xx_capture_trigger,
1747 .pointer = snd_cs46xx_capture_direct_pointer,
1750 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1751 .open = snd_cs46xx_capture_open,
1752 .close = snd_cs46xx_capture_close,
1753 .ioctl = snd_pcm_lib_ioctl,
1754 .hw_params = snd_cs46xx_capture_hw_params,
1755 .hw_free = snd_cs46xx_capture_hw_free,
1756 .prepare = snd_cs46xx_capture_prepare,
1757 .trigger = snd_cs46xx_capture_trigger,
1758 .pointer = snd_cs46xx_capture_indirect_pointer,
1759 .ack = snd_cs46xx_capture_transfer,
1762 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1763 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1765 #define MAX_PLAYBACK_CHANNELS 1
1768 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1770 struct snd_pcm *pcm;
1773 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1776 pcm->private_data = chip;
1778 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1779 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1782 pcm->info_flags = 0;
1783 strcpy(pcm->name, "CS46xx");
1786 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1794 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1795 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1797 struct snd_pcm *pcm;
1800 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1803 pcm->private_data = chip;
1805 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1808 pcm->info_flags = 0;
1809 strcpy(pcm->name, "CS46xx - Rear");
1810 chip->pcm_rear = pcm;
1812 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1819 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1821 struct snd_pcm *pcm;
1824 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1827 pcm->private_data = chip;
1829 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1832 pcm->info_flags = 0;
1833 strcpy(pcm->name, "CS46xx - Center LFE");
1834 chip->pcm_center_lfe = pcm;
1836 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1843 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1845 struct snd_pcm *pcm;
1848 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1851 pcm->private_data = chip;
1853 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1856 pcm->info_flags = 0;
1857 strcpy(pcm->name, "CS46xx - IEC958");
1858 chip->pcm_iec958 = pcm;
1860 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1871 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1873 struct snd_cs46xx *chip = bus->private_data;
1875 chip->ac97_bus = NULL;
1878 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1880 struct snd_cs46xx *chip = ac97->private_data;
1882 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1883 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1886 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1887 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1888 chip->eapd_switch = NULL;
1891 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1894 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1895 struct snd_ctl_elem_info *uinfo)
1897 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1899 uinfo->value.integer.min = 0;
1900 uinfo->value.integer.max = 0x7fff;
1904 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1906 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1907 int reg = kcontrol->private_value;
1908 unsigned int val = snd_cs46xx_peek(chip, reg);
1909 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1910 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1914 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1916 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1917 int reg = kcontrol->private_value;
1918 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1919 (0xffff - ucontrol->value.integer.value[1]));
1920 unsigned int old = snd_cs46xx_peek(chip, reg);
1921 int change = (old != val);
1924 snd_cs46xx_poke(chip, reg, val);
1930 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1932 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1934 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1936 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1937 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1942 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1944 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1947 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1948 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1949 cs46xx_dsp_set_dac_volume(chip,
1950 ucontrol->value.integer.value[0],
1951 ucontrol->value.integer.value[1]);
1959 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1961 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1963 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1964 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1968 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1970 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1973 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1974 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1975 cs46xx_dsp_set_iec958_volume (chip,
1976 ucontrol->value.integer.value[0],
1977 ucontrol->value.integer.value[1]);
1985 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1987 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1988 struct snd_ctl_elem_value *ucontrol)
1990 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1991 int reg = kcontrol->private_value;
1993 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1994 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1996 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
2001 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
2002 struct snd_ctl_elem_value *ucontrol)
2004 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2007 switch (kcontrol->private_value) {
2008 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
2009 mutex_lock(&chip->spos_mutex);
2010 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2011 if (ucontrol->value.integer.value[0] && !change)
2012 cs46xx_dsp_enable_spdif_out(chip);
2013 else if (change && !ucontrol->value.integer.value[0])
2014 cs46xx_dsp_disable_spdif_out(chip);
2016 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
2017 mutex_unlock(&chip->spos_mutex);
2019 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
2020 change = chip->dsp_spos_instance->spdif_status_in;
2021 if (ucontrol->value.integer.value[0] && !change) {
2022 cs46xx_dsp_enable_spdif_in(chip);
2023 /* restore volume */
2025 else if (change && !ucontrol->value.integer.value[0])
2026 cs46xx_dsp_disable_spdif_in(chip);
2028 res = (change != chip->dsp_spos_instance->spdif_status_in);
2032 snd_BUG(); /* should never happen ... */
2038 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2039 struct snd_ctl_elem_value *ucontrol)
2041 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2042 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2044 if (ins->adc_input != NULL)
2045 ucontrol->value.integer.value[0] = 1;
2047 ucontrol->value.integer.value[0] = 0;
2052 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2053 struct snd_ctl_elem_value *ucontrol)
2055 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2056 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2059 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2060 cs46xx_dsp_enable_adc_capture(chip);
2062 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2063 cs46xx_dsp_disable_adc_capture(chip);
2069 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2070 struct snd_ctl_elem_value *ucontrol)
2072 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2073 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2075 if (ins->pcm_input != NULL)
2076 ucontrol->value.integer.value[0] = 1;
2078 ucontrol->value.integer.value[0] = 0;
2084 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2085 struct snd_ctl_elem_value *ucontrol)
2087 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2088 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2091 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2092 cs46xx_dsp_enable_pcm_capture(chip);
2094 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2095 cs46xx_dsp_disable_pcm_capture(chip);
2102 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2103 struct snd_ctl_elem_value *ucontrol)
2105 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2107 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2109 if (val1 & EGPIODR_GPOE0)
2110 ucontrol->value.integer.value[0] = 1;
2112 ucontrol->value.integer.value[0] = 0;
2118 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2120 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2121 struct snd_ctl_elem_value *ucontrol)
2123 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2124 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2125 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2127 if (ucontrol->value.integer.value[0]) {
2128 /* optical is default */
2129 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2130 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2131 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2132 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2135 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2136 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2139 /* checking diff from the EGPIO direction register
2141 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2145 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2147 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2152 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2153 struct snd_ctl_elem_value *ucontrol)
2155 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2156 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2158 mutex_lock(&chip->spos_mutex);
2159 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2160 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2161 ucontrol->value.iec958.status[2] = 0;
2162 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2163 mutex_unlock(&chip->spos_mutex);
2168 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2169 struct snd_ctl_elem_value *ucontrol)
2171 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2172 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2176 mutex_lock(&chip->spos_mutex);
2177 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2178 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2179 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2180 /* left and right validity bit */
2181 (1 << 13) | (1 << 12);
2184 change = (unsigned int)ins->spdif_csuv_default != val;
2185 ins->spdif_csuv_default = val;
2187 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2188 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2190 mutex_unlock(&chip->spos_mutex);
2195 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2196 struct snd_ctl_elem_value *ucontrol)
2198 ucontrol->value.iec958.status[0] = 0xff;
2199 ucontrol->value.iec958.status[1] = 0xff;
2200 ucontrol->value.iec958.status[2] = 0x00;
2201 ucontrol->value.iec958.status[3] = 0xff;
2205 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2206 struct snd_ctl_elem_value *ucontrol)
2208 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2209 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2211 mutex_lock(&chip->spos_mutex);
2212 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2213 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2214 ucontrol->value.iec958.status[2] = 0;
2215 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2216 mutex_unlock(&chip->spos_mutex);
2221 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2222 struct snd_ctl_elem_value *ucontrol)
2224 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2225 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2229 mutex_lock(&chip->spos_mutex);
2230 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2231 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2232 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2233 /* left and right validity bit */
2234 (1 << 13) | (1 << 12);
2237 change = ins->spdif_csuv_stream != val;
2238 ins->spdif_csuv_stream = val;
2240 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2241 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2243 mutex_unlock(&chip->spos_mutex);
2248 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2251 static struct snd_kcontrol_new snd_cs46xx_controls[] = {
2253 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2254 .name = "DAC Volume",
2255 .info = snd_cs46xx_vol_info,
2256 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2257 .get = snd_cs46xx_vol_get,
2258 .put = snd_cs46xx_vol_put,
2259 .private_value = BA1_PVOL,
2261 .get = snd_cs46xx_vol_dac_get,
2262 .put = snd_cs46xx_vol_dac_put,
2267 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2268 .name = "ADC Volume",
2269 .info = snd_cs46xx_vol_info,
2270 .get = snd_cs46xx_vol_get,
2271 .put = snd_cs46xx_vol_put,
2272 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2273 .private_value = BA1_CVOL,
2275 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2278 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2280 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2281 .name = "ADC Capture Switch",
2282 .info = snd_mixer_boolean_info,
2283 .get = snd_cs46xx_adc_capture_get,
2284 .put = snd_cs46xx_adc_capture_put
2287 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2288 .name = "DAC Capture Switch",
2289 .info = snd_mixer_boolean_info,
2290 .get = snd_cs46xx_pcm_capture_get,
2291 .put = snd_cs46xx_pcm_capture_put
2294 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2295 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2296 .info = snd_mixer_boolean_info,
2297 .get = snd_cs46xx_iec958_get,
2298 .put = snd_cs46xx_iec958_put,
2299 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2302 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2303 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2304 .info = snd_mixer_boolean_info,
2305 .get = snd_cs46xx_iec958_get,
2306 .put = snd_cs46xx_iec958_put,
2307 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2310 /* Input IEC958 volume does not work for the moment. (Benny) */
2312 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2313 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2314 .info = snd_cs46xx_vol_info,
2315 .get = snd_cs46xx_vol_iec958_get,
2316 .put = snd_cs46xx_vol_iec958_put,
2317 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2321 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2322 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2323 .info = snd_cs46xx_spdif_info,
2324 .get = snd_cs46xx_spdif_default_get,
2325 .put = snd_cs46xx_spdif_default_put,
2328 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2329 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2330 .info = snd_cs46xx_spdif_info,
2331 .get = snd_cs46xx_spdif_mask_get,
2332 .access = SNDRV_CTL_ELEM_ACCESS_READ
2335 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2336 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2337 .info = snd_cs46xx_spdif_info,
2338 .get = snd_cs46xx_spdif_stream_get,
2339 .put = snd_cs46xx_spdif_stream_put
2345 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2346 /* set primary cs4294 codec into Extended Audio Mode */
2347 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2348 struct snd_ctl_elem_value *ucontrol)
2350 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2352 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2353 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2357 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2358 struct snd_ctl_elem_value *ucontrol)
2360 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2361 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2362 AC97_CSR_ACMODE, 0x200,
2363 ucontrol->value.integer.value[0] ? 0 : 0x200);
2366 static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2367 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2368 .name = "Duplicate Front",
2369 .info = snd_mixer_boolean_info,
2370 .get = snd_cs46xx_front_dup_get,
2371 .put = snd_cs46xx_front_dup_put,
2375 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2376 /* Only available on the Hercules Game Theater XP soundcard */
2377 static struct snd_kcontrol_new snd_hercules_controls[] = {
2379 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2380 .name = "Optical/Coaxial SPDIF Input Switch",
2381 .info = snd_mixer_boolean_info,
2382 .get = snd_herc_spdif_select_get,
2383 .put = snd_herc_spdif_select_put,
2388 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2390 unsigned long end_time;
2393 /* reset to defaults */
2394 snd_ac97_write(ac97, AC97_RESET, 0);
2396 /* set the desired CODEC mode */
2397 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2398 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2399 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2400 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2401 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2402 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2404 snd_BUG(); /* should never happen ... */
2409 /* it's necessary to wait awhile until registers are accessible after RESET */
2410 /* because the PCM or MASTER volume registers can be modified, */
2411 /* the REC_GAIN register is used for tests */
2412 end_time = jiffies + HZ;
2414 unsigned short ext_mid;
2416 /* use preliminary reads to settle the communication */
2417 snd_ac97_read(ac97, AC97_RESET);
2418 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2419 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2421 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2422 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2425 /* test if we can write to the record gain volume register */
2426 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2427 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2431 } while (time_after_eq(end_time, jiffies));
2433 dev_err(ac97->bus->card->dev,
2434 "CS46xx secondary codec doesn't respond!\n");
2438 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2441 struct snd_ac97_template ac97;
2443 memset(&ac97, 0, sizeof(ac97));
2444 ac97.private_data = chip;
2445 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2447 if (chip->amplifier_ctrl == amp_voyetra)
2448 ac97.scaps = AC97_SCAP_INV_EAPD;
2450 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2451 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2453 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2454 dev_dbg(chip->card->dev,
2455 "secondary codec not present\n");
2460 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2461 for (idx = 0; idx < 100; ++idx) {
2462 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2463 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2468 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2472 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2474 struct snd_card *card = chip->card;
2475 struct snd_ctl_elem_id id;
2478 static struct snd_ac97_bus_ops ops = {
2479 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2480 .reset = snd_cs46xx_codec_reset,
2482 .write = snd_cs46xx_ac97_write,
2483 .read = snd_cs46xx_ac97_read,
2486 /* detect primary codec */
2487 chip->nr_ac97_codecs = 0;
2488 dev_dbg(chip->card->dev, "detecting primary codec\n");
2489 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2491 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2493 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2495 chip->nr_ac97_codecs = 1;
2497 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2498 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2499 /* try detect a secondary codec */
2500 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2501 chip->nr_ac97_codecs = 2;
2502 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2504 /* add cs4630 mixer controls */
2505 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2506 struct snd_kcontrol *kctl;
2507 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2508 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2509 kctl->id.device = spdif_device;
2510 if ((err = snd_ctl_add(card, kctl)) < 0)
2514 /* get EAPD mixer switch (for voyetra hack) */
2515 memset(&id, 0, sizeof(id));
2516 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2517 strcpy(id.name, "External Amplifier");
2518 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2520 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2521 if (chip->nr_ac97_codecs == 1) {
2522 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2523 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
2524 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2527 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2528 AC97_CSR_ACMODE, 0x200);
2531 /* do soundcard specific mixer setup */
2532 if (chip->mixer_init) {
2533 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2534 chip->mixer_init(chip);
2538 /* turn on amplifier */
2539 chip->amplifier_ctrl(chip, 1);
2548 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2550 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2552 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2555 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2557 struct snd_cs46xx *chip = substream->rmidi->private_data;
2559 chip->active_ctrl(chip, 1);
2560 spin_lock_irq(&chip->reg_lock);
2561 chip->uartm |= CS46XX_MODE_INPUT;
2562 chip->midcr |= MIDCR_RXE;
2563 chip->midi_input = substream;
2564 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2565 snd_cs46xx_midi_reset(chip);
2567 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2569 spin_unlock_irq(&chip->reg_lock);
2573 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2575 struct snd_cs46xx *chip = substream->rmidi->private_data;
2577 spin_lock_irq(&chip->reg_lock);
2578 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2579 chip->midi_input = NULL;
2580 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2581 snd_cs46xx_midi_reset(chip);
2583 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2585 chip->uartm &= ~CS46XX_MODE_INPUT;
2586 spin_unlock_irq(&chip->reg_lock);
2587 chip->active_ctrl(chip, -1);
2591 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2593 struct snd_cs46xx *chip = substream->rmidi->private_data;
2595 chip->active_ctrl(chip, 1);
2597 spin_lock_irq(&chip->reg_lock);
2598 chip->uartm |= CS46XX_MODE_OUTPUT;
2599 chip->midcr |= MIDCR_TXE;
2600 chip->midi_output = substream;
2601 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2602 snd_cs46xx_midi_reset(chip);
2604 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2606 spin_unlock_irq(&chip->reg_lock);
2610 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2612 struct snd_cs46xx *chip = substream->rmidi->private_data;
2614 spin_lock_irq(&chip->reg_lock);
2615 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2616 chip->midi_output = NULL;
2617 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2618 snd_cs46xx_midi_reset(chip);
2620 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2622 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2623 spin_unlock_irq(&chip->reg_lock);
2624 chip->active_ctrl(chip, -1);
2628 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2630 unsigned long flags;
2631 struct snd_cs46xx *chip = substream->rmidi->private_data;
2633 spin_lock_irqsave(&chip->reg_lock, flags);
2635 if ((chip->midcr & MIDCR_RIE) == 0) {
2636 chip->midcr |= MIDCR_RIE;
2637 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2640 if (chip->midcr & MIDCR_RIE) {
2641 chip->midcr &= ~MIDCR_RIE;
2642 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2645 spin_unlock_irqrestore(&chip->reg_lock, flags);
2648 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2650 unsigned long flags;
2651 struct snd_cs46xx *chip = substream->rmidi->private_data;
2654 spin_lock_irqsave(&chip->reg_lock, flags);
2656 if ((chip->midcr & MIDCR_TIE) == 0) {
2657 chip->midcr |= MIDCR_TIE;
2658 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2659 while ((chip->midcr & MIDCR_TIE) &&
2660 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2661 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2662 chip->midcr &= ~MIDCR_TIE;
2664 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2667 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2670 if (chip->midcr & MIDCR_TIE) {
2671 chip->midcr &= ~MIDCR_TIE;
2672 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2675 spin_unlock_irqrestore(&chip->reg_lock, flags);
2678 static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2680 .open = snd_cs46xx_midi_output_open,
2681 .close = snd_cs46xx_midi_output_close,
2682 .trigger = snd_cs46xx_midi_output_trigger,
2685 static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2687 .open = snd_cs46xx_midi_input_open,
2688 .close = snd_cs46xx_midi_input_close,
2689 .trigger = snd_cs46xx_midi_input_trigger,
2692 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2694 struct snd_rawmidi *rmidi;
2697 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2699 strcpy(rmidi->name, "CS46XX");
2700 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2701 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2702 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2703 rmidi->private_data = chip;
2704 chip->rmidi = rmidi;
2710 * gameport interface
2713 #if IS_REACHABLE(CONFIG_GAMEPORT)
2715 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2717 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2719 if (snd_BUG_ON(!chip))
2721 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2724 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2726 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2728 if (snd_BUG_ON(!chip))
2730 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2733 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2735 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2736 unsigned js1, js2, jst;
2738 if (snd_BUG_ON(!chip))
2741 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2742 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2743 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2745 *buttons = (~jst >> 4) & 0x0F;
2747 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2748 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2749 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2750 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2752 for(jst=0;jst<4;++jst)
2753 if(axes[jst]==0xFFFF) axes[jst] = -1;
2757 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2760 case GAMEPORT_MODE_COOKED:
2762 case GAMEPORT_MODE_RAW:
2770 int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2772 struct gameport *gp;
2774 chip->gameport = gp = gameport_allocate_port();
2776 dev_err(chip->card->dev,
2777 "cannot allocate memory for gameport\n");
2781 gameport_set_name(gp, "CS46xx Gameport");
2782 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2783 gameport_set_dev_parent(gp, &chip->pci->dev);
2784 gameport_set_port_data(gp, chip);
2786 gp->open = snd_cs46xx_gameport_open;
2787 gp->read = snd_cs46xx_gameport_read;
2788 gp->trigger = snd_cs46xx_gameport_trigger;
2789 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2791 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2792 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2794 gameport_register_port(gp);
2799 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2801 if (chip->gameport) {
2802 gameport_unregister_port(chip->gameport);
2803 chip->gameport = NULL;
2807 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2808 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2809 #endif /* CONFIG_GAMEPORT */
2811 #ifdef CONFIG_SND_PROC_FS
2816 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2817 void *file_private_data,
2818 struct file *file, char __user *buf,
2819 size_t count, loff_t pos)
2821 struct snd_cs46xx_region *region = entry->private_data;
2823 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2828 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2829 .read = snd_cs46xx_io_read,
2832 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2834 struct snd_info_entry *entry;
2837 for (idx = 0; idx < 5; idx++) {
2838 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2839 if (! snd_card_proc_new(card, region->name, &entry)) {
2840 entry->content = SNDRV_INFO_CONTENT_DATA;
2841 entry->private_data = chip;
2842 entry->c.ops = &snd_cs46xx_proc_io_ops;
2843 entry->size = region->size;
2844 entry->mode = S_IFREG | 0400;
2847 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2848 cs46xx_dsp_proc_init(card, chip);
2853 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2855 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2856 cs46xx_dsp_proc_done(chip);
2860 #else /* !CONFIG_SND_PROC_FS */
2861 #define snd_cs46xx_proc_init(card, chip)
2862 #define snd_cs46xx_proc_done(chip)
2868 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2872 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2875 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2877 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2880 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2883 * Stop playback DMA.
2885 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2886 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2891 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2892 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2895 * Reset the processor.
2897 snd_cs46xx_reset(chip);
2899 snd_cs46xx_proc_stop(chip);
2902 * Power down the PLL.
2904 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2907 * Turn off the Processor by turning off the software clock enable flag in
2908 * the clock control register.
2910 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2911 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2915 static int snd_cs46xx_free(struct snd_cs46xx *chip)
2919 if (snd_BUG_ON(!chip))
2922 if (chip->active_ctrl)
2923 chip->active_ctrl(chip, 1);
2925 snd_cs46xx_remove_gameport(chip);
2927 if (chip->amplifier_ctrl)
2928 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2930 snd_cs46xx_proc_done(chip);
2932 if (chip->region.idx[0].resource)
2933 snd_cs46xx_hw_stop(chip);
2936 free_irq(chip->irq, chip);
2938 if (chip->active_ctrl)
2939 chip->active_ctrl(chip, -chip->amplifier);
2941 for (idx = 0; idx < 5; idx++) {
2942 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2944 iounmap(region->remap_addr);
2945 release_and_free_resource(region->resource);
2948 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2949 if (chip->dsp_spos_instance) {
2950 cs46xx_dsp_spos_destroy(chip);
2951 chip->dsp_spos_instance = NULL;
2953 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2954 free_module_desc(chip->modules[idx]);
2959 #ifdef CONFIG_PM_SLEEP
2960 kfree(chip->saved_regs);
2963 pci_disable_device(chip->pci);
2968 static int snd_cs46xx_dev_free(struct snd_device *device)
2970 struct snd_cs46xx *chip = device->device_data;
2971 return snd_cs46xx_free(chip);
2977 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2982 * First, blast the clock control register to zero so that the PLL starts
2983 * out in a known state, and blast the master serial port control register
2984 * to zero so that the serial ports also start out in a known state.
2986 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2987 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2990 * If we are in AC97 mode, then we must set the part to a host controlled
2991 * AC-link. Otherwise, we won't be able to bring up the link.
2993 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2994 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2995 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2996 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2998 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
3002 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
3003 * spec) and then drive it high. This is done for non AC97 modes since
3004 * there might be logic external to the CS461x that uses the ARST# line
3007 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
3008 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3009 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3012 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3013 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3014 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3018 * The first thing we do here is to enable sync generation. As soon
3019 * as we start receiving bit clock, we'll start producing the SYNC
3022 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3023 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3024 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3028 * Now wait for a short while to allow the AC97 part to start
3029 * generating bit clock (so we don't try to start the PLL without an
3035 * Set the serial port timing configuration, so that
3036 * the clock control circuit gets its clock from the correct place.
3038 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3041 * Write the selected clock control setup to the hardware. Do not turn on
3042 * SWCE yet (if requested), so that the devices clocked by the output of
3043 * PLL are not clocked until the PLL is stable.
3045 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3046 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3047 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3052 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3055 * Wait until the PLL has stabilized.
3060 * Turn on clocking of the core so that we can setup the serial ports.
3062 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3065 * Enable FIFO Host Bypass
3067 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3070 * Fill the serial port FIFOs with silence.
3072 snd_cs46xx_clear_serial_FIFOs(chip);
3075 * Set the serial port FIFO pointer to the first sample in the FIFO.
3077 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3080 * Write the serial port configuration to the part. The master
3081 * enable bit is not set until all other values have been written.
3083 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3084 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3085 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3088 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3089 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3090 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3091 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3092 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3093 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3100 * Wait for the codec ready signal from the AC97 codec.
3103 while (timeout-- > 0) {
3105 * Read the AC97 status register to see if we've seen a CODEC READY
3106 * signal from the AC97 codec.
3108 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3114 dev_err(chip->card->dev,
3115 "create - never read codec ready from AC'97\n");
3116 dev_err(chip->card->dev,
3117 "it is not probably bug, try to use CS4236 driver\n");
3120 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3123 for (count = 0; count < 150; count++) {
3124 /* First, we want to wait for a short time. */
3127 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3132 * Make sure CODEC is READY.
3134 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3135 dev_dbg(chip->card->dev,
3136 "never read card ready from secondary AC'97\n");
3141 * Assert the vaid frame signal so that we can start sending commands
3142 * to the AC97 codec.
3144 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3145 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3146 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3151 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3152 * the codec is pumping ADC data across the AC-link.
3155 while (timeout-- > 0) {
3157 * Read the input slot valid register and see if input slots 3 and
3160 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3165 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3166 dev_err(chip->card->dev,
3167 "create - never read ISV3 & ISV4 from AC'97\n");
3170 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3171 Reloading the driver may help, if there's other soundcards
3172 with the same problem I would like to know. (Benny) */
3174 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3175 dev_err(chip->card->dev,
3176 "Try reloading the ALSA driver, if you find something\n");
3177 dev_err(chip->card->dev,
3178 "broken or not working on your soundcard upon\n");
3179 dev_err(chip->card->dev,
3180 "this message please report to alsa-devel@alsa-project.org\n");
3187 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3188 * commense the transfer of digital audio data to the AC97 codec.
3191 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3195 * Power down the DAC and ADC. We will power them up (if) when we need
3198 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3201 * Turn off the Processor by turning off the software clock enable flag in
3202 * the clock control register.
3204 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3205 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3211 * start and load DSP
3214 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3218 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3220 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3222 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3224 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3227 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3230 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3233 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3239 * Reset the processor.
3241 snd_cs46xx_reset(chip);
3243 * Download the image to the processor.
3245 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3246 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3247 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3249 dev_err(chip->card->dev, "firmware load error [%s]\n",
3253 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3255 dev_err(chip->card->dev, "image download error [%s]\n",
3261 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3264 err = load_firmware(chip);
3269 err = snd_cs46xx_download_image(chip);
3271 dev_err(chip->card->dev, "image download error\n");
3276 * Stop playback DMA.
3278 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3279 chip->play_ctl = tmp & 0xffff0000;
3280 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3286 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3287 chip->capt.ctl = tmp & 0x0000ffff;
3288 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3292 snd_cs46xx_set_play_sample_rate(chip, 8000);
3293 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3295 snd_cs46xx_proc_start(chip);
3297 cs46xx_enable_stream_irqs(chip);
3299 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3300 /* set the attenuation to 0dB */
3301 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3302 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3310 * AMP control - null AMP
3313 static void amp_none(struct snd_cs46xx *chip, int change)
3317 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3318 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3321 u32 idx, valid_slots,tmp,powerdown = 0;
3322 u16 modem_power,pin_config,logic_type;
3324 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3327 * See if the devices are powered down. If so, we must power them up first
3328 * or they will not respond.
3330 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3332 if (!(tmp & CLKCR1_SWCE)) {
3333 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3338 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3341 if(chip->nr_ac97_codecs != 2) {
3342 dev_err(chip->card->dev,
3343 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3347 modem_power = snd_cs46xx_codec_read (chip,
3348 AC97_EXTENDED_MSTATUS,
3349 CS46XX_SECONDARY_CODEC_INDEX);
3350 modem_power &=0xFEFF;
3352 snd_cs46xx_codec_write(chip,
3353 AC97_EXTENDED_MSTATUS, modem_power,
3354 CS46XX_SECONDARY_CODEC_INDEX);
3357 * Set GPIO pin's 7 and 8 so that they are configured for output.
3359 pin_config = snd_cs46xx_codec_read (chip,
3361 CS46XX_SECONDARY_CODEC_INDEX);
3364 snd_cs46xx_codec_write(chip,
3365 AC97_GPIO_CFG, pin_config,
3366 CS46XX_SECONDARY_CODEC_INDEX);
3369 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3372 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3373 CS46XX_SECONDARY_CODEC_INDEX);
3376 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3377 CS46XX_SECONDARY_CODEC_INDEX);
3379 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3380 valid_slots |= 0x200;
3381 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3383 if ( cs46xx_wait_for_fifo(chip,1) ) {
3384 dev_dbg(chip->card->dev, "FIFO is busy\n");
3390 * Fill slots 12 with the correct value for the GPIO pins.
3392 for(idx = 0x90; idx <= 0x9F; idx++) {
3394 * Initialize the fifo so that bits 7 and 8 are on.
3396 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3397 * the left. 0x1800 corresponds to bits 7 and 8.
3399 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3402 * Wait for command to complete
3404 if ( cs46xx_wait_for_fifo(chip,200) ) {
3405 dev_dbg(chip->card->dev,
3406 "failed waiting for FIFO at addr (%02X)\n",
3413 * Write the serial port FIFO index.
3415 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3418 * Tell the serial port to load the new value into the FIFO location.
3420 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3423 /* wait for last command to complete */
3424 cs46xx_wait_for_fifo(chip,200);
3427 * Now, if we powered up the devices, then power them back down again.
3428 * This is kinda ugly, but should never happen.
3431 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3441 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3443 /* Manage the EAPD bit on the Crystal 4297
3444 and the Analog AD1885 */
3446 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3447 int old = chip->amplifier;
3451 chip->amplifier += change;
3452 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3453 CS46XX_PRIMARY_CODEC_INDEX);
3455 if (chip->amplifier) {
3456 /* Turn the EAPD amp on */
3459 /* Turn the EAPD amp off */
3463 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3464 CS46XX_PRIMARY_CODEC_INDEX);
3465 if (chip->eapd_switch)
3466 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3467 &chip->eapd_switch->id);
3470 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3471 if (chip->amplifier && !old) {
3472 voyetra_setup_eapd_slot(chip);
3477 static void hercules_init(struct snd_cs46xx *chip)
3479 /* default: AMP off, and SPDIF input optical */
3480 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3481 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3486 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3488 static void amp_hercules(struct snd_cs46xx *chip, int change)
3490 int old = chip->amplifier;
3491 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3492 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3494 chip->amplifier += change;
3495 if (chip->amplifier && !old) {
3496 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3498 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3499 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3500 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3501 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3502 } else if (old && !chip->amplifier) {
3503 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3504 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3505 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3509 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3511 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3513 /* Enable SPDIF out */
3514 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3515 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3518 static void hercules_mixer_init (struct snd_cs46xx *chip)
3520 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3523 struct snd_card *card = chip->card;
3526 /* set EGPIO to default */
3527 hercules_init(chip);
3529 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3531 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3532 if (chip->in_suspend)
3535 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3536 struct snd_kcontrol *kctl;
3538 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3539 if ((err = snd_ctl_add(card, kctl)) < 0) {
3541 "failed to initialize Hercules mixer (%d)\n",
3555 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3557 chip->amplifier += change;
3559 if (chip->amplifier) {
3560 /* Switch the GPIO pins 7 and 8 to open drain */
3561 snd_cs46xx_codec_write(chip, 0x4C,
3562 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3563 snd_cs46xx_codec_write(chip, 0x4E,
3564 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3565 /* Now wake the AMP (this might be backwards) */
3566 snd_cs46xx_codec_write(chip, 0x54,
3567 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3569 snd_cs46xx_codec_write(chip, 0x54,
3570 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3577 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3578 * whenever we need to beat on the chip.
3580 * The original idea and code for this hack comes from David Kaiser at
3581 * Linuxcare. Perhaps one day Crystal will document their chips well
3582 * enough to make them useful.
3585 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3589 if (!chip->acpi_port)
3592 chip->amplifier += change;
3594 /* Read ACPI port */
3595 nval = control = inw(chip->acpi_port + 0x10);
3597 /* Flip CLKRUN off while running */
3598 if (! chip->amplifier)
3602 if (nval != control)
3603 outw(nval, chip->acpi_port + 0x10);
3608 * detect intel piix4
3610 static void clkrun_init(struct snd_cs46xx *chip)
3612 struct pci_dev *pdev;
3615 chip->acpi_port = 0;
3617 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3618 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3620 return; /* Not a thinkpad thats for sure */
3622 /* Find the control port */
3623 pci_read_config_byte(pdev, 0x41, &pp);
3624 chip->acpi_port = pp << 8;
3638 void (*init)(struct snd_cs46xx *);
3639 void (*amp)(struct snd_cs46xx *, int);
3640 void (*active)(struct snd_cs46xx *, int);
3641 void (*mixer_init)(struct snd_cs46xx *);
3644 static struct cs_card_type cards[] = {
3648 .name = "Genius Soundmaker 128 value",
3649 /* nothing special */
3656 .mixer_init = voyetra_mixer_init,
3661 .name = "Mitac MI6020/21",
3664 /* Hercules Game Theatre XP */
3666 .vendor = 0x14af, /* Guillemot Corporation */
3668 .name = "Hercules Game Theatre XP",
3669 .amp = amp_hercules,
3670 .mixer_init = hercules_mixer_init,
3675 .name = "Hercules Game Theatre XP",
3676 .amp = amp_hercules,
3677 .mixer_init = hercules_mixer_init,
3682 .name = "Hercules Game Theatre XP",
3683 .amp = amp_hercules,
3684 .mixer_init = hercules_mixer_init,
3690 .name = "Hercules Game Theatre XP",
3691 .amp = amp_hercules,
3692 .mixer_init = hercules_mixer_init,
3697 .name = "Hercules Game Theatre XP",
3698 .amp = amp_hercules,
3699 .mixer_init = hercules_mixer_init,
3704 .name = "Hercules Game Theatre XP",
3705 .amp = amp_hercules,
3706 .mixer_init = hercules_mixer_init,
3708 /* Herculess Fortissimo */
3712 .name = "Hercules Gamesurround Fortissimo II",
3717 .name = "Hercules Gamesurround Fortissimo III 7.1",
3723 .name = "Terratec DMX XFire 1024",
3728 .name = "Terratec SiXPack 5.1",
3730 /* Not sure if the 570 needs the clkrun hack */
3732 .vendor = PCI_VENDOR_ID_IBM,
3734 .name = "Thinkpad 570",
3735 .init = clkrun_init,
3736 .active = clkrun_hack,
3739 .vendor = PCI_VENDOR_ID_IBM,
3741 .name = "Thinkpad 600X/A20/T20",
3742 .init = clkrun_init,
3743 .active = clkrun_hack,
3746 .vendor = PCI_VENDOR_ID_IBM,
3748 .name = "Thinkpad 600E (unsupported)",
3757 #ifdef CONFIG_PM_SLEEP
3758 static unsigned int saved_regs[] = {
3766 static int snd_cs46xx_suspend(struct device *dev)
3768 struct snd_card *card = dev_get_drvdata(dev);
3769 struct snd_cs46xx *chip = card->private_data;
3772 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3773 chip->in_suspend = 1;
3774 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3775 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3777 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3778 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3780 /* save some registers */
3781 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3782 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3784 amp_saved = chip->amplifier;
3786 chip->amplifier_ctrl(chip, -chip->amplifier);
3787 snd_cs46xx_hw_stop(chip);
3788 /* disable CLKRUN */
3789 chip->active_ctrl(chip, -chip->amplifier);
3790 chip->amplifier = amp_saved; /* restore the status */
3794 static int snd_cs46xx_resume(struct device *dev)
3796 struct snd_card *card = dev_get_drvdata(dev);
3797 struct snd_cs46xx *chip = card->private_data;
3799 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3804 amp_saved = chip->amplifier;
3805 chip->amplifier = 0;
3806 chip->active_ctrl(chip, 1); /* force to on */
3808 snd_cs46xx_chip_init(chip);
3810 snd_cs46xx_reset(chip);
3811 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3812 cs46xx_dsp_resume(chip);
3813 /* restore some registers */
3814 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3815 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3817 snd_cs46xx_download_image(chip);
3821 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3822 chip->ac97_general_purpose);
3823 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3824 chip->ac97_powerdown);
3826 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3827 chip->ac97_powerdown);
3831 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3832 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3837 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3838 chip->capt.ctl = tmp & 0x0000ffff;
3839 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3843 /* reset playback/capture */
3844 snd_cs46xx_set_play_sample_rate(chip, 8000);
3845 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3846 snd_cs46xx_proc_start(chip);
3848 cs46xx_enable_stream_irqs(chip);
3851 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3853 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3854 chip->amplifier = amp_saved;
3855 chip->in_suspend = 0;
3856 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3860 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3861 #endif /* CONFIG_PM_SLEEP */
3867 int snd_cs46xx_create(struct snd_card *card,
3868 struct pci_dev *pci,
3869 int external_amp, int thinkpad,
3870 struct snd_cs46xx **rchip)
3872 struct snd_cs46xx *chip;
3874 struct snd_cs46xx_region *region;
3875 struct cs_card_type *cp;
3876 u16 ss_card, ss_vendor;
3877 static struct snd_device_ops ops = {
3878 .dev_free = snd_cs46xx_dev_free,
3883 /* enable PCI device */
3884 if ((err = pci_enable_device(pci)) < 0)
3887 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3889 pci_disable_device(pci);
3892 spin_lock_init(&chip->reg_lock);
3893 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3894 mutex_init(&chip->spos_mutex);
3899 chip->ba0_addr = pci_resource_start(pci, 0);
3900 chip->ba1_addr = pci_resource_start(pci, 1);
3901 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3902 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3903 dev_err(chip->card->dev,
3904 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3905 chip->ba0_addr, chip->ba1_addr);
3906 snd_cs46xx_free(chip);
3910 region = &chip->region.name.ba0;
3911 strcpy(region->name, "CS46xx_BA0");
3912 region->base = chip->ba0_addr;
3913 region->size = CS46XX_BA0_SIZE;
3915 region = &chip->region.name.data0;
3916 strcpy(region->name, "CS46xx_BA1_data0");
3917 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3918 region->size = CS46XX_BA1_DATA0_SIZE;
3920 region = &chip->region.name.data1;
3921 strcpy(region->name, "CS46xx_BA1_data1");
3922 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3923 region->size = CS46XX_BA1_DATA1_SIZE;
3925 region = &chip->region.name.pmem;
3926 strcpy(region->name, "CS46xx_BA1_pmem");
3927 region->base = chip->ba1_addr + BA1_SP_PMEM;
3928 region->size = CS46XX_BA1_PRG_SIZE;
3930 region = &chip->region.name.reg;
3931 strcpy(region->name, "CS46xx_BA1_reg");
3932 region->base = chip->ba1_addr + BA1_SP_REG;
3933 region->size = CS46XX_BA1_REG_SIZE;
3935 /* set up amp and clkrun hack */
3936 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3937 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3939 for (cp = &cards[0]; cp->name; cp++) {
3940 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3941 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3944 chip->amplifier_ctrl = cp->amp;
3945 chip->active_ctrl = cp->active;
3946 chip->mixer_init = cp->mixer_init;
3955 dev_info(chip->card->dev,
3956 "Crystal EAPD support forced on.\n");
3957 chip->amplifier_ctrl = amp_voyetra;
3961 dev_info(chip->card->dev,
3962 "Activating CLKRUN hack for Thinkpad.\n");
3963 chip->active_ctrl = clkrun_hack;
3967 if (chip->amplifier_ctrl == NULL)
3968 chip->amplifier_ctrl = amp_none;
3969 if (chip->active_ctrl == NULL)
3970 chip->active_ctrl = amp_none;
3972 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3974 pci_set_master(pci);
3976 for (idx = 0; idx < 5; idx++) {
3977 region = &chip->region.idx[idx];
3978 if ((region->resource = request_mem_region(region->base, region->size,
3979 region->name)) == NULL) {
3980 dev_err(chip->card->dev,
3981 "unable to request memory region 0x%lx-0x%lx\n",
3982 region->base, region->base + region->size - 1);
3983 snd_cs46xx_free(chip);
3986 region->remap_addr = ioremap_nocache(region->base, region->size);
3987 if (region->remap_addr == NULL) {
3988 dev_err(chip->card->dev,
3989 "%s ioremap problem\n", region->name);
3990 snd_cs46xx_free(chip);
3995 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
3996 KBUILD_MODNAME, chip)) {
3997 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3998 snd_cs46xx_free(chip);
4001 chip->irq = pci->irq;
4003 #ifdef CONFIG_SND_CS46XX_NEW_DSP
4004 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
4005 if (chip->dsp_spos_instance == NULL) {
4006 snd_cs46xx_free(chip);
4011 err = snd_cs46xx_chip_init(chip);
4013 snd_cs46xx_free(chip);
4017 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
4018 snd_cs46xx_free(chip);
4022 snd_cs46xx_proc_init(card, chip);
4024 #ifdef CONFIG_PM_SLEEP
4025 chip->saved_regs = kmalloc_array(ARRAY_SIZE(saved_regs),
4026 sizeof(*chip->saved_regs),
4028 if (!chip->saved_regs) {
4029 snd_cs46xx_free(chip);
4034 chip->active_ctrl(chip, -1); /* disable CLKRUN */