1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
4 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
7 /* Does not work. Warning may block system in capture mode */
8 /* #define USE_VAR48KRATE */
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/gameport.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <sound/core.h>
20 #include <sound/info.h>
21 #include <sound/control.h>
22 #include <sound/pcm.h>
23 #include <sound/rawmidi.h>
24 #include <sound/mpu401.h>
25 #include <sound/opl3.h>
27 #include <sound/asoundef.h>
28 #include <sound/initval.h>
30 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
31 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
32 MODULE_LICENSE("GPL");
34 #if IS_REACHABLE(CONFIG_GAMEPORT)
35 #define SUPPORT_JOYSTICK 1
38 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
39 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
40 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
41 static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
42 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
43 static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
44 #ifdef SUPPORT_JOYSTICK
45 static int joystick_port[SNDRV_CARDS];
48 module_param_array(index, int, NULL, 0444);
49 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
50 module_param_array(id, charp, NULL, 0444);
51 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
52 module_param_array(enable, bool, NULL, 0444);
53 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
54 module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
55 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
56 module_param_hw_array(fm_port, long, ioport, NULL, 0444);
57 MODULE_PARM_DESC(fm_port, "FM port.");
58 module_param_array(soft_ac3, bool, NULL, 0444);
59 MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
60 #ifdef SUPPORT_JOYSTICK
61 module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
62 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
66 * CM8x38 registers definition
69 #define CM_REG_FUNCTRL0 0x00
70 #define CM_RST_CH1 0x00080000
71 #define CM_RST_CH0 0x00040000
72 #define CM_CHEN1 0x00020000 /* ch1: enable */
73 #define CM_CHEN0 0x00010000 /* ch0: enable */
74 #define CM_PAUSE1 0x00000008 /* ch1: pause */
75 #define CM_PAUSE0 0x00000004 /* ch0: pause */
76 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
77 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
79 #define CM_REG_FUNCTRL1 0x04
80 #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
81 #define CM_DSFC_SHIFT 13
82 #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
83 #define CM_ASFC_SHIFT 10
84 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
85 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
86 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
87 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
88 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
89 #define CM_BREQ 0x00000010 /* bus master enabled */
90 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
91 #define CM_UART_EN 0x00000004 /* legacy UART */
92 #define CM_JYSTK_EN 0x00000002 /* legacy joystick */
93 #define CM_ZVPORT 0x00000001 /* ZVPORT */
95 #define CM_REG_CHFORMAT 0x08
97 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
98 #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
99 #define CM_CHB3D 0x20000000 /* 4 channels */
101 #define CM_CHIP_MASK1 0x1f000000
102 #define CM_CHIP_037 0x01000000
103 #define CM_SETLAT48 0x00800000 /* set latency timer 48h */
104 #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
105 #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
106 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
107 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
108 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
109 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
111 #define CM_ADCBITLEN_MASK 0x0000C000
112 #define CM_ADCBITLEN_16 0x00000000
113 #define CM_ADCBITLEN_15 0x00004000
114 #define CM_ADCBITLEN_14 0x00008000
115 #define CM_ADCBITLEN_13 0x0000C000
117 #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
118 #define CM_ADCDACLEN_060 0x00000000
119 #define CM_ADCDACLEN_066 0x00001000
120 #define CM_ADCDACLEN_130 0x00002000
121 #define CM_ADCDACLEN_280 0x00003000
123 #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
124 #define CM_ADCDLEN_ORIGINAL 0x00000000
125 #define CM_ADCDLEN_EXTRA 0x00001000
126 #define CM_ADCDLEN_24K 0x00002000
127 #define CM_ADCDLEN_WEIGHT 0x00003000
129 #define CM_CH1_SRATE_176K 0x00000800
130 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
131 #define CM_CH1_SRATE_88K 0x00000400
132 #define CM_CH0_SRATE_176K 0x00000200
133 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
134 #define CM_CH0_SRATE_88K 0x00000100
135 #define CM_CH0_SRATE_128K 0x00000300
136 #define CM_CH0_SRATE_MASK 0x00000300
138 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
139 #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
140 #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
141 #define CM_SPDLOCKED 0x00000010
143 #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
144 #define CM_CH1FMT_SHIFT 2
145 #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
146 #define CM_CH0FMT_SHIFT 0
148 #define CM_REG_INT_HLDCLR 0x0C
149 #define CM_CHIP_MASK2 0xff000000
150 #define CM_CHIP_8768 0x20000000
151 #define CM_CHIP_055 0x08000000
152 #define CM_CHIP_039 0x04000000
153 #define CM_CHIP_039_6CH 0x01000000
154 #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
155 #define CM_TDMA_INT_EN 0x00040000
156 #define CM_CH1_INT_EN 0x00020000
157 #define CM_CH0_INT_EN 0x00010000
159 #define CM_REG_INT_STATUS 0x10
160 #define CM_INTR 0x80000000
161 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
162 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
163 #define CM_UARTINT 0x00010000
164 #define CM_LTDMAINT 0x00008000
165 #define CM_HTDMAINT 0x00004000
166 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
167 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
168 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
169 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
170 #define CM_CH1BUSY 0x00000008
171 #define CM_CH0BUSY 0x00000004
172 #define CM_CHINT1 0x00000002
173 #define CM_CHINT0 0x00000001
175 #define CM_REG_LEGACY_CTRL 0x14
176 #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
177 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
178 #define CM_VMPU_330 0x00000000
179 #define CM_VMPU_320 0x20000000
180 #define CM_VMPU_310 0x40000000
181 #define CM_VMPU_300 0x60000000
182 #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
183 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
184 #define CM_VSBSEL_220 0x00000000
185 #define CM_VSBSEL_240 0x04000000
186 #define CM_VSBSEL_260 0x08000000
187 #define CM_VSBSEL_280 0x0C000000
188 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
189 #define CM_FMSEL_388 0x00000000
190 #define CM_FMSEL_3C8 0x01000000
191 #define CM_FMSEL_3E0 0x02000000
192 #define CM_FMSEL_3E8 0x03000000
193 #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
194 #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
195 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
196 #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
197 #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
198 #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
199 #define CM_C_EECS 0x00040000
200 #define CM_C_EEDI46 0x00020000
201 #define CM_C_EECK46 0x00010000
202 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
203 #define CM_CENTR2LIN 0x00004000 /* line-in as center out */
204 #define CM_BASE2LIN 0x00002000 /* line-in as bass out */
205 #define CM_EXBASEN 0x00001000 /* external bass input enable */
207 #define CM_REG_MISC_CTRL 0x18
208 #define CM_PWD 0x80000000 /* power down */
209 #define CM_RESET 0x40000000
210 #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
211 #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
212 #define CM_TXVX 0x08000000 /* model 037? */
213 #define CM_N4SPK3D 0x04000000 /* copy front to rear */
214 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
215 #define CM_SPDIF48K 0x01000000 /* write */
216 #define CM_SPATUS48K 0x01000000 /* read */
217 #define CM_ENDBDAC 0x00800000 /* enable double dac */
218 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
219 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
220 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
221 #define CM_FM_EN 0x00080000 /* enable legacy FM */
222 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
223 #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
224 #define CM_VIDWPDSB 0x00010000 /* model 037? */
225 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
226 #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
227 #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
228 #define CM_VIDWPPRT 0x00002000 /* model 037? */
229 #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
230 #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
231 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
232 #define CM_ENCENTER 0x00000080
233 #define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
234 #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
235 #define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
236 #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
237 #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
238 #define CM_UPDDMA_2048 0x00000000
239 #define CM_UPDDMA_1024 0x00000004
240 #define CM_UPDDMA_512 0x00000008
241 #define CM_UPDDMA_256 0x0000000C
242 #define CM_TWAIT_MASK 0x00000003 /* model 037 */
243 #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
244 #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
246 #define CM_REG_TDMA_POSITION 0x1C
247 #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
248 #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
251 #define CM_REG_MIXER0 0x20
252 #define CM_REG_SBVR 0x20 /* write: sb16 version */
253 #define CM_REG_DEV 0x20 /* read: hardware device version */
255 #define CM_REG_MIXER21 0x21
256 #define CM_UNKNOWN_21_MASK 0x78 /* ? */
257 #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
258 #define CM_PROINV 0x02 /* SBPro left/right channel switching */
259 #define CM_X_SB16 0x01 /* SB16 compatible */
261 #define CM_REG_SB16_DATA 0x22
262 #define CM_REG_SB16_ADDR 0x23
264 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
265 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
266 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
267 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
269 #define CM_REG_MIXER1 0x24
270 #define CM_FMMUTE 0x80 /* mute FM */
271 #define CM_FMMUTE_SHIFT 7
272 #define CM_WSMUTE 0x40 /* mute PCM */
273 #define CM_WSMUTE_SHIFT 6
274 #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
275 #define CM_REAR2LIN_SHIFT 5
276 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
277 #define CM_REAR2FRONT_SHIFT 4
278 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
279 #define CM_WAVEINL_SHIFT 3
280 #define CM_WAVEINR 0x04 /* digical wave rec. right */
281 #define CM_WAVEINR_SHIFT 2
282 #define CM_X3DEN 0x02 /* 3D surround enable */
283 #define CM_X3DEN_SHIFT 1
284 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
285 #define CM_CDPLAY_SHIFT 0
287 #define CM_REG_MIXER2 0x25
288 #define CM_RAUXREN 0x80 /* AUX right capture */
289 #define CM_RAUXREN_SHIFT 7
290 #define CM_RAUXLEN 0x40 /* AUX left capture */
291 #define CM_RAUXLEN_SHIFT 6
292 #define CM_VAUXRM 0x20 /* AUX right mute */
293 #define CM_VAUXRM_SHIFT 5
294 #define CM_VAUXLM 0x10 /* AUX left mute */
295 #define CM_VAUXLM_SHIFT 4
296 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
297 #define CM_VADMIC_SHIFT 1
298 #define CM_MICGAINZ 0x01 /* mic boost */
299 #define CM_MICGAINZ_SHIFT 0
301 #define CM_REG_MIXER3 0x24
302 #define CM_REG_AUX_VOL 0x26
303 #define CM_VAUXL_MASK 0xf0
304 #define CM_VAUXR_MASK 0x0f
306 #define CM_REG_MISC 0x27
307 #define CM_UNKNOWN_27_MASK 0xd8 /* ? */
308 #define CM_XGPO1 0x20
309 // #define CM_XGPBIO 0x04
310 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
311 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
312 #define CM_SPDVALID 0x02 /* spdif input valid check */
313 #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
315 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
317 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
318 * or identical with AC97 codec?
320 #define CM_REG_EXTERN_CODEC CM_REG_AC97
323 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
325 #define CM_REG_MPU_PCI 0x40
328 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
330 #define CM_REG_FM_PCI 0x50
333 * access from SB-mixer port
335 #define CM_REG_EXTENT_IND 0xf0
336 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
337 #define CM_VPHONE_SHIFT 5
338 #define CM_VPHOM 0x10 /* Phone mute control */
339 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
340 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
341 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
342 #define CM_VADMIC3 0x01 /* Mic record boost */
345 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
346 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
349 #define CM_REG_PLL 0xf8
354 #define CM_REG_CH0_FRAME1 0x80 /* write: base address */
355 #define CM_REG_CH0_FRAME2 0x84 /* read: current address */
356 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
357 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
359 #define CM_REG_EXT_MISC 0x90
360 #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
361 #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
362 #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
363 #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
364 #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
365 #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
366 #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
367 #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
372 #define CM_EXTENT_CODEC 0x100
373 #define CM_EXTENT_MIDI 0x2
374 #define CM_EXTENT_SYNTH 0x4
378 * channels for playback / capture
384 * flags to check device open/close
386 #define CM_OPEN_NONE 0
387 #define CM_OPEN_CH_MASK 0x01
388 #define CM_OPEN_DAC 0x10
389 #define CM_OPEN_ADC 0x20
390 #define CM_OPEN_SPDIF 0x40
391 #define CM_OPEN_MCHAN 0x80
392 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
393 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
394 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
395 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
396 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
397 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
401 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
402 #define CM_PLAYBACK_SPDF CM_SPDF_1
403 #define CM_CAPTURE_SPDF CM_SPDF_0
405 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
406 #define CM_PLAYBACK_SPDF CM_SPDF_0
407 #define CM_CAPTURE_SPDF CM_SPDF_1
416 struct snd_pcm_substream *substream;
417 u8 running; /* dac/adc running? */
418 u8 fmt; /* format bits */
421 unsigned int dma_size; /* in frames */
423 unsigned int ch; /* channel (0/1) */
424 unsigned int offset; /* physical address of the buffer */
427 /* mixer elements toggled/resumed during ac3 playback */
428 struct cmipci_mixer_auto_switches {
429 const char *name; /* switch to toggle */
430 int toggle_on; /* value to change when ac3 mode */
432 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
433 {"PCM Playback Switch", 0},
434 {"IEC958 Output Switch", 1},
435 {"IEC958 Mix Analog", 0},
436 // {"IEC958 Out To DAC", 1}, // no longer used
439 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
442 struct snd_card *card;
445 unsigned int device; /* device ID */
448 unsigned long iobase;
449 unsigned int ctrl; /* FUNCTRL0 current value */
451 struct snd_pcm *pcm; /* DAC/ADC PCM */
452 struct snd_pcm *pcm2; /* 2nd DAC */
453 struct snd_pcm *pcm_spdif; /* SPDIF */
457 unsigned int can_ac3_sw: 1;
458 unsigned int can_ac3_hw: 1;
459 unsigned int can_multi_ch: 1;
460 unsigned int can_96k: 1; /* samplerate above 48k */
461 unsigned int do_soft_ac3: 1;
463 unsigned int spdif_playback_avail: 1; /* spdif ready? */
464 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
465 int spdif_counter; /* for software AC3 */
467 unsigned int dig_status;
468 unsigned int dig_pcm_status;
470 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
472 int opened[2]; /* open mode */
473 struct mutex open_mutex;
475 unsigned int mixer_insensitive: 1;
476 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
477 int mixer_res_status[CM_SAVED_MIXERS];
479 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
482 struct snd_rawmidi *rmidi;
484 #ifdef SUPPORT_JOYSTICK
485 struct gameport *gameport;
490 #ifdef CONFIG_PM_SLEEP
491 unsigned int saved_regs[0x20];
492 unsigned char saved_mixers[0x20];
497 /* read/write operations for dword register */
498 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
500 outl(data, cm->iobase + cmd);
503 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
505 return inl(cm->iobase + cmd);
508 /* read/write operations for word register */
509 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
511 outw(data, cm->iobase + cmd);
514 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
516 return inw(cm->iobase + cmd);
519 /* read/write operations for byte register */
520 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
522 outb(data, cm->iobase + cmd);
525 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
527 return inb(cm->iobase + cmd);
530 /* bit operations for dword register */
531 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
533 unsigned int val, oval;
534 val = oval = inl(cm->iobase + cmd);
538 outl(val, cm->iobase + cmd);
542 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
544 unsigned int val, oval;
545 val = oval = inl(cm->iobase + cmd);
549 outl(val, cm->iobase + cmd);
553 /* bit operations for byte register */
554 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
556 unsigned char val, oval;
557 val = oval = inb(cm->iobase + cmd);
561 outb(val, cm->iobase + cmd);
565 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
567 unsigned char val, oval;
568 val = oval = inb(cm->iobase + cmd);
572 outb(val, cm->iobase + cmd);
582 * calculate frequency
585 static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
587 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
591 for (i = 0; i < ARRAY_SIZE(rates); i++) {
592 if (rates[i] == rate)
599 #ifdef USE_VAR48KRATE
601 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
602 * does it this way .. maybe not. Never get any information from C-Media about
603 * that <werner@suse.de>.
605 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
607 unsigned int delta, tolerance;
610 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
615 tolerance = rate*CM_TOLERANCE_RATE;
617 for (xn = (1+2); xn < (0x1f+2); xn++) {
618 for (xm = (1+2); xm < (0xff+2); xm++) {
619 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
627 * If we found one, remember this,
628 * and try to find a closer one
630 if (delta < tolerance) {
642 * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
643 * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
644 * at the register CM_REG_FUNCTRL1 (0x04).
645 * Problem: other ways are also possible (any information about that?)
647 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
649 unsigned int reg = CM_REG_PLL + slot;
651 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
652 * for DSFC/ASFC (000 up to 111).
655 /* FIXME: Init (Do we've to set an other register first before programming?) */
657 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
658 snd_cmipci_write_b(cm, reg, rate>>8);
659 snd_cmipci_write_b(cm, reg, rate&0xff);
661 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
663 #endif /* USE_VAR48KRATE */
665 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
666 struct snd_pcm_hw_params *hw_params)
668 struct cmipci *cm = snd_pcm_substream_chip(substream);
669 if (params_channels(hw_params) > 2) {
670 mutex_lock(&cm->open_mutex);
671 if (cm->opened[CM_CH_PLAY]) {
672 mutex_unlock(&cm->open_mutex);
675 /* reserve the channel A */
676 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
677 mutex_unlock(&cm->open_mutex);
682 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
684 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
685 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
686 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
694 static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
695 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
700 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
705 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
711 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
714 if (!cm->can_multi_ch || !rec->ch)
716 if (rec->fmt != 0x03) /* stereo 16bit only */
720 if (cm->can_multi_ch) {
721 spin_lock_irq(&cm->reg_lock);
723 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
724 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
726 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
727 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
730 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
732 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
734 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
735 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
737 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
738 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
741 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
743 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
744 spin_unlock_irq(&cm->reg_lock);
751 * prepare playback/capture channel
752 * channel to be used must have been set in rec->ch.
754 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
755 struct snd_pcm_substream *substream)
757 unsigned int reg, freq, freq_ext, val;
758 unsigned int period_size;
759 struct snd_pcm_runtime *runtime = substream->runtime;
763 if (snd_pcm_format_width(runtime->format) >= 16) {
765 if (snd_pcm_format_width(runtime->format) > 16)
766 rec->shift++; /* 24/32bit */
768 if (runtime->channels > 1)
770 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
771 dev_dbg(cm->card->dev, "cannot set dac channels\n");
775 rec->offset = runtime->dma_addr;
776 /* buffer and period sizes in frame */
777 rec->dma_size = runtime->buffer_size << rec->shift;
778 period_size = runtime->period_size << rec->shift;
779 if (runtime->channels > 2) {
781 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
782 period_size = (period_size * runtime->channels) / 2;
785 spin_lock_irq(&cm->reg_lock);
787 /* set buffer address */
788 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
789 snd_cmipci_write(cm, reg, rec->offset);
790 /* program sample counts */
791 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
792 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
793 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
795 /* set adc/dac flag */
796 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
801 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
802 /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
804 /* set sample rate */
807 if (runtime->rate > 48000)
808 switch (runtime->rate) {
809 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
810 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
811 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
812 default: snd_BUG(); break;
815 freq = snd_cmipci_rate_freq(runtime->rate);
816 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
818 val &= ~CM_DSFC_MASK;
819 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
821 val &= ~CM_ASFC_MASK;
822 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
824 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
825 dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
828 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
830 val &= ~CM_CH1FMT_MASK;
831 val |= rec->fmt << CM_CH1FMT_SHIFT;
833 val &= ~CM_CH0FMT_MASK;
834 val |= rec->fmt << CM_CH0FMT_SHIFT;
837 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
838 val |= freq_ext << (rec->ch * 2);
840 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
841 dev_dbg(cm->card->dev, "chformat = %08x\n", val);
843 if (!rec->is_dac && cm->chip_version) {
844 if (runtime->rate > 44100)
845 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
847 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
851 spin_unlock_irq(&cm->reg_lock);
859 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
862 unsigned int inthld, chen, reset, pause;
865 inthld = CM_CH0_INT_EN << rec->ch;
866 chen = CM_CHEN0 << rec->ch;
867 reset = CM_RST_CH0 << rec->ch;
868 pause = CM_PAUSE0 << rec->ch;
870 spin_lock(&cm->reg_lock);
872 case SNDRV_PCM_TRIGGER_START:
875 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
878 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
879 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
881 case SNDRV_PCM_TRIGGER_STOP:
883 /* disable interrupt */
884 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
887 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
888 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
889 rec->needs_silencing = rec->is_dac;
891 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
892 case SNDRV_PCM_TRIGGER_SUSPEND:
894 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
896 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
897 case SNDRV_PCM_TRIGGER_RESUME:
899 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
905 spin_unlock(&cm->reg_lock);
910 * return the current pointer
912 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
913 struct snd_pcm_substream *substream)
916 unsigned int reg, rem, tries;
920 #if 1 // this seems better..
921 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
922 for (tries = 0; tries < 3; tries++) {
923 rem = snd_cmipci_read_w(cm, reg);
924 if (rem < rec->dma_size)
927 dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
928 return SNDRV_PCM_POS_XRUN;
930 ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
932 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
933 ptr = snd_cmipci_read(cm, reg) - rec->offset;
934 ptr = bytes_to_frames(substream->runtime, ptr);
936 if (substream->runtime->channels > 2)
937 ptr = (ptr * 2) / substream->runtime->channels;
945 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
948 struct cmipci *cm = snd_pcm_substream_chip(substream);
949 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
952 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
954 struct cmipci *cm = snd_pcm_substream_chip(substream);
955 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
964 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
967 struct cmipci *cm = snd_pcm_substream_chip(substream);
968 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
971 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
973 struct cmipci *cm = snd_pcm_substream_chip(substream);
974 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
979 * hw preparation for spdif
982 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
983 struct snd_ctl_elem_info *uinfo)
985 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
990 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
991 struct snd_ctl_elem_value *ucontrol)
993 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
996 spin_lock_irq(&chip->reg_lock);
997 for (i = 0; i < 4; i++)
998 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
999 spin_unlock_irq(&chip->reg_lock);
1003 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1004 struct snd_ctl_elem_value *ucontrol)
1006 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1011 spin_lock_irq(&chip->reg_lock);
1012 for (i = 0; i < 4; i++)
1013 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1014 change = val != chip->dig_status;
1015 chip->dig_status = val;
1016 spin_unlock_irq(&chip->reg_lock);
1020 static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1022 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1023 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1024 .info = snd_cmipci_spdif_default_info,
1025 .get = snd_cmipci_spdif_default_get,
1026 .put = snd_cmipci_spdif_default_put
1029 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1030 struct snd_ctl_elem_info *uinfo)
1032 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1037 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1038 struct snd_ctl_elem_value *ucontrol)
1040 ucontrol->value.iec958.status[0] = 0xff;
1041 ucontrol->value.iec958.status[1] = 0xff;
1042 ucontrol->value.iec958.status[2] = 0xff;
1043 ucontrol->value.iec958.status[3] = 0xff;
1047 static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1049 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1050 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1051 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1052 .info = snd_cmipci_spdif_mask_info,
1053 .get = snd_cmipci_spdif_mask_get,
1056 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1057 struct snd_ctl_elem_info *uinfo)
1059 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1064 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1065 struct snd_ctl_elem_value *ucontrol)
1067 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1070 spin_lock_irq(&chip->reg_lock);
1071 for (i = 0; i < 4; i++)
1072 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1073 spin_unlock_irq(&chip->reg_lock);
1077 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1078 struct snd_ctl_elem_value *ucontrol)
1080 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1085 spin_lock_irq(&chip->reg_lock);
1086 for (i = 0; i < 4; i++)
1087 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1088 change = val != chip->dig_pcm_status;
1089 chip->dig_pcm_status = val;
1090 spin_unlock_irq(&chip->reg_lock);
1094 static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1096 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1097 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1098 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1099 .info = snd_cmipci_spdif_stream_info,
1100 .get = snd_cmipci_spdif_stream_get,
1101 .put = snd_cmipci_spdif_stream_put
1107 /* save mixer setting and mute for AC3 playback */
1108 static int save_mixer_state(struct cmipci *cm)
1110 if (! cm->mixer_insensitive) {
1111 struct snd_ctl_elem_value *val;
1114 val = kmalloc(sizeof(*val), GFP_KERNEL);
1117 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1118 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1121 memset(val, 0, sizeof(*val));
1123 cm->mixer_res_status[i] = val->value.integer.value[0];
1124 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1125 event = SNDRV_CTL_EVENT_MASK_INFO;
1126 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1127 ctl->put(ctl, val); /* toggle */
1128 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1130 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1131 snd_ctl_notify(cm->card, event, &ctl->id);
1135 cm->mixer_insensitive = 1;
1141 /* restore the previously saved mixer status */
1142 static void restore_mixer_state(struct cmipci *cm)
1144 if (cm->mixer_insensitive) {
1145 struct snd_ctl_elem_value *val;
1148 val = kmalloc(sizeof(*val), GFP_KERNEL);
1151 cm->mixer_insensitive = 0; /* at first clear this;
1152 otherwise the changes will be ignored */
1153 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1154 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1158 memset(val, 0, sizeof(*val));
1159 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1161 event = SNDRV_CTL_EVENT_MASK_INFO;
1162 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1163 val->value.integer.value[0] = cm->mixer_res_status[i];
1165 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1167 snd_ctl_notify(cm->card, event, &ctl->id);
1174 /* spinlock held! */
1175 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1179 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1181 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1183 if (cm->can_ac3_hw) {
1184 /* SPD24SEL for 037, 0x02 */
1185 /* SPD24SEL for 039, 0x20, but cannot be set */
1186 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1187 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1188 } else { /* can_ac3_sw */
1189 /* SPD32SEL for 037 & 039, 0x20 */
1190 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1191 /* set 176K sample rate to fix 033 HW bug */
1192 if (cm->chip_version == 33) {
1193 if (rate >= 48000) {
1194 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1196 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1202 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1203 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1205 if (cm->can_ac3_hw) {
1206 /* chip model >= 37 */
1207 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1208 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1209 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1211 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1212 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1215 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1216 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1217 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1222 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1226 rate = subs->runtime->rate;
1229 if ((err = save_mixer_state(cm)) < 0)
1232 spin_lock_irq(&cm->reg_lock);
1233 cm->spdif_playback_avail = up;
1235 /* they are controlled via "IEC958 Output Switch" */
1236 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1237 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1238 if (cm->spdif_playback_enabled)
1239 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1240 setup_ac3(cm, subs, do_ac3, rate);
1242 if (rate == 48000 || rate == 96000)
1243 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1245 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1247 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1249 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1251 /* they are controlled via "IEC958 Output Switch" */
1252 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1253 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1254 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1255 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1256 setup_ac3(cm, subs, 0, 0);
1258 spin_unlock_irq(&cm->reg_lock);
1267 /* playback - enable spdif only on the certain condition */
1268 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1270 struct cmipci *cm = snd_pcm_substream_chip(substream);
1271 int rate = substream->runtime->rate;
1272 int err, do_spdif, do_ac3 = 0;
1274 do_spdif = (rate >= 44100 && rate <= 96000 &&
1275 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1276 substream->runtime->channels == 2);
1277 if (do_spdif && cm->can_ac3_hw)
1278 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1279 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1281 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1284 /* playback (via device #2) - enable spdif always */
1285 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1287 struct cmipci *cm = snd_pcm_substream_chip(substream);
1291 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1293 do_ac3 = 1; /* doesn't matter */
1294 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1296 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1300 * Apparently, the samples last played on channel A stay in some buffer, even
1301 * after the channel is reset, and get added to the data for the rear DACs when
1302 * playing a multichannel stream on channel B. This is likely to generate
1303 * wraparounds and thus distortions.
1304 * To avoid this, we play at least one zero sample after the actual stream has
1307 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1309 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1310 unsigned int reg, val;
1312 if (rec->needs_silencing && runtime && runtime->dma_area) {
1313 /* set up a small silence buffer */
1314 memset(runtime->dma_area, 0, PAGE_SIZE);
1315 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1316 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1317 snd_cmipci_write(cm, reg, val);
1319 /* configure for 16 bits, 2 channels, 8 kHz */
1320 if (runtime->channels > 2)
1321 set_dac_channels(cm, rec, 2);
1322 spin_lock_irq(&cm->reg_lock);
1323 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1324 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1325 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1326 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1327 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1328 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1329 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1331 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1332 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1334 /* start stream (we don't need interrupts) */
1335 cm->ctrl |= CM_CHEN0 << rec->ch;
1336 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1337 spin_unlock_irq(&cm->reg_lock);
1341 /* stop and reset stream */
1342 spin_lock_irq(&cm->reg_lock);
1343 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1344 val = CM_RST_CH0 << rec->ch;
1345 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1346 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1347 spin_unlock_irq(&cm->reg_lock);
1349 rec->needs_silencing = 0;
1353 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1355 struct cmipci *cm = snd_pcm_substream_chip(substream);
1356 setup_spdif_playback(cm, substream, 0, 0);
1357 restore_mixer_state(cm);
1358 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1362 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1364 struct cmipci *cm = snd_pcm_substream_chip(substream);
1365 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1370 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1372 struct cmipci *cm = snd_pcm_substream_chip(substream);
1373 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1376 /* capture with spdif (via device #2) */
1377 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1379 struct cmipci *cm = snd_pcm_substream_chip(substream);
1381 spin_lock_irq(&cm->reg_lock);
1382 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1384 if (substream->runtime->rate > 48000)
1385 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1387 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1389 if (snd_pcm_format_width(substream->runtime->format) > 16)
1390 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1392 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1394 spin_unlock_irq(&cm->reg_lock);
1396 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1399 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1401 struct cmipci *cm = snd_pcm_substream_chip(subs);
1403 spin_lock_irq(&cm->reg_lock);
1404 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1405 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1406 spin_unlock_irq(&cm->reg_lock);
1415 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1417 struct cmipci *cm = dev_id;
1418 unsigned int status, mask = 0;
1420 /* fastpath out, to ease interrupt sharing */
1421 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1422 if (!(status & CM_INTR))
1425 /* acknowledge interrupt */
1426 spin_lock(&cm->reg_lock);
1427 if (status & CM_CHINT0)
1428 mask |= CM_CH0_INT_EN;
1429 if (status & CM_CHINT1)
1430 mask |= CM_CH1_INT_EN;
1431 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1432 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1433 spin_unlock(&cm->reg_lock);
1435 if (cm->rmidi && (status & CM_UARTINT))
1436 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1439 if ((status & CM_CHINT0) && cm->channel[0].running)
1440 snd_pcm_period_elapsed(cm->channel[0].substream);
1441 if ((status & CM_CHINT1) && cm->channel[1].running)
1442 snd_pcm_period_elapsed(cm->channel[1].substream);
1451 /* playback on channel A */
1452 static const struct snd_pcm_hardware snd_cmipci_playback =
1454 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1455 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1456 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1457 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1458 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1463 .buffer_bytes_max = (128*1024),
1464 .period_bytes_min = 64,
1465 .period_bytes_max = (128*1024),
1467 .periods_max = 1024,
1471 /* capture on channel B */
1472 static const struct snd_pcm_hardware snd_cmipci_capture =
1474 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1475 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1476 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1477 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1478 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1483 .buffer_bytes_max = (128*1024),
1484 .period_bytes_min = 64,
1485 .period_bytes_max = (128*1024),
1487 .periods_max = 1024,
1491 /* playback on channel B - stereo 16bit only? */
1492 static const struct snd_pcm_hardware snd_cmipci_playback2 =
1494 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1495 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1496 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1497 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1498 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1503 .buffer_bytes_max = (128*1024),
1504 .period_bytes_min = 64,
1505 .period_bytes_max = (128*1024),
1507 .periods_max = 1024,
1511 /* spdif playback on channel A */
1512 static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1514 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1515 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1516 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1517 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1518 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1523 .buffer_bytes_max = (128*1024),
1524 .period_bytes_min = 64,
1525 .period_bytes_max = (128*1024),
1527 .periods_max = 1024,
1531 /* spdif playback on channel A (32bit, IEC958 subframes) */
1532 static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1534 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1535 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1536 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1537 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1538 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1543 .buffer_bytes_max = (128*1024),
1544 .period_bytes_min = 64,
1545 .period_bytes_max = (128*1024),
1547 .periods_max = 1024,
1551 /* spdif capture on channel B */
1552 static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1554 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1555 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1556 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1557 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1558 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1559 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1564 .buffer_bytes_max = (128*1024),
1565 .period_bytes_min = 64,
1566 .period_bytes_max = (128*1024),
1568 .periods_max = 1024,
1572 static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1573 32000, 44100, 48000, 88200, 96000, 128000 };
1574 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1575 .count = ARRAY_SIZE(rate_constraints),
1576 .list = rate_constraints,
1581 * check device open/close
1583 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1585 int ch = mode & CM_OPEN_CH_MASK;
1587 /* FIXME: a file should wait until the device becomes free
1588 * when it's opened on blocking mode. however, since the current
1589 * pcm framework doesn't pass file pointer before actually opened,
1590 * we can't know whether blocking mode or not in open callback..
1592 mutex_lock(&cm->open_mutex);
1593 if (cm->opened[ch]) {
1594 mutex_unlock(&cm->open_mutex);
1597 cm->opened[ch] = mode;
1598 cm->channel[ch].substream = subs;
1599 if (! (mode & CM_OPEN_DAC)) {
1600 /* disable dual DAC mode */
1601 cm->channel[ch].is_dac = 0;
1602 spin_lock_irq(&cm->reg_lock);
1603 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1604 spin_unlock_irq(&cm->reg_lock);
1606 mutex_unlock(&cm->open_mutex);
1610 static void close_device_check(struct cmipci *cm, int mode)
1612 int ch = mode & CM_OPEN_CH_MASK;
1614 mutex_lock(&cm->open_mutex);
1615 if (cm->opened[ch] == mode) {
1616 if (cm->channel[ch].substream) {
1617 snd_cmipci_ch_reset(cm, ch);
1618 cm->channel[ch].running = 0;
1619 cm->channel[ch].substream = NULL;
1622 if (! cm->channel[ch].is_dac) {
1623 /* enable dual DAC mode again */
1624 cm->channel[ch].is_dac = 1;
1625 spin_lock_irq(&cm->reg_lock);
1626 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1627 spin_unlock_irq(&cm->reg_lock);
1630 mutex_unlock(&cm->open_mutex);
1636 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1638 struct cmipci *cm = snd_pcm_substream_chip(substream);
1639 struct snd_pcm_runtime *runtime = substream->runtime;
1642 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1644 runtime->hw = snd_cmipci_playback;
1645 if (cm->chip_version == 68) {
1646 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1647 SNDRV_PCM_RATE_96000;
1648 runtime->hw.rate_max = 96000;
1649 } else if (cm->chip_version == 55) {
1650 err = snd_pcm_hw_constraint_list(runtime, 0,
1651 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1654 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1655 runtime->hw.rate_max = 128000;
1657 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1658 cm->dig_pcm_status = cm->dig_status;
1662 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1664 struct cmipci *cm = snd_pcm_substream_chip(substream);
1665 struct snd_pcm_runtime *runtime = substream->runtime;
1668 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1670 runtime->hw = snd_cmipci_capture;
1671 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1672 runtime->hw.rate_min = 41000;
1673 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1674 } else if (cm->chip_version == 55) {
1675 err = snd_pcm_hw_constraint_list(runtime, 0,
1676 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1679 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1680 runtime->hw.rate_max = 128000;
1682 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1686 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1688 struct cmipci *cm = snd_pcm_substream_chip(substream);
1689 struct snd_pcm_runtime *runtime = substream->runtime;
1692 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1694 runtime->hw = snd_cmipci_playback2;
1695 mutex_lock(&cm->open_mutex);
1696 if (! cm->opened[CM_CH_PLAY]) {
1697 if (cm->can_multi_ch) {
1698 runtime->hw.channels_max = cm->max_channels;
1699 if (cm->max_channels == 4)
1700 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1701 else if (cm->max_channels == 6)
1702 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1703 else if (cm->max_channels == 8)
1704 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1707 mutex_unlock(&cm->open_mutex);
1708 if (cm->chip_version == 68) {
1709 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1710 SNDRV_PCM_RATE_96000;
1711 runtime->hw.rate_max = 96000;
1712 } else if (cm->chip_version == 55) {
1713 err = snd_pcm_hw_constraint_list(runtime, 0,
1714 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1717 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1718 runtime->hw.rate_max = 128000;
1720 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1724 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1726 struct cmipci *cm = snd_pcm_substream_chip(substream);
1727 struct snd_pcm_runtime *runtime = substream->runtime;
1730 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1732 if (cm->can_ac3_hw) {
1733 runtime->hw = snd_cmipci_playback_spdif;
1734 if (cm->chip_version >= 37) {
1735 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1736 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1739 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1740 SNDRV_PCM_RATE_96000;
1741 runtime->hw.rate_max = 96000;
1744 runtime->hw = snd_cmipci_playback_iec958_subframe;
1746 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1747 cm->dig_pcm_status = cm->dig_status;
1751 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1753 struct cmipci *cm = snd_pcm_substream_chip(substream);
1754 struct snd_pcm_runtime *runtime = substream->runtime;
1757 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1759 runtime->hw = snd_cmipci_capture_spdif;
1760 if (cm->can_96k && !(cm->chip_version == 68)) {
1761 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1762 SNDRV_PCM_RATE_96000;
1763 runtime->hw.rate_max = 96000;
1765 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1773 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1775 struct cmipci *cm = snd_pcm_substream_chip(substream);
1776 close_device_check(cm, CM_OPEN_PLAYBACK);
1780 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1782 struct cmipci *cm = snd_pcm_substream_chip(substream);
1783 close_device_check(cm, CM_OPEN_CAPTURE);
1787 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1789 struct cmipci *cm = snd_pcm_substream_chip(substream);
1790 close_device_check(cm, CM_OPEN_PLAYBACK2);
1791 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1795 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1797 struct cmipci *cm = snd_pcm_substream_chip(substream);
1798 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1802 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1804 struct cmipci *cm = snd_pcm_substream_chip(substream);
1805 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1813 static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1814 .open = snd_cmipci_playback_open,
1815 .close = snd_cmipci_playback_close,
1816 .hw_free = snd_cmipci_playback_hw_free,
1817 .prepare = snd_cmipci_playback_prepare,
1818 .trigger = snd_cmipci_playback_trigger,
1819 .pointer = snd_cmipci_playback_pointer,
1822 static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1823 .open = snd_cmipci_capture_open,
1824 .close = snd_cmipci_capture_close,
1825 .prepare = snd_cmipci_capture_prepare,
1826 .trigger = snd_cmipci_capture_trigger,
1827 .pointer = snd_cmipci_capture_pointer,
1830 static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1831 .open = snd_cmipci_playback2_open,
1832 .close = snd_cmipci_playback2_close,
1833 .hw_params = snd_cmipci_playback2_hw_params,
1834 .hw_free = snd_cmipci_playback2_hw_free,
1835 .prepare = snd_cmipci_capture_prepare, /* channel B */
1836 .trigger = snd_cmipci_capture_trigger, /* channel B */
1837 .pointer = snd_cmipci_capture_pointer, /* channel B */
1840 static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1841 .open = snd_cmipci_playback_spdif_open,
1842 .close = snd_cmipci_playback_spdif_close,
1843 .hw_free = snd_cmipci_playback_hw_free,
1844 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1845 .trigger = snd_cmipci_playback_trigger,
1846 .pointer = snd_cmipci_playback_pointer,
1849 static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1850 .open = snd_cmipci_capture_spdif_open,
1851 .close = snd_cmipci_capture_spdif_close,
1852 .hw_free = snd_cmipci_capture_spdif_hw_free,
1853 .prepare = snd_cmipci_capture_spdif_prepare,
1854 .trigger = snd_cmipci_capture_trigger,
1855 .pointer = snd_cmipci_capture_pointer,
1862 static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1864 struct snd_pcm *pcm;
1867 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1871 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1872 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1874 pcm->private_data = cm;
1875 pcm->info_flags = 0;
1876 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1879 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1880 &cm->pci->dev, 64*1024, 128*1024);
1885 static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1887 struct snd_pcm *pcm;
1890 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1894 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1896 pcm->private_data = cm;
1897 pcm->info_flags = 0;
1898 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1901 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1902 &cm->pci->dev, 64*1024, 128*1024);
1907 static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1909 struct snd_pcm *pcm;
1912 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1916 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1917 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1919 pcm->private_data = cm;
1920 pcm->info_flags = 0;
1921 strcpy(pcm->name, "C-Media PCI IEC958");
1922 cm->pcm_spdif = pcm;
1924 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1925 &cm->pci->dev, 64*1024, 128*1024);
1927 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1928 snd_pcm_alt_chmaps, cm->max_channels, 0,
1938 * - CM8338/8738 has a compatible mixer interface with SB16, but
1939 * lack of some elements like tone control, i/o gain and AGC.
1940 * - Access to native registers:
1942 * - Output mute switches
1945 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1947 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1948 outb(data, s->iobase + CM_REG_SB16_DATA);
1951 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1955 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1956 v = inb(s->iobase + CM_REG_SB16_DATA);
1961 * general mixer element
1963 struct cmipci_sb_reg {
1964 unsigned int left_reg, right_reg;
1965 unsigned int left_shift, right_shift;
1967 unsigned int invert: 1;
1968 unsigned int stereo: 1;
1971 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1972 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1974 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1975 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1976 .info = snd_cmipci_info_volume, \
1977 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1978 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1981 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1982 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1983 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1984 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1986 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1988 r->left_reg = val & 0xff;
1989 r->right_reg = (val >> 8) & 0xff;
1990 r->left_shift = (val >> 16) & 0x07;
1991 r->right_shift = (val >> 19) & 0x07;
1992 r->invert = (val >> 22) & 1;
1993 r->stereo = (val >> 23) & 1;
1994 r->mask = (val >> 24) & 0xff;
1997 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
1998 struct snd_ctl_elem_info *uinfo)
2000 struct cmipci_sb_reg reg;
2002 cmipci_sb_reg_decode(®, kcontrol->private_value);
2003 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2004 uinfo->count = reg.stereo + 1;
2005 uinfo->value.integer.min = 0;
2006 uinfo->value.integer.max = reg.mask;
2010 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2011 struct snd_ctl_elem_value *ucontrol)
2013 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2014 struct cmipci_sb_reg reg;
2017 cmipci_sb_reg_decode(®, kcontrol->private_value);
2018 spin_lock_irq(&cm->reg_lock);
2019 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2021 val = reg.mask - val;
2022 ucontrol->value.integer.value[0] = val;
2024 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2026 val = reg.mask - val;
2027 ucontrol->value.integer.value[1] = val;
2029 spin_unlock_irq(&cm->reg_lock);
2033 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2034 struct snd_ctl_elem_value *ucontrol)
2036 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2037 struct cmipci_sb_reg reg;
2039 int left, right, oleft, oright;
2041 cmipci_sb_reg_decode(®, kcontrol->private_value);
2042 left = ucontrol->value.integer.value[0] & reg.mask;
2044 left = reg.mask - left;
2045 left <<= reg.left_shift;
2047 right = ucontrol->value.integer.value[1] & reg.mask;
2049 right = reg.mask - right;
2050 right <<= reg.right_shift;
2053 spin_lock_irq(&cm->reg_lock);
2054 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2055 left |= oleft & ~(reg.mask << reg.left_shift);
2056 change = left != oleft;
2058 if (reg.left_reg != reg.right_reg) {
2059 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2060 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2063 right |= oright & ~(reg.mask << reg.right_shift);
2064 change |= right != oright;
2065 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2067 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2068 spin_unlock_irq(&cm->reg_lock);
2073 * input route (left,right) -> (left,right)
2075 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2076 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2077 .info = snd_cmipci_info_input_sw, \
2078 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2079 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2082 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2083 struct snd_ctl_elem_info *uinfo)
2085 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2087 uinfo->value.integer.min = 0;
2088 uinfo->value.integer.max = 1;
2092 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2093 struct snd_ctl_elem_value *ucontrol)
2095 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2096 struct cmipci_sb_reg reg;
2099 cmipci_sb_reg_decode(®, kcontrol->private_value);
2100 spin_lock_irq(&cm->reg_lock);
2101 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2102 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2103 spin_unlock_irq(&cm->reg_lock);
2104 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2105 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2106 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2107 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2111 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2112 struct snd_ctl_elem_value *ucontrol)
2114 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2115 struct cmipci_sb_reg reg;
2117 int val1, val2, oval1, oval2;
2119 cmipci_sb_reg_decode(®, kcontrol->private_value);
2120 spin_lock_irq(&cm->reg_lock);
2121 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2122 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2123 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2124 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2125 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2126 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2127 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2128 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2129 change = val1 != oval1 || val2 != oval2;
2130 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2131 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2132 spin_unlock_irq(&cm->reg_lock);
2137 * native mixer switches/volumes
2140 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2141 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2142 .info = snd_cmipci_info_native_mixer, \
2143 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2144 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2147 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2148 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2149 .info = snd_cmipci_info_native_mixer, \
2150 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2151 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2154 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2155 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2156 .info = snd_cmipci_info_native_mixer, \
2157 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2158 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2161 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2162 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2163 .info = snd_cmipci_info_native_mixer, \
2164 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2165 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2168 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2169 struct snd_ctl_elem_info *uinfo)
2171 struct cmipci_sb_reg reg;
2173 cmipci_sb_reg_decode(®, kcontrol->private_value);
2174 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2175 uinfo->count = reg.stereo + 1;
2176 uinfo->value.integer.min = 0;
2177 uinfo->value.integer.max = reg.mask;
2182 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2183 struct snd_ctl_elem_value *ucontrol)
2185 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2186 struct cmipci_sb_reg reg;
2187 unsigned char oreg, val;
2189 cmipci_sb_reg_decode(®, kcontrol->private_value);
2190 spin_lock_irq(&cm->reg_lock);
2191 oreg = inb(cm->iobase + reg.left_reg);
2192 val = (oreg >> reg.left_shift) & reg.mask;
2194 val = reg.mask - val;
2195 ucontrol->value.integer.value[0] = val;
2197 val = (oreg >> reg.right_shift) & reg.mask;
2199 val = reg.mask - val;
2200 ucontrol->value.integer.value[1] = val;
2202 spin_unlock_irq(&cm->reg_lock);
2206 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2207 struct snd_ctl_elem_value *ucontrol)
2209 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2210 struct cmipci_sb_reg reg;
2211 unsigned char oreg, nreg, val;
2213 cmipci_sb_reg_decode(®, kcontrol->private_value);
2214 spin_lock_irq(&cm->reg_lock);
2215 oreg = inb(cm->iobase + reg.left_reg);
2216 val = ucontrol->value.integer.value[0] & reg.mask;
2218 val = reg.mask - val;
2219 nreg = oreg & ~(reg.mask << reg.left_shift);
2220 nreg |= (val << reg.left_shift);
2222 val = ucontrol->value.integer.value[1] & reg.mask;
2224 val = reg.mask - val;
2225 nreg &= ~(reg.mask << reg.right_shift);
2226 nreg |= (val << reg.right_shift);
2228 outb(nreg, cm->iobase + reg.left_reg);
2229 spin_unlock_irq(&cm->reg_lock);
2230 return (nreg != oreg);
2234 * special case - check mixer sensitivity
2236 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2237 struct snd_ctl_elem_value *ucontrol)
2239 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2240 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2243 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2244 struct snd_ctl_elem_value *ucontrol)
2246 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2247 if (cm->mixer_insensitive) {
2251 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2255 static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2256 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2257 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2258 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2259 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2260 { /* switch with sensitivity */
2261 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2262 .name = "PCM Playback Switch",
2263 .info = snd_cmipci_info_native_mixer,
2264 .get = snd_cmipci_get_native_mixer_sensitive,
2265 .put = snd_cmipci_put_native_mixer_sensitive,
2266 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2268 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2269 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2270 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2271 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2272 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2273 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2274 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2275 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2276 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2277 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2278 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2279 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2280 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2281 CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2282 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2283 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2284 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2285 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2286 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2287 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2288 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2289 CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2290 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2297 struct cmipci_switch_args {
2298 int reg; /* register index */
2299 unsigned int mask; /* mask bits */
2300 unsigned int mask_on; /* mask bits to turn on */
2301 unsigned int is_byte: 1; /* byte access? */
2302 unsigned int ac3_sensitive: 1; /* access forbidden during
2303 * non-audio operation?
2307 #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2309 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2310 struct snd_ctl_elem_value *ucontrol,
2311 struct cmipci_switch_args *args)
2314 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2316 spin_lock_irq(&cm->reg_lock);
2317 if (args->ac3_sensitive && cm->mixer_insensitive) {
2318 ucontrol->value.integer.value[0] = 0;
2319 spin_unlock_irq(&cm->reg_lock);
2323 val = inb(cm->iobase + args->reg);
2325 val = snd_cmipci_read(cm, args->reg);
2326 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2327 spin_unlock_irq(&cm->reg_lock);
2331 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2332 struct snd_ctl_elem_value *ucontrol)
2334 struct cmipci_switch_args *args;
2335 args = (struct cmipci_switch_args *)kcontrol->private_value;
2336 if (snd_BUG_ON(!args))
2338 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2341 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2342 struct snd_ctl_elem_value *ucontrol,
2343 struct cmipci_switch_args *args)
2347 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2349 spin_lock_irq(&cm->reg_lock);
2350 if (args->ac3_sensitive && cm->mixer_insensitive) {
2352 spin_unlock_irq(&cm->reg_lock);
2356 val = inb(cm->iobase + args->reg);
2358 val = snd_cmipci_read(cm, args->reg);
2359 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2360 args->mask_on : (args->mask & ~args->mask_on));
2363 if (ucontrol->value.integer.value[0])
2364 val |= args->mask_on;
2366 val |= (args->mask & ~args->mask_on);
2368 outb((unsigned char)val, cm->iobase + args->reg);
2370 snd_cmipci_write(cm, args->reg, val);
2372 spin_unlock_irq(&cm->reg_lock);
2376 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2377 struct snd_ctl_elem_value *ucontrol)
2379 struct cmipci_switch_args *args;
2380 args = (struct cmipci_switch_args *)kcontrol->private_value;
2381 if (snd_BUG_ON(!args))
2383 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2386 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2387 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2390 .mask_on = xmask_on, \
2391 .is_byte = xis_byte, \
2392 .ac3_sensitive = xac3, \
2395 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2396 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2398 #if 0 /* these will be controlled in pcm device */
2399 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2400 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2402 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2403 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2404 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2405 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2406 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2407 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2408 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2409 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2410 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2411 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2412 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2413 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2414 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2415 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2417 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2419 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2421 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2422 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2423 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2424 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2425 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2427 #define DEFINE_SWITCH(sname, stype, sarg) \
2430 .info = snd_cmipci_uswitch_info, \
2431 .get = snd_cmipci_uswitch_get, \
2432 .put = snd_cmipci_uswitch_put, \
2433 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2436 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2437 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2441 * callbacks for spdif output switch
2442 * needs toggle two registers..
2444 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2445 struct snd_ctl_elem_value *ucontrol)
2448 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2449 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2453 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2454 struct snd_ctl_elem_value *ucontrol)
2456 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2458 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2459 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2461 if (ucontrol->value.integer.value[0]) {
2462 if (chip->spdif_playback_avail)
2463 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2465 if (chip->spdif_playback_avail)
2466 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2469 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2474 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2475 struct snd_ctl_elem_info *uinfo)
2477 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2478 static const char *const texts[3] = {
2479 "Line-In", "Rear Output", "Bass Output"
2482 return snd_ctl_enum_info(uinfo, 1,
2483 cm->chip_version >= 39 ? 3 : 2, texts);
2486 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2489 if (cm->chip_version >= 39) {
2490 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2491 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2494 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2495 if (val & CM_REAR2LIN)
2500 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2501 struct snd_ctl_elem_value *ucontrol)
2503 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2505 spin_lock_irq(&cm->reg_lock);
2506 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2507 spin_unlock_irq(&cm->reg_lock);
2511 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2512 struct snd_ctl_elem_value *ucontrol)
2514 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2517 spin_lock_irq(&cm->reg_lock);
2518 if (ucontrol->value.enumerated.item[0] == 2)
2519 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2521 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2522 if (ucontrol->value.enumerated.item[0] == 1)
2523 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2525 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2526 spin_unlock_irq(&cm->reg_lock);
2530 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2531 struct snd_ctl_elem_info *uinfo)
2533 static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2535 return snd_ctl_enum_info(uinfo, 1, 2, texts);
2538 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2539 struct snd_ctl_elem_value *ucontrol)
2541 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2542 /* same bit as spdi_phase */
2543 spin_lock_irq(&cm->reg_lock);
2544 ucontrol->value.enumerated.item[0] =
2545 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2546 spin_unlock_irq(&cm->reg_lock);
2550 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2551 struct snd_ctl_elem_value *ucontrol)
2553 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2556 spin_lock_irq(&cm->reg_lock);
2557 if (ucontrol->value.enumerated.item[0])
2558 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2560 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2561 spin_unlock_irq(&cm->reg_lock);
2565 /* both for CM8338/8738 */
2566 static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2567 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2569 .name = "Line-In Mode",
2570 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2571 .info = snd_cmipci_line_in_mode_info,
2572 .get = snd_cmipci_line_in_mode_get,
2573 .put = snd_cmipci_line_in_mode_put,
2577 /* for non-multichannel chips */
2578 static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2579 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2581 /* only for CM8738 */
2582 static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2583 #if 0 /* controlled in pcm device */
2584 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2585 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2586 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2588 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2589 { .name = "IEC958 Output Switch",
2590 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2591 .info = snd_cmipci_uswitch_info,
2592 .get = snd_cmipci_spdout_enable_get,
2593 .put = snd_cmipci_spdout_enable_put,
2595 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2596 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2597 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2598 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2599 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2600 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2603 /* only for model 033/037 */
2604 static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2605 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2606 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2607 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2610 /* only for model 039 or later */
2611 static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2612 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2613 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2615 .name = "Mic-In Mode",
2616 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2617 .info = snd_cmipci_mic_in_mode_info,
2618 .get = snd_cmipci_mic_in_mode_get,
2619 .put = snd_cmipci_mic_in_mode_put,
2623 /* card control switches */
2624 static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2625 DEFINE_CARD_SWITCH("Modem", modem);
2628 static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2630 struct snd_card *card;
2631 const struct snd_kcontrol_new *sw;
2632 struct snd_kcontrol *kctl;
2636 if (snd_BUG_ON(!cm || !cm->card))
2641 strcpy(card->mixername, "CMedia PCI");
2643 spin_lock_irq(&cm->reg_lock);
2644 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2645 spin_unlock_irq(&cm->reg_lock);
2647 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2648 if (cm->chip_version == 68) { // 8768 has no PCM volume
2649 if (!strcmp(snd_cmipci_mixers[idx].name,
2650 "PCM Playback Volume"))
2653 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2657 /* mixer switches */
2658 sw = snd_cmipci_mixer_switches;
2659 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2660 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2664 if (! cm->can_multi_ch) {
2665 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2669 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2670 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2671 sw = snd_cmipci_8738_mixer_switches;
2672 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2673 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2677 if (cm->can_ac3_hw) {
2678 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2680 kctl->id.device = pcm_spdif_device;
2681 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2683 kctl->id.device = pcm_spdif_device;
2684 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2686 kctl->id.device = pcm_spdif_device;
2688 if (cm->chip_version <= 37) {
2689 sw = snd_cmipci_old_mixer_switches;
2690 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2691 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2697 if (cm->chip_version >= 39) {
2698 sw = snd_cmipci_extra_mixer_switches;
2699 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2700 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2708 * newer chips don't have the register bits to force modem link
2709 * detection; the bit that was FLINKON now mutes CH1
2711 if (cm->chip_version < 39) {
2712 err = snd_ctl_add(cm->card,
2713 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2718 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2719 struct snd_ctl_elem_id elem_id;
2720 struct snd_kcontrol *ctl;
2721 memset(&elem_id, 0, sizeof(elem_id));
2722 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2723 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2724 ctl = snd_ctl_find_id(cm->card, &elem_id);
2726 cm->mixer_res_ctl[idx] = ctl;
2737 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2738 struct snd_info_buffer *buffer)
2740 struct cmipci *cm = entry->private_data;
2743 snd_iprintf(buffer, "%s\n", cm->card->longname);
2744 for (i = 0; i < 0x94; i++) {
2747 v = inb(cm->iobase + i);
2749 snd_iprintf(buffer, "\n%02x:", i);
2750 snd_iprintf(buffer, " %02x", v);
2752 snd_iprintf(buffer, "\n");
2755 static void snd_cmipci_proc_init(struct cmipci *cm)
2757 snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2760 static const struct pci_device_id snd_cmipci_ids[] = {
2761 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2762 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2763 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2764 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2765 {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2771 * check chip version and capabilities
2772 * driver name is modified according to the chip model
2774 static void query_chip(struct cmipci *cm)
2776 unsigned int detect;
2778 /* check reg 0Ch, bit 24-31 */
2779 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2781 /* check reg 08h, bit 24-28 */
2782 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2785 cm->chip_version = 33;
2786 if (cm->do_soft_ac3)
2792 cm->chip_version = 37;
2796 cm->chip_version = 39;
2800 cm->max_channels = 2;
2802 if (detect & CM_CHIP_039) {
2803 cm->chip_version = 39;
2804 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2805 cm->max_channels = 6;
2807 cm->max_channels = 4;
2808 } else if (detect & CM_CHIP_8768) {
2809 cm->chip_version = 68;
2810 cm->max_channels = 8;
2813 cm->chip_version = 55;
2814 cm->max_channels = 6;
2818 cm->can_multi_ch = 1;
2822 #ifdef SUPPORT_JOYSTICK
2823 static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2825 static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2826 struct gameport *gp;
2827 struct resource *r = NULL;
2830 if (joystick_port[dev] == 0)
2833 if (joystick_port[dev] == 1) { /* auto-detect */
2834 for (i = 0; ports[i]; i++) {
2836 r = request_region(io_port, 1, "CMIPCI gameport");
2841 io_port = joystick_port[dev];
2842 r = request_region(io_port, 1, "CMIPCI gameport");
2846 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2850 cm->gameport = gp = gameport_allocate_port();
2852 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2853 release_and_free_resource(r);
2856 gameport_set_name(gp, "C-Media Gameport");
2857 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2858 gameport_set_dev_parent(gp, &cm->pci->dev);
2860 gameport_set_port_data(gp, r);
2862 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2864 gameport_register_port(cm->gameport);
2869 static void snd_cmipci_free_gameport(struct cmipci *cm)
2872 struct resource *r = gameport_get_port_data(cm->gameport);
2874 gameport_unregister_port(cm->gameport);
2875 cm->gameport = NULL;
2877 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2878 release_and_free_resource(r);
2882 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2883 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2886 static int snd_cmipci_free(struct cmipci *cm)
2889 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2890 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2891 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2892 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2893 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2894 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2895 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2898 snd_cmipci_mixer_write(cm, 0, 0);
2900 free_irq(cm->irq, cm);
2903 snd_cmipci_free_gameport(cm);
2904 pci_release_regions(cm->pci);
2905 pci_disable_device(cm->pci);
2910 static int snd_cmipci_dev_free(struct snd_device *device)
2912 struct cmipci *cm = device->device_data;
2913 return snd_cmipci_free(cm);
2916 static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2920 struct snd_opl3 *opl3;
2926 if (cm->chip_version >= 39) {
2927 /* first try FM regs in PCI port range */
2928 iosynth = cm->iobase + CM_REG_FM_PCI;
2929 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2930 OPL3_HW_OPL3, 1, &opl3);
2935 /* then try legacy ports */
2936 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2939 case 0x3E8: val |= CM_FMSEL_3E8; break;
2940 case 0x3E0: val |= CM_FMSEL_3E0; break;
2941 case 0x3C8: val |= CM_FMSEL_3C8; break;
2942 case 0x388: val |= CM_FMSEL_388; break;
2946 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2948 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2950 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2951 OPL3_HW_OPL3, 0, &opl3) < 0) {
2952 dev_err(cm->card->dev,
2953 "no OPL device at %#lx, skipping...\n",
2958 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2959 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2965 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2966 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2970 static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2971 int dev, struct cmipci **rcmipci)
2975 static const struct snd_device_ops ops = {
2976 .dev_free = snd_cmipci_dev_free,
2980 int integrated_midi = 0;
2982 int pcm_index, pcm_spdif_index;
2983 static const struct pci_device_id intel_82437vx[] = {
2984 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2990 if ((err = pci_enable_device(pci)) < 0)
2993 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2995 pci_disable_device(pci);
2999 spin_lock_init(&cm->reg_lock);
3000 mutex_init(&cm->open_mutex);
3001 cm->device = pci->device;
3005 cm->channel[0].ch = 0;
3006 cm->channel[1].ch = 1;
3007 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3009 if ((err = pci_request_regions(pci, card->driver)) < 0) {
3011 pci_disable_device(pci);
3014 cm->iobase = pci_resource_start(pci, 0);
3016 if (request_irq(pci->irq, snd_cmipci_interrupt,
3017 IRQF_SHARED, KBUILD_MODNAME, cm)) {
3018 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3019 snd_cmipci_free(cm);
3023 card->sync_irq = cm->irq;
3025 pci_set_master(cm->pci);
3028 * check chip version, max channels and capabilities
3031 cm->chip_version = 0;
3032 cm->max_channels = 2;
3033 cm->do_soft_ac3 = soft_ac3[dev];
3035 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3036 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3038 /* added -MCx suffix for chip supporting multi-channels */
3039 if (cm->can_multi_ch)
3040 sprintf(cm->card->driver + strlen(cm->card->driver),
3041 "-MC%d", cm->max_channels);
3042 else if (cm->can_ac3_sw)
3043 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3045 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3046 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3049 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3051 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3054 /* initialize codec registers */
3055 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3056 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3057 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3058 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3059 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3060 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3061 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3063 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3064 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3066 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3068 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3070 if (cm->chip_version) {
3071 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3072 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3074 /* Set Bus Master Request */
3075 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3077 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3078 switch (pci->device) {
3079 case PCI_DEVICE_ID_CMEDIA_CM8738:
3080 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3081 if (!pci_dev_present(intel_82437vx))
3082 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3088 if (cm->chip_version < 68) {
3089 val = pci->device < 0x110 ? 8338 : 8738;
3091 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3099 switch ((pci->subsystem_vendor << 16) |
3100 pci->subsystem_device) {
3115 sprintf(card->shortname, "C-Media CMI%d", val);
3116 if (cm->chip_version < 68)
3117 sprintf(modelstr, " (model %d)", cm->chip_version);
3120 sprintf(card->longname, "%s%s at %#lx, irq %i",
3121 card->shortname, modelstr, cm->iobase, cm->irq);
3123 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3124 snd_cmipci_free(cm);
3128 if (cm->chip_version >= 39) {
3129 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3130 if (val != 0x00 && val != 0xff) {
3132 iomidi = cm->iobase + CM_REG_MPU_PCI;
3133 integrated_midi = 1;
3136 if (!integrated_midi) {
3138 iomidi = mpu_port[dev];
3140 case 0x320: val = CM_VMPU_320; break;
3141 case 0x310: val = CM_VMPU_310; break;
3142 case 0x300: val = CM_VMPU_300; break;
3143 case 0x330: val = CM_VMPU_330; break;
3148 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3150 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3151 if (inb(iomidi + 1) == 0xff) {
3152 dev_err(cm->card->dev,
3153 "cannot enable MPU-401 port at %#lx\n",
3155 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3162 if (cm->chip_version < 68) {
3163 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3169 snd_cmipci_mixer_write(cm, 0, 0);
3171 snd_cmipci_proc_init(cm);
3173 /* create pcm devices */
3174 pcm_index = pcm_spdif_index = 0;
3175 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3178 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3181 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3182 pcm_spdif_index = pcm_index;
3183 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3187 /* create mixer interface & switches */
3188 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3192 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3195 MPU401_INFO_INTEGRATED : 0) |
3196 MPU401_INFO_IRQ_HOOK,
3197 -1, &cm->rmidi)) < 0) {
3198 dev_err(cm->card->dev,
3199 "no UART401 device at 0x%lx\n", iomidi);
3203 #ifdef USE_VAR48KRATE
3204 for (val = 0; val < ARRAY_SIZE(rates); val++)
3205 snd_cmipci_set_pll(cm, rates[val], val);
3208 * (Re-)Enable external switch spdo_48k
3210 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3211 #endif /* USE_VAR48KRATE */
3213 if (snd_cmipci_create_gameport(cm, dev) < 0)
3214 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3223 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3225 static int snd_cmipci_probe(struct pci_dev *pci,
3226 const struct pci_device_id *pci_id)
3229 struct snd_card *card;
3233 if (dev >= SNDRV_CARDS)
3235 if (! enable[dev]) {
3240 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3245 switch (pci->device) {
3246 case PCI_DEVICE_ID_CMEDIA_CM8738:
3247 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3248 strcpy(card->driver, "CMI8738");
3250 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3251 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3252 strcpy(card->driver, "CMI8338");
3255 strcpy(card->driver, "CMIPCI");
3259 err = snd_cmipci_create(card, pci, dev, &cm);
3263 card->private_data = cm;
3265 err = snd_card_register(card);
3269 pci_set_drvdata(pci, card);
3274 snd_card_free(card);
3278 static void snd_cmipci_remove(struct pci_dev *pci)
3280 snd_card_free(pci_get_drvdata(pci));
3284 #ifdef CONFIG_PM_SLEEP
3288 static const unsigned char saved_regs[] = {
3289 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3290 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3291 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3292 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3293 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3296 static const unsigned char saved_mixers[] = {
3297 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3298 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3299 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3300 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3301 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3302 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3303 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3304 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3307 static int snd_cmipci_suspend(struct device *dev)
3309 struct snd_card *card = dev_get_drvdata(dev);
3310 struct cmipci *cm = card->private_data;
3313 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3315 /* save registers */
3316 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3317 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3318 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3319 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3322 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3326 static int snd_cmipci_resume(struct device *dev)
3328 struct snd_card *card = dev_get_drvdata(dev);
3329 struct cmipci *cm = card->private_data;
3332 /* reset / initialize to a sane state */
3333 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3334 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3335 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3336 snd_cmipci_mixer_write(cm, 0, 0);
3338 /* restore registers */
3339 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3340 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3341 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3342 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3344 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3348 static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3349 #define SND_CMIPCI_PM_OPS &snd_cmipci_pm
3351 #define SND_CMIPCI_PM_OPS NULL
3352 #endif /* CONFIG_PM_SLEEP */
3354 static struct pci_driver cmipci_driver = {
3355 .name = KBUILD_MODNAME,
3356 .id_table = snd_cmipci_ids,
3357 .probe = snd_cmipci_probe,
3358 .remove = snd_cmipci_remove,
3360 .pm = SND_CMIPCI_PM_OPS,
3364 module_pci_driver(cmipci_driver);