Merge tag 'gpio-updates-for-v5.13-v2' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-microblaze.git] / sound / hda / hdac_stream.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * HD-audio stream operations
4  */
5
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <linux/clocksource.h>
10 #include <sound/core.h>
11 #include <sound/pcm.h>
12 #include <sound/hdaudio.h>
13 #include <sound/hda_register.h>
14 #include "trace.h"
15
16 /**
17  * snd_hdac_get_stream_stripe_ctl - get stripe control value
18  * @bus: HD-audio core bus
19  * @substream: PCM substream
20  */
21 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
22                                    struct snd_pcm_substream *substream)
23 {
24         struct snd_pcm_runtime *runtime = substream->runtime;
25         unsigned int channels = runtime->channels,
26                      rate = runtime->rate,
27                      bits_per_sample = runtime->sample_bits,
28                      max_sdo_lines, value, sdo_line;
29
30         /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
31         max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
32
33         /* following is from HD audio spec */
34         for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
35                 if (rate > 48000)
36                         value = (channels * bits_per_sample *
37                                         (rate / 48000)) / sdo_line;
38                 else
39                         value = (channels * bits_per_sample) / sdo_line;
40
41                 if (value >= bus->sdo_limit)
42                         break;
43         }
44
45         /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
46         return sdo_line >> 1;
47 }
48 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
49
50 /**
51  * snd_hdac_stream_init - initialize each stream (aka device)
52  * @bus: HD-audio core bus
53  * @azx_dev: HD-audio core stream object to initialize
54  * @idx: stream index number
55  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
56  * @tag: the tag id to assign
57  *
58  * Assign the starting bdl address to each stream (device) and initialize.
59  */
60 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
61                           int idx, int direction, int tag)
62 {
63         azx_dev->bus = bus;
64         /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
65         azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
66         /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
67         azx_dev->sd_int_sta_mask = 1 << idx;
68         azx_dev->index = idx;
69         azx_dev->direction = direction;
70         azx_dev->stream_tag = tag;
71         snd_hdac_dsp_lock_init(azx_dev);
72         list_add_tail(&azx_dev->list, &bus->stream_list);
73 }
74 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
75
76 /**
77  * snd_hdac_stream_start - start a stream
78  * @azx_dev: HD-audio core stream to start
79  * @fresh_start: false = wallclock timestamp relative to period wallclock
80  *
81  * Start a stream, set start_wallclk and set the running flag.
82  */
83 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
84 {
85         struct hdac_bus *bus = azx_dev->bus;
86         int stripe_ctl;
87
88         trace_snd_hdac_stream_start(bus, azx_dev);
89
90         azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
91         if (!fresh_start)
92                 azx_dev->start_wallclk -= azx_dev->period_wallclk;
93
94         /* enable SIE */
95         snd_hdac_chip_updatel(bus, INTCTL,
96                               1 << azx_dev->index,
97                               1 << azx_dev->index);
98         /* set stripe control */
99         if (azx_dev->stripe) {
100                 if (azx_dev->substream)
101                         stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
102                 else
103                         stripe_ctl = 0;
104                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
105                                         stripe_ctl);
106         }
107         /* set DMA start and interrupt mask */
108         snd_hdac_stream_updateb(azx_dev, SD_CTL,
109                                 0, SD_CTL_DMA_START | SD_INT_MASK);
110         azx_dev->running = true;
111 }
112 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
113
114 /**
115  * snd_hdac_stream_clear - stop a stream DMA
116  * @azx_dev: HD-audio core stream to stop
117  */
118 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
119 {
120         snd_hdac_stream_updateb(azx_dev, SD_CTL,
121                                 SD_CTL_DMA_START | SD_INT_MASK, 0);
122         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
123         if (azx_dev->stripe)
124                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
125         azx_dev->running = false;
126 }
127 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
128
129 /**
130  * snd_hdac_stream_stop - stop a stream
131  * @azx_dev: HD-audio core stream to stop
132  *
133  * Stop a stream DMA and disable stream interrupt
134  */
135 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
136 {
137         trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
138
139         snd_hdac_stream_clear(azx_dev);
140         /* disable SIE */
141         snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
142 }
143 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
144
145 /**
146  * snd_hdac_stream_reset - reset a stream
147  * @azx_dev: HD-audio core stream to reset
148  */
149 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
150 {
151         unsigned char val;
152         int timeout;
153         int dma_run_state;
154
155         snd_hdac_stream_clear(azx_dev);
156
157         dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
158
159         snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
160         udelay(3);
161         timeout = 300;
162         do {
163                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
164                         SD_CTL_STREAM_RESET;
165                 if (val)
166                         break;
167         } while (--timeout);
168
169         if (azx_dev->bus->dma_stop_delay && dma_run_state)
170                 udelay(azx_dev->bus->dma_stop_delay);
171
172         val &= ~SD_CTL_STREAM_RESET;
173         snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
174         udelay(3);
175
176         timeout = 300;
177         /* waiting for hardware to report that the stream is out of reset */
178         do {
179                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
180                         SD_CTL_STREAM_RESET;
181                 if (!val)
182                         break;
183         } while (--timeout);
184
185         /* reset first position - may not be synced with hw at this time */
186         if (azx_dev->posbuf)
187                 *azx_dev->posbuf = 0;
188 }
189 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
190
191 /**
192  * snd_hdac_stream_setup -  set up the SD for streaming
193  * @azx_dev: HD-audio core stream to set up
194  */
195 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
196 {
197         struct hdac_bus *bus = azx_dev->bus;
198         struct snd_pcm_runtime *runtime;
199         unsigned int val;
200
201         if (azx_dev->substream)
202                 runtime = azx_dev->substream->runtime;
203         else
204                 runtime = NULL;
205         /* make sure the run bit is zero for SD */
206         snd_hdac_stream_clear(azx_dev);
207         /* program the stream_tag */
208         val = snd_hdac_stream_readl(azx_dev, SD_CTL);
209         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
210                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
211         if (!bus->snoop)
212                 val |= SD_CTL_TRAFFIC_PRIO;
213         snd_hdac_stream_writel(azx_dev, SD_CTL, val);
214
215         /* program the length of samples in cyclic buffer */
216         snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
217
218         /* program the stream format */
219         /* this value needs to be the same as the one programmed */
220         snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
221
222         /* program the stream LVI (last valid index) of the BDL */
223         snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
224
225         /* program the BDL address */
226         /* lower BDL address */
227         snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
228         /* upper BDL address */
229         snd_hdac_stream_writel(azx_dev, SD_BDLPU,
230                                upper_32_bits(azx_dev->bdl.addr));
231
232         /* enable the position buffer */
233         if (bus->use_posbuf && bus->posbuf.addr) {
234                 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
235                         snd_hdac_chip_writel(bus, DPLBASE,
236                                 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
237         }
238
239         /* set the interrupt enable bits in the descriptor control register */
240         snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
241
242         azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
243
244         /* when LPIB delay correction gives a small negative value,
245          * we ignore it; currently set the threshold statically to
246          * 64 frames
247          */
248         if (runtime && runtime->period_size > 64)
249                 azx_dev->delay_negative_threshold =
250                         -frames_to_bytes(runtime, 64);
251         else
252                 azx_dev->delay_negative_threshold = 0;
253
254         /* wallclk has 24Mhz clock source */
255         if (runtime)
256                 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
257                                     runtime->rate) * 1000);
258
259         return 0;
260 }
261 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
262
263 /**
264  * snd_hdac_stream_cleanup - cleanup a stream
265  * @azx_dev: HD-audio core stream to clean up
266  */
267 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
268 {
269         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
270         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
271         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
272         azx_dev->bufsize = 0;
273         azx_dev->period_bytes = 0;
274         azx_dev->format_val = 0;
275 }
276 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
277
278 /**
279  * snd_hdac_stream_assign - assign a stream for the PCM
280  * @bus: HD-audio core bus
281  * @substream: PCM substream to assign
282  *
283  * Look for an unused stream for the given PCM substream, assign it
284  * and return the stream object.  If no stream is free, returns NULL.
285  * The function tries to keep using the same stream object when it's used
286  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
287  * or matching entry is returned.  This is needed for some strange codecs.
288  */
289 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
290                                            struct snd_pcm_substream *substream)
291 {
292         struct hdac_stream *azx_dev;
293         struct hdac_stream *res = NULL;
294
295         /* make a non-zero unique key for the substream */
296         int key = (substream->pcm->device << 16) | (substream->number << 2) |
297                 (substream->stream + 1);
298
299         list_for_each_entry(azx_dev, &bus->stream_list, list) {
300                 if (azx_dev->direction != substream->stream)
301                         continue;
302                 if (azx_dev->opened)
303                         continue;
304                 if (azx_dev->assigned_key == key) {
305                         res = azx_dev;
306                         break;
307                 }
308                 if (!res || bus->reverse_assign)
309                         res = azx_dev;
310         }
311         if (res) {
312                 spin_lock_irq(&bus->reg_lock);
313                 res->opened = 1;
314                 res->running = 0;
315                 res->assigned_key = key;
316                 res->substream = substream;
317                 spin_unlock_irq(&bus->reg_lock);
318         }
319         return res;
320 }
321 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
322
323 /**
324  * snd_hdac_stream_release - release the assigned stream
325  * @azx_dev: HD-audio core stream to release
326  *
327  * Release the stream that has been assigned by snd_hdac_stream_assign().
328  */
329 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
330 {
331         struct hdac_bus *bus = azx_dev->bus;
332
333         spin_lock_irq(&bus->reg_lock);
334         azx_dev->opened = 0;
335         azx_dev->running = 0;
336         azx_dev->substream = NULL;
337         spin_unlock_irq(&bus->reg_lock);
338 }
339 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
340
341 /**
342  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
343  * direction
344  *
345  * @bus: HD-audio core bus
346  * @dir: direction for the stream to be found
347  * @stream_tag: stream tag for stream to be found
348  */
349 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
350                                         int dir, int stream_tag)
351 {
352         struct hdac_stream *s;
353
354         list_for_each_entry(s, &bus->stream_list, list) {
355                 if (s->direction == dir && s->stream_tag == stream_tag)
356                         return s;
357         }
358
359         return NULL;
360 }
361 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
362
363 /*
364  * set up a BDL entry
365  */
366 static int setup_bdle(struct hdac_bus *bus,
367                       struct snd_dma_buffer *dmab,
368                       struct hdac_stream *azx_dev, __le32 **bdlp,
369                       int ofs, int size, int with_ioc)
370 {
371         __le32 *bdl = *bdlp;
372
373         while (size > 0) {
374                 dma_addr_t addr;
375                 int chunk;
376
377                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
378                         return -EINVAL;
379
380                 addr = snd_sgbuf_get_addr(dmab, ofs);
381                 /* program the address field of the BDL entry */
382                 bdl[0] = cpu_to_le32((u32)addr);
383                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
384                 /* program the size field of the BDL entry */
385                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
386                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
387                 if (bus->align_bdle_4k) {
388                         u32 remain = 0x1000 - (ofs & 0xfff);
389
390                         if (chunk > remain)
391                                 chunk = remain;
392                 }
393                 bdl[2] = cpu_to_le32(chunk);
394                 /* program the IOC to enable interrupt
395                  * only when the whole fragment is processed
396                  */
397                 size -= chunk;
398                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
399                 bdl += 4;
400                 azx_dev->frags++;
401                 ofs += chunk;
402         }
403         *bdlp = bdl;
404         return ofs;
405 }
406
407 /**
408  * snd_hdac_stream_setup_periods - set up BDL entries
409  * @azx_dev: HD-audio core stream to set up
410  *
411  * Set up the buffer descriptor table of the given stream based on the
412  * period and buffer sizes of the assigned PCM substream.
413  */
414 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
415 {
416         struct hdac_bus *bus = azx_dev->bus;
417         struct snd_pcm_substream *substream = azx_dev->substream;
418         struct snd_pcm_runtime *runtime = substream->runtime;
419         __le32 *bdl;
420         int i, ofs, periods, period_bytes;
421         int pos_adj, pos_align;
422
423         /* reset BDL address */
424         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
425         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
426
427         period_bytes = azx_dev->period_bytes;
428         periods = azx_dev->bufsize / period_bytes;
429
430         /* program the initial BDL entries */
431         bdl = (__le32 *)azx_dev->bdl.area;
432         ofs = 0;
433         azx_dev->frags = 0;
434
435         pos_adj = bus->bdl_pos_adj;
436         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
437                 pos_align = pos_adj;
438                 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
439                 if (!pos_adj)
440                         pos_adj = pos_align;
441                 else
442                         pos_adj = roundup(pos_adj, pos_align);
443                 pos_adj = frames_to_bytes(runtime, pos_adj);
444                 if (pos_adj >= period_bytes) {
445                         dev_warn(bus->dev, "Too big adjustment %d\n",
446                                  pos_adj);
447                         pos_adj = 0;
448                 } else {
449                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
450                                          azx_dev,
451                                          &bdl, ofs, pos_adj, true);
452                         if (ofs < 0)
453                                 goto error;
454                 }
455         } else
456                 pos_adj = 0;
457
458         for (i = 0; i < periods; i++) {
459                 if (i == periods - 1 && pos_adj)
460                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
461                                          azx_dev, &bdl, ofs,
462                                          period_bytes - pos_adj, 0);
463                 else
464                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
465                                          azx_dev, &bdl, ofs,
466                                          period_bytes,
467                                          !azx_dev->no_period_wakeup);
468                 if (ofs < 0)
469                         goto error;
470         }
471         return 0;
472
473  error:
474         dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
475                 azx_dev->bufsize, period_bytes);
476         return -EINVAL;
477 }
478 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
479
480 /**
481  * snd_hdac_stream_set_params - set stream parameters
482  * @azx_dev: HD-audio core stream for which parameters are to be set
483  * @format_val: format value parameter
484  *
485  * Setup the HD-audio core stream parameters from substream of the stream
486  * and passed format value
487  */
488 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
489                                  unsigned int format_val)
490 {
491
492         unsigned int bufsize, period_bytes;
493         struct snd_pcm_substream *substream = azx_dev->substream;
494         struct snd_pcm_runtime *runtime;
495         int err;
496
497         if (!substream)
498                 return -EINVAL;
499         runtime = substream->runtime;
500         bufsize = snd_pcm_lib_buffer_bytes(substream);
501         period_bytes = snd_pcm_lib_period_bytes(substream);
502
503         if (bufsize != azx_dev->bufsize ||
504             period_bytes != azx_dev->period_bytes ||
505             format_val != azx_dev->format_val ||
506             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
507                 azx_dev->bufsize = bufsize;
508                 azx_dev->period_bytes = period_bytes;
509                 azx_dev->format_val = format_val;
510                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
511                 err = snd_hdac_stream_setup_periods(azx_dev);
512                 if (err < 0)
513                         return err;
514         }
515         return 0;
516 }
517 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
518
519 static u64 azx_cc_read(const struct cyclecounter *cc)
520 {
521         struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
522
523         return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
524 }
525
526 static void azx_timecounter_init(struct hdac_stream *azx_dev,
527                                  bool force, u64 last)
528 {
529         struct timecounter *tc = &azx_dev->tc;
530         struct cyclecounter *cc = &azx_dev->cc;
531         u64 nsec;
532
533         cc->read = azx_cc_read;
534         cc->mask = CLOCKSOURCE_MASK(32);
535
536         /*
537          * Converting from 24 MHz to ns means applying a 125/3 factor.
538          * To avoid any saturation issues in intermediate operations,
539          * the 125 factor is applied first. The division is applied
540          * last after reading the timecounter value.
541          * Applying the 1/3 factor as part of the multiplication
542          * requires at least 20 bits for a decent precision, however
543          * overflows occur after about 4 hours or less, not a option.
544          */
545
546         cc->mult = 125; /* saturation after 195 years */
547         cc->shift = 0;
548
549         nsec = 0; /* audio time is elapsed time since trigger */
550         timecounter_init(tc, cc, nsec);
551         if (force) {
552                 /*
553                  * force timecounter to use predefined value,
554                  * used for synchronized starts
555                  */
556                 tc->cycle_last = last;
557         }
558 }
559
560 /**
561  * snd_hdac_stream_timecounter_init - initialize time counter
562  * @azx_dev: HD-audio core stream (master stream)
563  * @streams: bit flags of streams to set up
564  *
565  * Initializes the time counter of streams marked by the bit flags (each
566  * bit corresponds to the stream index).
567  * The trigger timestamp of PCM substream assigned to the given stream is
568  * updated accordingly, too.
569  */
570 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
571                                       unsigned int streams)
572 {
573         struct hdac_bus *bus = azx_dev->bus;
574         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
575         struct hdac_stream *s;
576         bool inited = false;
577         u64 cycle_last = 0;
578         int i = 0;
579
580         list_for_each_entry(s, &bus->stream_list, list) {
581                 if (streams & (1 << i)) {
582                         azx_timecounter_init(s, inited, cycle_last);
583                         if (!inited) {
584                                 inited = true;
585                                 cycle_last = s->tc.cycle_last;
586                         }
587                 }
588                 i++;
589         }
590
591         snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
592         runtime->trigger_tstamp_latched = true;
593 }
594 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
595
596 /**
597  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
598  * @azx_dev: HD-audio core stream (master stream)
599  * @set: true = set, false = clear
600  * @streams: bit flags of streams to sync
601  * @reg: the stream sync register address
602  */
603 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
604                                   unsigned int streams, unsigned int reg)
605 {
606         struct hdac_bus *bus = azx_dev->bus;
607         unsigned int val;
608
609         if (!reg)
610                 reg = AZX_REG_SSYNC;
611         val = _snd_hdac_chip_readl(bus, reg);
612         if (set)
613                 val |= streams;
614         else
615                 val &= ~streams;
616         _snd_hdac_chip_writel(bus, reg, val);
617 }
618 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
619
620 /**
621  * snd_hdac_stream_sync - sync with start/stop trigger operation
622  * @azx_dev: HD-audio core stream (master stream)
623  * @start: true = start, false = stop
624  * @streams: bit flags of streams to sync
625  *
626  * For @start = true, wait until all FIFOs get ready.
627  * For @start = false, wait until all RUN bits are cleared.
628  */
629 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
630                           unsigned int streams)
631 {
632         struct hdac_bus *bus = azx_dev->bus;
633         int i, nwait, timeout;
634         struct hdac_stream *s;
635
636         for (timeout = 5000; timeout; timeout--) {
637                 nwait = 0;
638                 i = 0;
639                 list_for_each_entry(s, &bus->stream_list, list) {
640                         if (!(streams & (1 << i++)))
641                                 continue;
642
643                         if (start) {
644                                 /* check FIFO gets ready */
645                                 if (!(snd_hdac_stream_readb(s, SD_STS) &
646                                       SD_STS_FIFO_READY))
647                                         nwait++;
648                         } else {
649                                 /* check RUN bit is cleared */
650                                 if (snd_hdac_stream_readb(s, SD_CTL) &
651                                     SD_CTL_DMA_START) {
652                                         nwait++;
653                                         /*
654                                          * Perform stream reset if DMA RUN
655                                          * bit not cleared within given timeout
656                                          */
657                                         if (timeout == 1)
658                                                 snd_hdac_stream_reset(s);
659                                 }
660                         }
661                 }
662                 if (!nwait)
663                         break;
664                 cpu_relax();
665         }
666 }
667 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
668
669 #ifdef CONFIG_SND_HDA_DSP_LOADER
670 /**
671  * snd_hdac_dsp_prepare - prepare for DSP loading
672  * @azx_dev: HD-audio core stream used for DSP loading
673  * @format: HD-audio stream format
674  * @byte_size: data chunk byte size
675  * @bufp: allocated buffer
676  *
677  * Allocate the buffer for the given size and set up the given stream for
678  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
679  */
680 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
681                          unsigned int byte_size, struct snd_dma_buffer *bufp)
682 {
683         struct hdac_bus *bus = azx_dev->bus;
684         __le32 *bdl;
685         int err;
686
687         snd_hdac_dsp_lock(azx_dev);
688         spin_lock_irq(&bus->reg_lock);
689         if (azx_dev->running || azx_dev->locked) {
690                 spin_unlock_irq(&bus->reg_lock);
691                 err = -EBUSY;
692                 goto unlock;
693         }
694         azx_dev->locked = true;
695         spin_unlock_irq(&bus->reg_lock);
696
697         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
698                                   byte_size, bufp);
699         if (err < 0)
700                 goto err_alloc;
701
702         azx_dev->substream = NULL;
703         azx_dev->bufsize = byte_size;
704         azx_dev->period_bytes = byte_size;
705         azx_dev->format_val = format;
706
707         snd_hdac_stream_reset(azx_dev);
708
709         /* reset BDL address */
710         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
711         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
712
713         azx_dev->frags = 0;
714         bdl = (__le32 *)azx_dev->bdl.area;
715         err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
716         if (err < 0)
717                 goto error;
718
719         snd_hdac_stream_setup(azx_dev);
720         snd_hdac_dsp_unlock(azx_dev);
721         return azx_dev->stream_tag;
722
723  error:
724         snd_dma_free_pages(bufp);
725  err_alloc:
726         spin_lock_irq(&bus->reg_lock);
727         azx_dev->locked = false;
728         spin_unlock_irq(&bus->reg_lock);
729  unlock:
730         snd_hdac_dsp_unlock(azx_dev);
731         return err;
732 }
733 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
734
735 /**
736  * snd_hdac_dsp_trigger - start / stop DSP loading
737  * @azx_dev: HD-audio core stream used for DSP loading
738  * @start: trigger start or stop
739  */
740 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
741 {
742         if (start)
743                 snd_hdac_stream_start(azx_dev, true);
744         else
745                 snd_hdac_stream_stop(azx_dev);
746 }
747 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
748
749 /**
750  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
751  * @azx_dev: HD-audio core stream used for DSP loading
752  * @dmab: buffer used by DSP loading
753  */
754 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
755                           struct snd_dma_buffer *dmab)
756 {
757         struct hdac_bus *bus = azx_dev->bus;
758
759         if (!dmab->area || !azx_dev->locked)
760                 return;
761
762         snd_hdac_dsp_lock(azx_dev);
763         /* reset BDL address */
764         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
765         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
766         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
767         azx_dev->bufsize = 0;
768         azx_dev->period_bytes = 0;
769         azx_dev->format_val = 0;
770
771         snd_dma_free_pages(dmab);
772         dmab->area = NULL;
773
774         spin_lock_irq(&bus->reg_lock);
775         azx_dev->locked = false;
776         spin_unlock_irq(&bus->reg_lock);
777         snd_hdac_dsp_unlock(azx_dev);
778 }
779 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
780 #endif /* CONFIG_SND_HDA_DSP_LOADER */