2 * HD-audio stream operations
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/export.h>
8 #include <linux/clocksource.h>
9 #include <sound/core.h>
10 #include <sound/pcm.h>
11 #include <sound/hdaudio.h>
12 #include <sound/hda_register.h>
16 * snd_hdac_get_stream_stripe_ctl - get stripe control value
17 * @bus: HD-audio core bus
18 * @substream: PCM substream
20 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
21 struct snd_pcm_substream *substream)
23 struct snd_pcm_runtime *runtime = substream->runtime;
24 unsigned int channels = runtime->channels,
26 bits_per_sample = runtime->sample_bits,
27 max_sdo_lines, value, sdo_line;
29 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
30 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
32 /* following is from HD audio spec */
33 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
35 value = (channels * bits_per_sample *
36 (rate / 48000)) / sdo_line;
38 value = (channels * bits_per_sample) / sdo_line;
44 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
47 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
50 * snd_hdac_stream_init - initialize each stream (aka device)
51 * @bus: HD-audio core bus
52 * @azx_dev: HD-audio core stream object to initialize
53 * @idx: stream index number
54 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
55 * @tag: the tag id to assign
57 * Assign the starting bdl address to each stream (device) and initialize.
59 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
60 int idx, int direction, int tag)
63 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
64 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
65 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
66 azx_dev->sd_int_sta_mask = 1 << idx;
68 azx_dev->direction = direction;
69 azx_dev->stream_tag = tag;
70 snd_hdac_dsp_lock_init(azx_dev);
71 list_add_tail(&azx_dev->list, &bus->stream_list);
73 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
76 * snd_hdac_stream_start - start a stream
77 * @azx_dev: HD-audio core stream to start
78 * @fresh_start: false = wallclock timestamp relative to period wallclock
80 * Start a stream, set start_wallclk and set the running flag.
82 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
84 struct hdac_bus *bus = azx_dev->bus;
87 trace_snd_hdac_stream_start(bus, azx_dev);
89 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
91 azx_dev->start_wallclk -= azx_dev->period_wallclk;
94 snd_hdac_chip_updatel(bus, INTCTL,
97 /* set stripe control */
98 if (azx_dev->substream)
99 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
102 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
104 /* set DMA start and interrupt mask */
105 snd_hdac_stream_updateb(azx_dev, SD_CTL,
106 0, SD_CTL_DMA_START | SD_INT_MASK);
107 azx_dev->running = true;
109 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
112 * snd_hdac_stream_clear - stop a stream DMA
113 * @azx_dev: HD-audio core stream to stop
115 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
117 snd_hdac_stream_updateb(azx_dev, SD_CTL,
118 SD_CTL_DMA_START | SD_INT_MASK, 0);
119 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
120 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
121 azx_dev->running = false;
123 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
126 * snd_hdac_stream_stop - stop a stream
127 * @azx_dev: HD-audio core stream to stop
129 * Stop a stream DMA and disable stream interrupt
131 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
133 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
135 snd_hdac_stream_clear(azx_dev);
137 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
139 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
142 * snd_hdac_stream_reset - reset a stream
143 * @azx_dev: HD-audio core stream to reset
145 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
150 snd_hdac_stream_clear(azx_dev);
152 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
156 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
161 val &= ~SD_CTL_STREAM_RESET;
162 snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
166 /* waiting for hardware to report that the stream is out of reset */
168 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
174 /* reset first position - may not be synced with hw at this time */
176 *azx_dev->posbuf = 0;
178 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
181 * snd_hdac_stream_setup - set up the SD for streaming
182 * @azx_dev: HD-audio core stream to set up
184 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
186 struct hdac_bus *bus = azx_dev->bus;
187 struct snd_pcm_runtime *runtime;
190 if (azx_dev->substream)
191 runtime = azx_dev->substream->runtime;
194 /* make sure the run bit is zero for SD */
195 snd_hdac_stream_clear(azx_dev);
196 /* program the stream_tag */
197 val = snd_hdac_stream_readl(azx_dev, SD_CTL);
198 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
199 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
201 val |= SD_CTL_TRAFFIC_PRIO;
202 snd_hdac_stream_writel(azx_dev, SD_CTL, val);
204 /* program the length of samples in cyclic buffer */
205 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
207 /* program the stream format */
208 /* this value needs to be the same as the one programmed */
209 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
211 /* program the stream LVI (last valid index) of the BDL */
212 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
214 /* program the BDL address */
215 /* lower BDL address */
216 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
217 /* upper BDL address */
218 snd_hdac_stream_writel(azx_dev, SD_BDLPU,
219 upper_32_bits(azx_dev->bdl.addr));
221 /* enable the position buffer */
222 if (bus->use_posbuf && bus->posbuf.addr) {
223 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
224 snd_hdac_chip_writel(bus, DPLBASE,
225 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
228 /* set the interrupt enable bits in the descriptor control register */
229 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
231 if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
233 snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
235 azx_dev->fifo_size = 0;
237 /* when LPIB delay correction gives a small negative value,
238 * we ignore it; currently set the threshold statically to
241 if (runtime && runtime->period_size > 64)
242 azx_dev->delay_negative_threshold =
243 -frames_to_bytes(runtime, 64);
245 azx_dev->delay_negative_threshold = 0;
247 /* wallclk has 24Mhz clock source */
249 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
250 runtime->rate) * 1000);
254 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
257 * snd_hdac_stream_cleanup - cleanup a stream
258 * @azx_dev: HD-audio core stream to clean up
260 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
262 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
263 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
264 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
265 azx_dev->bufsize = 0;
266 azx_dev->period_bytes = 0;
267 azx_dev->format_val = 0;
269 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
272 * snd_hdac_stream_assign - assign a stream for the PCM
273 * @bus: HD-audio core bus
274 * @substream: PCM substream to assign
276 * Look for an unused stream for the given PCM substream, assign it
277 * and return the stream object. If no stream is free, returns NULL.
278 * The function tries to keep using the same stream object when it's used
279 * beforehand. Also, when bus->reverse_assign flag is set, the last free
280 * or matching entry is returned. This is needed for some strange codecs.
282 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
283 struct snd_pcm_substream *substream)
285 struct hdac_stream *azx_dev;
286 struct hdac_stream *res = NULL;
288 /* make a non-zero unique key for the substream */
289 int key = (substream->pcm->device << 16) | (substream->number << 2) |
290 (substream->stream + 1);
292 list_for_each_entry(azx_dev, &bus->stream_list, list) {
293 if (azx_dev->direction != substream->stream)
297 if (azx_dev->assigned_key == key) {
301 if (!res || bus->reverse_assign)
305 spin_lock_irq(&bus->reg_lock);
308 res->assigned_key = key;
309 res->substream = substream;
310 spin_unlock_irq(&bus->reg_lock);
314 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
317 * snd_hdac_stream_release - release the assigned stream
318 * @azx_dev: HD-audio core stream to release
320 * Release the stream that has been assigned by snd_hdac_stream_assign().
322 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
324 struct hdac_bus *bus = azx_dev->bus;
326 spin_lock_irq(&bus->reg_lock);
328 azx_dev->running = 0;
329 azx_dev->substream = NULL;
330 spin_unlock_irq(&bus->reg_lock);
332 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
335 * snd_hdac_get_stream - return hdac_stream based on stream_tag and
338 * @bus: HD-audio core bus
339 * @dir: direction for the stream to be found
340 * @stream_tag: stream tag for stream to be found
342 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
343 int dir, int stream_tag)
345 struct hdac_stream *s;
347 list_for_each_entry(s, &bus->stream_list, list) {
348 if (s->direction == dir && s->stream_tag == stream_tag)
354 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
359 static int setup_bdle(struct hdac_bus *bus,
360 struct snd_dma_buffer *dmab,
361 struct hdac_stream *azx_dev, __le32 **bdlp,
362 int ofs, int size, int with_ioc)
370 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
373 addr = snd_sgbuf_get_addr(dmab, ofs);
374 /* program the address field of the BDL entry */
375 bdl[0] = cpu_to_le32((u32)addr);
376 bdl[1] = cpu_to_le32(upper_32_bits(addr));
377 /* program the size field of the BDL entry */
378 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
379 /* one BDLE cannot cross 4K boundary on CTHDA chips */
380 if (bus->align_bdle_4k) {
381 u32 remain = 0x1000 - (ofs & 0xfff);
386 bdl[2] = cpu_to_le32(chunk);
387 /* program the IOC to enable interrupt
388 * only when the whole fragment is processed
391 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
401 * snd_hdac_stream_setup_periods - set up BDL entries
402 * @azx_dev: HD-audio core stream to set up
404 * Set up the buffer descriptor table of the given stream based on the
405 * period and buffer sizes of the assigned PCM substream.
407 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
409 struct hdac_bus *bus = azx_dev->bus;
410 struct snd_pcm_substream *substream = azx_dev->substream;
411 struct snd_pcm_runtime *runtime = substream->runtime;
413 int i, ofs, periods, period_bytes;
414 int pos_adj, pos_align;
416 /* reset BDL address */
417 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
418 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
420 period_bytes = azx_dev->period_bytes;
421 periods = azx_dev->bufsize / period_bytes;
423 /* program the initial BDL entries */
424 bdl = (__le32 *)azx_dev->bdl.area;
428 pos_adj = bus->bdl_pos_adj;
429 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
431 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
435 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
437 pos_adj = frames_to_bytes(runtime, pos_adj);
438 if (pos_adj >= period_bytes) {
439 dev_warn(bus->dev, "Too big adjustment %d\n",
443 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
445 &bdl, ofs, pos_adj, true);
452 for (i = 0; i < periods; i++) {
453 if (i == periods - 1 && pos_adj)
454 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
456 period_bytes - pos_adj, 0);
458 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
461 !azx_dev->no_period_wakeup);
468 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
469 azx_dev->bufsize, period_bytes);
472 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
475 * snd_hdac_stream_set_params - set stream parameters
476 * @azx_dev: HD-audio core stream for which parameters are to be set
477 * @format_val: format value parameter
479 * Setup the HD-audio core stream parameters from substream of the stream
480 * and passed format value
482 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
483 unsigned int format_val)
486 unsigned int bufsize, period_bytes;
487 struct snd_pcm_substream *substream = azx_dev->substream;
488 struct snd_pcm_runtime *runtime;
493 runtime = substream->runtime;
494 bufsize = snd_pcm_lib_buffer_bytes(substream);
495 period_bytes = snd_pcm_lib_period_bytes(substream);
497 if (bufsize != azx_dev->bufsize ||
498 period_bytes != azx_dev->period_bytes ||
499 format_val != azx_dev->format_val ||
500 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
501 azx_dev->bufsize = bufsize;
502 azx_dev->period_bytes = period_bytes;
503 azx_dev->format_val = format_val;
504 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
505 err = snd_hdac_stream_setup_periods(azx_dev);
511 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
513 static u64 azx_cc_read(const struct cyclecounter *cc)
515 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
517 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
520 static void azx_timecounter_init(struct hdac_stream *azx_dev,
521 bool force, u64 last)
523 struct timecounter *tc = &azx_dev->tc;
524 struct cyclecounter *cc = &azx_dev->cc;
527 cc->read = azx_cc_read;
528 cc->mask = CLOCKSOURCE_MASK(32);
531 * Converting from 24 MHz to ns means applying a 125/3 factor.
532 * To avoid any saturation issues in intermediate operations,
533 * the 125 factor is applied first. The division is applied
534 * last after reading the timecounter value.
535 * Applying the 1/3 factor as part of the multiplication
536 * requires at least 20 bits for a decent precision, however
537 * overflows occur after about 4 hours or less, not a option.
540 cc->mult = 125; /* saturation after 195 years */
543 nsec = 0; /* audio time is elapsed time since trigger */
544 timecounter_init(tc, cc, nsec);
547 * force timecounter to use predefined value,
548 * used for synchronized starts
550 tc->cycle_last = last;
555 * snd_hdac_stream_timecounter_init - initialize time counter
556 * @azx_dev: HD-audio core stream (master stream)
557 * @streams: bit flags of streams to set up
559 * Initializes the time counter of streams marked by the bit flags (each
560 * bit corresponds to the stream index).
561 * The trigger timestamp of PCM substream assigned to the given stream is
562 * updated accordingly, too.
564 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
565 unsigned int streams)
567 struct hdac_bus *bus = azx_dev->bus;
568 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
569 struct hdac_stream *s;
574 list_for_each_entry(s, &bus->stream_list, list) {
575 if (streams & (1 << i)) {
576 azx_timecounter_init(s, inited, cycle_last);
579 cycle_last = s->tc.cycle_last;
585 snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
586 runtime->trigger_tstamp_latched = true;
588 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
591 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
592 * @azx_dev: HD-audio core stream (master stream)
593 * @streams: bit flags of streams to sync
595 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
596 unsigned int streams, unsigned int reg)
598 struct hdac_bus *bus = azx_dev->bus;
603 val = _snd_hdac_chip_readl(bus, reg);
608 _snd_hdac_chip_writel(bus, reg, val);
610 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
613 * snd_hdac_stream_sync - sync with start/strop trigger operation
614 * @azx_dev: HD-audio core stream (master stream)
615 * @start: true = start, false = stop
616 * @streams: bit flags of streams to sync
618 * For @start = true, wait until all FIFOs get ready.
619 * For @start = false, wait until all RUN bits are cleared.
621 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
622 unsigned int streams)
624 struct hdac_bus *bus = azx_dev->bus;
625 int i, nwait, timeout;
626 struct hdac_stream *s;
628 for (timeout = 5000; timeout; timeout--) {
631 list_for_each_entry(s, &bus->stream_list, list) {
632 if (streams & (1 << i)) {
634 /* check FIFO gets ready */
635 if (!(snd_hdac_stream_readb(s, SD_STS) &
639 /* check RUN bit is cleared */
640 if (snd_hdac_stream_readb(s, SD_CTL) &
652 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
654 #ifdef CONFIG_SND_HDA_DSP_LOADER
656 * snd_hdac_dsp_prepare - prepare for DSP loading
657 * @azx_dev: HD-audio core stream used for DSP loading
658 * @format: HD-audio stream format
659 * @byte_size: data chunk byte size
660 * @bufp: allocated buffer
662 * Allocate the buffer for the given size and set up the given stream for
663 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
665 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
666 unsigned int byte_size, struct snd_dma_buffer *bufp)
668 struct hdac_bus *bus = azx_dev->bus;
672 snd_hdac_dsp_lock(azx_dev);
673 spin_lock_irq(&bus->reg_lock);
674 if (azx_dev->running || azx_dev->locked) {
675 spin_unlock_irq(&bus->reg_lock);
679 azx_dev->locked = true;
680 spin_unlock_irq(&bus->reg_lock);
682 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG,
687 azx_dev->substream = NULL;
688 azx_dev->bufsize = byte_size;
689 azx_dev->period_bytes = byte_size;
690 azx_dev->format_val = format;
692 snd_hdac_stream_reset(azx_dev);
694 /* reset BDL address */
695 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
696 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
699 bdl = (__le32 *)azx_dev->bdl.area;
700 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
704 snd_hdac_stream_setup(azx_dev);
705 snd_hdac_dsp_unlock(azx_dev);
706 return azx_dev->stream_tag;
709 bus->io_ops->dma_free_pages(bus, bufp);
711 spin_lock_irq(&bus->reg_lock);
712 azx_dev->locked = false;
713 spin_unlock_irq(&bus->reg_lock);
715 snd_hdac_dsp_unlock(azx_dev);
718 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
721 * snd_hdac_dsp_trigger - start / stop DSP loading
722 * @azx_dev: HD-audio core stream used for DSP loading
723 * @start: trigger start or stop
725 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
728 snd_hdac_stream_start(azx_dev, true);
730 snd_hdac_stream_stop(azx_dev);
732 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
735 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
736 * @azx_dev: HD-audio core stream used for DSP loading
737 * @dmab: buffer used by DSP loading
739 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
740 struct snd_dma_buffer *dmab)
742 struct hdac_bus *bus = azx_dev->bus;
744 if (!dmab->area || !azx_dev->locked)
747 snd_hdac_dsp_lock(azx_dev);
748 /* reset BDL address */
749 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
750 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
751 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
752 azx_dev->bufsize = 0;
753 azx_dev->period_bytes = 0;
754 azx_dev->format_val = 0;
756 bus->io_ops->dma_free_pages(bus, dmab);
759 spin_lock_irq(&bus->reg_lock);
760 azx_dev->locked = false;
761 spin_unlock_irq(&bus->reg_lock);
762 snd_hdac_dsp_unlock(azx_dev);
764 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
765 #endif /* CONFIG_SND_HDA_DSP_LOADER */