1 // SPDX-License-Identifier: GPL-2.0-only
3 * motu-protocol-v2.c - a part of driver for MOTU FireWire series
5 * Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp>
10 #define V2_CLOCK_STATUS_OFFSET 0x0b14
11 #define V2_CLOCK_RATE_MASK 0x00000038
12 #define V2_CLOCK_RATE_SHIFT 3
13 #define V2_CLOCK_SRC_MASK 0x00000007
14 #define V2_CLOCK_SRC_SHIFT 0
15 #define V2_CLOCK_FETCH_ENABLE 0x02000000
16 #define V2_CLOCK_MODEL_SPECIFIC 0x04000000
18 #define V2_IN_OUT_CONF_OFFSET 0x0c04
19 #define V2_OPT_OUT_IFACE_MASK 0x00000c00
20 #define V2_OPT_OUT_IFACE_SHIFT 10
21 #define V2_OPT_IN_IFACE_MASK 0x00000300
22 #define V2_OPT_IN_IFACE_SHIFT 8
23 #define V2_OPT_IFACE_MODE_NONE 0
24 #define V2_OPT_IFACE_MODE_ADAT 1
25 #define V2_OPT_IFACE_MODE_SPDIF 2
27 static int get_clock_rate(u32 data, unsigned int *rate)
29 unsigned int index = (data & V2_CLOCK_RATE_MASK) >> V2_CLOCK_RATE_SHIFT;
30 if (index >= ARRAY_SIZE(snd_motu_clock_rates))
33 *rate = snd_motu_clock_rates[index];
38 int snd_motu_protocol_v2_get_clock_rate(struct snd_motu *motu,
44 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
49 return get_clock_rate(be32_to_cpu(reg), rate);
52 int snd_motu_protocol_v2_set_clock_rate(struct snd_motu *motu,
60 for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) {
61 if (snd_motu_clock_rates[i] == rate)
64 if (i == ARRAY_SIZE(snd_motu_clock_rates))
67 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
71 data = be32_to_cpu(reg);
73 data &= ~V2_CLOCK_RATE_MASK;
74 data |= i << V2_CLOCK_RATE_SHIFT;
76 reg = cpu_to_be32(data);
77 return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®,
81 static int get_clock_source(struct snd_motu *motu, u32 data,
82 enum snd_motu_clock_source *src)
84 unsigned int index = data & V2_CLOCK_SRC_MASK;
90 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
96 // To check the configuration of optical interface.
97 int err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET,
102 if (be32_to_cpu(reg) & 0x00000200)
103 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT;
105 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
109 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
112 *src = SND_MOTU_CLOCK_SOURCE_SPH;
115 *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
118 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
127 int snd_motu_protocol_v2_get_clock_source(struct snd_motu *motu,
128 enum snd_motu_clock_source *src)
133 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
138 return get_clock_source(motu, be32_to_cpu(reg), src);
141 int snd_motu_protocol_v2_switch_fetching_mode(struct snd_motu *motu,
144 enum snd_motu_clock_source src;
149 // 828mkII implements Altera ACEX 1K EP1K30. Nothing to do.
150 if (motu->spec == &snd_motu_spec_828mk2)
153 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
157 data = be32_to_cpu(reg);
159 err = get_clock_source(motu, data, &src);
163 data &= ~(V2_CLOCK_FETCH_ENABLE | V2_CLOCK_MODEL_SPECIFIC);
165 data |= V2_CLOCK_FETCH_ENABLE;
167 if (motu->spec->flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4) {
168 // Expected for Traveler and 896HD, which implements Altera
170 data |= V2_CLOCK_MODEL_SPECIFIC;
172 // For UltraLite and 8pre, which implements Xilinx Spartan
176 err = get_clock_rate(data, &rate);
180 if (src == SND_MOTU_CLOCK_SOURCE_SPH && rate > 48000)
181 data |= V2_CLOCK_MODEL_SPECIFIC;
184 reg = cpu_to_be32(data);
185 return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®,
189 static void calculate_fixed_part(struct snd_motu_packet_format *formats,
190 enum amdtp_stream_direction dir,
191 enum snd_motu_spec_flags flags,
192 unsigned char analog_ports)
194 unsigned char pcm_chunks[3] = {0, 0, 0};
196 formats->msg_chunks = 2;
198 pcm_chunks[0] = analog_ports;
199 pcm_chunks[1] = analog_ports;
200 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4)
201 pcm_chunks[2] = analog_ports;
203 if (dir == AMDTP_IN_STREAM) {
204 if (flags & SND_MOTU_SPEC_TX_MICINST_CHUNK) {
208 if (flags & SND_MOTU_SPEC_TX_RETURN_CHUNK) {
213 if (flags & SND_MOTU_SPEC_RX_SEPARATED_MAIN) {
218 // Packets to v2 units include 2 chunks for phone 1/2, except
219 // for 176.4/192.0 kHz.
224 if (flags & SND_MOTU_SPEC_HAS_AESEBU_IFACE) {
230 * All of v2 models have a pair of coaxial interfaces for digital in/out
231 * port. At 44.1/48.0/88.2/96.0 kHz, packets includes PCM from these
237 formats->fixed_part_pcm_chunks[0] = pcm_chunks[0];
238 formats->fixed_part_pcm_chunks[1] = pcm_chunks[1];
239 formats->fixed_part_pcm_chunks[2] = pcm_chunks[2];
242 static void calculate_differed_part(struct snd_motu_packet_format *formats,
243 enum snd_motu_spec_flags flags,
244 u32 data, u32 mask, u32 shift)
246 unsigned char pcm_chunks[2] = {0, 0};
249 * When optical interfaces are configured for S/PDIF (TOSLINK),
250 * the above PCM frames come from them, instead of coaxial
253 data = (data & mask) >> shift;
254 if (data == V2_OPT_IFACE_MODE_ADAT) {
255 if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_A) {
259 // 8pre has two sets of optical interface and doesn't reduce
260 // chunks for ADAT signals.
261 if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_B) {
266 /* At mode x4, no data chunks are supported in this part. */
267 formats->differed_part_pcm_chunks[0] = pcm_chunks[0];
268 formats->differed_part_pcm_chunks[1] = pcm_chunks[1];
271 int snd_motu_protocol_v2_cache_packet_formats(struct snd_motu *motu)
277 err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®,
281 data = be32_to_cpu(reg);
283 calculate_fixed_part(&motu->tx_packet_formats, AMDTP_IN_STREAM,
284 motu->spec->flags, motu->spec->analog_in_ports);
285 calculate_differed_part(&motu->tx_packet_formats, motu->spec->flags,
286 data, V2_OPT_IN_IFACE_MASK, V2_OPT_IN_IFACE_SHIFT);
288 calculate_fixed_part(&motu->rx_packet_formats, AMDTP_OUT_STREAM,
289 motu->spec->flags, motu->spec->analog_out_ports);
290 calculate_differed_part(&motu->rx_packet_formats, motu->spec->flags,
291 data, V2_OPT_OUT_IFACE_MASK, V2_OPT_OUT_IFACE_SHIFT);
293 motu->tx_packet_formats.pcm_byte_offset = 10;
294 motu->rx_packet_formats.pcm_byte_offset = 10;
299 const struct snd_motu_spec snd_motu_spec_828mk2 = {
301 .protocol_version = SND_MOTU_PROTOCOL_V2,
302 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 |
303 SND_MOTU_SPEC_TX_MICINST_CHUNK |
304 SND_MOTU_SPEC_TX_RETURN_CHUNK |
305 SND_MOTU_SPEC_RX_SEPARATED_MAIN |
306 SND_MOTU_SPEC_HAS_OPT_IFACE_A |
307 SND_MOTU_SPEC_RX_MIDI_2ND_Q |
308 SND_MOTU_SPEC_TX_MIDI_2ND_Q,
310 .analog_in_ports = 8,
311 .analog_out_ports = 8,
314 const struct snd_motu_spec snd_motu_spec_traveler = {
316 .protocol_version = SND_MOTU_PROTOCOL_V2,
317 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 |
318 SND_MOTU_SPEC_SUPPORT_CLOCK_X4 |
319 SND_MOTU_SPEC_TX_RETURN_CHUNK |
320 SND_MOTU_SPEC_HAS_AESEBU_IFACE |
321 SND_MOTU_SPEC_HAS_OPT_IFACE_A |
322 SND_MOTU_SPEC_RX_MIDI_2ND_Q |
323 SND_MOTU_SPEC_TX_MIDI_2ND_Q,
325 .analog_in_ports = 8,
326 .analog_out_ports = 8,
329 const struct snd_motu_spec snd_motu_spec_ultralite = {
331 .protocol_version = SND_MOTU_PROTOCOL_V2,
332 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 |
333 SND_MOTU_SPEC_TX_MICINST_CHUNK | // padding.
334 SND_MOTU_SPEC_TX_RETURN_CHUNK |
335 SND_MOTU_SPEC_RX_MIDI_2ND_Q |
336 SND_MOTU_SPEC_TX_MIDI_2ND_Q |
337 SND_MOTU_SPEC_RX_SEPARATED_MAIN,
338 .analog_in_ports = 8,
339 .analog_out_ports = 8,
342 const struct snd_motu_spec snd_motu_spec_8pre = {
344 .protocol_version = SND_MOTU_PROTOCOL_V2,
345 // In tx, use coax chunks for mix-return 1/2. In rx, use coax chunks for
347 .flags = SND_MOTU_SPEC_SUPPORT_CLOCK_X2 |
348 SND_MOTU_SPEC_HAS_OPT_IFACE_A |
349 SND_MOTU_SPEC_HAS_OPT_IFACE_B |
350 SND_MOTU_SPEC_RX_MIDI_2ND_Q |
351 SND_MOTU_SPEC_TX_MIDI_2ND_Q,
352 .analog_in_ports = 8,
353 .analog_out_ports = 2,