sound/firewire/amdtp-stream.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
   4  * with Common Isochronous Packet (IEC 61883-1) headers
   5  *
   6  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/err.h>
  11 #include <linux/firewire.h>
  12 #include <linux/firewire-constants.h>
  13 #include <linux/module.h>
  14 #include <linux/slab.h>
  15 #include <sound/pcm.h>
  16 #include <sound/pcm_params.h>
  17 #include "amdtp-stream.h"
  18
  19 #define TICKS_PER_CYCLE         3072
  20 #define CYCLES_PER_SECOND       8000
  21 #define TICKS_PER_SECOND        (TICKS_PER_CYCLE * CYCLES_PER_SECOND)
  22
  23 #define OHCI_SECOND_MODULUS             8
  24
  25 /* Always support Linux tracing subsystem. */
  26 #define CREATE_TRACE_POINTS
  27 #include "amdtp-stream-trace.h"
  28
  29 #define TRANSFER_DELAY_TICKS    0x2e00 /* 479.17 microseconds */
  30
  31 /* isochronous header parameters */
  32 #define ISO_DATA_LENGTH_SHIFT   16
  33 #define TAG_NO_CIP_HEADER       0
  34 #define TAG_CIP                 1
  35
  36 // Common Isochronous Packet (CIP) header parameters. Use two quadlets CIP header when supported.
  37 #define CIP_HEADER_QUADLETS     2
  38 #define CIP_EOH_SHIFT           31
  39 #define CIP_EOH                 (1u << CIP_EOH_SHIFT)
  40 #define CIP_EOH_MASK            0x80000000
  41 #define CIP_SID_SHIFT           24
  42 #define CIP_SID_MASK            0x3f000000
  43 #define CIP_DBS_MASK            0x00ff0000
  44 #define CIP_DBS_SHIFT           16
  45 #define CIP_SPH_MASK            0x00000400
  46 #define CIP_SPH_SHIFT           10
  47 #define CIP_DBC_MASK            0x000000ff
  48 #define CIP_FMT_SHIFT           24
  49 #define CIP_FMT_MASK            0x3f000000
  50 #define CIP_FDF_MASK            0x00ff0000
  51 #define CIP_FDF_SHIFT           16
  52 #define CIP_FDF_NO_DATA         0xff
  53 #define CIP_SYT_MASK            0x0000ffff
  54 #define CIP_SYT_NO_INFO         0xffff
  55 #define CIP_SYT_CYCLE_MODULUS   16
  56 #define CIP_NO_DATA             ((CIP_FDF_NO_DATA << CIP_FDF_SHIFT) | CIP_SYT_NO_INFO)
  57
  58 #define CIP_HEADER_SIZE         (sizeof(__be32) * CIP_HEADER_QUADLETS)
  59
  60 /* Audio and Music transfer protocol specific parameters */
  61 #define CIP_FMT_AM              0x10
  62 #define AMDTP_FDF_NO_DATA       0xff
  63
  64 // For iso header and tstamp.
  65 #define IR_CTX_HEADER_DEFAULT_QUADLETS  2
  66 // Add nothing.
  67 #define IR_CTX_HEADER_SIZE_NO_CIP       (sizeof(__be32) * IR_CTX_HEADER_DEFAULT_QUADLETS)
  68 // Add two quadlets CIP header.
  69 #define IR_CTX_HEADER_SIZE_CIP          (IR_CTX_HEADER_SIZE_NO_CIP + CIP_HEADER_SIZE)
  70 #define HEADER_TSTAMP_MASK      0x0000ffff
  71
  72 #define IT_PKT_HEADER_SIZE_CIP          CIP_HEADER_SIZE
  73 #define IT_PKT_HEADER_SIZE_NO_CIP       0 // Nothing.
  74
  75 // The initial firmware of OXFW970 can postpone transmission of packet during finishing
  76 // asynchronous transaction. This module accepts 5 cycles to skip as maximum to avoid buffer
  77 // overrun. Actual device can skip more, then this module stops the packet streaming.
  78 #define IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES        5
  79
  80 static void pcm_period_work(struct work_struct *work);
  81
  82 /**
  83  * amdtp_stream_init - initialize an AMDTP stream structure
  84  * @s: the AMDTP stream to initialize
  85  * @unit: the target of the stream
  86  * @dir: the direction of stream
  87  * @flags: the details of the streaming protocol consist of cip_flags enumeration-constants.
  88  * @fmt: the value of fmt field in CIP header
  89  * @process_ctx_payloads: callback handler to process payloads of isoc context
  90  * @protocol_size: the size to allocate newly for protocol
  91  */
  92 int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit,
  93                       enum amdtp_stream_direction dir, unsigned int flags,
  94                       unsigned int fmt,
  95                       amdtp_stream_process_ctx_payloads_t process_ctx_payloads,
  96                       unsigned int protocol_size)
  97 {
  98         if (process_ctx_payloads == NULL)
  99                 return -EINVAL;
 100
 101         s->protocol = kzalloc(protocol_size, GFP_KERNEL);
 102         if (!s->protocol)
 103                 return -ENOMEM;
 104
 105         s->unit = unit;
 106         s->direction = dir;
 107         s->flags = flags;
 108         s->context = ERR_PTR(-1);
 109         mutex_init(&s->mutex);
 110         INIT_WORK(&s->period_work, pcm_period_work);
 111         s->packet_index = 0;
 112
 113         init_waitqueue_head(&s->ready_wait);
 114
 115         s->fmt = fmt;
 116         s->process_ctx_payloads = process_ctx_payloads;
 117
 118         return 0;
 119 }
 120 EXPORT_SYMBOL(amdtp_stream_init);
 121
 122 /**
 123  * amdtp_stream_destroy - free stream resources
 124  * @s: the AMDTP stream to destroy
 125  */
 126 void amdtp_stream_destroy(struct amdtp_stream *s)
 127 {
 128         /* Not initialized. */
 129         if (s->protocol == NULL)
 130                 return;
 131
 132         WARN_ON(amdtp_stream_running(s));
 133         kfree(s->protocol);
 134         mutex_destroy(&s->mutex);
 135 }
 136 EXPORT_SYMBOL(amdtp_stream_destroy);
 137
 138 const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = {
 139         [CIP_SFC_32000]  =  8,
 140         [CIP_SFC_44100]  =  8,
 141         [CIP_SFC_48000]  =  8,
 142         [CIP_SFC_88200]  = 16,
 143         [CIP_SFC_96000]  = 16,
 144         [CIP_SFC_176400] = 32,
 145         [CIP_SFC_192000] = 32,
 146 };
 147 EXPORT_SYMBOL(amdtp_syt_intervals);
 148
 149 const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = {
 150         [CIP_SFC_32000]  =  32000,
 151         [CIP_SFC_44100]  =  44100,
 152         [CIP_SFC_48000]  =  48000,
 153         [CIP_SFC_88200]  =  88200,
 154         [CIP_SFC_96000]  =  96000,
 155         [CIP_SFC_176400] = 176400,
 156         [CIP_SFC_192000] = 192000,
 157 };
 158 EXPORT_SYMBOL(amdtp_rate_table);
 159
 160 static int apply_constraint_to_size(struct snd_pcm_hw_params *params,
 161                                     struct snd_pcm_hw_rule *rule)
 162 {
 163         struct snd_interval *s = hw_param_interval(params, rule->var);
 164         const struct snd_interval *r =
 165                 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
 166         struct snd_interval t = {0};
 167         unsigned int step = 0;
 168         int i;
 169
 170         for (i = 0; i < CIP_SFC_COUNT; ++i) {
 171                 if (snd_interval_test(r, amdtp_rate_table[i]))
 172                         step = max(step, amdtp_syt_intervals[i]);
 173         }
 174
 175         t.min = roundup(s->min, step);
 176         t.max = rounddown(s->max, step);
 177         t.integer = 1;
 178
 179         return snd_interval_refine(s, &t);
 180 }
 181
 182 /**
 183  * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream
 184  * @s:          the AMDTP stream, which must be initialized.
 185  * @runtime:    the PCM substream runtime
 186  */
 187 int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s,
 188                                         struct snd_pcm_runtime *runtime)
 189 {
 190         struct snd_pcm_hardware *hw = &runtime->hw;
 191         unsigned int ctx_header_size;
 192         unsigned int maximum_usec_per_period;
 193         int err;
 194
 195         hw->info = SNDRV_PCM_INFO_BATCH |
 196                    SNDRV_PCM_INFO_BLOCK_TRANSFER |
 197                    SNDRV_PCM_INFO_INTERLEAVED |
 198                    SNDRV_PCM_INFO_JOINT_DUPLEX |
 199                    SNDRV_PCM_INFO_MMAP |
 200                    SNDRV_PCM_INFO_MMAP_VALID;
 201
 202         /* SNDRV_PCM_INFO_BATCH */
 203         hw->periods_min = 2;
 204         hw->periods_max = UINT_MAX;
 205
 206         /* bytes for a frame */
 207         hw->period_bytes_min = 4 * hw->channels_max;
 208
 209         /* Just to prevent from allocating much pages. */
 210         hw->period_bytes_max = hw->period_bytes_min * 2048;
 211         hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min;
 212
 213         // Linux driver for 1394 OHCI controller voluntarily flushes isoc
 214         // context when total size of accumulated context header reaches
 215         // PAGE_SIZE. This kicks work for the isoc context and brings
 216         // callback in the middle of scheduled interrupts.
 217         // Although AMDTP streams in the same domain use the same events per
 218         // IRQ, use the largest size of context header between IT/IR contexts.
 219         // Here, use the value of context header in IR context is for both
 220         // contexts.
 221         if (!(s->flags & CIP_NO_HEADER))
 222                 ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
 223         else
 224                 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
 225         maximum_usec_per_period = USEC_PER_SEC * PAGE_SIZE /
 226                                   CYCLES_PER_SECOND / ctx_header_size;
 227
 228         // In IEC 61883-6, one isoc packet can transfer events up to the value
 229         // of syt interval. This comes from the interval of isoc cycle. As 1394
 230         // OHCI controller can generate hardware IRQ per isoc packet, the
 231         // interval is 125 usec.
 232         // However, there are two ways of transmission in IEC 61883-6; blocking
 233         // and non-blocking modes. In blocking mode, the sequence of isoc packet
 234         // includes 'empty' or 'NODATA' packets which include no event. In
 235         // non-blocking mode, the number of events per packet is variable up to
 236         // the syt interval.
 237         // Due to the above protocol design, the minimum PCM frames per
 238         // interrupt should be double of the value of syt interval, thus it is
 239         // 250 usec.
 240         err = snd_pcm_hw_constraint_minmax(runtime,
 241                                            SNDRV_PCM_HW_PARAM_PERIOD_TIME,
 242                                            250, maximum_usec_per_period);
 243         if (err < 0)
 244                 goto end;
 245
 246         /* Non-Blocking stream has no more constraints */
 247         if (!(s->flags & CIP_BLOCKING))
 248                 goto end;
 249
 250         /*
 251          * One AMDTP packet can include some frames. In blocking mode, the
 252          * number equals to SYT_INTERVAL. So the number is 8, 16 or 32,
 253          * depending on its sampling rate. For accurate period interrupt, it's
 254          * preferrable to align period/buffer sizes to current SYT_INTERVAL.
 255          */
 256         err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 257                                   apply_constraint_to_size, NULL,
 258                                   SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 259                                   SNDRV_PCM_HW_PARAM_RATE, -1);
 260         if (err < 0)
 261                 goto end;
 262         err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 263                                   apply_constraint_to_size, NULL,
 264                                   SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 265                                   SNDRV_PCM_HW_PARAM_RATE, -1);
 266         if (err < 0)
 267                 goto end;
 268 end:
 269         return err;
 270 }
 271 EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints);
 272
 273 /**
 274  * amdtp_stream_set_parameters - set stream parameters
 275  * @s: the AMDTP stream to configure
 276  * @rate: the sample rate
 277  * @data_block_quadlets: the size of a data block in quadlet unit
 278  *
 279  * The parameters must be set before the stream is started, and must not be
 280  * changed while the stream is running.
 281  */
 282 int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate,
 283                                 unsigned int data_block_quadlets)
 284 {
 285         unsigned int sfc;
 286
 287         for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) {
 288                 if (amdtp_rate_table[sfc] == rate)
 289                         break;
 290         }
 291         if (sfc == ARRAY_SIZE(amdtp_rate_table))
 292                 return -EINVAL;
 293
 294         s->sfc = sfc;
 295         s->data_block_quadlets = data_block_quadlets;
 296         s->syt_interval = amdtp_syt_intervals[sfc];
 297
 298         // default buffering in the device.
 299         s->transfer_delay = TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
 300
 301         // additional buffering needed to adjust for no-data packets.
 302         if (s->flags & CIP_BLOCKING)
 303                 s->transfer_delay += TICKS_PER_SECOND * s->syt_interval / rate;
 304
 305         return 0;
 306 }
 307 EXPORT_SYMBOL(amdtp_stream_set_parameters);
 308
 309 // The CIP header is processed in context header apart from context payload.
 310 static int amdtp_stream_get_max_ctx_payload_size(struct amdtp_stream *s)
 311 {
 312         unsigned int multiplier;
 313
 314         if (s->flags & CIP_JUMBO_PAYLOAD)
 315                 multiplier = IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES;
 316         else
 317                 multiplier = 1;
 318
 319         return s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier;
 320 }
 321
 322 /**
 323  * amdtp_stream_get_max_payload - get the stream's packet size
 324  * @s: the AMDTP stream
 325  *
 326  * This function must not be called before the stream has been configured
 327  * with amdtp_stream_set_parameters().
 328  */
 329 unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s)
 330 {
 331         unsigned int cip_header_size;
 332
 333         if (!(s->flags & CIP_NO_HEADER))
 334                 cip_header_size = CIP_HEADER_SIZE;
 335         else
 336                 cip_header_size = 0;
 337
 338         return cip_header_size + amdtp_stream_get_max_ctx_payload_size(s);
 339 }
 340 EXPORT_SYMBOL(amdtp_stream_get_max_payload);
 341
 342 /**
 343  * amdtp_stream_pcm_prepare - prepare PCM device for running
 344  * @s: the AMDTP stream
 345  *
 346  * This function should be called from the PCM device's .prepare callback.
 347  */
 348 void amdtp_stream_pcm_prepare(struct amdtp_stream *s)
 349 {
 350         cancel_work_sync(&s->period_work);
 351         s->pcm_buffer_pointer = 0;
 352         s->pcm_period_pointer = 0;
 353 }
 354 EXPORT_SYMBOL(amdtp_stream_pcm_prepare);
 355
 356 static void pool_blocking_data_blocks(struct amdtp_stream *s, struct seq_desc *descs,
 357                                       const unsigned int seq_size, unsigned int seq_tail,
 358                                       unsigned int count)
 359 {
 360         const unsigned int syt_interval = s->syt_interval;
 361         int i;
 362
 363         for (i = 0; i < count; ++i) {
 364                 struct seq_desc *desc = descs + seq_tail;
 365
 366                 if (desc->syt_offset != CIP_SYT_NO_INFO)
 367                         desc->data_blocks = syt_interval;
 368                 else
 369                         desc->data_blocks = 0;
 370
 371                 seq_tail = (seq_tail + 1) % seq_size;
 372         }
 373 }
 374
 375 static void pool_ideal_nonblocking_data_blocks(struct amdtp_stream *s, struct seq_desc *descs,
 376                                                const unsigned int seq_size, unsigned int seq_tail,
 377                                                unsigned int count)
 378 {
 379         const enum cip_sfc sfc = s->sfc;
 380         unsigned int state = s->ctx_data.rx.data_block_state;
 381         int i;
 382
 383         for (i = 0; i < count; ++i) {
 384                 struct seq_desc *desc = descs + seq_tail;
 385
 386                 if (!cip_sfc_is_base_44100(sfc)) {
 387                         // Sample_rate / 8000 is an integer, and precomputed.
 388                         desc->data_blocks = state;
 389                 } else {
 390                         unsigned int phase = state;
 391
 392                 /*
 393                  * This calculates the number of data blocks per packet so that
 394                  * 1) the overall rate is correct and exactly synchronized to
 395                  *    the bus clock, and
 396                  * 2) packets with a rounded-up number of blocks occur as early
 397                  *    as possible in the sequence (to prevent underruns of the
 398                  *    device's buffer).
 399                  */
 400                         if (sfc == CIP_SFC_44100)
 401                                 /* 6 6 5 6 5 6 5 ... */
 402                                 desc->data_blocks = 5 + ((phase & 1) ^ (phase == 0 || phase >= 40));
 403                         else
 404                                 /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */
 405                                 desc->data_blocks = 11 * (sfc >> 1) + (phase == 0);
 406                         if (++phase >= (80 >> (sfc >> 1)))
 407                                 phase = 0;
 408                         state = phase;
 409                 }
 410
 411                 seq_tail = (seq_tail + 1) % seq_size;
 412         }
 413
 414         s->ctx_data.rx.data_block_state = state;
 415 }
 416
 417 static unsigned int calculate_syt_offset(unsigned int *last_syt_offset,
 418                         unsigned int *syt_offset_state, enum cip_sfc sfc)
 419 {
 420         unsigned int syt_offset;
 421
 422         if (*last_syt_offset < TICKS_PER_CYCLE) {
 423                 if (!cip_sfc_is_base_44100(sfc))
 424                         syt_offset = *last_syt_offset + *syt_offset_state;
 425                 else {
 426                 /*
 427                  * The time, in ticks, of the n'th SYT_INTERVAL sample is:
 428                  *   n * SYT_INTERVAL * 24576000 / sample_rate
 429                  * Modulo TICKS_PER_CYCLE, the difference between successive
 430                  * elements is about 1386.23.  Rounding the results of this
 431                  * formula to the SYT precision results in a sequence of
 432                  * differences that begins with:
 433                  *   1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ...
 434                  * This code generates _exactly_ the same sequence.
 435                  */
 436                         unsigned int phase = *syt_offset_state;
 437                         unsigned int index = phase % 13;
 438
 439                         syt_offset = *last_syt_offset;
 440                         syt_offset += 1386 + ((index && !(index & 3)) ||
 441                                               phase == 146);
 442                         if (++phase >= 147)
 443                                 phase = 0;
 444                         *syt_offset_state = phase;
 445                 }
 446         } else
 447                 syt_offset = *last_syt_offset - TICKS_PER_CYCLE;
 448         *last_syt_offset = syt_offset;
 449
 450         if (syt_offset >= TICKS_PER_CYCLE)
 451                 syt_offset = CIP_SYT_NO_INFO;
 452
 453         return syt_offset;
 454 }
 455
 456 static void pool_ideal_syt_offsets(struct amdtp_stream *s, struct seq_desc *descs,
 457                                    const unsigned int seq_size, unsigned int seq_tail,
 458                                    unsigned int count)
 459 {
 460         const enum cip_sfc sfc = s->sfc;
 461         unsigned int last = s->ctx_data.rx.last_syt_offset;
 462         unsigned int state = s->ctx_data.rx.syt_offset_state;
 463         int i;
 464
 465         for (i = 0; i < count; ++i) {
 466                 struct seq_desc *desc = descs + seq_tail;
 467
 468                 desc->syt_offset = calculate_syt_offset(&last, &state, sfc);
 469
 470                 seq_tail = (seq_tail + 1) % seq_size;
 471         }
 472
 473         s->ctx_data.rx.last_syt_offset = last;
 474         s->ctx_data.rx.syt_offset_state = state;
 475 }
 476
 477 static unsigned int compute_syt_offset(unsigned int syt, unsigned int cycle,
 478                                        unsigned int transfer_delay)
 479 {
 480         unsigned int cycle_lo = (cycle % CYCLES_PER_SECOND) & 0x0f;
 481         unsigned int syt_cycle_lo = (syt & 0xf000) >> 12;
 482         unsigned int syt_offset;
 483
 484         // Round up.
 485         if (syt_cycle_lo < cycle_lo)
 486                 syt_cycle_lo += CIP_SYT_CYCLE_MODULUS;
 487         syt_cycle_lo -= cycle_lo;
 488
 489         // Subtract transfer delay so that the synchronization offset is not so large
 490         // at transmission.
 491         syt_offset = syt_cycle_lo * TICKS_PER_CYCLE + (syt & 0x0fff);
 492         if (syt_offset < transfer_delay)
 493                 syt_offset += CIP_SYT_CYCLE_MODULUS * TICKS_PER_CYCLE;
 494
 495         return syt_offset - transfer_delay;
 496 }
 497
 498 static void cache_seq(struct amdtp_stream *s, const struct pkt_desc *descs, unsigned int desc_count)
 499 {
 500         const unsigned int transfer_delay = s->transfer_delay;
 501         const unsigned int cache_size = s->ctx_data.tx.cache.size;
 502         struct seq_desc *cache = s->ctx_data.tx.cache.descs;
 503         unsigned int cache_tail = s->ctx_data.tx.cache.tail;
 504         bool aware_syt = !(s->flags & CIP_UNAWARE_SYT);
 505         int i;
 506
 507         for (i = 0; i < desc_count; ++i) {
 508                 struct seq_desc *dst = cache + cache_tail;
 509                 const struct pkt_desc *src = descs + i;
 510
 511                 if (aware_syt && src->syt != CIP_SYT_NO_INFO)
 512                         dst->syt_offset = compute_syt_offset(src->syt, src->cycle, transfer_delay);
 513                 else
 514                         dst->syt_offset = CIP_SYT_NO_INFO;
 515                 dst->data_blocks = src->data_blocks;
 516
 517                 cache_tail = (cache_tail + 1) % cache_size;
 518         }
 519
 520         s->ctx_data.tx.cache.tail = cache_tail;
 521 }
 522
 523 static void pool_ideal_seq_descs(struct amdtp_stream *s, unsigned int count)
 524 {
 525         struct seq_desc *descs = s->ctx_data.rx.seq.descs;
 526         unsigned int seq_tail = s->ctx_data.rx.seq.tail;
 527         const unsigned int seq_size = s->ctx_data.rx.seq.size;
 528
 529         pool_ideal_syt_offsets(s, descs, seq_size, seq_tail, count);
 530
 531         if (s->flags & CIP_BLOCKING)
 532                 pool_blocking_data_blocks(s, descs, seq_size, seq_tail, count);
 533         else
 534                 pool_ideal_nonblocking_data_blocks(s, descs, seq_size, seq_tail, count);
 535
 536         s->ctx_data.rx.seq.tail = (seq_tail + count) % seq_size;
 537 }
 538
 539 static void update_pcm_pointers(struct amdtp_stream *s,
 540                                 struct snd_pcm_substream *pcm,
 541                                 unsigned int frames)
 542 {
 543         unsigned int ptr;
 544
 545         ptr = s->pcm_buffer_pointer + frames;
 546         if (ptr >= pcm->runtime->buffer_size)
 547                 ptr -= pcm->runtime->buffer_size;
 548         WRITE_ONCE(s->pcm_buffer_pointer, ptr);
 549
 550         s->pcm_period_pointer += frames;
 551         if (s->pcm_period_pointer >= pcm->runtime->period_size) {
 552                 s->pcm_period_pointer -= pcm->runtime->period_size;
 553                 queue_work(system_highpri_wq, &s->period_work);
 554         }
 555 }
 556
 557 static void pcm_period_work(struct work_struct *work)
 558 {
 559         struct amdtp_stream *s = container_of(work, struct amdtp_stream,
 560                                               period_work);
 561         struct snd_pcm_substream *pcm = READ_ONCE(s->pcm);
 562
 563         if (pcm)
 564                 snd_pcm_period_elapsed(pcm);
 565 }
 566
 567 static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params,
 568                         bool sched_irq)
 569 {
 570         int err;
 571
 572         params->interrupt = sched_irq;
 573         params->tag = s->tag;
 574         params->sy = 0;
 575
 576         err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer,
 577                                    s->buffer.packets[s->packet_index].offset);
 578         if (err < 0) {
 579                 dev_err(&s->unit->device, "queueing error: %d\n", err);
 580                 goto end;
 581         }
 582
 583         if (++s->packet_index >= s->queue_size)
 584                 s->packet_index = 0;
 585 end:
 586         return err;
 587 }
 588
 589 static inline int queue_out_packet(struct amdtp_stream *s,
 590                                    struct fw_iso_packet *params, bool sched_irq)
 591 {
 592         params->skip =
 593                 !!(params->header_length == 0 && params->payload_length == 0);
 594         return queue_packet(s, params, sched_irq);
 595 }
 596
 597 static inline int queue_in_packet(struct amdtp_stream *s,
 598                                   struct fw_iso_packet *params)
 599 {
 600         // Queue one packet for IR context.
 601         params->header_length = s->ctx_data.tx.ctx_header_size;
 602         params->payload_length = s->ctx_data.tx.max_ctx_payload_length;
 603         params->skip = false;
 604         return queue_packet(s, params, false);
 605 }
 606
 607 static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2],
 608                         unsigned int data_block_counter, unsigned int syt)
 609 {
 610         cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) |
 611                                 (s->data_block_quadlets << CIP_DBS_SHIFT) |
 612                                 ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) |
 613                                 data_block_counter);
 614         cip_header[1] = cpu_to_be32(CIP_EOH |
 615                         ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) |
 616                         ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) |
 617                         (syt & CIP_SYT_MASK));
 618 }
 619
 620 static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle,
 621                                 struct fw_iso_packet *params, unsigned int header_length,
 622                                 unsigned int data_blocks,
 623                                 unsigned int data_block_counter,
 624                                 unsigned int syt, unsigned int index)
 625 {
 626         unsigned int payload_length;
 627         __be32 *cip_header;
 628
 629         payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets;
 630         params->payload_length = payload_length;
 631
 632         if (header_length > 0) {
 633                 cip_header = (__be32 *)params->header;
 634                 generate_cip_header(s, cip_header, data_block_counter, syt);
 635                 params->header_length = header_length;
 636         } else {
 637                 cip_header = NULL;
 638         }
 639
 640         trace_amdtp_packet(s, cycle, cip_header, payload_length + header_length, data_blocks,
 641                            data_block_counter, s->packet_index, index);
 642 }
 643
 644 static int check_cip_header(struct amdtp_stream *s, const __be32 *buf,
 645                             unsigned int payload_length,
 646                             unsigned int *data_blocks,
 647                             unsigned int *data_block_counter, unsigned int *syt)
 648 {
 649         u32 cip_header[2];
 650         unsigned int sph;
 651         unsigned int fmt;
 652         unsigned int fdf;
 653         unsigned int dbc;
 654         bool lost;
 655
 656         cip_header[0] = be32_to_cpu(buf[0]);
 657         cip_header[1] = be32_to_cpu(buf[1]);
 658
 659         /*
 660          * This module supports 'Two-quadlet CIP header with SYT field'.
 661          * For convenience, also check FMT field is AM824 or not.
 662          */
 663         if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) ||
 664              ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) &&
 665             (!(s->flags & CIP_HEADER_WITHOUT_EOH))) {
 666                 dev_info_ratelimited(&s->unit->device,
 667                                 "Invalid CIP header for AMDTP: %08X:%08X\n",
 668                                 cip_header[0], cip_header[1]);
 669                 return -EAGAIN;
 670         }
 671
 672         /* Check valid protocol or not. */
 673         sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT;
 674         fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT;
 675         if (sph != s->sph || fmt != s->fmt) {
 676                 dev_info_ratelimited(&s->unit->device,
 677                                      "Detect unexpected protocol: %08x %08x\n",
 678                                      cip_header[0], cip_header[1]);
 679                 return -EAGAIN;
 680         }
 681
 682         /* Calculate data blocks */
 683         fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT;
 684         if (payload_length == 0 || (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) {
 685                 *data_blocks = 0;
 686         } else {
 687                 unsigned int data_block_quadlets =
 688                                 (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT;
 689                 /* avoid division by zero */
 690                 if (data_block_quadlets == 0) {
 691                         dev_err(&s->unit->device,
 692                                 "Detect invalid value in dbs field: %08X\n",
 693                                 cip_header[0]);
 694                         return -EPROTO;
 695                 }
 696                 if (s->flags & CIP_WRONG_DBS)
 697                         data_block_quadlets = s->data_block_quadlets;
 698
 699                 *data_blocks = payload_length / sizeof(__be32) / data_block_quadlets;
 700         }
 701
 702         /* Check data block counter continuity */
 703         dbc = cip_header[0] & CIP_DBC_MASK;
 704         if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) &&
 705             *data_block_counter != UINT_MAX)
 706                 dbc = *data_block_counter;
 707
 708         if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) ||
 709             *data_block_counter == UINT_MAX) {
 710                 lost = false;
 711         } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) {
 712                 lost = dbc != *data_block_counter;
 713         } else {
 714                 unsigned int dbc_interval;
 715
 716                 if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0)
 717                         dbc_interval = s->ctx_data.tx.dbc_interval;
 718                 else
 719                         dbc_interval = *data_blocks;
 720
 721                 lost = dbc != ((*data_block_counter + dbc_interval) & 0xff);
 722         }
 723
 724         if (lost) {
 725                 dev_err(&s->unit->device,
 726                         "Detect discontinuity of CIP: %02X %02X\n",
 727                         *data_block_counter, dbc);
 728                 return -EIO;
 729         }
 730
 731         *data_block_counter = dbc;
 732
 733         if (!(s->flags & CIP_UNAWARE_SYT))
 734                 *syt = cip_header[1] & CIP_SYT_MASK;
 735
 736         return 0;
 737 }
 738
 739 static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle,
 740                                const __be32 *ctx_header,
 741                                unsigned int *data_blocks,
 742                                unsigned int *data_block_counter,
 743                                unsigned int *syt, unsigned int packet_index, unsigned int index)
 744 {
 745         unsigned int payload_length;
 746         const __be32 *cip_header;
 747         unsigned int cip_header_size;
 748
 749         payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT;
 750
 751         if (!(s->flags & CIP_NO_HEADER))
 752                 cip_header_size = CIP_HEADER_SIZE;
 753         else
 754                 cip_header_size = 0;
 755
 756         if (payload_length > cip_header_size + s->ctx_data.tx.max_ctx_payload_length) {
 757                 dev_err(&s->unit->device,
 758                         "Detect jumbo payload: %04x %04x\n",
 759                         payload_length, cip_header_size + s->ctx_data.tx.max_ctx_payload_length);
 760                 return -EIO;
 761         }
 762
 763         if (cip_header_size > 0) {
 764                 if (payload_length >= cip_header_size) {
 765                         int err;
 766
 767                         cip_header = ctx_header + IR_CTX_HEADER_DEFAULT_QUADLETS;
 768                         err = check_cip_header(s, cip_header, payload_length - cip_header_size,
 769                                                data_blocks, data_block_counter, syt);
 770                         if (err < 0)
 771                                 return err;
 772                 } else {
 773                         // Handle the cycle so that empty packet arrives.
 774                         cip_header = NULL;
 775                         *data_blocks = 0;
 776                         *syt = 0;
 777                 }
 778         } else {
 779                 cip_header = NULL;
 780                 *data_blocks = payload_length / sizeof(__be32) / s->data_block_quadlets;
 781                 *syt = 0;
 782
 783                 if (*data_block_counter == UINT_MAX)
 784                         *data_block_counter = 0;
 785         }
 786
 787         trace_amdtp_packet(s, cycle, cip_header, payload_length, *data_blocks,
 788                            *data_block_counter, packet_index, index);
 789
 790         return 0;
 791 }
 792
 793 // In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On
 794 // the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent
 795 // it. Thus, via Linux firewire subsystem, we can get the 3 bits for second.
 796 static inline u32 compute_ohci_cycle_count(__be32 ctx_header_tstamp)
 797 {
 798         u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK;
 799         return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff);
 800 }
 801
 802 static inline u32 increment_ohci_cycle_count(u32 cycle, unsigned int addend)
 803 {
 804         cycle += addend;
 805         if (cycle >= OHCI_SECOND_MODULUS * CYCLES_PER_SECOND)
 806                 cycle -= OHCI_SECOND_MODULUS * CYCLES_PER_SECOND;
 807         return cycle;
 808 }
 809
 810 static int compare_ohci_cycle_count(u32 lval, u32 rval)
 811 {
 812         if (lval == rval)
 813                 return 0;
 814         else if (lval < rval && rval - lval < OHCI_SECOND_MODULUS * CYCLES_PER_SECOND / 2)
 815                 return -1;
 816         else
 817                 return 1;
 818 }
 819
 820 // Align to actual cycle count for the packet which is going to be scheduled.
 821 // This module queued the same number of isochronous cycle as the size of queue
 822 // to kip isochronous cycle, therefore it's OK to just increment the cycle by
 823 // the size of queue for scheduled cycle.
 824 static inline u32 compute_ohci_it_cycle(const __be32 ctx_header_tstamp,
 825                                         unsigned int queue_size)
 826 {
 827         u32 cycle = compute_ohci_cycle_count(ctx_header_tstamp);
 828         return increment_ohci_cycle_count(cycle, queue_size);
 829 }
 830
 831 static int generate_device_pkt_descs(struct amdtp_stream *s,
 832                                      struct pkt_desc *descs,
 833                                      const __be32 *ctx_header,
 834                                      unsigned int packets,
 835                                      unsigned int *desc_count)
 836 {
 837         unsigned int next_cycle = s->next_cycle;
 838         unsigned int dbc = s->data_block_counter;
 839         unsigned int packet_index = s->packet_index;
 840         unsigned int queue_size = s->queue_size;
 841         int i;
 842         int err;
 843
 844         *desc_count = 0;
 845         for (i = 0; i < packets; ++i) {
 846                 struct pkt_desc *desc = descs + *desc_count;
 847                 unsigned int cycle;
 848                 bool lost;
 849                 unsigned int data_blocks;
 850                 unsigned int syt;
 851
 852                 cycle = compute_ohci_cycle_count(ctx_header[1]);
 853                 lost = (next_cycle != cycle);
 854                 if (lost) {
 855                         if (s->flags & CIP_NO_HEADER) {
 856                                 // Fireface skips transmission just for an isoc cycle corresponding
 857                                 // to empty packet.
 858                                 unsigned int prev_cycle = next_cycle;
 859
 860                                 next_cycle = increment_ohci_cycle_count(next_cycle, 1);
 861                                 lost = (next_cycle != cycle);
 862                                 if (!lost) {
 863                                         // Prepare a description for the skipped cycle for
 864                                         // sequence replay.
 865                                         desc->cycle = prev_cycle;
 866                                         desc->syt = 0;
 867                                         desc->data_blocks = 0;
 868                                         desc->data_block_counter = dbc;
 869                                         desc->ctx_payload = NULL;
 870                                         ++desc;
 871                                         ++(*desc_count);
 872                                 }
 873                         } else if (s->flags & CIP_JUMBO_PAYLOAD) {
 874                                 // OXFW970 skips transmission for several isoc cycles during
 875                                 // asynchronous transaction. The sequence replay is impossible due
 876                                 // to the reason.
 877                                 unsigned int safe_cycle = increment_ohci_cycle_count(next_cycle,
 878                                                                 IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES);
 879                                 lost = (compare_ohci_cycle_count(safe_cycle, cycle) > 0);
 880                         }
 881                         if (lost) {
 882                                 dev_err(&s->unit->device, "Detect discontinuity of cycle: %d %d\n",
 883                                         next_cycle, cycle);
 884                                 return -EIO;
 885                         }
 886                 }
 887
 888                 err = parse_ir_ctx_header(s, cycle, ctx_header, &data_blocks, &dbc, &syt,
 889                                           packet_index, i);
 890                 if (err < 0)
 891                         return err;
 892
 893                 desc->cycle = cycle;
 894                 desc->syt = syt;
 895                 desc->data_blocks = data_blocks;
 896                 desc->data_block_counter = dbc;
 897                 desc->ctx_payload = s->buffer.packets[packet_index].buffer;
 898
 899                 if (!(s->flags & CIP_DBC_IS_END_EVENT))
 900                         dbc = (dbc + desc->data_blocks) & 0xff;
 901
 902                 next_cycle = increment_ohci_cycle_count(next_cycle, 1);
 903                 ++(*desc_count);
 904                 ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
 905                 packet_index = (packet_index + 1) % queue_size;
 906         }
 907
 908         s->next_cycle = next_cycle;
 909         s->data_block_counter = dbc;
 910
 911         return 0;
 912 }
 913
 914 static unsigned int compute_syt(unsigned int syt_offset, unsigned int cycle,
 915                                 unsigned int transfer_delay)
 916 {
 917         unsigned int syt;
 918
 919         syt_offset += transfer_delay;
 920         syt = ((cycle + syt_offset / TICKS_PER_CYCLE) << 12) |
 921               (syt_offset % TICKS_PER_CYCLE);
 922         return syt & CIP_SYT_MASK;
 923 }
 924
 925 static void generate_pkt_descs(struct amdtp_stream *s, const __be32 *ctx_header, unsigned int packets)
 926 {
 927         struct pkt_desc *descs = s->pkt_descs;
 928         const struct seq_desc *seq_descs = s->ctx_data.rx.seq.descs;
 929         const unsigned int seq_size = s->ctx_data.rx.seq.size;
 930         unsigned int dbc = s->data_block_counter;
 931         unsigned int seq_head = s->ctx_data.rx.seq.head;
 932         bool aware_syt = !(s->flags & CIP_UNAWARE_SYT);
 933         int i;
 934
 935         for (i = 0; i < packets; ++i) {
 936                 struct pkt_desc *desc = descs + i;
 937                 unsigned int index = (s->packet_index + i) % s->queue_size;
 938                 const struct seq_desc *seq = seq_descs + seq_head;
 939
 940                 desc->cycle = compute_ohci_it_cycle(*ctx_header, s->queue_size);
 941
 942                 if (aware_syt && seq->syt_offset != CIP_SYT_NO_INFO)
 943                         desc->syt = compute_syt(seq->syt_offset, desc->cycle, s->transfer_delay);
 944                 else
 945                         desc->syt = CIP_SYT_NO_INFO;
 946
 947                 desc->data_blocks = seq->data_blocks;
 948
 949                 if (s->flags & CIP_DBC_IS_END_EVENT)
 950                         dbc = (dbc + desc->data_blocks) & 0xff;
 951
 952                 desc->data_block_counter = dbc;
 953
 954                 if (!(s->flags & CIP_DBC_IS_END_EVENT))
 955                         dbc = (dbc + desc->data_blocks) & 0xff;
 956
 957                 desc->ctx_payload = s->buffer.packets[index].buffer;
 958
 959                 seq_head = (seq_head + 1) % seq_size;
 960
 961                 ++ctx_header;
 962         }
 963
 964         s->data_block_counter = dbc;
 965         s->ctx_data.rx.seq.head = seq_head;
 966 }
 967
 968 static inline void cancel_stream(struct amdtp_stream *s)
 969 {
 970         s->packet_index = -1;
 971         if (current_work() == &s->period_work)
 972                 amdtp_stream_pcm_abort(s);
 973         WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN);
 974 }
 975
 976 static void process_ctx_payloads(struct amdtp_stream *s,
 977                                  const struct pkt_desc *descs,
 978                                  unsigned int packets)
 979 {
 980         struct snd_pcm_substream *pcm;
 981         unsigned int pcm_frames;
 982
 983         pcm = READ_ONCE(s->pcm);
 984         pcm_frames = s->process_ctx_payloads(s, descs, packets, pcm);
 985         if (pcm)
 986                 update_pcm_pointers(s, pcm, pcm_frames);
 987 }
 988
 989 static void process_rx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
 990                                void *header, void *private_data)
 991 {
 992         struct amdtp_stream *s = private_data;
 993         const struct amdtp_domain *d = s->domain;
 994         const __be32 *ctx_header = header;
 995         const unsigned int events_per_period = d->events_per_period;
 996         unsigned int event_count = s->ctx_data.rx.event_count;
 997         unsigned int pkt_header_length;
 998         unsigned int packets;
 999         int i;
1000
1001         if (s->packet_index < 0)
1002                 return;
1003
1004         // Calculate the number of packets in buffer and check XRUN.
1005         packets = header_length / sizeof(*ctx_header);
1006
1007         pool_ideal_seq_descs(s, packets);
1008
1009         generate_pkt_descs(s, ctx_header, packets);
1010
1011         process_ctx_payloads(s, s->pkt_descs, packets);
1012
1013         if (!(s->flags & CIP_NO_HEADER))
1014                 pkt_header_length = IT_PKT_HEADER_SIZE_CIP;
1015         else
1016                 pkt_header_length = 0;
1017
1018         for (i = 0; i < packets; ++i) {
1019                 const struct pkt_desc *desc = s->pkt_descs + i;
1020                 struct {
1021                         struct fw_iso_packet params;
1022                         __be32 header[CIP_HEADER_QUADLETS];
1023                 } template = { {0}, {0} };
1024                 bool sched_irq = false;
1025
1026                 build_it_pkt_header(s, desc->cycle, &template.params, pkt_header_length,
1027                                     desc->data_blocks, desc->data_block_counter,
1028                                     desc->syt, i);
1029
1030                 if (s == s->domain->irq_target) {
1031                         event_count += desc->data_blocks;
1032                         if (event_count >= events_per_period) {
1033                                 event_count -= events_per_period;
1034                                 sched_irq = true;
1035                         }
1036                 }
1037
1038                 if (queue_out_packet(s, &template.params, sched_irq) < 0) {
1039                         cancel_stream(s);
1040                         return;
1041                 }
1042         }
1043
1044         s->ctx_data.rx.event_count = event_count;
1045 }
1046
1047 static void skip_rx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1048                             void *header, void *private_data)
1049 {
1050         struct amdtp_stream *s = private_data;
1051         struct amdtp_domain *d = s->domain;
1052         const __be32 *ctx_header = header;
1053         unsigned int packets;
1054         unsigned int cycle;
1055         int i;
1056
1057         if (s->packet_index < 0)
1058                 return;
1059
1060         packets = header_length / sizeof(*ctx_header);
1061
1062         cycle = compute_ohci_it_cycle(ctx_header[packets - 1], s->queue_size);
1063         s->next_cycle = increment_ohci_cycle_count(cycle, 1);
1064
1065         for (i = 0; i < packets; ++i) {
1066                 struct fw_iso_packet params = {
1067                         .header_length = 0,
1068                         .payload_length = 0,
1069                 };
1070                 bool sched_irq = (s == d->irq_target && i == packets - 1);
1071
1072                 if (queue_out_packet(s, &params, sched_irq) < 0) {
1073                         cancel_stream(s);
1074                         return;
1075                 }
1076         }
1077 }
1078
1079 static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1080                                 void *header, void *private_data);
1081
1082 static void process_rx_packets_intermediately(struct fw_iso_context *context, u32 tstamp,
1083                                         size_t header_length, void *header, void *private_data)
1084 {
1085         struct amdtp_stream *s = private_data;
1086         struct amdtp_domain *d = s->domain;
1087         __be32 *ctx_header = header;
1088         const unsigned int queue_size = s->queue_size;
1089         unsigned int packets;
1090         unsigned int offset;
1091
1092         if (s->packet_index < 0)
1093                 return;
1094
1095         packets = header_length / sizeof(*ctx_header);
1096
1097         offset = 0;
1098         while (offset < packets) {
1099                 unsigned int cycle = compute_ohci_it_cycle(ctx_header[offset], queue_size);
1100
1101                 if (compare_ohci_cycle_count(cycle, d->processing_cycle.rx_start) >= 0)
1102                         break;
1103
1104                 ++offset;
1105         }
1106
1107         if (offset > 0) {
1108                 unsigned int length = sizeof(*ctx_header) * offset;
1109
1110                 skip_rx_packets(context, tstamp, length, ctx_header, private_data);
1111                 if (amdtp_streaming_error(s))
1112                         return;
1113
1114                 ctx_header += offset;
1115                 header_length -= length;
1116         }
1117
1118         if (offset < packets) {
1119                 s->ready_processing = true;
1120                 wake_up(&s->ready_wait);
1121
1122                 process_rx_packets(context, tstamp, header_length, ctx_header, private_data);
1123                 if (amdtp_streaming_error(s))
1124                         return;
1125
1126                 if (s == d->irq_target)
1127                         s->context->callback.sc = irq_target_callback;
1128                 else
1129                         s->context->callback.sc = process_rx_packets;
1130         }
1131 }
1132
1133 static void process_tx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1134                                void *header, void *private_data)
1135 {
1136         struct amdtp_stream *s = private_data;
1137         __be32 *ctx_header = header;
1138         unsigned int packets;
1139         unsigned int desc_count;
1140         int i;
1141         int err;
1142
1143         if (s->packet_index < 0)
1144                 return;
1145
1146         // Calculate the number of packets in buffer and check XRUN.
1147         packets = header_length / s->ctx_data.tx.ctx_header_size;
1148
1149         desc_count = 0;
1150         err = generate_device_pkt_descs(s, s->pkt_descs, ctx_header, packets, &desc_count);
1151         if (err < 0) {
1152                 if (err != -EAGAIN) {
1153                         cancel_stream(s);
1154                         return;
1155                 }
1156         } else {
1157                 struct amdtp_domain *d = s->domain;
1158
1159                 process_ctx_payloads(s, s->pkt_descs, desc_count);
1160
1161                 if (d->replay.enable)
1162                         cache_seq(s, s->pkt_descs, desc_count);
1163         }
1164
1165         for (i = 0; i < packets; ++i) {
1166                 struct fw_iso_packet params = {0};
1167
1168                 if (queue_in_packet(s, &params) < 0) {
1169                         cancel_stream(s);
1170                         return;
1171                 }
1172         }
1173 }
1174
1175 static void drop_tx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1176                             void *header, void *private_data)
1177 {
1178         struct amdtp_stream *s = private_data;
1179         const __be32 *ctx_header = header;
1180         unsigned int packets;
1181         unsigned int cycle;
1182         int i;
1183
1184         if (s->packet_index < 0)
1185                 return;
1186
1187         packets = header_length / s->ctx_data.tx.ctx_header_size;
1188
1189         ctx_header += (packets - 1) * s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
1190         cycle = compute_ohci_cycle_count(ctx_header[1]);
1191         s->next_cycle = increment_ohci_cycle_count(cycle, 1);
1192
1193         for (i = 0; i < packets; ++i) {
1194                 struct fw_iso_packet params = {0};
1195
1196                 if (queue_in_packet(s, &params) < 0) {
1197                         cancel_stream(s);
1198                         return;
1199                 }
1200         }
1201 }
1202
1203 static void process_tx_packets_intermediately(struct fw_iso_context *context, u32 tstamp,
1204                                         size_t header_length, void *header, void *private_data)
1205 {
1206         struct amdtp_stream *s = private_data;
1207         struct amdtp_domain *d = s->domain;
1208         __be32 *ctx_header;
1209         unsigned int packets;
1210         unsigned int offset;
1211
1212         if (s->packet_index < 0)
1213                 return;
1214
1215         packets = header_length / s->ctx_data.tx.ctx_header_size;
1216
1217         offset = 0;
1218         ctx_header = header;
1219         while (offset < packets) {
1220                 unsigned int cycle = compute_ohci_cycle_count(ctx_header[1]);
1221
1222                 if (compare_ohci_cycle_count(cycle, d->processing_cycle.tx_start) >= 0)
1223                         break;
1224
1225                 ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(__be32);
1226                 ++offset;
1227         }
1228
1229         ctx_header = header;
1230
1231         if (offset > 0) {
1232                 size_t length = s->ctx_data.tx.ctx_header_size * offset;
1233
1234                 drop_tx_packets(context, tstamp, length, ctx_header, s);
1235                 if (amdtp_streaming_error(s))
1236                         return;
1237
1238                 ctx_header += length / sizeof(*ctx_header);
1239                 header_length -= length;
1240         }
1241
1242         if (offset < packets) {
1243                 s->ready_processing = true;
1244                 wake_up(&s->ready_wait);
1245
1246                 process_tx_packets(context, tstamp, header_length, ctx_header, s);
1247                 if (amdtp_streaming_error(s))
1248                         return;
1249
1250                 context->callback.sc = process_tx_packets;
1251         }
1252 }
1253
1254 static void drop_tx_packets_initially(struct fw_iso_context *context, u32 tstamp,
1255                                       size_t header_length, void *header, void *private_data)
1256 {
1257         struct amdtp_stream *s = private_data;
1258         struct amdtp_domain *d = s->domain;
1259         __be32 *ctx_header;
1260         unsigned int count;
1261         unsigned int events;
1262         int i;
1263
1264         if (s->packet_index < 0)
1265                 return;
1266
1267         count = header_length / s->ctx_data.tx.ctx_header_size;
1268
1269         // Attempt to detect any event in the batch of packets.
1270         events = 0;
1271         ctx_header = header;
1272         for (i = 0; i < count; ++i) {
1273                 unsigned int payload_quads =
1274                         (be32_to_cpu(*ctx_header) >> ISO_DATA_LENGTH_SHIFT) / sizeof(__be32);
1275                 unsigned int data_blocks;
1276
1277                 if (s->flags & CIP_NO_HEADER) {
1278                         data_blocks = payload_quads / s->data_block_quadlets;
1279                 } else {
1280                         __be32 *cip_headers = ctx_header + IR_CTX_HEADER_DEFAULT_QUADLETS;
1281
1282                         if (payload_quads < CIP_HEADER_QUADLETS) {
1283                                 data_blocks = 0;
1284                         } else {
1285                                 payload_quads -= CIP_HEADER_QUADLETS;
1286
1287                                 if (s->flags & CIP_UNAWARE_SYT) {
1288                                         data_blocks = payload_quads / s->data_block_quadlets;
1289                                 } else {
1290                                         u32 cip1 = be32_to_cpu(cip_headers[1]);
1291
1292                                         // NODATA packet can includes any data blocks but they are
1293                                         // not available as event.
1294                                         if ((cip1 & CIP_NO_DATA) == CIP_NO_DATA)
1295                                                 data_blocks = 0;
1296                                         else
1297                                                 data_blocks = payload_quads / s->data_block_quadlets;
1298                                 }
1299                         }
1300                 }
1301
1302                 events += data_blocks;
1303
1304                 ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(__be32);
1305         }
1306
1307         drop_tx_packets(context, tstamp, header_length, header, s);
1308
1309         if (events > 0)
1310                 s->ctx_data.tx.event_starts = true;
1311
1312         // Decide the cycle count to begin processing content of packet in IR contexts.
1313         {
1314                 unsigned int stream_count = 0;
1315                 unsigned int event_starts_count = 0;
1316                 unsigned int cycle = UINT_MAX;
1317
1318                 list_for_each_entry(s, &d->streams, list) {
1319                         if (s->direction == AMDTP_IN_STREAM) {
1320                                 ++stream_count;
1321                                 if (s->ctx_data.tx.event_starts)
1322                                         ++event_starts_count;
1323                         }
1324                 }
1325
1326                 if (stream_count == event_starts_count) {
1327                         unsigned int next_cycle;
1328
1329                         list_for_each_entry(s, &d->streams, list) {
1330                                 if (s->direction != AMDTP_IN_STREAM)
1331                                         continue;
1332
1333                                 next_cycle = increment_ohci_cycle_count(s->next_cycle,
1334                                                                 d->processing_cycle.tx_init_skip);
1335                                 if (cycle == UINT_MAX ||
1336                                     compare_ohci_cycle_count(next_cycle, cycle) > 0)
1337                                         cycle = next_cycle;
1338
1339                                 s->context->callback.sc = process_tx_packets_intermediately;
1340                         }
1341
1342                         d->processing_cycle.tx_start = cycle;
1343                 }
1344         }
1345 }
1346
1347 static void process_ctxs_in_domain(struct amdtp_domain *d)
1348 {
1349         struct amdtp_stream *s;
1350
1351         list_for_each_entry(s, &d->streams, list) {
1352                 if (s != d->irq_target && amdtp_stream_running(s))
1353                         fw_iso_context_flush_completions(s->context);
1354
1355                 if (amdtp_streaming_error(s))
1356                         goto error;
1357         }
1358
1359         return;
1360 error:
1361         if (amdtp_stream_running(d->irq_target))
1362                 cancel_stream(d->irq_target);
1363
1364         list_for_each_entry(s, &d->streams, list) {
1365                 if (amdtp_stream_running(s))
1366                         cancel_stream(s);
1367         }
1368 }
1369
1370 static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1371                                 void *header, void *private_data)
1372 {
1373         struct amdtp_stream *s = private_data;
1374         struct amdtp_domain *d = s->domain;
1375
1376         process_rx_packets(context, tstamp, header_length, header, private_data);
1377         process_ctxs_in_domain(d);
1378 }
1379
1380 static void irq_target_callback_intermediately(struct fw_iso_context *context, u32 tstamp,
1381                                         size_t header_length, void *header, void *private_data)
1382 {
1383         struct amdtp_stream *s = private_data;
1384         struct amdtp_domain *d = s->domain;
1385
1386         process_rx_packets_intermediately(context, tstamp, header_length, header, private_data);
1387         process_ctxs_in_domain(d);
1388 }
1389
1390 static void irq_target_callback_skip(struct fw_iso_context *context, u32 tstamp,
1391                                      size_t header_length, void *header, void *private_data)
1392 {
1393         struct amdtp_stream *s = private_data;
1394         struct amdtp_domain *d = s->domain;
1395         unsigned int cycle;
1396
1397         skip_rx_packets(context, tstamp, header_length, header, private_data);
1398         process_ctxs_in_domain(d);
1399
1400         // Decide the cycle count to begin processing content of packet in IT contexts. All of IT
1401         // contexts are expected to start and get callback when reaching here.
1402         cycle = s->next_cycle;
1403         list_for_each_entry(s, &d->streams, list) {
1404                 if (s->direction != AMDTP_OUT_STREAM)
1405                         continue;
1406
1407                 if (compare_ohci_cycle_count(s->next_cycle, cycle) > 0)
1408                         cycle = s->next_cycle;
1409
1410                 if (s == d->irq_target)
1411                         s->context->callback.sc = irq_target_callback_intermediately;
1412                 else
1413                         s->context->callback.sc = process_rx_packets_intermediately;
1414         }
1415
1416         d->processing_cycle.rx_start = cycle;
1417 }
1418
1419 // This is executed one time. For in-stream, first packet has come. For out-stream, prepared to
1420 // transmit first packet.
1421 static void amdtp_stream_first_callback(struct fw_iso_context *context,
1422                                         u32 tstamp, size_t header_length,
1423                                         void *header, void *private_data)
1424 {
1425         struct amdtp_stream *s = private_data;
1426         struct amdtp_domain *d = s->domain;
1427
1428         if (s->direction == AMDTP_IN_STREAM) {
1429                 context->callback.sc = drop_tx_packets_initially;
1430         } else {
1431                 if (s == d->irq_target)
1432                         context->callback.sc = irq_target_callback_skip;
1433                 else
1434                         context->callback.sc = skip_rx_packets;
1435         }
1436
1437         context->callback.sc(context, tstamp, header_length, header, s);
1438 }
1439
1440 /**
1441  * amdtp_stream_start - start transferring packets
1442  * @s: the AMDTP stream to start
1443  * @channel: the isochronous channel on the bus
1444  * @speed: firewire speed code
1445  * @queue_size: The number of packets in the queue.
1446  * @idle_irq_interval: the interval to queue packet during initial state.
1447  *
1448  * The stream cannot be started until it has been configured with
1449  * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI
1450  * device can be started.
1451  */
1452 static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed,
1453                               unsigned int queue_size, unsigned int idle_irq_interval)
1454 {
1455         bool is_irq_target = (s == s->domain->irq_target);
1456         unsigned int ctx_header_size;
1457         unsigned int max_ctx_payload_size;
1458         enum dma_data_direction dir;
1459         int type, tag, err;
1460
1461         mutex_lock(&s->mutex);
1462
1463         if (WARN_ON(amdtp_stream_running(s) ||
1464                     (s->data_block_quadlets < 1))) {
1465                 err = -EBADFD;
1466                 goto err_unlock;
1467         }
1468
1469         if (s->direction == AMDTP_IN_STREAM) {
1470                 // NOTE: IT context should be used for constant IRQ.
1471                 if (is_irq_target) {
1472                         err = -EINVAL;
1473                         goto err_unlock;
1474                 }
1475
1476                 s->data_block_counter = UINT_MAX;
1477         } else {
1478                 s->data_block_counter = 0;
1479         }
1480
1481         // initialize packet buffer.
1482         if (s->direction == AMDTP_IN_STREAM) {
1483                 dir = DMA_FROM_DEVICE;
1484                 type = FW_ISO_CONTEXT_RECEIVE;
1485                 if (!(s->flags & CIP_NO_HEADER))
1486                         ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
1487                 else
1488                         ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
1489         } else {
1490                 dir = DMA_TO_DEVICE;
1491                 type = FW_ISO_CONTEXT_TRANSMIT;
1492                 ctx_header_size = 0;    // No effect for IT context.
1493         }
1494         max_ctx_payload_size = amdtp_stream_get_max_ctx_payload_size(s);
1495
1496         err = iso_packets_buffer_init(&s->buffer, s->unit, queue_size, max_ctx_payload_size, dir);
1497         if (err < 0)
1498                 goto err_unlock;
1499         s->queue_size = queue_size;
1500
1501         s->context = fw_iso_context_create(fw_parent_device(s->unit)->card,
1502                                           type, channel, speed, ctx_header_size,
1503                                           amdtp_stream_first_callback, s);
1504         if (IS_ERR(s->context)) {
1505                 err = PTR_ERR(s->context);
1506                 if (err == -EBUSY)
1507                         dev_err(&s->unit->device,
1508                                 "no free stream on this controller\n");
1509                 goto err_buffer;
1510         }
1511
1512         amdtp_stream_update(s);
1513
1514         if (s->direction == AMDTP_IN_STREAM) {
1515                 s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size;
1516                 s->ctx_data.tx.ctx_header_size = ctx_header_size;
1517                 s->ctx_data.tx.event_starts = false;
1518
1519                 if (s->domain->replay.enable) {
1520                         // struct fw_iso_context.drop_overflow_headers is false therefore it's
1521                         // possible to cache much unexpectedly.
1522                         s->ctx_data.tx.cache.size = max_t(unsigned int, s->syt_interval * 2,
1523                                                           queue_size * 3 / 2);
1524                         s->ctx_data.tx.cache.tail = 0;
1525                         s->ctx_data.tx.cache.descs = kcalloc(s->ctx_data.tx.cache.size,
1526                                                 sizeof(*s->ctx_data.tx.cache.descs), GFP_KERNEL);
1527                         if (!s->ctx_data.tx.cache.descs)
1528                                 goto err_context;
1529                 }
1530         } else {
1531                 static const struct {
1532                         unsigned int data_block;
1533                         unsigned int syt_offset;
1534                 } *entry, initial_state[] = {
1535                         [CIP_SFC_32000]  = {  4, 3072 },
1536                         [CIP_SFC_48000]  = {  6, 1024 },
1537                         [CIP_SFC_96000]  = { 12, 1024 },
1538                         [CIP_SFC_192000] = { 24, 1024 },
1539                         [CIP_SFC_44100]  = {  0,   67 },
1540                         [CIP_SFC_88200]  = {  0,   67 },
1541                         [CIP_SFC_176400] = {  0,   67 },
1542                 };
1543
1544                 s->ctx_data.rx.seq.descs = kcalloc(queue_size, sizeof(*s->ctx_data.rx.seq.descs), GFP_KERNEL);
1545                 if (!s->ctx_data.rx.seq.descs)
1546                         goto err_context;
1547                 s->ctx_data.rx.seq.size = queue_size;
1548                 s->ctx_data.rx.seq.tail = 0;
1549                 s->ctx_data.rx.seq.head = 0;
1550
1551                 entry = &initial_state[s->sfc];
1552                 s->ctx_data.rx.data_block_state = entry->data_block;
1553                 s->ctx_data.rx.syt_offset_state = entry->syt_offset;
1554                 s->ctx_data.rx.last_syt_offset = TICKS_PER_CYCLE;
1555
1556                 s->ctx_data.rx.event_count = 0;
1557         }
1558
1559         if (s->flags & CIP_NO_HEADER)
1560                 s->tag = TAG_NO_CIP_HEADER;
1561         else
1562                 s->tag = TAG_CIP;
1563
1564         s->pkt_descs = kcalloc(s->queue_size, sizeof(*s->pkt_descs),
1565                                GFP_KERNEL);
1566         if (!s->pkt_descs) {
1567                 err = -ENOMEM;
1568                 goto err_context;
1569         }
1570
1571         s->packet_index = 0;
1572         do {
1573                 struct fw_iso_packet params;
1574
1575                 if (s->direction == AMDTP_IN_STREAM) {
1576                         err = queue_in_packet(s, &params);
1577                 } else {
1578                         bool sched_irq = false;
1579
1580                         params.header_length = 0;
1581                         params.payload_length = 0;
1582
1583                         if (is_irq_target) {
1584                                 sched_irq = !((s->packet_index + 1) %
1585                                               idle_irq_interval);
1586                         }
1587
1588                         err = queue_out_packet(s, &params, sched_irq);
1589                 }
1590                 if (err < 0)
1591                         goto err_pkt_descs;
1592         } while (s->packet_index > 0);
1593
1594         /* NOTE: TAG1 matches CIP. This just affects in stream. */
1595         tag = FW_ISO_CONTEXT_MATCH_TAG1;
1596         if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER))
1597                 tag |= FW_ISO_CONTEXT_MATCH_TAG0;
1598
1599         s->ready_processing = false;
1600         err = fw_iso_context_start(s->context, -1, 0, tag);
1601         if (err < 0)
1602                 goto err_pkt_descs;
1603
1604         mutex_unlock(&s->mutex);
1605
1606         return 0;
1607 err_pkt_descs:
1608         kfree(s->pkt_descs);
1609 err_context:
1610         if (s->direction == AMDTP_OUT_STREAM) {
1611                 kfree(s->ctx_data.rx.seq.descs);
1612         } else {
1613                 if (s->domain->replay.enable)
1614                         kfree(s->ctx_data.tx.cache.descs);
1615         }
1616         fw_iso_context_destroy(s->context);
1617         s->context = ERR_PTR(-1);
1618 err_buffer:
1619         iso_packets_buffer_destroy(&s->buffer, s->unit);
1620 err_unlock:
1621         mutex_unlock(&s->mutex);
1622
1623         return err;
1624 }
1625
1626 /**
1627  * amdtp_domain_stream_pcm_pointer - get the PCM buffer position
1628  * @d: the AMDTP domain.
1629  * @s: the AMDTP stream that transports the PCM data
1630  *
1631  * Returns the current buffer position, in frames.
1632  */
1633 unsigned long amdtp_domain_stream_pcm_pointer(struct amdtp_domain *d,
1634                                               struct amdtp_stream *s)
1635 {
1636         struct amdtp_stream *irq_target = d->irq_target;
1637
1638         if (irq_target && amdtp_stream_running(irq_target)) {
1639                 // This function is called in software IRQ context of
1640                 // period_work or process context.
1641                 //
1642                 // When the software IRQ context was scheduled by software IRQ
1643                 // context of IT contexts, queued packets were already handled.
1644                 // Therefore, no need to flush the queue in buffer furthermore.
1645                 //
1646                 // When the process context reach here, some packets will be
1647                 // already queued in the buffer. These packets should be handled
1648                 // immediately to keep better granularity of PCM pointer.
1649                 //
1650                 // Later, the process context will sometimes schedules software
1651                 // IRQ context of the period_work. Then, no need to flush the
1652                 // queue by the same reason as described in the above
1653                 if (current_work() != &s->period_work) {
1654                         // Queued packet should be processed without any kernel
1655                         // preemption to keep latency against bus cycle.
1656                         preempt_disable();
1657                         fw_iso_context_flush_completions(irq_target->context);
1658                         preempt_enable();
1659                 }
1660         }
1661
1662         return READ_ONCE(s->pcm_buffer_pointer);
1663 }
1664 EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_pointer);
1665
1666 /**
1667  * amdtp_domain_stream_pcm_ack - acknowledge queued PCM frames
1668  * @d: the AMDTP domain.
1669  * @s: the AMDTP stream that transfers the PCM frames
1670  *
1671  * Returns zero always.
1672  */
1673 int amdtp_domain_stream_pcm_ack(struct amdtp_domain *d, struct amdtp_stream *s)
1674 {
1675         struct amdtp_stream *irq_target = d->irq_target;
1676
1677         // Process isochronous packets for recent isochronous cycle to handle
1678         // queued PCM frames.
1679         if (irq_target && amdtp_stream_running(irq_target)) {
1680                 // Queued packet should be processed without any kernel
1681                 // preemption to keep latency against bus cycle.
1682                 preempt_disable();
1683                 fw_iso_context_flush_completions(irq_target->context);
1684                 preempt_enable();
1685         }
1686
1687         return 0;
1688 }
1689 EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_ack);
1690
1691 /**
1692  * amdtp_stream_update - update the stream after a bus reset
1693  * @s: the AMDTP stream
1694  */
1695 void amdtp_stream_update(struct amdtp_stream *s)
1696 {
1697         /* Precomputing. */
1698         WRITE_ONCE(s->source_node_id_field,
1699                    (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK);
1700 }
1701 EXPORT_SYMBOL(amdtp_stream_update);
1702
1703 /**
1704  * amdtp_stream_stop - stop sending packets
1705  * @s: the AMDTP stream to stop
1706  *
1707  * All PCM and MIDI devices of the stream must be stopped before the stream
1708  * itself can be stopped.
1709  */
1710 static void amdtp_stream_stop(struct amdtp_stream *s)
1711 {
1712         mutex_lock(&s->mutex);
1713
1714         if (!amdtp_stream_running(s)) {
1715                 mutex_unlock(&s->mutex);
1716                 return;
1717         }
1718
1719         cancel_work_sync(&s->period_work);
1720         fw_iso_context_stop(s->context);
1721         fw_iso_context_destroy(s->context);
1722         s->context = ERR_PTR(-1);
1723         iso_packets_buffer_destroy(&s->buffer, s->unit);
1724         kfree(s->pkt_descs);
1725
1726         if (s->direction == AMDTP_OUT_STREAM) {
1727                 kfree(s->ctx_data.rx.seq.descs);
1728         } else {
1729                 if (s->domain->replay.enable)
1730                         kfree(s->ctx_data.tx.cache.descs);
1731         }
1732
1733         mutex_unlock(&s->mutex);
1734 }
1735
1736 /**
1737  * amdtp_stream_pcm_abort - abort the running PCM device
1738  * @s: the AMDTP stream about to be stopped
1739  *
1740  * If the isochronous stream needs to be stopped asynchronously, call this
1741  * function first to stop the PCM device.
1742  */
1743 void amdtp_stream_pcm_abort(struct amdtp_stream *s)
1744 {
1745         struct snd_pcm_substream *pcm;
1746
1747         pcm = READ_ONCE(s->pcm);
1748         if (pcm)
1749                 snd_pcm_stop_xrun(pcm);
1750 }
1751 EXPORT_SYMBOL(amdtp_stream_pcm_abort);
1752
1753 /**
1754  * amdtp_domain_init - initialize an AMDTP domain structure
1755  * @d: the AMDTP domain to initialize.
1756  */
1757 int amdtp_domain_init(struct amdtp_domain *d)
1758 {
1759         INIT_LIST_HEAD(&d->streams);
1760
1761         d->events_per_period = 0;
1762
1763         return 0;
1764 }
1765 EXPORT_SYMBOL_GPL(amdtp_domain_init);
1766
1767 /**
1768  * amdtp_domain_destroy - destroy an AMDTP domain structure
1769  * @d: the AMDTP domain to destroy.
1770  */
1771 void amdtp_domain_destroy(struct amdtp_domain *d)
1772 {
1773         // At present nothing to do.
1774         return;
1775 }
1776 EXPORT_SYMBOL_GPL(amdtp_domain_destroy);
1777
1778 /**
1779  * amdtp_domain_add_stream - register isoc context into the domain.
1780  * @d: the AMDTP domain.
1781  * @s: the AMDTP stream.
1782  * @channel: the isochronous channel on the bus.
1783  * @speed: firewire speed code.
1784  */
1785 int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s,
1786                             int channel, int speed)
1787 {
1788         struct amdtp_stream *tmp;
1789
1790         list_for_each_entry(tmp, &d->streams, list) {
1791                 if (s == tmp)
1792                         return -EBUSY;
1793         }
1794
1795         list_add(&s->list, &d->streams);
1796
1797         s->channel = channel;
1798         s->speed = speed;
1799         s->domain = d;
1800
1801         return 0;
1802 }
1803 EXPORT_SYMBOL_GPL(amdtp_domain_add_stream);
1804
1805 /**
1806  * amdtp_domain_start - start sending packets for isoc context in the domain.
1807  * @d: the AMDTP domain.
1808  * @tx_init_skip_cycles: the number of cycles to skip processing packets at initial stage of IR
1809  *                       contexts.
1810  * @replay_seq: whether to replay the sequence of packet in IR context for the sequence of packet in
1811  *              IT context.
1812  */
1813 int amdtp_domain_start(struct amdtp_domain *d, unsigned int tx_init_skip_cycles, bool replay_seq)
1814 {
1815         unsigned int events_per_buffer = d->events_per_buffer;
1816         unsigned int events_per_period = d->events_per_period;
1817         unsigned int queue_size;
1818         struct amdtp_stream *s;
1819         int err;
1820
1821         d->replay.enable = replay_seq;
1822
1823         // Select an IT context as IRQ target.
1824         list_for_each_entry(s, &d->streams, list) {
1825                 if (s->direction == AMDTP_OUT_STREAM)
1826                         break;
1827         }
1828         if (!s)
1829                 return -ENXIO;
1830         d->irq_target = s;
1831
1832         d->processing_cycle.tx_init_skip = tx_init_skip_cycles;
1833
1834         // This is a case that AMDTP streams in domain run just for MIDI
1835         // substream. Use the number of events equivalent to 10 msec as
1836         // interval of hardware IRQ.
1837         if (events_per_period == 0)
1838                 events_per_period = amdtp_rate_table[d->irq_target->sfc] / 100;
1839         if (events_per_buffer == 0)
1840                 events_per_buffer = events_per_period * 3;
1841
1842         queue_size = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_buffer,
1843                                   amdtp_rate_table[d->irq_target->sfc]);
1844
1845         list_for_each_entry(s, &d->streams, list) {
1846                 unsigned int idle_irq_interval = 0;
1847
1848                 if (s->direction == AMDTP_OUT_STREAM && s == d->irq_target) {
1849                         idle_irq_interval = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period,
1850                                                          amdtp_rate_table[d->irq_target->sfc]);
1851                 }
1852
1853                 // Starts immediately but actually DMA context starts several hundred cycles later.
1854                 err = amdtp_stream_start(s, s->channel, s->speed, queue_size, idle_irq_interval);
1855                 if (err < 0)
1856                         goto error;
1857         }
1858
1859         return 0;
1860 error:
1861         list_for_each_entry(s, &d->streams, list)
1862                 amdtp_stream_stop(s);
1863         return err;
1864 }
1865 EXPORT_SYMBOL_GPL(amdtp_domain_start);
1866
1867 /**
1868  * amdtp_domain_stop - stop sending packets for isoc context in the same domain.
1869  * @d: the AMDTP domain to which the isoc contexts belong.
1870  */
1871 void amdtp_domain_stop(struct amdtp_domain *d)
1872 {
1873         struct amdtp_stream *s, *next;
1874
1875         if (d->irq_target)
1876                 amdtp_stream_stop(d->irq_target);
1877
1878         list_for_each_entry_safe(s, next, &d->streams, list) {
1879                 list_del(&s->list);
1880
1881                 if (s != d->irq_target)
1882                         amdtp_stream_stop(s);
1883         }
1884
1885         d->events_per_period = 0;
1886         d->irq_target = NULL;
1887 }
1888 EXPORT_SYMBOL_GPL(amdtp_domain_stop);