sound/firewire/amdtp-stream.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
   4  * with Common Isochronous Packet (IEC 61883-1) headers
   5  *
   6  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/err.h>
  11 #include <linux/firewire.h>
  12 #include <linux/firewire-constants.h>
  13 #include <linux/module.h>
  14 #include <linux/slab.h>
  15 #include <sound/pcm.h>
  16 #include <sound/pcm_params.h>
  17 #include "amdtp-stream.h"
  18
  19 #define TICKS_PER_CYCLE         3072
  20 #define CYCLES_PER_SECOND       8000
  21 #define TICKS_PER_SECOND        (TICKS_PER_CYCLE * CYCLES_PER_SECOND)
  22
  23 #define OHCI_SECOND_MODULUS             8
  24
  25 /* Always support Linux tracing subsystem. */
  26 #define CREATE_TRACE_POINTS
  27 #include "amdtp-stream-trace.h"
  28
  29 #define TRANSFER_DELAY_TICKS    0x2e00 /* 479.17 microseconds */
  30
  31 /* isochronous header parameters */
  32 #define ISO_DATA_LENGTH_SHIFT   16
  33 #define TAG_NO_CIP_HEADER       0
  34 #define TAG_CIP                 1
  35
  36 // Common Isochronous Packet (CIP) header parameters. Use two quadlets CIP header when supported.
  37 #define CIP_HEADER_QUADLETS     2
  38 #define CIP_EOH_SHIFT           31
  39 #define CIP_EOH                 (1u << CIP_EOH_SHIFT)
  40 #define CIP_EOH_MASK            0x80000000
  41 #define CIP_SID_SHIFT           24
  42 #define CIP_SID_MASK            0x3f000000
  43 #define CIP_DBS_MASK            0x00ff0000
  44 #define CIP_DBS_SHIFT           16
  45 #define CIP_SPH_MASK            0x00000400
  46 #define CIP_SPH_SHIFT           10
  47 #define CIP_DBC_MASK            0x000000ff
  48 #define CIP_FMT_SHIFT           24
  49 #define CIP_FMT_MASK            0x3f000000
  50 #define CIP_FDF_MASK            0x00ff0000
  51 #define CIP_FDF_SHIFT           16
  52 #define CIP_SYT_MASK            0x0000ffff
  53 #define CIP_SYT_NO_INFO         0xffff
  54
  55 #define CIP_HEADER_SIZE         (sizeof(__be32) * CIP_HEADER_QUADLETS)
  56
  57 /* Audio and Music transfer protocol specific parameters */
  58 #define CIP_FMT_AM              0x10
  59 #define AMDTP_FDF_NO_DATA       0xff
  60
  61 // For iso header and tstamp.
  62 #define IR_CTX_HEADER_DEFAULT_QUADLETS  2
  63 // Add nothing.
  64 #define IR_CTX_HEADER_SIZE_NO_CIP       (sizeof(__be32) * IR_CTX_HEADER_DEFAULT_QUADLETS)
  65 // Add two quadlets CIP header.
  66 #define IR_CTX_HEADER_SIZE_CIP          (IR_CTX_HEADER_SIZE_NO_CIP + CIP_HEADER_SIZE)
  67 #define HEADER_TSTAMP_MASK      0x0000ffff
  68
  69 #define IT_PKT_HEADER_SIZE_CIP          CIP_HEADER_SIZE
  70 #define IT_PKT_HEADER_SIZE_NO_CIP       0 // Nothing.
  71
  72 // The initial firmware of OXFW970 can postpone transmission of packet during finishing
  73 // asynchronous transaction. This module accepts 5 cycles to skip as maximum to avoid buffer
  74 // overrun. Actual device can skip more, then this module stops the packet streaming.
  75 #define IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES        5
  76
  77 static void pcm_period_work(struct work_struct *work);
  78
  79 /**
  80  * amdtp_stream_init - initialize an AMDTP stream structure
  81  * @s: the AMDTP stream to initialize
  82  * @unit: the target of the stream
  83  * @dir: the direction of stream
  84  * @flags: the details of the streaming protocol consist of cip_flags enumeration-constants.
  85  * @fmt: the value of fmt field in CIP header
  86  * @process_ctx_payloads: callback handler to process payloads of isoc context
  87  * @protocol_size: the size to allocate newly for protocol
  88  */
  89 int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit,
  90                       enum amdtp_stream_direction dir, unsigned int flags,
  91                       unsigned int fmt,
  92                       amdtp_stream_process_ctx_payloads_t process_ctx_payloads,
  93                       unsigned int protocol_size)
  94 {
  95         if (process_ctx_payloads == NULL)
  96                 return -EINVAL;
  97
  98         s->protocol = kzalloc(protocol_size, GFP_KERNEL);
  99         if (!s->protocol)
 100                 return -ENOMEM;
 101
 102         s->unit = unit;
 103         s->direction = dir;
 104         s->flags = flags;
 105         s->context = ERR_PTR(-1);
 106         mutex_init(&s->mutex);
 107         INIT_WORK(&s->period_work, pcm_period_work);
 108         s->packet_index = 0;
 109
 110         init_waitqueue_head(&s->ready_wait);
 111         s->callbacked = false;
 112
 113         s->fmt = fmt;
 114         s->process_ctx_payloads = process_ctx_payloads;
 115
 116         return 0;
 117 }
 118 EXPORT_SYMBOL(amdtp_stream_init);
 119
 120 /**
 121  * amdtp_stream_destroy - free stream resources
 122  * @s: the AMDTP stream to destroy
 123  */
 124 void amdtp_stream_destroy(struct amdtp_stream *s)
 125 {
 126         /* Not initialized. */
 127         if (s->protocol == NULL)
 128                 return;
 129
 130         WARN_ON(amdtp_stream_running(s));
 131         kfree(s->protocol);
 132         mutex_destroy(&s->mutex);
 133 }
 134 EXPORT_SYMBOL(amdtp_stream_destroy);
 135
 136 const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = {
 137         [CIP_SFC_32000]  =  8,
 138         [CIP_SFC_44100]  =  8,
 139         [CIP_SFC_48000]  =  8,
 140         [CIP_SFC_88200]  = 16,
 141         [CIP_SFC_96000]  = 16,
 142         [CIP_SFC_176400] = 32,
 143         [CIP_SFC_192000] = 32,
 144 };
 145 EXPORT_SYMBOL(amdtp_syt_intervals);
 146
 147 const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = {
 148         [CIP_SFC_32000]  =  32000,
 149         [CIP_SFC_44100]  =  44100,
 150         [CIP_SFC_48000]  =  48000,
 151         [CIP_SFC_88200]  =  88200,
 152         [CIP_SFC_96000]  =  96000,
 153         [CIP_SFC_176400] = 176400,
 154         [CIP_SFC_192000] = 192000,
 155 };
 156 EXPORT_SYMBOL(amdtp_rate_table);
 157
 158 static int apply_constraint_to_size(struct snd_pcm_hw_params *params,
 159                                     struct snd_pcm_hw_rule *rule)
 160 {
 161         struct snd_interval *s = hw_param_interval(params, rule->var);
 162         const struct snd_interval *r =
 163                 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
 164         struct snd_interval t = {0};
 165         unsigned int step = 0;
 166         int i;
 167
 168         for (i = 0; i < CIP_SFC_COUNT; ++i) {
 169                 if (snd_interval_test(r, amdtp_rate_table[i]))
 170                         step = max(step, amdtp_syt_intervals[i]);
 171         }
 172
 173         t.min = roundup(s->min, step);
 174         t.max = rounddown(s->max, step);
 175         t.integer = 1;
 176
 177         return snd_interval_refine(s, &t);
 178 }
 179
 180 /**
 181  * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream
 182  * @s:          the AMDTP stream, which must be initialized.
 183  * @runtime:    the PCM substream runtime
 184  */
 185 int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s,
 186                                         struct snd_pcm_runtime *runtime)
 187 {
 188         struct snd_pcm_hardware *hw = &runtime->hw;
 189         unsigned int ctx_header_size;
 190         unsigned int maximum_usec_per_period;
 191         int err;
 192
 193         hw->info = SNDRV_PCM_INFO_BATCH |
 194                    SNDRV_PCM_INFO_BLOCK_TRANSFER |
 195                    SNDRV_PCM_INFO_INTERLEAVED |
 196                    SNDRV_PCM_INFO_JOINT_DUPLEX |
 197                    SNDRV_PCM_INFO_MMAP |
 198                    SNDRV_PCM_INFO_MMAP_VALID;
 199
 200         /* SNDRV_PCM_INFO_BATCH */
 201         hw->periods_min = 2;
 202         hw->periods_max = UINT_MAX;
 203
 204         /* bytes for a frame */
 205         hw->period_bytes_min = 4 * hw->channels_max;
 206
 207         /* Just to prevent from allocating much pages. */
 208         hw->period_bytes_max = hw->period_bytes_min * 2048;
 209         hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min;
 210
 211         // Linux driver for 1394 OHCI controller voluntarily flushes isoc
 212         // context when total size of accumulated context header reaches
 213         // PAGE_SIZE. This kicks work for the isoc context and brings
 214         // callback in the middle of scheduled interrupts.
 215         // Although AMDTP streams in the same domain use the same events per
 216         // IRQ, use the largest size of context header between IT/IR contexts.
 217         // Here, use the value of context header in IR context is for both
 218         // contexts.
 219         if (!(s->flags & CIP_NO_HEADER))
 220                 ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
 221         else
 222                 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
 223         maximum_usec_per_period = USEC_PER_SEC * PAGE_SIZE /
 224                                   CYCLES_PER_SECOND / ctx_header_size;
 225
 226         // In IEC 61883-6, one isoc packet can transfer events up to the value
 227         // of syt interval. This comes from the interval of isoc cycle. As 1394
 228         // OHCI controller can generate hardware IRQ per isoc packet, the
 229         // interval is 125 usec.
 230         // However, there are two ways of transmission in IEC 61883-6; blocking
 231         // and non-blocking modes. In blocking mode, the sequence of isoc packet
 232         // includes 'empty' or 'NODATA' packets which include no event. In
 233         // non-blocking mode, the number of events per packet is variable up to
 234         // the syt interval.
 235         // Due to the above protocol design, the minimum PCM frames per
 236         // interrupt should be double of the value of syt interval, thus it is
 237         // 250 usec.
 238         err = snd_pcm_hw_constraint_minmax(runtime,
 239                                            SNDRV_PCM_HW_PARAM_PERIOD_TIME,
 240                                            250, maximum_usec_per_period);
 241         if (err < 0)
 242                 goto end;
 243
 244         /* Non-Blocking stream has no more constraints */
 245         if (!(s->flags & CIP_BLOCKING))
 246                 goto end;
 247
 248         /*
 249          * One AMDTP packet can include some frames. In blocking mode, the
 250          * number equals to SYT_INTERVAL. So the number is 8, 16 or 32,
 251          * depending on its sampling rate. For accurate period interrupt, it's
 252          * preferrable to align period/buffer sizes to current SYT_INTERVAL.
 253          */
 254         err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 255                                   apply_constraint_to_size, NULL,
 256                                   SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
 257                                   SNDRV_PCM_HW_PARAM_RATE, -1);
 258         if (err < 0)
 259                 goto end;
 260         err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 261                                   apply_constraint_to_size, NULL,
 262                                   SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 263                                   SNDRV_PCM_HW_PARAM_RATE, -1);
 264         if (err < 0)
 265                 goto end;
 266 end:
 267         return err;
 268 }
 269 EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints);
 270
 271 /**
 272  * amdtp_stream_set_parameters - set stream parameters
 273  * @s: the AMDTP stream to configure
 274  * @rate: the sample rate
 275  * @data_block_quadlets: the size of a data block in quadlet unit
 276  *
 277  * The parameters must be set before the stream is started, and must not be
 278  * changed while the stream is running.
 279  */
 280 int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate,
 281                                 unsigned int data_block_quadlets)
 282 {
 283         unsigned int sfc;
 284
 285         for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) {
 286                 if (amdtp_rate_table[sfc] == rate)
 287                         break;
 288         }
 289         if (sfc == ARRAY_SIZE(amdtp_rate_table))
 290                 return -EINVAL;
 291
 292         s->sfc = sfc;
 293         s->data_block_quadlets = data_block_quadlets;
 294         s->syt_interval = amdtp_syt_intervals[sfc];
 295
 296         // default buffering in the device.
 297         if (s->direction == AMDTP_OUT_STREAM) {
 298                 s->ctx_data.rx.transfer_delay =
 299                                         TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
 300
 301                 if (s->flags & CIP_BLOCKING) {
 302                         // additional buffering needed to adjust for no-data
 303                         // packets.
 304                         s->ctx_data.rx.transfer_delay +=
 305                                 TICKS_PER_SECOND * s->syt_interval / rate;
 306                 }
 307         }
 308
 309         return 0;
 310 }
 311 EXPORT_SYMBOL(amdtp_stream_set_parameters);
 312
 313 // The CIP header is processed in context header apart from context payload.
 314 static int amdtp_stream_get_max_ctx_payload_size(struct amdtp_stream *s)
 315 {
 316         unsigned int multiplier;
 317
 318         if (s->flags & CIP_JUMBO_PAYLOAD)
 319                 multiplier = IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES;
 320         else
 321                 multiplier = 1;
 322
 323         return s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier;
 324 }
 325
 326 /**
 327  * amdtp_stream_get_max_payload - get the stream's packet size
 328  * @s: the AMDTP stream
 329  *
 330  * This function must not be called before the stream has been configured
 331  * with amdtp_stream_set_parameters().
 332  */
 333 unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s)
 334 {
 335         unsigned int cip_header_size;
 336
 337         if (!(s->flags & CIP_NO_HEADER))
 338                 cip_header_size = CIP_HEADER_SIZE;
 339         else
 340                 cip_header_size = 0;
 341
 342         return cip_header_size + amdtp_stream_get_max_ctx_payload_size(s);
 343 }
 344 EXPORT_SYMBOL(amdtp_stream_get_max_payload);
 345
 346 /**
 347  * amdtp_stream_pcm_prepare - prepare PCM device for running
 348  * @s: the AMDTP stream
 349  *
 350  * This function should be called from the PCM device's .prepare callback.
 351  */
 352 void amdtp_stream_pcm_prepare(struct amdtp_stream *s)
 353 {
 354         cancel_work_sync(&s->period_work);
 355         s->pcm_buffer_pointer = 0;
 356         s->pcm_period_pointer = 0;
 357 }
 358 EXPORT_SYMBOL(amdtp_stream_pcm_prepare);
 359
 360 static unsigned int calculate_data_blocks(unsigned int *data_block_state,
 361                                 bool is_blocking, bool is_no_info,
 362                                 unsigned int syt_interval, enum cip_sfc sfc)
 363 {
 364         unsigned int data_blocks;
 365
 366         /* Blocking mode. */
 367         if (is_blocking) {
 368                 /* This module generate empty packet for 'no data'. */
 369                 if (is_no_info)
 370                         data_blocks = 0;
 371                 else
 372                         data_blocks = syt_interval;
 373         /* Non-blocking mode. */
 374         } else {
 375                 if (!cip_sfc_is_base_44100(sfc)) {
 376                         // Sample_rate / 8000 is an integer, and precomputed.
 377                         data_blocks = *data_block_state;
 378                 } else {
 379                         unsigned int phase = *data_block_state;
 380
 381                 /*
 382                  * This calculates the number of data blocks per packet so that
 383                  * 1) the overall rate is correct and exactly synchronized to
 384                  *    the bus clock, and
 385                  * 2) packets with a rounded-up number of blocks occur as early
 386                  *    as possible in the sequence (to prevent underruns of the
 387                  *    device's buffer).
 388                  */
 389                         if (sfc == CIP_SFC_44100)
 390                                 /* 6 6 5 6 5 6 5 ... */
 391                                 data_blocks = 5 + ((phase & 1) ^
 392                                                    (phase == 0 || phase >= 40));
 393                         else
 394                                 /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */
 395                                 data_blocks = 11 * (sfc >> 1) + (phase == 0);
 396                         if (++phase >= (80 >> (sfc >> 1)))
 397                                 phase = 0;
 398                         *data_block_state = phase;
 399                 }
 400         }
 401
 402         return data_blocks;
 403 }
 404
 405 static unsigned int calculate_syt_offset(unsigned int *last_syt_offset,
 406                         unsigned int *syt_offset_state, enum cip_sfc sfc)
 407 {
 408         unsigned int syt_offset;
 409
 410         if (*last_syt_offset < TICKS_PER_CYCLE) {
 411                 if (!cip_sfc_is_base_44100(sfc))
 412                         syt_offset = *last_syt_offset + *syt_offset_state;
 413                 else {
 414                 /*
 415                  * The time, in ticks, of the n'th SYT_INTERVAL sample is:
 416                  *   n * SYT_INTERVAL * 24576000 / sample_rate
 417                  * Modulo TICKS_PER_CYCLE, the difference between successive
 418                  * elements is about 1386.23.  Rounding the results of this
 419                  * formula to the SYT precision results in a sequence of
 420                  * differences that begins with:
 421                  *   1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ...
 422                  * This code generates _exactly_ the same sequence.
 423                  */
 424                         unsigned int phase = *syt_offset_state;
 425                         unsigned int index = phase % 13;
 426
 427                         syt_offset = *last_syt_offset;
 428                         syt_offset += 1386 + ((index && !(index & 3)) ||
 429                                               phase == 146);
 430                         if (++phase >= 147)
 431                                 phase = 0;
 432                         *syt_offset_state = phase;
 433                 }
 434         } else
 435                 syt_offset = *last_syt_offset - TICKS_PER_CYCLE;
 436         *last_syt_offset = syt_offset;
 437
 438         if (syt_offset >= TICKS_PER_CYCLE)
 439                 syt_offset = CIP_SYT_NO_INFO;
 440
 441         return syt_offset;
 442 }
 443
 444 static void update_pcm_pointers(struct amdtp_stream *s,
 445                                 struct snd_pcm_substream *pcm,
 446                                 unsigned int frames)
 447 {
 448         unsigned int ptr;
 449
 450         ptr = s->pcm_buffer_pointer + frames;
 451         if (ptr >= pcm->runtime->buffer_size)
 452                 ptr -= pcm->runtime->buffer_size;
 453         WRITE_ONCE(s->pcm_buffer_pointer, ptr);
 454
 455         s->pcm_period_pointer += frames;
 456         if (s->pcm_period_pointer >= pcm->runtime->period_size) {
 457                 s->pcm_period_pointer -= pcm->runtime->period_size;
 458                 queue_work(system_highpri_wq, &s->period_work);
 459         }
 460 }
 461
 462 static void pcm_period_work(struct work_struct *work)
 463 {
 464         struct amdtp_stream *s = container_of(work, struct amdtp_stream,
 465                                               period_work);
 466         struct snd_pcm_substream *pcm = READ_ONCE(s->pcm);
 467
 468         if (pcm)
 469                 snd_pcm_period_elapsed(pcm);
 470 }
 471
 472 static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params,
 473                         bool sched_irq)
 474 {
 475         int err;
 476
 477         params->interrupt = sched_irq;
 478         params->tag = s->tag;
 479         params->sy = 0;
 480
 481         err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer,
 482                                    s->buffer.packets[s->packet_index].offset);
 483         if (err < 0) {
 484                 dev_err(&s->unit->device, "queueing error: %d\n", err);
 485                 goto end;
 486         }
 487
 488         if (++s->packet_index >= s->queue_size)
 489                 s->packet_index = 0;
 490 end:
 491         return err;
 492 }
 493
 494 static inline int queue_out_packet(struct amdtp_stream *s,
 495                                    struct fw_iso_packet *params, bool sched_irq)
 496 {
 497         params->skip =
 498                 !!(params->header_length == 0 && params->payload_length == 0);
 499         return queue_packet(s, params, sched_irq);
 500 }
 501
 502 static inline int queue_in_packet(struct amdtp_stream *s,
 503                                   struct fw_iso_packet *params)
 504 {
 505         // Queue one packet for IR context.
 506         params->header_length = s->ctx_data.tx.ctx_header_size;
 507         params->payload_length = s->ctx_data.tx.max_ctx_payload_length;
 508         params->skip = false;
 509         return queue_packet(s, params, false);
 510 }
 511
 512 static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2],
 513                         unsigned int data_block_counter, unsigned int syt)
 514 {
 515         cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) |
 516                                 (s->data_block_quadlets << CIP_DBS_SHIFT) |
 517                                 ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) |
 518                                 data_block_counter);
 519         cip_header[1] = cpu_to_be32(CIP_EOH |
 520                         ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) |
 521                         ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) |
 522                         (syt & CIP_SYT_MASK));
 523 }
 524
 525 static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle,
 526                                 struct fw_iso_packet *params, unsigned int header_length,
 527                                 unsigned int data_blocks,
 528                                 unsigned int data_block_counter,
 529                                 unsigned int syt, unsigned int index)
 530 {
 531         unsigned int payload_length;
 532         __be32 *cip_header;
 533
 534         payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets;
 535         params->payload_length = payload_length;
 536
 537         if (header_length > 0) {
 538                 cip_header = (__be32 *)params->header;
 539                 generate_cip_header(s, cip_header, data_block_counter, syt);
 540                 params->header_length = header_length;
 541         } else {
 542                 cip_header = NULL;
 543         }
 544
 545         trace_amdtp_packet(s, cycle, cip_header, payload_length + header_length, data_blocks,
 546                            data_block_counter, s->packet_index, index);
 547 }
 548
 549 static int check_cip_header(struct amdtp_stream *s, const __be32 *buf,
 550                             unsigned int payload_length,
 551                             unsigned int *data_blocks,
 552                             unsigned int *data_block_counter, unsigned int *syt)
 553 {
 554         u32 cip_header[2];
 555         unsigned int sph;
 556         unsigned int fmt;
 557         unsigned int fdf;
 558         unsigned int dbc;
 559         bool lost;
 560
 561         cip_header[0] = be32_to_cpu(buf[0]);
 562         cip_header[1] = be32_to_cpu(buf[1]);
 563
 564         /*
 565          * This module supports 'Two-quadlet CIP header with SYT field'.
 566          * For convenience, also check FMT field is AM824 or not.
 567          */
 568         if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) ||
 569              ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) &&
 570             (!(s->flags & CIP_HEADER_WITHOUT_EOH))) {
 571                 dev_info_ratelimited(&s->unit->device,
 572                                 "Invalid CIP header for AMDTP: %08X:%08X\n",
 573                                 cip_header[0], cip_header[1]);
 574                 return -EAGAIN;
 575         }
 576
 577         /* Check valid protocol or not. */
 578         sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT;
 579         fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT;
 580         if (sph != s->sph || fmt != s->fmt) {
 581                 dev_info_ratelimited(&s->unit->device,
 582                                      "Detect unexpected protocol: %08x %08x\n",
 583                                      cip_header[0], cip_header[1]);
 584                 return -EAGAIN;
 585         }
 586
 587         /* Calculate data blocks */
 588         fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT;
 589         if (payload_length == 0 || (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) {
 590                 *data_blocks = 0;
 591         } else {
 592                 unsigned int data_block_quadlets =
 593                                 (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT;
 594                 /* avoid division by zero */
 595                 if (data_block_quadlets == 0) {
 596                         dev_err(&s->unit->device,
 597                                 "Detect invalid value in dbs field: %08X\n",
 598                                 cip_header[0]);
 599                         return -EPROTO;
 600                 }
 601                 if (s->flags & CIP_WRONG_DBS)
 602                         data_block_quadlets = s->data_block_quadlets;
 603
 604                 *data_blocks = payload_length / sizeof(__be32) / data_block_quadlets;
 605         }
 606
 607         /* Check data block counter continuity */
 608         dbc = cip_header[0] & CIP_DBC_MASK;
 609         if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) &&
 610             *data_block_counter != UINT_MAX)
 611                 dbc = *data_block_counter;
 612
 613         if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) ||
 614             *data_block_counter == UINT_MAX) {
 615                 lost = false;
 616         } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) {
 617                 lost = dbc != *data_block_counter;
 618         } else {
 619                 unsigned int dbc_interval;
 620
 621                 if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0)
 622                         dbc_interval = s->ctx_data.tx.dbc_interval;
 623                 else
 624                         dbc_interval = *data_blocks;
 625
 626                 lost = dbc != ((*data_block_counter + dbc_interval) & 0xff);
 627         }
 628
 629         if (lost) {
 630                 dev_err(&s->unit->device,
 631                         "Detect discontinuity of CIP: %02X %02X\n",
 632                         *data_block_counter, dbc);
 633                 return -EIO;
 634         }
 635
 636         *data_block_counter = dbc;
 637
 638         if (!(s->flags & CIP_UNAWARE_SYT))
 639                 *syt = cip_header[1] & CIP_SYT_MASK;
 640
 641         return 0;
 642 }
 643
 644 static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle,
 645                                const __be32 *ctx_header,
 646                                unsigned int *data_blocks,
 647                                unsigned int *data_block_counter,
 648                                unsigned int *syt, unsigned int packet_index, unsigned int index)
 649 {
 650         unsigned int payload_length;
 651         const __be32 *cip_header;
 652         unsigned int cip_header_size;
 653
 654         payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT;
 655
 656         if (!(s->flags & CIP_NO_HEADER))
 657                 cip_header_size = CIP_HEADER_SIZE;
 658         else
 659                 cip_header_size = 0;
 660
 661         if (payload_length > cip_header_size + s->ctx_data.tx.max_ctx_payload_length) {
 662                 dev_err(&s->unit->device,
 663                         "Detect jumbo payload: %04x %04x\n",
 664                         payload_length, cip_header_size + s->ctx_data.tx.max_ctx_payload_length);
 665                 return -EIO;
 666         }
 667
 668         if (cip_header_size > 0) {
 669                 if (payload_length >= cip_header_size) {
 670                         int err;
 671
 672                         cip_header = ctx_header + IR_CTX_HEADER_DEFAULT_QUADLETS;
 673                         err = check_cip_header(s, cip_header, payload_length - cip_header_size,
 674                                                data_blocks, data_block_counter, syt);
 675                         if (err < 0)
 676                                 return err;
 677                 } else {
 678                         // Handle the cycle so that empty packet arrives.
 679                         cip_header = NULL;
 680                         *data_blocks = 0;
 681                         *syt = 0;
 682                 }
 683         } else {
 684                 cip_header = NULL;
 685                 *data_blocks = payload_length / sizeof(__be32) / s->data_block_quadlets;
 686                 *syt = 0;
 687
 688                 if (*data_block_counter == UINT_MAX)
 689                         *data_block_counter = 0;
 690         }
 691
 692         trace_amdtp_packet(s, cycle, cip_header, payload_length, *data_blocks,
 693                            *data_block_counter, packet_index, index);
 694
 695         return 0;
 696 }
 697
 698 // In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On
 699 // the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent
 700 // it. Thus, via Linux firewire subsystem, we can get the 3 bits for second.
 701 static inline u32 compute_ohci_cycle_count(__be32 ctx_header_tstamp)
 702 {
 703         u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK;
 704         return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff);
 705 }
 706
 707 static inline u32 increment_ohci_cycle_count(u32 cycle, unsigned int addend)
 708 {
 709         cycle += addend;
 710         if (cycle >= OHCI_SECOND_MODULUS * CYCLES_PER_SECOND)
 711                 cycle -= OHCI_SECOND_MODULUS * CYCLES_PER_SECOND;
 712         return cycle;
 713 }
 714
 715 static int compare_ohci_cycle_count(u32 lval, u32 rval)
 716 {
 717         if (lval == rval)
 718                 return 0;
 719         else if (lval < rval && rval - lval < OHCI_SECOND_MODULUS * CYCLES_PER_SECOND / 2)
 720                 return -1;
 721         else
 722                 return 1;
 723 }
 724
 725 // Align to actual cycle count for the packet which is going to be scheduled.
 726 // This module queued the same number of isochronous cycle as the size of queue
 727 // to kip isochronous cycle, therefore it's OK to just increment the cycle by
 728 // the size of queue for scheduled cycle.
 729 static inline u32 compute_ohci_it_cycle(const __be32 ctx_header_tstamp,
 730                                         unsigned int queue_size)
 731 {
 732         u32 cycle = compute_ohci_cycle_count(ctx_header_tstamp);
 733         return increment_ohci_cycle_count(cycle, queue_size);
 734 }
 735
 736 static int generate_device_pkt_descs(struct amdtp_stream *s,
 737                                      struct pkt_desc *descs,
 738                                      const __be32 *ctx_header,
 739                                      unsigned int packets,
 740                                      unsigned int *desc_count)
 741 {
 742         unsigned int next_cycle = s->next_cycle;
 743         unsigned int dbc = s->data_block_counter;
 744         unsigned int packet_index = s->packet_index;
 745         unsigned int queue_size = s->queue_size;
 746         int i;
 747         int err;
 748
 749         *desc_count = 0;
 750         for (i = 0; i < packets; ++i) {
 751                 struct pkt_desc *desc = descs + *desc_count;
 752                 unsigned int cycle;
 753                 bool lost;
 754                 unsigned int data_blocks;
 755                 unsigned int syt;
 756
 757                 cycle = compute_ohci_cycle_count(ctx_header[1]);
 758                 lost = (next_cycle != cycle);
 759                 if (lost) {
 760                         if (s->flags & CIP_NO_HEADER) {
 761                                 // Fireface skips transmission just for an isoc cycle corresponding
 762                                 // to empty packet.
 763                                 unsigned int prev_cycle = next_cycle;
 764
 765                                 next_cycle = increment_ohci_cycle_count(next_cycle, 1);
 766                                 lost = (next_cycle != cycle);
 767                                 if (!lost) {
 768                                         // Prepare a description for the skipped cycle for
 769                                         // sequence replay.
 770                                         desc->cycle = prev_cycle;
 771                                         desc->syt = 0;
 772                                         desc->data_blocks = 0;
 773                                         desc->data_block_counter = dbc;
 774                                         desc->ctx_payload = NULL;
 775                                         ++desc;
 776                                         ++(*desc_count);
 777                                 }
 778                         } else if (s->flags & CIP_JUMBO_PAYLOAD) {
 779                                 // OXFW970 skips transmission for several isoc cycles during
 780                                 // asynchronous transaction. The sequence replay is impossible due
 781                                 // to the reason.
 782                                 unsigned int safe_cycle = increment_ohci_cycle_count(next_cycle,
 783                                                                 IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES);
 784                                 lost = (compare_ohci_cycle_count(safe_cycle, cycle) > 0);
 785                         }
 786                         if (lost) {
 787                                 dev_err(&s->unit->device, "Detect discontinuity of cycle: %d %d\n",
 788                                         next_cycle, cycle);
 789                                 return -EIO;
 790                         }
 791                 }
 792
 793                 err = parse_ir_ctx_header(s, cycle, ctx_header, &data_blocks, &dbc, &syt,
 794                                           packet_index, i);
 795                 if (err < 0)
 796                         return err;
 797
 798                 desc->cycle = cycle;
 799                 desc->syt = syt;
 800                 desc->data_blocks = data_blocks;
 801                 desc->data_block_counter = dbc;
 802                 desc->ctx_payload = s->buffer.packets[packet_index].buffer;
 803
 804                 if (!(s->flags & CIP_DBC_IS_END_EVENT))
 805                         dbc = (dbc + desc->data_blocks) & 0xff;
 806
 807                 next_cycle = increment_ohci_cycle_count(next_cycle, 1);
 808                 ++(*desc_count);
 809                 ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
 810                 packet_index = (packet_index + 1) % queue_size;
 811         }
 812
 813         s->next_cycle = next_cycle;
 814         s->data_block_counter = dbc;
 815
 816         return 0;
 817 }
 818
 819 static unsigned int compute_syt(unsigned int syt_offset, unsigned int cycle,
 820                                 unsigned int transfer_delay)
 821 {
 822         unsigned int syt;
 823
 824         syt_offset += transfer_delay;
 825         syt = ((cycle + syt_offset / TICKS_PER_CYCLE) << 12) |
 826               (syt_offset % TICKS_PER_CYCLE);
 827         return syt & CIP_SYT_MASK;
 828 }
 829
 830 static void generate_pkt_descs(struct amdtp_stream *s, struct pkt_desc *descs,
 831                                const __be32 *ctx_header, unsigned int packets,
 832                                const struct seq_desc *seq_descs,
 833                                unsigned int seq_size)
 834 {
 835         unsigned int dbc = s->data_block_counter;
 836         unsigned int seq_index = s->ctx_data.rx.seq_index;
 837         bool aware_syt = !(s->flags & CIP_UNAWARE_SYT);
 838         int i;
 839
 840         for (i = 0; i < packets; ++i) {
 841                 struct pkt_desc *desc = descs + i;
 842                 unsigned int index = (s->packet_index + i) % s->queue_size;
 843                 const struct seq_desc *seq = seq_descs + seq_index;
 844
 845                 desc->cycle = compute_ohci_it_cycle(*ctx_header, s->queue_size);
 846
 847                 if (aware_syt && seq->syt_offset != CIP_SYT_NO_INFO) {
 848                         desc->syt = compute_syt(seq->syt_offset, desc->cycle,
 849                                                 s->ctx_data.rx.transfer_delay);
 850                 } else {
 851                         desc->syt = CIP_SYT_NO_INFO;
 852                 }
 853
 854                 desc->data_blocks = seq->data_blocks;
 855
 856                 if (s->flags & CIP_DBC_IS_END_EVENT)
 857                         dbc = (dbc + desc->data_blocks) & 0xff;
 858
 859                 desc->data_block_counter = dbc;
 860
 861                 if (!(s->flags & CIP_DBC_IS_END_EVENT))
 862                         dbc = (dbc + desc->data_blocks) & 0xff;
 863
 864                 desc->ctx_payload = s->buffer.packets[index].buffer;
 865
 866                 seq_index = (seq_index + 1) % seq_size;
 867
 868                 ++ctx_header;
 869         }
 870
 871         s->data_block_counter = dbc;
 872         s->ctx_data.rx.seq_index = seq_index;
 873 }
 874
 875 static inline void cancel_stream(struct amdtp_stream *s)
 876 {
 877         s->packet_index = -1;
 878         if (current_work() == &s->period_work)
 879                 amdtp_stream_pcm_abort(s);
 880         WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN);
 881 }
 882
 883 static void process_ctx_payloads(struct amdtp_stream *s,
 884                                  const struct pkt_desc *descs,
 885                                  unsigned int packets)
 886 {
 887         struct snd_pcm_substream *pcm;
 888         unsigned int pcm_frames;
 889
 890         pcm = READ_ONCE(s->pcm);
 891         pcm_frames = s->process_ctx_payloads(s, descs, packets, pcm);
 892         if (pcm)
 893                 update_pcm_pointers(s, pcm, pcm_frames);
 894 }
 895
 896 static void process_rx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
 897                                void *header, void *private_data)
 898 {
 899         struct amdtp_stream *s = private_data;
 900         const struct amdtp_domain *d = s->domain;
 901         const __be32 *ctx_header = header;
 902         const unsigned int events_per_period = d->events_per_period;
 903         unsigned int event_count = s->ctx_data.rx.event_count;
 904         unsigned int pkt_header_length;
 905         unsigned int packets;
 906         int i;
 907
 908         if (s->packet_index < 0)
 909                 return;
 910
 911         // Calculate the number of packets in buffer and check XRUN.
 912         packets = header_length / sizeof(*ctx_header);
 913
 914         generate_pkt_descs(s, s->pkt_descs, ctx_header, packets, d->seq.descs,
 915                            d->seq.size);
 916
 917         process_ctx_payloads(s, s->pkt_descs, packets);
 918
 919         if (!(s->flags & CIP_NO_HEADER))
 920                 pkt_header_length = IT_PKT_HEADER_SIZE_CIP;
 921         else
 922                 pkt_header_length = 0;
 923
 924         for (i = 0; i < packets; ++i) {
 925                 const struct pkt_desc *desc = s->pkt_descs + i;
 926                 struct {
 927                         struct fw_iso_packet params;
 928                         __be32 header[CIP_HEADER_QUADLETS];
 929                 } template = { {0}, {0} };
 930                 bool sched_irq = false;
 931
 932                 build_it_pkt_header(s, desc->cycle, &template.params, pkt_header_length,
 933                                     desc->data_blocks, desc->data_block_counter,
 934                                     desc->syt, i);
 935
 936                 if (s == s->domain->irq_target) {
 937                         event_count += desc->data_blocks;
 938                         if (event_count >= events_per_period) {
 939                                 event_count -= events_per_period;
 940                                 sched_irq = true;
 941                         }
 942                 }
 943
 944                 if (queue_out_packet(s, &template.params, sched_irq) < 0) {
 945                         cancel_stream(s);
 946                         return;
 947                 }
 948         }
 949
 950         s->ctx_data.rx.event_count = event_count;
 951 }
 952
 953 static void skip_rx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
 954                             void *header, void *private_data)
 955 {
 956         struct amdtp_stream *s = private_data;
 957         struct amdtp_domain *d = s->domain;
 958         const __be32 *ctx_header = header;
 959         unsigned int packets;
 960         unsigned int cycle;
 961         int i;
 962
 963         if (s->packet_index < 0)
 964                 return;
 965
 966         packets = header_length / sizeof(*ctx_header);
 967
 968         cycle = compute_ohci_it_cycle(ctx_header[packets - 1], s->queue_size);
 969         s->next_cycle = increment_ohci_cycle_count(cycle, 1);
 970
 971         for (i = 0; i < packets; ++i) {
 972                 struct fw_iso_packet params = {
 973                         .header_length = 0,
 974                         .payload_length = 0,
 975                 };
 976                 bool sched_irq = (s == d->irq_target && i == packets - 1);
 977
 978                 if (queue_out_packet(s, &params, sched_irq) < 0) {
 979                         cancel_stream(s);
 980                         return;
 981                 }
 982         }
 983 }
 984
 985 static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, size_t header_length,
 986                                 void *header, void *private_data);
 987
 988 static void process_rx_packets_intermediately(struct fw_iso_context *context, u32 tstamp,
 989                                         size_t header_length, void *header, void *private_data)
 990 {
 991         struct amdtp_stream *s = private_data;
 992         struct amdtp_domain *d = s->domain;
 993         __be32 *ctx_header = header;
 994         const unsigned int queue_size = s->queue_size;
 995         unsigned int packets;
 996         unsigned int offset;
 997
 998         if (s->packet_index < 0)
 999                 return;
1000
1001         packets = header_length / sizeof(*ctx_header);
1002
1003         offset = 0;
1004         while (offset < packets) {
1005                 unsigned int cycle = compute_ohci_it_cycle(ctx_header[offset], queue_size);
1006
1007                 if (compare_ohci_cycle_count(cycle, d->processing_cycle.rx_start) >= 0)
1008                         break;
1009
1010                 ++offset;
1011         }
1012
1013         if (offset > 0) {
1014                 unsigned int length = sizeof(*ctx_header) * offset;
1015
1016                 skip_rx_packets(context, tstamp, length, ctx_header, private_data);
1017                 if (amdtp_streaming_error(s))
1018                         return;
1019
1020                 ctx_header += offset;
1021                 header_length -= length;
1022         }
1023
1024         if (offset < packets) {
1025                 s->ready_processing = true;
1026                 wake_up(&s->ready_wait);
1027
1028                 process_rx_packets(context, tstamp, header_length, ctx_header, private_data);
1029                 if (amdtp_streaming_error(s))
1030                         return;
1031
1032                 if (s == d->irq_target)
1033                         s->context->callback.sc = irq_target_callback;
1034                 else
1035                         s->context->callback.sc = process_rx_packets;
1036         }
1037 }
1038
1039 static void process_tx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1040                                void *header, void *private_data)
1041 {
1042         struct amdtp_stream *s = private_data;
1043         __be32 *ctx_header = header;
1044         unsigned int packets;
1045         unsigned int desc_count;
1046         int i;
1047         int err;
1048
1049         if (s->packet_index < 0)
1050                 return;
1051
1052         // Calculate the number of packets in buffer and check XRUN.
1053         packets = header_length / s->ctx_data.tx.ctx_header_size;
1054
1055         desc_count = 0;
1056         err = generate_device_pkt_descs(s, s->pkt_descs, ctx_header, packets, &desc_count);
1057         if (err < 0) {
1058                 if (err != -EAGAIN) {
1059                         cancel_stream(s);
1060                         return;
1061                 }
1062         } else {
1063                 process_ctx_payloads(s, s->pkt_descs, desc_count);
1064         }
1065
1066         for (i = 0; i < packets; ++i) {
1067                 struct fw_iso_packet params = {0};
1068
1069                 if (queue_in_packet(s, &params) < 0) {
1070                         cancel_stream(s);
1071                         return;
1072                 }
1073         }
1074 }
1075
1076 static void drop_tx_packets(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1077                             void *header, void *private_data)
1078 {
1079         struct amdtp_stream *s = private_data;
1080         const __be32 *ctx_header = header;
1081         unsigned int packets;
1082         unsigned int cycle;
1083         int i;
1084
1085         if (s->packet_index < 0)
1086                 return;
1087
1088         packets = header_length / s->ctx_data.tx.ctx_header_size;
1089
1090         ctx_header += (packets - 1) * s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header);
1091         cycle = compute_ohci_cycle_count(ctx_header[1]);
1092         s->next_cycle = increment_ohci_cycle_count(cycle, 1);
1093
1094         for (i = 0; i < packets; ++i) {
1095                 struct fw_iso_packet params = {0};
1096
1097                 if (queue_in_packet(s, &params) < 0) {
1098                         cancel_stream(s);
1099                         return;
1100                 }
1101         }
1102 }
1103
1104 static void process_tx_packets_intermediately(struct fw_iso_context *context, u32 tstamp,
1105                                         size_t header_length, void *header, void *private_data)
1106 {
1107         struct amdtp_stream *s = private_data;
1108         struct amdtp_domain *d = s->domain;
1109         __be32 *ctx_header;
1110         unsigned int packets;
1111         unsigned int offset;
1112
1113         if (s->packet_index < 0)
1114                 return;
1115
1116         packets = header_length / s->ctx_data.tx.ctx_header_size;
1117
1118         offset = 0;
1119         ctx_header = header;
1120         while (offset < packets) {
1121                 unsigned int cycle = compute_ohci_cycle_count(ctx_header[1]);
1122
1123                 if (compare_ohci_cycle_count(cycle, d->processing_cycle.tx_start) >= 0)
1124                         break;
1125
1126                 ctx_header += s->ctx_data.tx.ctx_header_size / sizeof(__be32);
1127                 ++offset;
1128         }
1129
1130         ctx_header = header;
1131
1132         if (offset > 0) {
1133                 size_t length = s->ctx_data.tx.ctx_header_size * offset;
1134
1135                 drop_tx_packets(context, tstamp, length, ctx_header, s);
1136                 if (amdtp_streaming_error(s))
1137                         return;
1138
1139                 ctx_header += length / sizeof(*ctx_header);
1140                 header_length -= length;
1141         }
1142
1143         if (offset < packets) {
1144                 s->ready_processing = true;
1145                 wake_up(&s->ready_wait);
1146
1147                 process_tx_packets(context, tstamp, header_length, ctx_header, s);
1148                 if (amdtp_streaming_error(s))
1149                         return;
1150
1151                 context->callback.sc = process_tx_packets;
1152         }
1153 }
1154
1155 static void pool_ideal_seq_descs(struct amdtp_domain *d, unsigned int packets)
1156 {
1157         struct amdtp_stream *irq_target = d->irq_target;
1158         unsigned int seq_tail = d->seq.tail;
1159         unsigned int seq_size = d->seq.size;
1160         unsigned int min_avail;
1161         struct amdtp_stream *s;
1162
1163         min_avail = d->seq.size;
1164         list_for_each_entry(s, &d->streams, list) {
1165                 unsigned int seq_index;
1166                 unsigned int avail;
1167
1168                 if (s->direction == AMDTP_IN_STREAM)
1169                         continue;
1170
1171                 seq_index = s->ctx_data.rx.seq_index;
1172                 avail = d->seq.tail;
1173                 if (seq_index > avail)
1174                         avail += d->seq.size;
1175                 avail -= seq_index;
1176
1177                 if (avail < min_avail)
1178                         min_avail = avail;
1179         }
1180
1181         while (min_avail < packets) {
1182                 struct seq_desc *desc = d->seq.descs + seq_tail;
1183
1184                 desc->syt_offset = calculate_syt_offset(&d->last_syt_offset,
1185                                         &d->syt_offset_state, irq_target->sfc);
1186                 desc->data_blocks = calculate_data_blocks(&d->data_block_state,
1187                                 !!(irq_target->flags & CIP_BLOCKING),
1188                                 desc->syt_offset == CIP_SYT_NO_INFO,
1189                                 irq_target->syt_interval, irq_target->sfc);
1190
1191                 ++seq_tail;
1192                 seq_tail %= seq_size;
1193
1194                 ++min_avail;
1195         }
1196
1197         d->seq.tail = seq_tail;
1198 }
1199
1200 static void process_ctxs_in_domain(struct amdtp_domain *d)
1201 {
1202         struct amdtp_stream *s;
1203
1204         list_for_each_entry(s, &d->streams, list) {
1205                 if (s != d->irq_target && amdtp_stream_running(s))
1206                         fw_iso_context_flush_completions(s->context);
1207
1208                 if (amdtp_streaming_error(s))
1209                         goto error;
1210         }
1211
1212         return;
1213 error:
1214         if (amdtp_stream_running(d->irq_target))
1215                 cancel_stream(d->irq_target);
1216
1217         list_for_each_entry(s, &d->streams, list) {
1218                 if (amdtp_stream_running(s))
1219                         cancel_stream(s);
1220         }
1221 }
1222
1223 static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, size_t header_length,
1224                                 void *header, void *private_data)
1225 {
1226         struct amdtp_stream *s = private_data;
1227         struct amdtp_domain *d = s->domain;
1228         unsigned int packets = header_length / sizeof(__be32);
1229
1230         pool_ideal_seq_descs(d, packets);
1231
1232         process_rx_packets(context, tstamp, header_length, header, private_data);
1233         process_ctxs_in_domain(d);
1234 }
1235
1236 static void irq_target_callback_intermediately(struct fw_iso_context *context, u32 tstamp,
1237                                         size_t header_length, void *header, void *private_data)
1238 {
1239         struct amdtp_stream *s = private_data;
1240         struct amdtp_domain *d = s->domain;
1241         unsigned int packets = header_length / sizeof(__be32);
1242
1243         pool_ideal_seq_descs(d, packets);
1244
1245         process_rx_packets_intermediately(context, tstamp, header_length, header, private_data);
1246         process_ctxs_in_domain(d);
1247 }
1248
1249 static void irq_target_callback_skip(struct fw_iso_context *context, u32 tstamp,
1250                                      size_t header_length, void *header, void *private_data)
1251 {
1252         struct amdtp_stream *s = private_data;
1253         struct amdtp_domain *d = s->domain;
1254         unsigned int cycle;
1255
1256         skip_rx_packets(context, tstamp, header_length, header, private_data);
1257         process_ctxs_in_domain(d);
1258
1259         // Decide the cycle count to begin processing content of packet in IT contexts. All of IT
1260         // contexts are expected to start and get callback when reaching here.
1261         cycle = s->next_cycle;
1262         list_for_each_entry(s, &d->streams, list) {
1263                 if (s->direction != AMDTP_OUT_STREAM)
1264                         continue;
1265
1266                 if (compare_ohci_cycle_count(s->next_cycle, cycle) > 0)
1267                         cycle = s->next_cycle;
1268
1269                 if (s == d->irq_target)
1270                         s->context->callback.sc = irq_target_callback_intermediately;
1271                 else
1272                         s->context->callback.sc = process_rx_packets_intermediately;
1273         }
1274
1275         d->processing_cycle.rx_start = cycle;
1276 }
1277
1278 // this is executed one time.
1279 static void amdtp_stream_first_callback(struct fw_iso_context *context,
1280                                         u32 tstamp, size_t header_length,
1281                                         void *header, void *private_data)
1282 {
1283         struct amdtp_stream *s = private_data;
1284         struct amdtp_domain *d = s->domain;
1285         const __be32 *ctx_header = header;
1286         u32 cycle;
1287
1288         // For in-stream, first packet has come.
1289         // For out-stream, prepared to transmit first packet
1290         s->callbacked = true;
1291
1292         if (s->direction == AMDTP_IN_STREAM) {
1293                 cycle = compute_ohci_cycle_count(ctx_header[1]);
1294
1295                 context->callback.sc = drop_tx_packets;
1296         } else {
1297                 cycle = compute_ohci_it_cycle(*ctx_header, s->queue_size);
1298
1299                 if (s == d->irq_target)
1300                         context->callback.sc = irq_target_callback_skip;
1301                 else
1302                         context->callback.sc = skip_rx_packets;
1303         }
1304
1305         context->callback.sc(context, tstamp, header_length, header, s);
1306
1307         // Decide the cycle count to begin processing content of packet in IR contexts.
1308         if (s->direction == AMDTP_IN_STREAM) {
1309                 unsigned int stream_count = 0;
1310                 unsigned int callbacked_count = 0;
1311
1312                 list_for_each_entry(s, &d->streams, list) {
1313                         if (s->direction == AMDTP_IN_STREAM) {
1314                                 ++stream_count;
1315                                 if (s->callbacked)
1316                                         ++callbacked_count;
1317                         }
1318                 }
1319
1320                 if (stream_count == callbacked_count) {
1321                         unsigned int next_cycle;
1322
1323                         list_for_each_entry(s, &d->streams, list) {
1324                                 if (s->direction != AMDTP_IN_STREAM)
1325                                         continue;
1326
1327                                 next_cycle = increment_ohci_cycle_count(s->next_cycle,
1328                                                                 d->processing_cycle.tx_init_skip);
1329                                 if (compare_ohci_cycle_count(next_cycle, cycle) > 0)
1330                                         cycle = next_cycle;
1331
1332                                 s->context->callback.sc = process_tx_packets_intermediately;
1333                         }
1334
1335                         d->processing_cycle.tx_start = cycle;
1336                 }
1337         }
1338 }
1339
1340 /**
1341  * amdtp_stream_start - start transferring packets
1342  * @s: the AMDTP stream to start
1343  * @channel: the isochronous channel on the bus
1344  * @speed: firewire speed code
1345  * @queue_size: The number of packets in the queue.
1346  * @idle_irq_interval: the interval to queue packet during initial state.
1347  *
1348  * The stream cannot be started until it has been configured with
1349  * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI
1350  * device can be started.
1351  */
1352 static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed,
1353                               unsigned int queue_size, unsigned int idle_irq_interval)
1354 {
1355         bool is_irq_target = (s == s->domain->irq_target);
1356         unsigned int ctx_header_size;
1357         unsigned int max_ctx_payload_size;
1358         enum dma_data_direction dir;
1359         int type, tag, err;
1360
1361         mutex_lock(&s->mutex);
1362
1363         if (WARN_ON(amdtp_stream_running(s) ||
1364                     (s->data_block_quadlets < 1))) {
1365                 err = -EBADFD;
1366                 goto err_unlock;
1367         }
1368
1369         if (s->direction == AMDTP_IN_STREAM) {
1370                 // NOTE: IT context should be used for constant IRQ.
1371                 if (is_irq_target) {
1372                         err = -EINVAL;
1373                         goto err_unlock;
1374                 }
1375
1376                 s->data_block_counter = UINT_MAX;
1377         } else {
1378                 s->data_block_counter = 0;
1379         }
1380
1381         // initialize packet buffer.
1382         if (s->direction == AMDTP_IN_STREAM) {
1383                 dir = DMA_FROM_DEVICE;
1384                 type = FW_ISO_CONTEXT_RECEIVE;
1385                 if (!(s->flags & CIP_NO_HEADER))
1386                         ctx_header_size = IR_CTX_HEADER_SIZE_CIP;
1387                 else
1388                         ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP;
1389         } else {
1390                 dir = DMA_TO_DEVICE;
1391                 type = FW_ISO_CONTEXT_TRANSMIT;
1392                 ctx_header_size = 0;    // No effect for IT context.
1393         }
1394         max_ctx_payload_size = amdtp_stream_get_max_ctx_payload_size(s);
1395
1396         err = iso_packets_buffer_init(&s->buffer, s->unit, queue_size, max_ctx_payload_size, dir);
1397         if (err < 0)
1398                 goto err_unlock;
1399         s->queue_size = queue_size;
1400
1401         s->context = fw_iso_context_create(fw_parent_device(s->unit)->card,
1402                                           type, channel, speed, ctx_header_size,
1403                                           amdtp_stream_first_callback, s);
1404         if (IS_ERR(s->context)) {
1405                 err = PTR_ERR(s->context);
1406                 if (err == -EBUSY)
1407                         dev_err(&s->unit->device,
1408                                 "no free stream on this controller\n");
1409                 goto err_buffer;
1410         }
1411
1412         amdtp_stream_update(s);
1413
1414         if (s->direction == AMDTP_IN_STREAM) {
1415                 s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size;
1416                 s->ctx_data.tx.ctx_header_size = ctx_header_size;
1417         } else {
1418                 s->ctx_data.rx.seq_index = 0;
1419                 s->ctx_data.rx.event_count = 0;
1420         }
1421
1422         if (s->flags & CIP_NO_HEADER)
1423                 s->tag = TAG_NO_CIP_HEADER;
1424         else
1425                 s->tag = TAG_CIP;
1426
1427         s->pkt_descs = kcalloc(s->queue_size, sizeof(*s->pkt_descs),
1428                                GFP_KERNEL);
1429         if (!s->pkt_descs) {
1430                 err = -ENOMEM;
1431                 goto err_context;
1432         }
1433
1434         s->packet_index = 0;
1435         do {
1436                 struct fw_iso_packet params;
1437
1438                 if (s->direction == AMDTP_IN_STREAM) {
1439                         err = queue_in_packet(s, &params);
1440                 } else {
1441                         bool sched_irq = false;
1442
1443                         params.header_length = 0;
1444                         params.payload_length = 0;
1445
1446                         if (is_irq_target) {
1447                                 sched_irq = !((s->packet_index + 1) %
1448                                               idle_irq_interval);
1449                         }
1450
1451                         err = queue_out_packet(s, &params, sched_irq);
1452                 }
1453                 if (err < 0)
1454                         goto err_pkt_descs;
1455         } while (s->packet_index > 0);
1456
1457         /* NOTE: TAG1 matches CIP. This just affects in stream. */
1458         tag = FW_ISO_CONTEXT_MATCH_TAG1;
1459         if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER))
1460                 tag |= FW_ISO_CONTEXT_MATCH_TAG0;
1461
1462         s->callbacked = false;
1463         s->ready_processing = false;
1464         err = fw_iso_context_start(s->context, -1, 0, tag);
1465         if (err < 0)
1466                 goto err_pkt_descs;
1467
1468         mutex_unlock(&s->mutex);
1469
1470         return 0;
1471 err_pkt_descs:
1472         kfree(s->pkt_descs);
1473 err_context:
1474         fw_iso_context_destroy(s->context);
1475         s->context = ERR_PTR(-1);
1476 err_buffer:
1477         iso_packets_buffer_destroy(&s->buffer, s->unit);
1478 err_unlock:
1479         mutex_unlock(&s->mutex);
1480
1481         return err;
1482 }
1483
1484 /**
1485  * amdtp_domain_stream_pcm_pointer - get the PCM buffer position
1486  * @d: the AMDTP domain.
1487  * @s: the AMDTP stream that transports the PCM data
1488  *
1489  * Returns the current buffer position, in frames.
1490  */
1491 unsigned long amdtp_domain_stream_pcm_pointer(struct amdtp_domain *d,
1492                                               struct amdtp_stream *s)
1493 {
1494         struct amdtp_stream *irq_target = d->irq_target;
1495
1496         if (irq_target && amdtp_stream_running(irq_target)) {
1497                 // This function is called in software IRQ context of
1498                 // period_work or process context.
1499                 //
1500                 // When the software IRQ context was scheduled by software IRQ
1501                 // context of IT contexts, queued packets were already handled.
1502                 // Therefore, no need to flush the queue in buffer furthermore.
1503                 //
1504                 // When the process context reach here, some packets will be
1505                 // already queued in the buffer. These packets should be handled
1506                 // immediately to keep better granularity of PCM pointer.
1507                 //
1508                 // Later, the process context will sometimes schedules software
1509                 // IRQ context of the period_work. Then, no need to flush the
1510                 // queue by the same reason as described in the above
1511                 if (current_work() != &s->period_work) {
1512                         // Queued packet should be processed without any kernel
1513                         // preemption to keep latency against bus cycle.
1514                         preempt_disable();
1515                         fw_iso_context_flush_completions(irq_target->context);
1516                         preempt_enable();
1517                 }
1518         }
1519
1520         return READ_ONCE(s->pcm_buffer_pointer);
1521 }
1522 EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_pointer);
1523
1524 /**
1525  * amdtp_domain_stream_pcm_ack - acknowledge queued PCM frames
1526  * @d: the AMDTP domain.
1527  * @s: the AMDTP stream that transfers the PCM frames
1528  *
1529  * Returns zero always.
1530  */
1531 int amdtp_domain_stream_pcm_ack(struct amdtp_domain *d, struct amdtp_stream *s)
1532 {
1533         struct amdtp_stream *irq_target = d->irq_target;
1534
1535         // Process isochronous packets for recent isochronous cycle to handle
1536         // queued PCM frames.
1537         if (irq_target && amdtp_stream_running(irq_target)) {
1538                 // Queued packet should be processed without any kernel
1539                 // preemption to keep latency against bus cycle.
1540                 preempt_disable();
1541                 fw_iso_context_flush_completions(irq_target->context);
1542                 preempt_enable();
1543         }
1544
1545         return 0;
1546 }
1547 EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_ack);
1548
1549 /**
1550  * amdtp_stream_update - update the stream after a bus reset
1551  * @s: the AMDTP stream
1552  */
1553 void amdtp_stream_update(struct amdtp_stream *s)
1554 {
1555         /* Precomputing. */
1556         WRITE_ONCE(s->source_node_id_field,
1557                    (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK);
1558 }
1559 EXPORT_SYMBOL(amdtp_stream_update);
1560
1561 /**
1562  * amdtp_stream_stop - stop sending packets
1563  * @s: the AMDTP stream to stop
1564  *
1565  * All PCM and MIDI devices of the stream must be stopped before the stream
1566  * itself can be stopped.
1567  */
1568 static void amdtp_stream_stop(struct amdtp_stream *s)
1569 {
1570         mutex_lock(&s->mutex);
1571
1572         if (!amdtp_stream_running(s)) {
1573                 mutex_unlock(&s->mutex);
1574                 return;
1575         }
1576
1577         cancel_work_sync(&s->period_work);
1578         fw_iso_context_stop(s->context);
1579         fw_iso_context_destroy(s->context);
1580         s->context = ERR_PTR(-1);
1581         iso_packets_buffer_destroy(&s->buffer, s->unit);
1582         kfree(s->pkt_descs);
1583
1584         s->callbacked = false;
1585
1586         mutex_unlock(&s->mutex);
1587 }
1588
1589 /**
1590  * amdtp_stream_pcm_abort - abort the running PCM device
1591  * @s: the AMDTP stream about to be stopped
1592  *
1593  * If the isochronous stream needs to be stopped asynchronously, call this
1594  * function first to stop the PCM device.
1595  */
1596 void amdtp_stream_pcm_abort(struct amdtp_stream *s)
1597 {
1598         struct snd_pcm_substream *pcm;
1599
1600         pcm = READ_ONCE(s->pcm);
1601         if (pcm)
1602                 snd_pcm_stop_xrun(pcm);
1603 }
1604 EXPORT_SYMBOL(amdtp_stream_pcm_abort);
1605
1606 /**
1607  * amdtp_domain_init - initialize an AMDTP domain structure
1608  * @d: the AMDTP domain to initialize.
1609  */
1610 int amdtp_domain_init(struct amdtp_domain *d)
1611 {
1612         INIT_LIST_HEAD(&d->streams);
1613
1614         d->events_per_period = 0;
1615
1616         d->seq.descs = NULL;
1617
1618         return 0;
1619 }
1620 EXPORT_SYMBOL_GPL(amdtp_domain_init);
1621
1622 /**
1623  * amdtp_domain_destroy - destroy an AMDTP domain structure
1624  * @d: the AMDTP domain to destroy.
1625  */
1626 void amdtp_domain_destroy(struct amdtp_domain *d)
1627 {
1628         // At present nothing to do.
1629         return;
1630 }
1631 EXPORT_SYMBOL_GPL(amdtp_domain_destroy);
1632
1633 /**
1634  * amdtp_domain_add_stream - register isoc context into the domain.
1635  * @d: the AMDTP domain.
1636  * @s: the AMDTP stream.
1637  * @channel: the isochronous channel on the bus.
1638  * @speed: firewire speed code.
1639  */
1640 int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s,
1641                             int channel, int speed)
1642 {
1643         struct amdtp_stream *tmp;
1644
1645         list_for_each_entry(tmp, &d->streams, list) {
1646                 if (s == tmp)
1647                         return -EBUSY;
1648         }
1649
1650         list_add(&s->list, &d->streams);
1651
1652         s->channel = channel;
1653         s->speed = speed;
1654         s->domain = d;
1655
1656         return 0;
1657 }
1658 EXPORT_SYMBOL_GPL(amdtp_domain_add_stream);
1659
1660 /**
1661  * amdtp_domain_start - start sending packets for isoc context in the domain.
1662  * @d: the AMDTP domain.
1663  * @tx_init_skip_cycles: the number of cycles to skip processing packets at initial stage of IR
1664  *                       contexts.
1665  */
1666 int amdtp_domain_start(struct amdtp_domain *d, unsigned int tx_init_skip_cycles)
1667 {
1668         static const struct {
1669                 unsigned int data_block;
1670                 unsigned int syt_offset;
1671         } *entry, initial_state[] = {
1672                 [CIP_SFC_32000]  = {  4, 3072 },
1673                 [CIP_SFC_48000]  = {  6, 1024 },
1674                 [CIP_SFC_96000]  = { 12, 1024 },
1675                 [CIP_SFC_192000] = { 24, 1024 },
1676                 [CIP_SFC_44100]  = {  0,   67 },
1677                 [CIP_SFC_88200]  = {  0,   67 },
1678                 [CIP_SFC_176400] = {  0,   67 },
1679         };
1680         unsigned int events_per_buffer = d->events_per_buffer;
1681         unsigned int events_per_period = d->events_per_period;
1682         unsigned int queue_size;
1683         struct amdtp_stream *s;
1684         int err;
1685
1686         // Select an IT context as IRQ target.
1687         list_for_each_entry(s, &d->streams, list) {
1688                 if (s->direction == AMDTP_OUT_STREAM)
1689                         break;
1690         }
1691         if (!s)
1692                 return -ENXIO;
1693         d->irq_target = s;
1694
1695         d->processing_cycle.tx_init_skip = tx_init_skip_cycles;
1696
1697         // This is a case that AMDTP streams in domain run just for MIDI
1698         // substream. Use the number of events equivalent to 10 msec as
1699         // interval of hardware IRQ.
1700         if (events_per_period == 0)
1701                 events_per_period = amdtp_rate_table[d->irq_target->sfc] / 100;
1702         if (events_per_buffer == 0)
1703                 events_per_buffer = events_per_period * 3;
1704
1705         queue_size = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_buffer,
1706                                   amdtp_rate_table[d->irq_target->sfc]);
1707
1708         d->seq.descs = kcalloc(queue_size, sizeof(*d->seq.descs), GFP_KERNEL);
1709         if (!d->seq.descs)
1710                 return -ENOMEM;
1711         d->seq.size = queue_size;
1712         d->seq.tail = 0;
1713
1714         entry = &initial_state[s->sfc];
1715         d->data_block_state = entry->data_block;
1716         d->syt_offset_state = entry->syt_offset;
1717         d->last_syt_offset = TICKS_PER_CYCLE;
1718
1719         list_for_each_entry(s, &d->streams, list) {
1720                 unsigned int idle_irq_interval = 0;
1721
1722                 if (s->direction == AMDTP_OUT_STREAM && s == d->irq_target) {
1723                         idle_irq_interval = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period,
1724                                                          amdtp_rate_table[d->irq_target->sfc]);
1725                 }
1726
1727                 // Starts immediately but actually DMA context starts several hundred cycles later.
1728                 err = amdtp_stream_start(s, s->channel, s->speed, queue_size, idle_irq_interval);
1729                 if (err < 0)
1730                         goto error;
1731         }
1732
1733         return 0;
1734 error:
1735         list_for_each_entry(s, &d->streams, list)
1736                 amdtp_stream_stop(s);
1737         kfree(d->seq.descs);
1738         d->seq.descs = NULL;
1739         return err;
1740 }
1741 EXPORT_SYMBOL_GPL(amdtp_domain_start);
1742
1743 /**
1744  * amdtp_domain_stop - stop sending packets for isoc context in the same domain.
1745  * @d: the AMDTP domain to which the isoc contexts belong.
1746  */
1747 void amdtp_domain_stop(struct amdtp_domain *d)
1748 {
1749         struct amdtp_stream *s, *next;
1750
1751         if (d->irq_target)
1752                 amdtp_stream_stop(d->irq_target);
1753
1754         list_for_each_entry_safe(s, next, &d->streams, list) {
1755                 list_del(&s->list);
1756
1757                 if (s != d->irq_target)
1758                         amdtp_stream_stop(s);
1759         }
1760
1761         d->events_per_period = 0;
1762         d->irq_target = NULL;
1763
1764         kfree(d->seq.descs);
1765         d->seq.descs = NULL;
1766 }
1767 EXPORT_SYMBOL_GPL(amdtp_domain_stop);