2 * Library implementing the most common irq chip callback functions
4 * Copyright (C) 2011, Thomas Gleixner
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/irqdomain.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/syscore_ops.h>
15 #include "internals.h"
17 static LIST_HEAD(gc_list);
18 static DEFINE_RAW_SPINLOCK(gc_lock);
21 * irq_gc_noop - NOOP function
24 void irq_gc_noop(struct irq_data *d)
29 * irq_gc_mask_disable_reg - Mask chip via disable register
32 * Chip has separate enable/disable registers instead of a single mask
35 void irq_gc_mask_disable_reg(struct irq_data *d)
37 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
38 struct irq_chip_type *ct = irq_data_get_chip_type(d);
42 irq_reg_writel(gc, mask, ct->regs.disable);
43 *ct->mask_cache &= ~mask;
48 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
51 * Chip has a single mask register. Values of this register are cached
52 * and protected by gc->lock
54 void irq_gc_mask_set_bit(struct irq_data *d)
56 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
57 struct irq_chip_type *ct = irq_data_get_chip_type(d);
61 *ct->mask_cache |= mask;
62 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
65 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
68 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
71 * Chip has a single mask register. Values of this register are cached
72 * and protected by gc->lock
74 void irq_gc_mask_clr_bit(struct irq_data *d)
76 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77 struct irq_chip_type *ct = irq_data_get_chip_type(d);
81 *ct->mask_cache &= ~mask;
82 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
85 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
88 * irq_gc_unmask_enable_reg - Unmask chip via enable register
91 * Chip has separate enable/disable registers instead of a single mask
94 void irq_gc_unmask_enable_reg(struct irq_data *d)
96 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
97 struct irq_chip_type *ct = irq_data_get_chip_type(d);
101 irq_reg_writel(gc, mask, ct->regs.enable);
102 *ct->mask_cache |= mask;
107 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
110 void irq_gc_ack_set_bit(struct irq_data *d)
112 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
113 struct irq_chip_type *ct = irq_data_get_chip_type(d);
117 irq_reg_writel(gc, mask, ct->regs.ack);
120 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
123 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
126 void irq_gc_ack_clr_bit(struct irq_data *d)
128 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
129 struct irq_chip_type *ct = irq_data_get_chip_type(d);
133 irq_reg_writel(gc, mask, ct->regs.ack);
138 * irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
141 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
143 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
144 struct irq_chip_type *ct = irq_data_get_chip_type(d);
148 irq_reg_writel(gc, mask, ct->regs.mask);
149 irq_reg_writel(gc, mask, ct->regs.ack);
154 * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
157 * This generic implementation of the irq_mask_ack method is for chips
158 * with separate enable/disable registers instead of a single mask
159 * register and where a pending interrupt is acknowledged by setting a
162 * Note: This is the only permutation currently used. Similar generic
163 * functions should be added here if other permutations are required.
165 void irq_gc_mask_disable_and_ack_set(struct irq_data *d)
167 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
168 struct irq_chip_type *ct = irq_data_get_chip_type(d);
172 irq_reg_writel(gc, mask, ct->regs.disable);
173 *ct->mask_cache &= ~mask;
174 irq_reg_writel(gc, mask, ct->regs.ack);
179 * irq_gc_eoi - EOI interrupt
182 void irq_gc_eoi(struct irq_data *d)
184 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
185 struct irq_chip_type *ct = irq_data_get_chip_type(d);
189 irq_reg_writel(gc, mask, ct->regs.eoi);
194 * irq_gc_set_wake - Set/clr wake bit for an interrupt
196 * @on: Indicates whether the wake bit should be set or cleared
198 * For chips where the wake from suspend functionality is not
199 * configured in a separate register and the wakeup active state is
200 * just stored in a bitmask.
202 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
204 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
207 if (!(mask & gc->wake_enabled))
212 gc->wake_active |= mask;
214 gc->wake_active &= ~mask;
219 static u32 irq_readl_be(void __iomem *addr)
221 return ioread32be(addr);
224 static void irq_writel_be(u32 val, void __iomem *addr)
226 iowrite32be(val, addr);
229 void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
230 int num_ct, unsigned int irq_base,
231 void __iomem *reg_base, irq_flow_handler_t handler)
233 raw_spin_lock_init(&gc->lock);
235 gc->irq_base = irq_base;
236 gc->reg_base = reg_base;
237 gc->chip_types->chip.name = name;
238 gc->chip_types->handler = handler;
242 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
243 * @name: Name of the irq chip
244 * @num_ct: Number of irq_chip_type instances associated with this
245 * @irq_base: Interrupt base nr for this chip
246 * @reg_base: Register base address (virtual)
247 * @handler: Default flow handler associated with this chip
249 * Returns an initialized irq_chip_generic structure. The chip defaults
250 * to the primary (index 0) irq_chip_type and @handler
252 struct irq_chip_generic *
253 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
254 void __iomem *reg_base, irq_flow_handler_t handler)
256 struct irq_chip_generic *gc;
257 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
259 gc = kzalloc(sz, GFP_KERNEL);
261 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
266 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
269 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
271 struct irq_chip_type *ct = gc->chip_types;
272 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
275 for (i = 0; i < gc->num_ct; i++) {
276 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
277 mskptr = &ct[i].mask_cache_priv;
278 mskreg = ct[i].regs.mask;
280 ct[i].mask_cache = mskptr;
281 if (flags & IRQ_GC_INIT_MASK_CACHE)
282 *mskptr = irq_reg_readl(gc, mskreg);
287 * __irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
288 * @d: irq domain for which to allocate chips
289 * @irqs_per_chip: Number of interrupts each chip handles (max 32)
290 * @num_ct: Number of irq_chip_type instances associated with this
291 * @name: Name of the irq chip
292 * @handler: Default flow handler associated with these chips
293 * @clr: IRQ_* bits to clear in the mapping function
294 * @set: IRQ_* bits to set in the mapping function
295 * @gcflags: Generic chip specific setup flags
297 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
298 int num_ct, const char *name,
299 irq_flow_handler_t handler,
300 unsigned int clr, unsigned int set,
301 enum irq_gc_flags gcflags)
303 struct irq_domain_chip_generic *dgc;
304 struct irq_chip_generic *gc;
312 numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
316 /* Allocate a pointer, generic chip and chiptypes for each chip */
317 sz = sizeof(*dgc) + numchips * sizeof(gc);
318 sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));
320 tmp = dgc = kzalloc(sz, GFP_KERNEL);
323 dgc->irqs_per_chip = irqs_per_chip;
324 dgc->num_chips = numchips;
325 dgc->irq_flags_to_set = set;
326 dgc->irq_flags_to_clear = clr;
327 dgc->gc_flags = gcflags;
330 /* Calc pointer to the first generic chip */
331 tmp += sizeof(*dgc) + numchips * sizeof(gc);
332 for (i = 0; i < numchips; i++) {
333 /* Store the pointer to the generic chip */
334 dgc->gc[i] = gc = tmp;
335 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
339 if (gcflags & IRQ_GC_BE_IO) {
340 gc->reg_readl = &irq_readl_be;
341 gc->reg_writel = &irq_writel_be;
344 raw_spin_lock_irqsave(&gc_lock, flags);
345 list_add_tail(&gc->list, &gc_list);
346 raw_spin_unlock_irqrestore(&gc_lock, flags);
347 /* Calc pointer to the next generic chip */
348 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
352 EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
354 static struct irq_chip_generic *
355 __irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
357 struct irq_domain_chip_generic *dgc = d->gc;
361 return ERR_PTR(-ENODEV);
362 idx = hw_irq / dgc->irqs_per_chip;
363 if (idx >= dgc->num_chips)
364 return ERR_PTR(-EINVAL);
369 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
370 * @d: irq domain pointer
371 * @hw_irq: Hardware interrupt number
373 struct irq_chip_generic *
374 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
376 struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
378 return !IS_ERR(gc) ? gc : NULL;
380 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
383 * Separate lockdep class for interrupt chip which can nest irq_desc
386 static struct lock_class_key irq_nested_lock_class;
389 * irq_map_generic_chip - Map a generic chip for an irq domain
391 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
392 irq_hw_number_t hw_irq)
394 struct irq_data *data = irq_domain_get_irq_data(d, virq);
395 struct irq_domain_chip_generic *dgc = d->gc;
396 struct irq_chip_generic *gc;
397 struct irq_chip_type *ct;
398 struct irq_chip *chip;
402 gc = __irq_get_domain_generic_chip(d, hw_irq);
406 idx = hw_irq % dgc->irqs_per_chip;
408 if (test_bit(idx, &gc->unused))
411 if (test_bit(idx, &gc->installed))
417 /* We only init the cache for the first mapping of a generic chip */
418 if (!gc->installed) {
419 raw_spin_lock_irqsave(&gc->lock, flags);
420 irq_gc_init_mask_cache(gc, dgc->gc_flags);
421 raw_spin_unlock_irqrestore(&gc->lock, flags);
424 /* Mark the interrupt as installed */
425 set_bit(idx, &gc->installed);
427 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
428 irq_set_lockdep_class(virq, &irq_nested_lock_class);
430 if (chip->irq_calc_mask)
431 chip->irq_calc_mask(data);
433 data->mask = 1 << idx;
435 irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
436 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
440 static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
442 struct irq_data *data = irq_domain_get_irq_data(d, virq);
443 struct irq_domain_chip_generic *dgc = d->gc;
444 unsigned int hw_irq = data->hwirq;
445 struct irq_chip_generic *gc;
448 gc = irq_get_domain_generic_chip(d, hw_irq);
452 irq_idx = hw_irq % dgc->irqs_per_chip;
454 clear_bit(irq_idx, &gc->installed);
455 irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
460 struct irq_domain_ops irq_generic_chip_ops = {
461 .map = irq_map_generic_chip,
462 .unmap = irq_unmap_generic_chip,
463 .xlate = irq_domain_xlate_onetwocell,
465 EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
468 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
469 * @gc: Generic irq chip holding all data
470 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
471 * @flags: Flags for initialization
472 * @clr: IRQ_* bits to clear
473 * @set: IRQ_* bits to set
475 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
476 * initializes all interrupts to the primary irq_chip_type and its
477 * associated handler.
479 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
480 enum irq_gc_flags flags, unsigned int clr,
483 struct irq_chip_type *ct = gc->chip_types;
484 struct irq_chip *chip = &ct->chip;
487 raw_spin_lock(&gc_lock);
488 list_add_tail(&gc->list, &gc_list);
489 raw_spin_unlock(&gc_lock);
491 irq_gc_init_mask_cache(gc, flags);
493 for (i = gc->irq_base; msk; msk >>= 1, i++) {
497 if (flags & IRQ_GC_INIT_NESTED_LOCK)
498 irq_set_lockdep_class(i, &irq_nested_lock_class);
500 if (!(flags & IRQ_GC_NO_MASK)) {
501 struct irq_data *d = irq_get_irq_data(i);
503 if (chip->irq_calc_mask)
504 chip->irq_calc_mask(d);
506 d->mask = 1 << (i - gc->irq_base);
508 irq_set_chip_and_handler(i, chip, ct->handler);
509 irq_set_chip_data(i, gc);
510 irq_modify_status(i, clr, set);
512 gc->irq_cnt = i - gc->irq_base;
514 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
517 * irq_setup_alt_chip - Switch to alternative chip
518 * @d: irq_data for this interrupt
519 * @type: Flow type to be initialized
521 * Only to be called from chip->irq_set_type() callbacks.
523 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
525 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
526 struct irq_chip_type *ct = gc->chip_types;
529 for (i = 0; i < gc->num_ct; i++, ct++) {
530 if (ct->type & type) {
532 irq_data_to_desc(d)->handle_irq = ct->handler;
538 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
541 * irq_remove_generic_chip - Remove a chip
542 * @gc: Generic irq chip holding all data
543 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
544 * @clr: IRQ_* bits to clear
545 * @set: IRQ_* bits to set
547 * Remove up to 32 interrupts starting from gc->irq_base.
549 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
550 unsigned int clr, unsigned int set)
552 unsigned int i = gc->irq_base;
554 raw_spin_lock(&gc_lock);
556 raw_spin_unlock(&gc_lock);
558 for (; msk; msk >>= 1, i++) {
562 /* Remove handler first. That will mask the irq line */
563 irq_set_handler(i, NULL);
564 irq_set_chip(i, &no_irq_chip);
565 irq_set_chip_data(i, NULL);
566 irq_modify_status(i, clr, set);
569 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
571 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
576 return irq_get_irq_data(gc->irq_base);
579 * We don't know which of the irqs has been actually
580 * installed. Use the first one.
585 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
586 return virq ? irq_get_irq_data(virq) : NULL;
590 static int irq_gc_suspend(void)
592 struct irq_chip_generic *gc;
594 list_for_each_entry(gc, &gc_list, list) {
595 struct irq_chip_type *ct = gc->chip_types;
597 if (ct->chip.irq_suspend) {
598 struct irq_data *data = irq_gc_get_irq_data(gc);
601 ct->chip.irq_suspend(data);
610 static void irq_gc_resume(void)
612 struct irq_chip_generic *gc;
614 list_for_each_entry(gc, &gc_list, list) {
615 struct irq_chip_type *ct = gc->chip_types;
620 if (ct->chip.irq_resume) {
621 struct irq_data *data = irq_gc_get_irq_data(gc);
624 ct->chip.irq_resume(data);
629 #define irq_gc_suspend NULL
630 #define irq_gc_resume NULL
633 static void irq_gc_shutdown(void)
635 struct irq_chip_generic *gc;
637 list_for_each_entry(gc, &gc_list, list) {
638 struct irq_chip_type *ct = gc->chip_types;
640 if (ct->chip.irq_pm_shutdown) {
641 struct irq_data *data = irq_gc_get_irq_data(gc);
644 ct->chip.irq_pm_shutdown(data);
649 static struct syscore_ops irq_gc_syscore_ops = {
650 .suspend = irq_gc_suspend,
651 .resume = irq_gc_resume,
652 .shutdown = irq_gc_shutdown,
655 static int __init irq_gc_init_ops(void)
657 register_syscore_ops(&irq_gc_syscore_ops);
660 device_initcall(irq_gc_init_ops);