2 * Library implementing the most common irq chip callback functions
4 * Copyright (C) 2011, Thomas Gleixner
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/irqdomain.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/syscore_ops.h>
15 #include "internals.h"
17 static LIST_HEAD(gc_list);
18 static DEFINE_RAW_SPINLOCK(gc_lock);
21 * irq_gc_noop - NOOP function
24 void irq_gc_noop(struct irq_data *d)
29 * irq_gc_mask_disable_reg - Mask chip via disable register
32 * Chip has separate enable/disable registers instead of a single mask
35 void irq_gc_mask_disable_reg(struct irq_data *d)
37 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
38 struct irq_chip_type *ct = irq_data_get_chip_type(d);
42 irq_reg_writel(gc, mask, ct->regs.disable);
43 *ct->mask_cache &= ~mask;
48 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
51 * Chip has a single mask register. Values of this register are cached
52 * and protected by gc->lock
54 void irq_gc_mask_set_bit(struct irq_data *d)
56 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
57 struct irq_chip_type *ct = irq_data_get_chip_type(d);
61 *ct->mask_cache |= mask;
62 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
65 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
68 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
71 * Chip has a single mask register. Values of this register are cached
72 * and protected by gc->lock
74 void irq_gc_mask_clr_bit(struct irq_data *d)
76 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77 struct irq_chip_type *ct = irq_data_get_chip_type(d);
81 *ct->mask_cache &= ~mask;
82 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
85 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
88 * irq_gc_unmask_enable_reg - Unmask chip via enable register
91 * Chip has separate enable/disable registers instead of a single mask
94 void irq_gc_unmask_enable_reg(struct irq_data *d)
96 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
97 struct irq_chip_type *ct = irq_data_get_chip_type(d);
101 irq_reg_writel(gc, mask, ct->regs.enable);
102 *ct->mask_cache |= mask;
107 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
110 void irq_gc_ack_set_bit(struct irq_data *d)
112 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
113 struct irq_chip_type *ct = irq_data_get_chip_type(d);
117 irq_reg_writel(gc, mask, ct->regs.ack);
120 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
123 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
126 void irq_gc_ack_clr_bit(struct irq_data *d)
128 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
129 struct irq_chip_type *ct = irq_data_get_chip_type(d);
133 irq_reg_writel(gc, mask, ct->regs.ack);
138 * irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
141 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
143 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
144 struct irq_chip_type *ct = irq_data_get_chip_type(d);
148 irq_reg_writel(gc, mask, ct->regs.mask);
149 irq_reg_writel(gc, mask, ct->regs.ack);
154 * irq_gc_eoi - EOI interrupt
157 void irq_gc_eoi(struct irq_data *d)
159 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
160 struct irq_chip_type *ct = irq_data_get_chip_type(d);
164 irq_reg_writel(gc, mask, ct->regs.eoi);
169 * irq_gc_set_wake - Set/clr wake bit for an interrupt
171 * @on: Indicates whether the wake bit should be set or cleared
173 * For chips where the wake from suspend functionality is not
174 * configured in a separate register and the wakeup active state is
175 * just stored in a bitmask.
177 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
179 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
182 if (!(mask & gc->wake_enabled))
187 gc->wake_active |= mask;
189 gc->wake_active &= ~mask;
194 static u32 irq_readl_be(void __iomem *addr)
196 return ioread32be(addr);
199 static void irq_writel_be(u32 val, void __iomem *addr)
201 iowrite32be(val, addr);
205 irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
206 int num_ct, unsigned int irq_base,
207 void __iomem *reg_base, irq_flow_handler_t handler)
209 raw_spin_lock_init(&gc->lock);
211 gc->irq_base = irq_base;
212 gc->reg_base = reg_base;
213 gc->chip_types->chip.name = name;
214 gc->chip_types->handler = handler;
218 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
219 * @name: Name of the irq chip
220 * @num_ct: Number of irq_chip_type instances associated with this
221 * @irq_base: Interrupt base nr for this chip
222 * @reg_base: Register base address (virtual)
223 * @handler: Default flow handler associated with this chip
225 * Returns an initialized irq_chip_generic structure. The chip defaults
226 * to the primary (index 0) irq_chip_type and @handler
228 struct irq_chip_generic *
229 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
230 void __iomem *reg_base, irq_flow_handler_t handler)
232 struct irq_chip_generic *gc;
233 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
235 gc = kzalloc(sz, GFP_KERNEL);
237 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
242 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
245 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
247 struct irq_chip_type *ct = gc->chip_types;
248 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
251 for (i = 0; i < gc->num_ct; i++) {
252 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
253 mskptr = &ct[i].mask_cache_priv;
254 mskreg = ct[i].regs.mask;
256 ct[i].mask_cache = mskptr;
257 if (flags & IRQ_GC_INIT_MASK_CACHE)
258 *mskptr = irq_reg_readl(gc, mskreg);
263 * __irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
264 * @d: irq domain for which to allocate chips
265 * @irqs_per_chip: Number of interrupts each chip handles (max 32)
266 * @num_ct: Number of irq_chip_type instances associated with this
267 * @name: Name of the irq chip
268 * @handler: Default flow handler associated with these chips
269 * @clr: IRQ_* bits to clear in the mapping function
270 * @set: IRQ_* bits to set in the mapping function
271 * @gcflags: Generic chip specific setup flags
273 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
274 int num_ct, const char *name,
275 irq_flow_handler_t handler,
276 unsigned int clr, unsigned int set,
277 enum irq_gc_flags gcflags)
279 struct irq_domain_chip_generic *dgc;
280 struct irq_chip_generic *gc;
288 numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
292 /* Allocate a pointer, generic chip and chiptypes for each chip */
293 sz = sizeof(*dgc) + numchips * sizeof(gc);
294 sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));
296 tmp = dgc = kzalloc(sz, GFP_KERNEL);
299 dgc->irqs_per_chip = irqs_per_chip;
300 dgc->num_chips = numchips;
301 dgc->irq_flags_to_set = set;
302 dgc->irq_flags_to_clear = clr;
303 dgc->gc_flags = gcflags;
306 /* Calc pointer to the first generic chip */
307 tmp += sizeof(*dgc) + numchips * sizeof(gc);
308 for (i = 0; i < numchips; i++) {
309 /* Store the pointer to the generic chip */
310 dgc->gc[i] = gc = tmp;
311 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
315 if (gcflags & IRQ_GC_BE_IO) {
316 gc->reg_readl = &irq_readl_be;
317 gc->reg_writel = &irq_writel_be;
320 raw_spin_lock_irqsave(&gc_lock, flags);
321 list_add_tail(&gc->list, &gc_list);
322 raw_spin_unlock_irqrestore(&gc_lock, flags);
323 /* Calc pointer to the next generic chip */
324 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
329 EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
331 static struct irq_chip_generic *
332 __irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
334 struct irq_domain_chip_generic *dgc = d->gc;
338 return ERR_PTR(-ENODEV);
339 idx = hw_irq / dgc->irqs_per_chip;
340 if (idx >= dgc->num_chips)
341 return ERR_PTR(-EINVAL);
346 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
347 * @d: irq domain pointer
348 * @hw_irq: Hardware interrupt number
350 struct irq_chip_generic *
351 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
353 struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
355 return !IS_ERR(gc) ? gc : NULL;
357 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
360 * Separate lockdep class for interrupt chip which can nest irq_desc
363 static struct lock_class_key irq_nested_lock_class;
366 * irq_map_generic_chip - Map a generic chip for an irq domain
368 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
369 irq_hw_number_t hw_irq)
371 struct irq_data *data = irq_domain_get_irq_data(d, virq);
372 struct irq_domain_chip_generic *dgc = d->gc;
373 struct irq_chip_generic *gc;
374 struct irq_chip_type *ct;
375 struct irq_chip *chip;
379 gc = __irq_get_domain_generic_chip(d, hw_irq);
383 idx = hw_irq % dgc->irqs_per_chip;
385 if (test_bit(idx, &gc->unused))
388 if (test_bit(idx, &gc->installed))
394 /* We only init the cache for the first mapping of a generic chip */
395 if (!gc->installed) {
396 raw_spin_lock_irqsave(&gc->lock, flags);
397 irq_gc_init_mask_cache(gc, dgc->gc_flags);
398 raw_spin_unlock_irqrestore(&gc->lock, flags);
401 /* Mark the interrupt as installed */
402 set_bit(idx, &gc->installed);
404 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
405 irq_set_lockdep_class(virq, &irq_nested_lock_class);
407 if (chip->irq_calc_mask)
408 chip->irq_calc_mask(data);
410 data->mask = 1 << idx;
412 irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
413 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
417 static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
419 struct irq_data *data = irq_domain_get_irq_data(d, virq);
420 struct irq_domain_chip_generic *dgc = d->gc;
421 unsigned int hw_irq = data->hwirq;
422 struct irq_chip_generic *gc;
425 gc = irq_get_domain_generic_chip(d, hw_irq);
429 irq_idx = hw_irq % dgc->irqs_per_chip;
431 clear_bit(irq_idx, &gc->installed);
432 irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
437 struct irq_domain_ops irq_generic_chip_ops = {
438 .map = irq_map_generic_chip,
439 .unmap = irq_unmap_generic_chip,
440 .xlate = irq_domain_xlate_onetwocell,
442 EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
445 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
446 * @gc: Generic irq chip holding all data
447 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
448 * @flags: Flags for initialization
449 * @clr: IRQ_* bits to clear
450 * @set: IRQ_* bits to set
452 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
453 * initializes all interrupts to the primary irq_chip_type and its
454 * associated handler.
456 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
457 enum irq_gc_flags flags, unsigned int clr,
460 struct irq_chip_type *ct = gc->chip_types;
461 struct irq_chip *chip = &ct->chip;
464 raw_spin_lock(&gc_lock);
465 list_add_tail(&gc->list, &gc_list);
466 raw_spin_unlock(&gc_lock);
468 irq_gc_init_mask_cache(gc, flags);
470 for (i = gc->irq_base; msk; msk >>= 1, i++) {
474 if (flags & IRQ_GC_INIT_NESTED_LOCK)
475 irq_set_lockdep_class(i, &irq_nested_lock_class);
477 if (!(flags & IRQ_GC_NO_MASK)) {
478 struct irq_data *d = irq_get_irq_data(i);
480 if (chip->irq_calc_mask)
481 chip->irq_calc_mask(d);
483 d->mask = 1 << (i - gc->irq_base);
485 irq_set_chip_and_handler(i, chip, ct->handler);
486 irq_set_chip_data(i, gc);
487 irq_modify_status(i, clr, set);
489 gc->irq_cnt = i - gc->irq_base;
491 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
494 * irq_setup_alt_chip - Switch to alternative chip
495 * @d: irq_data for this interrupt
496 * @type: Flow type to be initialized
498 * Only to be called from chip->irq_set_type() callbacks.
500 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
502 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
503 struct irq_chip_type *ct = gc->chip_types;
506 for (i = 0; i < gc->num_ct; i++, ct++) {
507 if (ct->type & type) {
509 irq_data_to_desc(d)->handle_irq = ct->handler;
515 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
518 * irq_remove_generic_chip - Remove a chip
519 * @gc: Generic irq chip holding all data
520 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
521 * @clr: IRQ_* bits to clear
522 * @set: IRQ_* bits to set
524 * Remove up to 32 interrupts starting from gc->irq_base.
526 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
527 unsigned int clr, unsigned int set)
529 unsigned int i = gc->irq_base;
531 raw_spin_lock(&gc_lock);
533 raw_spin_unlock(&gc_lock);
535 for (; msk; msk >>= 1, i++) {
539 /* Remove handler first. That will mask the irq line */
540 irq_set_handler(i, NULL);
541 irq_set_chip(i, &no_irq_chip);
542 irq_set_chip_data(i, NULL);
543 irq_modify_status(i, clr, set);
546 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
548 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
553 return irq_get_irq_data(gc->irq_base);
556 * We don't know which of the irqs has been actually
557 * installed. Use the first one.
562 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
563 return virq ? irq_get_irq_data(virq) : NULL;
567 static int irq_gc_suspend(void)
569 struct irq_chip_generic *gc;
571 list_for_each_entry(gc, &gc_list, list) {
572 struct irq_chip_type *ct = gc->chip_types;
574 if (ct->chip.irq_suspend) {
575 struct irq_data *data = irq_gc_get_irq_data(gc);
578 ct->chip.irq_suspend(data);
587 static void irq_gc_resume(void)
589 struct irq_chip_generic *gc;
591 list_for_each_entry(gc, &gc_list, list) {
592 struct irq_chip_type *ct = gc->chip_types;
597 if (ct->chip.irq_resume) {
598 struct irq_data *data = irq_gc_get_irq_data(gc);
601 ct->chip.irq_resume(data);
606 #define irq_gc_suspend NULL
607 #define irq_gc_resume NULL
610 static void irq_gc_shutdown(void)
612 struct irq_chip_generic *gc;
614 list_for_each_entry(gc, &gc_list, list) {
615 struct irq_chip_type *ct = gc->chip_types;
617 if (ct->chip.irq_pm_shutdown) {
618 struct irq_data *data = irq_gc_get_irq_data(gc);
621 ct->chip.irq_pm_shutdown(data);
626 static struct syscore_ops irq_gc_syscore_ops = {
627 .suspend = irq_gc_suspend,
628 .resume = irq_gc_resume,
629 .shutdown = irq_gc_shutdown,
632 static int __init irq_gc_init_ops(void)
634 register_syscore_ops(&irq_gc_syscore_ops);
637 device_initcall(irq_gc_init_ops);