2 * Library implementing the most common irq chip callback functions
4 * Copyright (C) 2011, Thomas Gleixner
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/irqdomain.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/syscore_ops.h>
15 #include "internals.h"
17 static LIST_HEAD(gc_list);
18 static DEFINE_RAW_SPINLOCK(gc_lock);
21 * irq_gc_noop - NOOP function
24 void irq_gc_noop(struct irq_data *d)
29 * irq_gc_mask_disable_reg - Mask chip via disable register
32 * Chip has separate enable/disable registers instead of a single mask
35 void irq_gc_mask_disable_reg(struct irq_data *d)
37 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
38 struct irq_chip_type *ct = irq_data_get_chip_type(d);
42 irq_reg_writel(gc, mask, ct->regs.disable);
43 *ct->mask_cache &= ~mask;
48 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
51 * Chip has a single mask register. Values of this register are cached
52 * and protected by gc->lock
54 void irq_gc_mask_set_bit(struct irq_data *d)
56 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
57 struct irq_chip_type *ct = irq_data_get_chip_type(d);
61 *ct->mask_cache |= mask;
62 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
65 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
68 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
71 * Chip has a single mask register. Values of this register are cached
72 * and protected by gc->lock
74 void irq_gc_mask_clr_bit(struct irq_data *d)
76 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77 struct irq_chip_type *ct = irq_data_get_chip_type(d);
81 *ct->mask_cache &= ~mask;
82 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
85 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
88 * irq_gc_unmask_enable_reg - Unmask chip via enable register
91 * Chip has separate enable/disable registers instead of a single mask
94 void irq_gc_unmask_enable_reg(struct irq_data *d)
96 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
97 struct irq_chip_type *ct = irq_data_get_chip_type(d);
101 irq_reg_writel(gc, mask, ct->regs.enable);
102 *ct->mask_cache |= mask;
107 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
110 void irq_gc_ack_set_bit(struct irq_data *d)
112 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
113 struct irq_chip_type *ct = irq_data_get_chip_type(d);
117 irq_reg_writel(gc, mask, ct->regs.ack);
120 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
123 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
126 void irq_gc_ack_clr_bit(struct irq_data *d)
128 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
129 struct irq_chip_type *ct = irq_data_get_chip_type(d);
133 irq_reg_writel(gc, mask, ct->regs.ack);
138 * irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
141 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
143 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
144 struct irq_chip_type *ct = irq_data_get_chip_type(d);
148 irq_reg_writel(gc, mask, ct->regs.mask);
149 irq_reg_writel(gc, mask, ct->regs.ack);
154 * irq_gc_eoi - EOI interrupt
157 void irq_gc_eoi(struct irq_data *d)
159 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
160 struct irq_chip_type *ct = irq_data_get_chip_type(d);
164 irq_reg_writel(gc, mask, ct->regs.eoi);
169 * irq_gc_set_wake - Set/clr wake bit for an interrupt
171 * @on: Indicates whether the wake bit should be set or cleared
173 * For chips where the wake from suspend functionality is not
174 * configured in a separate register and the wakeup active state is
175 * just stored in a bitmask.
177 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
179 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
182 if (!(mask & gc->wake_enabled))
187 gc->wake_active |= mask;
189 gc->wake_active &= ~mask;
194 static u32 irq_readl_be(void __iomem *addr)
196 return ioread32be(addr);
199 static void irq_writel_be(u32 val, void __iomem *addr)
201 iowrite32be(val, addr);
204 void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
205 int num_ct, unsigned int irq_base,
206 void __iomem *reg_base, irq_flow_handler_t handler)
208 raw_spin_lock_init(&gc->lock);
210 gc->irq_base = irq_base;
211 gc->reg_base = reg_base;
212 gc->chip_types->chip.name = name;
213 gc->chip_types->handler = handler;
217 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
218 * @name: Name of the irq chip
219 * @num_ct: Number of irq_chip_type instances associated with this
220 * @irq_base: Interrupt base nr for this chip
221 * @reg_base: Register base address (virtual)
222 * @handler: Default flow handler associated with this chip
224 * Returns an initialized irq_chip_generic structure. The chip defaults
225 * to the primary (index 0) irq_chip_type and @handler
227 struct irq_chip_generic *
228 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
229 void __iomem *reg_base, irq_flow_handler_t handler)
231 struct irq_chip_generic *gc;
232 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
234 gc = kzalloc(sz, GFP_KERNEL);
236 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
241 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
244 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
246 struct irq_chip_type *ct = gc->chip_types;
247 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
250 for (i = 0; i < gc->num_ct; i++) {
251 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
252 mskptr = &ct[i].mask_cache_priv;
253 mskreg = ct[i].regs.mask;
255 ct[i].mask_cache = mskptr;
256 if (flags & IRQ_GC_INIT_MASK_CACHE)
257 *mskptr = irq_reg_readl(gc, mskreg);
262 * __irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
263 * @d: irq domain for which to allocate chips
264 * @irqs_per_chip: Number of interrupts each chip handles (max 32)
265 * @num_ct: Number of irq_chip_type instances associated with this
266 * @name: Name of the irq chip
267 * @handler: Default flow handler associated with these chips
268 * @clr: IRQ_* bits to clear in the mapping function
269 * @set: IRQ_* bits to set in the mapping function
270 * @gcflags: Generic chip specific setup flags
272 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
273 int num_ct, const char *name,
274 irq_flow_handler_t handler,
275 unsigned int clr, unsigned int set,
276 enum irq_gc_flags gcflags)
278 struct irq_domain_chip_generic *dgc;
279 struct irq_chip_generic *gc;
287 numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
291 /* Allocate a pointer, generic chip and chiptypes for each chip */
292 sz = sizeof(*dgc) + numchips * sizeof(gc);
293 sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));
295 tmp = dgc = kzalloc(sz, GFP_KERNEL);
298 dgc->irqs_per_chip = irqs_per_chip;
299 dgc->num_chips = numchips;
300 dgc->irq_flags_to_set = set;
301 dgc->irq_flags_to_clear = clr;
302 dgc->gc_flags = gcflags;
305 /* Calc pointer to the first generic chip */
306 tmp += sizeof(*dgc) + numchips * sizeof(gc);
307 for (i = 0; i < numchips; i++) {
308 /* Store the pointer to the generic chip */
309 dgc->gc[i] = gc = tmp;
310 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
314 if (gcflags & IRQ_GC_BE_IO) {
315 gc->reg_readl = &irq_readl_be;
316 gc->reg_writel = &irq_writel_be;
319 raw_spin_lock_irqsave(&gc_lock, flags);
320 list_add_tail(&gc->list, &gc_list);
321 raw_spin_unlock_irqrestore(&gc_lock, flags);
322 /* Calc pointer to the next generic chip */
323 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
327 EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
329 static struct irq_chip_generic *
330 __irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
332 struct irq_domain_chip_generic *dgc = d->gc;
336 return ERR_PTR(-ENODEV);
337 idx = hw_irq / dgc->irqs_per_chip;
338 if (idx >= dgc->num_chips)
339 return ERR_PTR(-EINVAL);
344 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
345 * @d: irq domain pointer
346 * @hw_irq: Hardware interrupt number
348 struct irq_chip_generic *
349 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
351 struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
353 return !IS_ERR(gc) ? gc : NULL;
355 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
358 * Separate lockdep class for interrupt chip which can nest irq_desc
361 static struct lock_class_key irq_nested_lock_class;
364 * irq_map_generic_chip - Map a generic chip for an irq domain
366 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
367 irq_hw_number_t hw_irq)
369 struct irq_data *data = irq_domain_get_irq_data(d, virq);
370 struct irq_domain_chip_generic *dgc = d->gc;
371 struct irq_chip_generic *gc;
372 struct irq_chip_type *ct;
373 struct irq_chip *chip;
377 gc = __irq_get_domain_generic_chip(d, hw_irq);
381 idx = hw_irq % dgc->irqs_per_chip;
383 if (test_bit(idx, &gc->unused))
386 if (test_bit(idx, &gc->installed))
392 /* We only init the cache for the first mapping of a generic chip */
393 if (!gc->installed) {
394 raw_spin_lock_irqsave(&gc->lock, flags);
395 irq_gc_init_mask_cache(gc, dgc->gc_flags);
396 raw_spin_unlock_irqrestore(&gc->lock, flags);
399 /* Mark the interrupt as installed */
400 set_bit(idx, &gc->installed);
402 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
403 irq_set_lockdep_class(virq, &irq_nested_lock_class);
405 if (chip->irq_calc_mask)
406 chip->irq_calc_mask(data);
408 data->mask = 1 << idx;
410 irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
411 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
415 static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
417 struct irq_data *data = irq_domain_get_irq_data(d, virq);
418 struct irq_domain_chip_generic *dgc = d->gc;
419 unsigned int hw_irq = data->hwirq;
420 struct irq_chip_generic *gc;
423 gc = irq_get_domain_generic_chip(d, hw_irq);
427 irq_idx = hw_irq % dgc->irqs_per_chip;
429 clear_bit(irq_idx, &gc->installed);
430 irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
435 struct irq_domain_ops irq_generic_chip_ops = {
436 .map = irq_map_generic_chip,
437 .unmap = irq_unmap_generic_chip,
438 .xlate = irq_domain_xlate_onetwocell,
440 EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
443 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
444 * @gc: Generic irq chip holding all data
445 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
446 * @flags: Flags for initialization
447 * @clr: IRQ_* bits to clear
448 * @set: IRQ_* bits to set
450 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
451 * initializes all interrupts to the primary irq_chip_type and its
452 * associated handler.
454 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
455 enum irq_gc_flags flags, unsigned int clr,
458 struct irq_chip_type *ct = gc->chip_types;
459 struct irq_chip *chip = &ct->chip;
462 raw_spin_lock(&gc_lock);
463 list_add_tail(&gc->list, &gc_list);
464 raw_spin_unlock(&gc_lock);
466 irq_gc_init_mask_cache(gc, flags);
468 for (i = gc->irq_base; msk; msk >>= 1, i++) {
472 if (flags & IRQ_GC_INIT_NESTED_LOCK)
473 irq_set_lockdep_class(i, &irq_nested_lock_class);
475 if (!(flags & IRQ_GC_NO_MASK)) {
476 struct irq_data *d = irq_get_irq_data(i);
478 if (chip->irq_calc_mask)
479 chip->irq_calc_mask(d);
481 d->mask = 1 << (i - gc->irq_base);
483 irq_set_chip_and_handler(i, chip, ct->handler);
484 irq_set_chip_data(i, gc);
485 irq_modify_status(i, clr, set);
487 gc->irq_cnt = i - gc->irq_base;
489 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
492 * irq_setup_alt_chip - Switch to alternative chip
493 * @d: irq_data for this interrupt
494 * @type: Flow type to be initialized
496 * Only to be called from chip->irq_set_type() callbacks.
498 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
500 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
501 struct irq_chip_type *ct = gc->chip_types;
504 for (i = 0; i < gc->num_ct; i++, ct++) {
505 if (ct->type & type) {
507 irq_data_to_desc(d)->handle_irq = ct->handler;
513 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
516 * irq_remove_generic_chip - Remove a chip
517 * @gc: Generic irq chip holding all data
518 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
519 * @clr: IRQ_* bits to clear
520 * @set: IRQ_* bits to set
522 * Remove up to 32 interrupts starting from gc->irq_base.
524 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
525 unsigned int clr, unsigned int set)
527 unsigned int i = gc->irq_base;
529 raw_spin_lock(&gc_lock);
531 raw_spin_unlock(&gc_lock);
533 for (; msk; msk >>= 1, i++) {
537 /* Remove handler first. That will mask the irq line */
538 irq_set_handler(i, NULL);
539 irq_set_chip(i, &no_irq_chip);
540 irq_set_chip_data(i, NULL);
541 irq_modify_status(i, clr, set);
544 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
546 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
551 return irq_get_irq_data(gc->irq_base);
554 * We don't know which of the irqs has been actually
555 * installed. Use the first one.
560 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
561 return virq ? irq_get_irq_data(virq) : NULL;
565 static int irq_gc_suspend(void)
567 struct irq_chip_generic *gc;
569 list_for_each_entry(gc, &gc_list, list) {
570 struct irq_chip_type *ct = gc->chip_types;
572 if (ct->chip.irq_suspend) {
573 struct irq_data *data = irq_gc_get_irq_data(gc);
576 ct->chip.irq_suspend(data);
585 static void irq_gc_resume(void)
587 struct irq_chip_generic *gc;
589 list_for_each_entry(gc, &gc_list, list) {
590 struct irq_chip_type *ct = gc->chip_types;
595 if (ct->chip.irq_resume) {
596 struct irq_data *data = irq_gc_get_irq_data(gc);
599 ct->chip.irq_resume(data);
604 #define irq_gc_suspend NULL
605 #define irq_gc_resume NULL
608 static void irq_gc_shutdown(void)
610 struct irq_chip_generic *gc;
612 list_for_each_entry(gc, &gc_list, list) {
613 struct irq_chip_type *ct = gc->chip_types;
615 if (ct->chip.irq_pm_shutdown) {
616 struct irq_data *data = irq_gc_get_irq_data(gc);
619 ct->chip.irq_pm_shutdown(data);
624 static struct syscore_ops irq_gc_syscore_ops = {
625 .suspend = irq_gc_suspend,
626 .resume = irq_gc_resume,
627 .shutdown = irq_gc_shutdown,
630 static int __init irq_gc_init_ops(void)
632 register_syscore_ops(&irq_gc_syscore_ops);
635 device_initcall(irq_gc_init_ops);