1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Christoph Hellwig.
5 * DMA operations that map physical memory directly without using an IOMMU.
7 #include <linux/memblock.h> /* for max_pfn */
8 #include <linux/export.h>
10 #include <linux/dma-direct.h>
11 #include <linux/scatterlist.h>
12 #include <linux/dma-contiguous.h>
13 #include <linux/dma-noncoherent.h>
14 #include <linux/pfn.h>
15 #include <linux/set_memory.h>
16 #include <linux/swiotlb.h>
19 * Most architectures use ZONE_DMA for the first 16 Megabytes, but
20 * some use it for entirely different regions:
22 #ifndef ARCH_ZONE_DMA_BITS
23 #define ARCH_ZONE_DMA_BITS 24
27 * For AMD SEV all DMA must be to unencrypted addresses.
29 static inline bool force_dma_unencrypted(void)
34 static void report_addr(struct device *dev, dma_addr_t dma_addr, size_t size)
37 dev_err_once(dev, "DMA map on device without dma_mask\n");
38 } else if (*dev->dma_mask >= DMA_BIT_MASK(32) || dev->bus_dma_mask) {
40 "overflow %pad+%zu of DMA mask %llx bus mask %llx\n",
41 &dma_addr, size, *dev->dma_mask, dev->bus_dma_mask);
46 static inline dma_addr_t phys_to_dma_direct(struct device *dev,
49 if (force_dma_unencrypted())
50 return __phys_to_dma(dev, phys);
51 return phys_to_dma(dev, phys);
54 u64 dma_direct_get_required_mask(struct device *dev)
56 u64 max_dma = phys_to_dma_direct(dev, (max_pfn - 1) << PAGE_SHIFT);
58 if (dev->bus_dma_mask && dev->bus_dma_mask < max_dma)
59 max_dma = dev->bus_dma_mask;
61 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
64 static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
67 if (dev->bus_dma_mask && dev->bus_dma_mask < dma_mask)
68 dma_mask = dev->bus_dma_mask;
70 if (force_dma_unencrypted())
71 *phys_mask = __dma_to_phys(dev, dma_mask);
73 *phys_mask = dma_to_phys(dev, dma_mask);
76 * Optimistically try the zone that the physical address mask falls
77 * into first. If that returns memory that isn't actually addressable
78 * we will fallback to the next lower zone and try again.
80 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
83 if (*phys_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
85 if (*phys_mask <= DMA_BIT_MASK(32))
90 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
92 return phys_to_dma_direct(dev, phys) + size - 1 <=
93 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_mask);
96 struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
97 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
99 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
100 int page_order = get_order(size);
101 struct page *page = NULL;
104 if (attrs & DMA_ATTR_NO_WARN)
107 /* we always manually zero the memory once we are done: */
109 gfp |= __dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
112 /* CMA can be used only in the context which permits sleeping */
113 if (gfpflags_allow_blocking(gfp)) {
114 page = dma_alloc_from_contiguous(dev, count, page_order,
116 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
117 dma_release_from_contiguous(dev, page, count);
122 page = alloc_pages_node(dev_to_node(dev), gfp, page_order);
124 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
125 __free_pages(page, page_order);
128 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
129 phys_mask < DMA_BIT_MASK(64) &&
130 !(gfp & (GFP_DMA32 | GFP_DMA))) {
135 if (IS_ENABLED(CONFIG_ZONE_DMA) &&
136 phys_mask < DMA_BIT_MASK(32) && !(gfp & GFP_DMA)) {
137 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
145 void *dma_direct_alloc_pages(struct device *dev, size_t size,
146 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
151 page = __dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
155 if (PageHighMem(page)) {
157 * Depending on the cma= arguments and per-arch setup
158 * dma_alloc_from_contiguous could return highmem pages.
159 * Without remapping there is no way to return them here,
160 * so log an error and fail.
162 dev_info(dev, "Rejecting highmem page from CMA.\n");
163 __dma_direct_free_pages(dev, size, page);
167 ret = page_address(page);
168 if (force_dma_unencrypted()) {
169 set_memory_decrypted((unsigned long)ret, 1 << get_order(size));
170 *dma_handle = __phys_to_dma(dev, page_to_phys(page));
172 *dma_handle = phys_to_dma(dev, page_to_phys(page));
174 memset(ret, 0, size);
178 void __dma_direct_free_pages(struct device *dev, size_t size, struct page *page)
180 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
182 if (!dma_release_from_contiguous(dev, page, count))
183 __free_pages(page, get_order(size));
186 void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr,
187 dma_addr_t dma_addr, unsigned long attrs)
189 unsigned int page_order = get_order(size);
191 if (force_dma_unencrypted())
192 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
193 __dma_direct_free_pages(dev, size, virt_to_page(cpu_addr));
196 void *dma_direct_alloc(struct device *dev, size_t size,
197 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
199 if (!dev_is_dma_coherent(dev))
200 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
201 return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
204 void dma_direct_free(struct device *dev, size_t size,
205 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
207 if (!dev_is_dma_coherent(dev))
208 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
210 dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs);
213 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
214 defined(CONFIG_SWIOTLB)
215 void dma_direct_sync_single_for_device(struct device *dev,
216 dma_addr_t addr, size_t size, enum dma_data_direction dir)
218 phys_addr_t paddr = dma_to_phys(dev, addr);
220 if (unlikely(is_swiotlb_buffer(paddr)))
221 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_DEVICE);
223 if (!dev_is_dma_coherent(dev))
224 arch_sync_dma_for_device(dev, paddr, size, dir);
226 EXPORT_SYMBOL(dma_direct_sync_single_for_device);
228 void dma_direct_sync_sg_for_device(struct device *dev,
229 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
231 struct scatterlist *sg;
234 for_each_sg(sgl, sg, nents, i) {
235 if (unlikely(is_swiotlb_buffer(sg_phys(sg))))
236 swiotlb_tbl_sync_single(dev, sg_phys(sg), sg->length,
237 dir, SYNC_FOR_DEVICE);
239 if (!dev_is_dma_coherent(dev))
240 arch_sync_dma_for_device(dev, sg_phys(sg), sg->length,
244 EXPORT_SYMBOL(dma_direct_sync_sg_for_device);
247 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
248 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
249 defined(CONFIG_SWIOTLB)
250 void dma_direct_sync_single_for_cpu(struct device *dev,
251 dma_addr_t addr, size_t size, enum dma_data_direction dir)
253 phys_addr_t paddr = dma_to_phys(dev, addr);
255 if (!dev_is_dma_coherent(dev)) {
256 arch_sync_dma_for_cpu(dev, paddr, size, dir);
257 arch_sync_dma_for_cpu_all(dev);
260 if (unlikely(is_swiotlb_buffer(paddr)))
261 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_CPU);
263 EXPORT_SYMBOL(dma_direct_sync_single_for_cpu);
265 void dma_direct_sync_sg_for_cpu(struct device *dev,
266 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
268 struct scatterlist *sg;
271 for_each_sg(sgl, sg, nents, i) {
272 if (!dev_is_dma_coherent(dev))
273 arch_sync_dma_for_cpu(dev, sg_phys(sg), sg->length, dir);
275 if (unlikely(is_swiotlb_buffer(sg_phys(sg))))
276 swiotlb_tbl_sync_single(dev, sg_phys(sg), sg->length, dir,
280 if (!dev_is_dma_coherent(dev))
281 arch_sync_dma_for_cpu_all(dev);
283 EXPORT_SYMBOL(dma_direct_sync_sg_for_cpu);
285 void dma_direct_unmap_page(struct device *dev, dma_addr_t addr,
286 size_t size, enum dma_data_direction dir, unsigned long attrs)
288 phys_addr_t phys = dma_to_phys(dev, addr);
290 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
291 dma_direct_sync_single_for_cpu(dev, addr, size, dir);
293 if (unlikely(is_swiotlb_buffer(phys)))
294 swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
296 EXPORT_SYMBOL(dma_direct_unmap_page);
298 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
299 int nents, enum dma_data_direction dir, unsigned long attrs)
301 struct scatterlist *sg;
304 for_each_sg(sgl, sg, nents, i)
305 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
308 EXPORT_SYMBOL(dma_direct_unmap_sg);
311 static inline bool dma_direct_possible(struct device *dev, dma_addr_t dma_addr,
314 return swiotlb_force != SWIOTLB_FORCE &&
315 (!dev || dma_capable(dev, dma_addr, size));
318 dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
319 unsigned long offset, size_t size, enum dma_data_direction dir,
322 phys_addr_t phys = page_to_phys(page) + offset;
323 dma_addr_t dma_addr = phys_to_dma(dev, phys);
325 if (unlikely(!dma_direct_possible(dev, dma_addr, size)) &&
326 !swiotlb_map(dev, &phys, &dma_addr, size, dir, attrs)) {
327 report_addr(dev, dma_addr, size);
328 return DMA_MAPPING_ERROR;
331 if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
332 arch_sync_dma_for_device(dev, phys, size, dir);
335 EXPORT_SYMBOL(dma_direct_map_page);
337 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
338 enum dma_data_direction dir, unsigned long attrs)
341 struct scatterlist *sg;
343 for_each_sg(sgl, sg, nents, i) {
344 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
345 sg->offset, sg->length, dir, attrs);
346 if (sg->dma_address == DMA_MAPPING_ERROR)
348 sg_dma_len(sg) = sg->length;
354 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
357 EXPORT_SYMBOL(dma_direct_map_sg);
360 * Because 32-bit DMA masks are so common we expect every architecture to be
361 * able to satisfy them - either by not supporting more physical memory, or by
362 * providing a ZONE_DMA32. If neither is the case, the architecture needs to
363 * use an IOMMU instead of the direct mapping.
365 int dma_direct_supported(struct device *dev, u64 mask)
369 if (IS_ENABLED(CONFIG_ZONE_DMA))
370 min_mask = DMA_BIT_MASK(ARCH_ZONE_DMA_BITS);
372 min_mask = DMA_BIT_MASK(32);
374 min_mask = min_t(u64, min_mask, (max_pfn - 1) << PAGE_SHIFT);
376 return mask >= phys_to_dma(dev, min_mask);