1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2020 Christoph Hellwig.
5 * DMA operations that map physical memory directly without using an IOMMU.
7 #include <linux/memblock.h> /* for max_pfn */
8 #include <linux/export.h>
10 #include <linux/dma-map-ops.h>
11 #include <linux/scatterlist.h>
12 #include <linux/pfn.h>
13 #include <linux/vmalloc.h>
14 #include <linux/set_memory.h>
15 #include <linux/slab.h>
19 * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use
20 * it for entirely different regions. In that case the arch code needs to
21 * override the variable below for dma-direct to work properly.
23 unsigned int zone_dma_bits __ro_after_init = 24;
25 static inline dma_addr_t phys_to_dma_direct(struct device *dev,
28 if (force_dma_unencrypted(dev))
29 return phys_to_dma_unencrypted(dev, phys);
30 return phys_to_dma(dev, phys);
33 static inline struct page *dma_direct_to_page(struct device *dev,
36 return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
39 u64 dma_direct_get_required_mask(struct device *dev)
41 phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
42 u64 max_dma = phys_to_dma_direct(dev, phys);
44 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
47 static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
50 u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
53 * Optimistically try the zone that the physical address mask falls
54 * into first. If that returns memory that isn't actually addressable
55 * we will fallback to the next lower zone and try again.
57 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
60 *phys_limit = dma_to_phys(dev, dma_limit);
61 if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
63 if (*phys_limit <= DMA_BIT_MASK(32))
68 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
70 dma_addr_t dma_addr = phys_to_dma_direct(dev, phys);
72 if (dma_addr == DMA_MAPPING_ERROR)
74 return dma_addr + size - 1 <=
75 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
78 static int dma_set_decrypted(struct device *dev, void *vaddr, size_t size)
80 if (!force_dma_unencrypted(dev))
82 return set_memory_decrypted((unsigned long)vaddr, 1 << get_order(size));
85 static int dma_set_encrypted(struct device *dev, void *vaddr, size_t size)
89 if (!force_dma_unencrypted(dev))
91 ret = set_memory_encrypted((unsigned long)vaddr, 1 << get_order(size));
93 pr_warn_ratelimited("leaking DMA memory that can't be re-encrypted\n");
97 static void __dma_direct_free_pages(struct device *dev, struct page *page,
100 if (swiotlb_free(dev, page, size))
102 dma_free_contiguous(dev, page, size);
105 static struct page *dma_direct_alloc_swiotlb(struct device *dev, size_t size)
107 struct page *page = swiotlb_alloc(dev, size);
109 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
110 swiotlb_free(dev, page, size);
117 static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
120 int node = dev_to_node(dev);
121 struct page *page = NULL;
124 WARN_ON_ONCE(!PAGE_ALIGNED(size));
126 if (is_swiotlb_for_alloc(dev))
127 return dma_direct_alloc_swiotlb(dev, size);
129 gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
131 page = dma_alloc_contiguous(dev, size, gfp);
132 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
133 dma_free_contiguous(dev, page, size);
138 page = alloc_pages_node(node, gfp, get_order(size));
139 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
140 dma_free_contiguous(dev, page, size);
143 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
144 phys_limit < DMA_BIT_MASK(64) &&
145 !(gfp & (GFP_DMA32 | GFP_DMA))) {
150 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
151 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
160 * Check if a potentially blocking operations needs to dip into the atomic
161 * pools for the given device/gfp.
163 static bool dma_direct_use_pool(struct device *dev, gfp_t gfp)
165 return !gfpflags_allow_blocking(gfp) && !is_swiotlb_for_alloc(dev);
168 static void *dma_direct_alloc_from_pool(struct device *dev, size_t size,
169 dma_addr_t *dma_handle, gfp_t gfp)
175 if (WARN_ON_ONCE(!IS_ENABLED(CONFIG_DMA_COHERENT_POOL)))
178 gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
180 page = dma_alloc_from_pool(dev, size, &ret, gfp, dma_coherent_ok);
183 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
187 static void *dma_direct_alloc_no_mapping(struct device *dev, size_t size,
188 dma_addr_t *dma_handle, gfp_t gfp)
192 page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
196 /* remove any dirty cache lines on the kernel alias */
197 if (!PageHighMem(page))
198 arch_dma_prep_coherent(page, size);
200 /* return the page pointer as the opaque cookie */
201 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
205 void *dma_direct_alloc(struct device *dev, size_t size,
206 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
208 bool remap = false, set_uncached = false;
212 size = PAGE_ALIGN(size);
213 if (attrs & DMA_ATTR_NO_WARN)
216 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
217 !force_dma_unencrypted(dev) && !is_swiotlb_for_alloc(dev))
218 return dma_direct_alloc_no_mapping(dev, size, dma_handle, gfp);
220 if (!dev_is_dma_coherent(dev)) {
222 * Fallback to the arch handler if it exists. This should
223 * eventually go away.
225 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
226 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
227 !IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
228 !is_swiotlb_for_alloc(dev))
229 return arch_dma_alloc(dev, size, dma_handle, gfp,
233 * If there is a global pool, always allocate from it for
234 * non-coherent devices.
236 if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL))
237 return dma_alloc_from_global_coherent(dev, size,
241 * Otherwise remap if the architecture is asking for it. But
242 * given that remapping memory is a blocking operation we'll
243 * instead have to dip into the atomic pools.
245 remap = IS_ENABLED(CONFIG_DMA_DIRECT_REMAP);
247 if (dma_direct_use_pool(dev, gfp))
248 return dma_direct_alloc_from_pool(dev, size,
251 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED))
258 * Decrypting memory may block, so allocate the memory from the atomic
259 * pools if we can't block.
261 if (force_dma_unencrypted(dev) && dma_direct_use_pool(dev, gfp))
262 return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
264 /* we always manually zero the memory once we are done */
265 page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
268 if (PageHighMem(page)) {
270 * Depending on the cma= arguments and per-arch setup,
271 * dma_alloc_contiguous could return highmem pages.
272 * Without remapping there is no way to return them here, so
273 * log an error and fail.
275 if (!IS_ENABLED(CONFIG_DMA_REMAP)) {
276 dev_info(dev, "Rejecting highmem page from CMA.\n");
280 set_uncached = false;
284 /* remove any dirty cache lines on the kernel alias */
285 arch_dma_prep_coherent(page, size);
287 /* create a coherent mapping */
288 ret = dma_common_contiguous_remap(page, size,
289 dma_pgprot(dev, PAGE_KERNEL, attrs),
290 __builtin_return_address(0));
294 ret = page_address(page);
295 if (dma_set_decrypted(dev, ret, size))
299 memset(ret, 0, size);
302 arch_dma_prep_coherent(page, size);
303 ret = arch_dma_set_uncached(ret, size);
305 goto out_encrypt_pages;
308 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
312 if (dma_set_encrypted(dev, page_address(page), size))
315 __dma_direct_free_pages(dev, page, size);
319 void dma_direct_free(struct device *dev, size_t size,
320 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
322 unsigned int page_order = get_order(size);
324 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
325 !force_dma_unencrypted(dev) && !is_swiotlb_for_alloc(dev)) {
326 /* cpu_addr is a struct page cookie, not a kernel address */
327 dma_free_contiguous(dev, cpu_addr, size);
331 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
332 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
333 !IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
334 !dev_is_dma_coherent(dev) &&
335 !is_swiotlb_for_alloc(dev)) {
336 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
340 if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
341 !dev_is_dma_coherent(dev)) {
342 if (!dma_release_from_global_coherent(page_order, cpu_addr))
347 /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
348 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
349 dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
352 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
355 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
356 arch_dma_clear_uncached(cpu_addr, size);
357 if (dma_set_encrypted(dev, cpu_addr, 1 << page_order))
361 __dma_direct_free_pages(dev, dma_direct_to_page(dev, dma_addr), size);
364 struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
365 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
370 if (force_dma_unencrypted(dev) && dma_direct_use_pool(dev, gfp))
371 return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
373 page = __dma_direct_alloc_pages(dev, size, gfp);
376 if (PageHighMem(page)) {
378 * Depending on the cma= arguments and per-arch setup
379 * dma_alloc_contiguous could return highmem pages.
380 * Without remapping there is no way to return them here,
381 * so log an error and fail.
383 dev_info(dev, "Rejecting highmem page from CMA.\n");
387 ret = page_address(page);
388 if (dma_set_decrypted(dev, ret, size))
390 memset(ret, 0, size);
391 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
394 __dma_direct_free_pages(dev, page, size);
398 void dma_direct_free_pages(struct device *dev, size_t size,
399 struct page *page, dma_addr_t dma_addr,
400 enum dma_data_direction dir)
402 unsigned int page_order = get_order(size);
403 void *vaddr = page_address(page);
405 /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
406 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
407 dma_free_from_pool(dev, vaddr, size))
410 if (dma_set_encrypted(dev, vaddr, 1 << page_order))
412 __dma_direct_free_pages(dev, page, size);
415 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
416 defined(CONFIG_SWIOTLB)
417 void dma_direct_sync_sg_for_device(struct device *dev,
418 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
420 struct scatterlist *sg;
423 for_each_sg(sgl, sg, nents, i) {
424 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
426 if (unlikely(is_swiotlb_buffer(dev, paddr)))
427 swiotlb_sync_single_for_device(dev, paddr, sg->length,
430 if (!dev_is_dma_coherent(dev))
431 arch_sync_dma_for_device(paddr, sg->length,
437 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
438 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
439 defined(CONFIG_SWIOTLB)
440 void dma_direct_sync_sg_for_cpu(struct device *dev,
441 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
443 struct scatterlist *sg;
446 for_each_sg(sgl, sg, nents, i) {
447 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
449 if (!dev_is_dma_coherent(dev))
450 arch_sync_dma_for_cpu(paddr, sg->length, dir);
452 if (unlikely(is_swiotlb_buffer(dev, paddr)))
453 swiotlb_sync_single_for_cpu(dev, paddr, sg->length,
456 if (dir == DMA_FROM_DEVICE)
457 arch_dma_mark_clean(paddr, sg->length);
460 if (!dev_is_dma_coherent(dev))
461 arch_sync_dma_for_cpu_all();
464 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
465 int nents, enum dma_data_direction dir, unsigned long attrs)
467 struct scatterlist *sg;
470 for_each_sg(sgl, sg, nents, i)
471 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
476 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
477 enum dma_data_direction dir, unsigned long attrs)
480 struct scatterlist *sg;
482 for_each_sg(sgl, sg, nents, i) {
483 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
484 sg->offset, sg->length, dir, attrs);
485 if (sg->dma_address == DMA_MAPPING_ERROR)
487 sg_dma_len(sg) = sg->length;
493 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
497 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
498 size_t size, enum dma_data_direction dir, unsigned long attrs)
500 dma_addr_t dma_addr = paddr;
502 if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
504 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
505 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
507 return DMA_MAPPING_ERROR;
513 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
514 void *cpu_addr, dma_addr_t dma_addr, size_t size,
517 struct page *page = dma_direct_to_page(dev, dma_addr);
520 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
522 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
526 bool dma_direct_can_mmap(struct device *dev)
528 return dev_is_dma_coherent(dev) ||
529 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
532 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
533 void *cpu_addr, dma_addr_t dma_addr, size_t size,
536 unsigned long user_count = vma_pages(vma);
537 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
538 unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
541 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
543 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
545 if (dma_mmap_from_global_coherent(vma, cpu_addr, size, &ret))
548 if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
550 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
551 user_count << PAGE_SHIFT, vma->vm_page_prot);
554 int dma_direct_supported(struct device *dev, u64 mask)
556 u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
559 * Because 32-bit DMA masks are so common we expect every architecture
560 * to be able to satisfy them - either by not supporting more physical
561 * memory, or by providing a ZONE_DMA32. If neither is the case, the
562 * architecture needs to use an IOMMU instead of the direct mapping.
564 if (mask >= DMA_BIT_MASK(32))
568 * This check needs to be against the actual bit mask value, so use
569 * phys_to_dma_unencrypted() here so that the SME encryption mask isn't
572 if (IS_ENABLED(CONFIG_ZONE_DMA))
573 min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
574 return mask >= phys_to_dma_unencrypted(dev, min_mask);
577 size_t dma_direct_max_mapping_size(struct device *dev)
579 /* If SWIOTLB is active, use its maximum mapping size */
580 if (is_swiotlb_active(dev) &&
581 (dma_addressing_limited(dev) || is_swiotlb_force_bounce(dev)))
582 return swiotlb_max_mapping_size(dev);
586 bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
588 return !dev_is_dma_coherent(dev) ||
589 is_swiotlb_buffer(dev, dma_to_phys(dev, dma_addr));
593 * dma_direct_set_offset - Assign scalar offset for a single DMA range.
594 * @dev: device pointer; needed to "own" the alloced memory.
595 * @cpu_start: beginning of memory region covered by this offset.
596 * @dma_start: beginning of DMA/PCI region covered by this offset.
597 * @size: size of the region.
599 * This is for the simple case of a uniform offset which cannot
600 * be discovered by "dma-ranges".
602 * It returns -ENOMEM if out of memory, -EINVAL if a map
603 * already exists, 0 otherwise.
605 * Note: any call to this from a driver is a bug. The mapping needs
606 * to be described by the device tree or other firmware interfaces.
608 int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
609 dma_addr_t dma_start, u64 size)
611 struct bus_dma_region *map;
612 u64 offset = (u64)cpu_start - (u64)dma_start;
614 if (dev->dma_range_map) {
615 dev_err(dev, "attempt to add DMA range to existing map\n");
622 map = kcalloc(2, sizeof(*map), GFP_KERNEL);
625 map[0].cpu_start = cpu_start;
626 map[0].dma_start = dma_start;
627 map[0].offset = offset;
629 dev->dma_range_map = map;