2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef MLX5_ABI_USER_H
34 #define MLX5_ABI_USER_H
36 #include <linux/types.h>
39 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
40 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
44 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
48 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
51 /* Increment this value if any changes that break userspace ABI
52 * compatibility are made.
54 #define MLX5_IB_UVERBS_ABI_VERSION 1
56 /* Make sure that all structs defined in this file remain laid out so
57 * that they pack the same way on 32-bit and 64-bit architectures (to
58 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
59 * In particular do not use pointer types -- pass pointers in __u64
63 struct mlx5_ib_alloc_ucontext_req {
64 __u32 total_num_uuars;
65 __u32 num_low_latency_uuars;
68 struct mlx5_ib_alloc_ucontext_req_v2 {
69 __u32 total_num_uuars;
70 __u32 num_low_latency_uuars;
79 enum mlx5_ib_alloc_ucontext_resp_mask {
80 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
83 enum mlx5_user_cmds_supp_uhw {
84 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
85 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
88 struct mlx5_ib_alloc_ucontext_resp {
92 __u32 cache_line_size;
97 __u32 max_srq_recv_wr;
101 __u32 response_length;
105 __u64 hca_core_clock_offset;
108 struct mlx5_ib_alloc_pd_resp {
112 struct mlx5_ib_tso_caps {
113 __u32 max_tso; /* Maximum tso payload size in bytes */
115 /* Corresponding bit will be set if qp type from
116 * 'enum ib_qp_type' is supported, e.g.
117 * supported_qpts |= 1 << IB_QPT_UD
119 __u32 supported_qpts;
122 struct mlx5_ib_rss_caps {
123 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
124 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
128 enum mlx5_ib_cqe_comp_res_format {
129 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
130 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
131 MLX5_IB_CQE_RES_RESERVED = 1 << 2,
134 struct mlx5_ib_cqe_comp_caps {
136 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
139 struct mlx5_packet_pacing_caps {
140 __u32 qp_rate_limit_min;
141 __u32 qp_rate_limit_max; /* In kpbs */
143 /* Corresponding bit will be set if qp type from
144 * 'enum ib_qp_type' is supported, e.g.
145 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
147 __u32 supported_qpts;
151 struct mlx5_ib_query_device_resp {
153 __u32 response_length;
154 struct mlx5_ib_tso_caps tso_caps;
155 struct mlx5_ib_rss_caps rss_caps;
156 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
157 struct mlx5_packet_pacing_caps packet_pacing_caps;
158 __u32 mlx5_ib_support_multi_pkt_send_wqes;
162 struct mlx5_ib_create_cq {
167 __u8 cqe_comp_res_format;
168 __u16 reserved; /* explicit padding (optional on i386) */
171 struct mlx5_ib_create_cq_resp {
176 struct mlx5_ib_resize_cq {
183 struct mlx5_ib_create_srq {
187 __u32 reserved0; /* explicit padding (optional on i386) */
192 struct mlx5_ib_create_srq_resp {
197 struct mlx5_ib_create_qp {
209 /* RX Hash function flags */
210 enum mlx5_rx_hash_function_flags {
211 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
215 * RX Hash flags, these flags allows to set which incoming packet's field should
216 * participates in RX Hash. Each flag represent certain packet's field,
217 * when the flag is set the field that is represented by the flag will
218 * participate in RX Hash calculation.
219 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
220 * and *TCP and *UDP flags can't be enabled together on the same QP.
222 enum mlx5_rx_hash_fields {
223 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
224 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
225 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
226 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
227 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
228 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
229 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
230 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7
233 struct mlx5_ib_create_qp_rss {
234 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
235 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
236 __u8 rx_key_len; /* valid only for Toeplitz */
238 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
243 struct mlx5_ib_create_qp_resp {
247 struct mlx5_ib_alloc_mw {
254 struct mlx5_ib_create_wq {
265 struct mlx5_ib_create_ah_resp {
266 __u32 response_length;
271 struct mlx5_ib_create_wq_resp {
272 __u32 response_length;
276 struct mlx5_ib_create_rwq_ind_tbl_resp {
277 __u32 response_length;
281 struct mlx5_ib_modify_wq {
285 #endif /* MLX5_ABI_USER_H */