2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #ifndef _UAPI_I915_DRM_H_
28 #define _UAPI_I915_DRM_H_
32 #if defined(__cplusplus)
36 /* Please note that modifications to all structs defined here are
37 * subject to backwards-compatibility constraints.
41 * DOC: uevents generated by i915 on it's device node
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the gpu l3 cache. Additional information supplied is ROW,
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
47 * persistent error remap it with the l3 remapping tool supplied in
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
51 * hangcheck. The error detection event is a good indicator of when things
52 * began to go badly. The value supplied with the event is a 1 upon error
53 * detection, and a 0 upon reset completion, signifying no more error
54 * exists. NOTE: Disabling hangcheck or reset via module parameter will
55 * cause the related events to not be seen.
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58 * GPU. The value supplied with the event is always 1. NOTE: Disable
59 * reset via module parameter will cause this event to not be seen.
61 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62 #define I915_ERROR_UEVENT "ERROR"
63 #define I915_RESET_UEVENT "RESET"
66 * struct i915_user_extension - Base class for defining a chain of extensions
68 * Many interfaces need to grow over time. In most cases we can simply
69 * extend the struct and have userspace pass in more data. Another option,
70 * as demonstrated by Vulkan's approach to providing extensions for forward
71 * and backward compatibility, is to use a list of optional structs to
72 * provide those extra details.
74 * The key advantage to using an extension chain is that it allows us to
75 * redefine the interface more easily than an ever growing struct of
76 * increasing complexity, and for large parts of that interface to be
77 * entirely optional. The downside is more pointer chasing; chasing across
78 * the __user boundary with pointers encapsulated inside u64.
84 * struct i915_user_extension ext3 {
85 * .next_extension = 0, // end
88 * struct i915_user_extension ext2 {
89 * .next_extension = (uintptr_t)&ext3,
92 * struct i915_user_extension ext1 {
93 * .next_extension = (uintptr_t)&ext2,
97 * Typically the struct i915_user_extension would be embedded in some uAPI
98 * struct, and in this case we would feed it the head of the chain(i.e ext1),
99 * which would then apply all of the above extensions.
102 struct i915_user_extension {
106 * Pointer to the next struct i915_user_extension, or zero if the end.
108 __u64 next_extension;
110 * @name: Name of the extension.
112 * Note that the name here is just some integer.
114 * Also note that the name space for this is not global for the whole
115 * driver, but rather its scope/meaning is limited to the specific piece
116 * of uAPI which has embedded the struct i915_user_extension.
122 * All undefined bits must be zero.
128 * Reserved for future use; must be zero.
134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
135 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
137 enum i915_mocs_table_index {
139 * Not cached anywhere, coherency between CPU and GPU accesses is
144 * Cacheability and coherency controlled by the kernel automatically
145 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
146 * usage of the surface (used for display scanout or not).
150 * Cached in all GPU caches available on the platform.
151 * Coherency between CPU and GPU accesses to the surface is not
152 * guaranteed without extra synchronization.
158 * Different engines serve different roles, and there may be more than one
159 * engine serving each role. enum drm_i915_gem_engine_class provides a
160 * classification of the role of the engine, which may be used when requesting
161 * operations to be performed on a certain subset of engines, or for providing
162 * information about that group.
164 enum drm_i915_gem_engine_class {
165 I915_ENGINE_CLASS_RENDER = 0,
166 I915_ENGINE_CLASS_COPY = 1,
167 I915_ENGINE_CLASS_VIDEO = 2,
168 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
170 /* should be kept compact */
172 I915_ENGINE_CLASS_INVALID = -1
176 * There may be more than one engine fulfilling any role within the system.
177 * Each engine of a class is given a unique instance number and therefore
178 * any engine can be specified by its class:instance tuplet. APIs that allow
179 * access to any engine in the system will use struct i915_engine_class_instance
180 * for this identification.
182 struct i915_engine_class_instance {
183 __u16 engine_class; /* see enum drm_i915_gem_engine_class */
184 __u16 engine_instance;
185 #define I915_ENGINE_CLASS_INVALID_NONE -1
186 #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
190 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
194 enum drm_i915_pmu_engine_sample {
195 I915_SAMPLE_BUSY = 0,
196 I915_SAMPLE_WAIT = 1,
200 #define I915_PMU_SAMPLE_BITS (4)
201 #define I915_PMU_SAMPLE_MASK (0xf)
202 #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
203 #define I915_PMU_CLASS_SHIFT \
204 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
206 #define __I915_PMU_ENGINE(class, instance, sample) \
207 ((class) << I915_PMU_CLASS_SHIFT | \
208 (instance) << I915_PMU_SAMPLE_BITS | \
211 #define I915_PMU_ENGINE_BUSY(class, instance) \
212 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
214 #define I915_PMU_ENGINE_WAIT(class, instance) \
215 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
217 #define I915_PMU_ENGINE_SEMA(class, instance) \
218 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
220 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
222 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
223 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
224 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
225 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
226 #define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)
228 #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
230 /* Each region is a minimum of 16k, and there are at most 255 of them.
232 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
233 * of chars for next/prev indices */
234 #define I915_LOG_MIN_TEX_REGION_SIZE 14
236 typedef struct _drm_i915_init {
238 I915_INIT_DMA = 0x01,
239 I915_CLEANUP_DMA = 0x02,
240 I915_RESUME_DMA = 0x03
242 unsigned int mmio_offset;
243 int sarea_priv_offset;
244 unsigned int ring_start;
245 unsigned int ring_end;
246 unsigned int ring_size;
247 unsigned int front_offset;
248 unsigned int back_offset;
249 unsigned int depth_offset;
253 unsigned int pitch_bits;
254 unsigned int back_pitch;
255 unsigned int depth_pitch;
257 unsigned int chipset;
260 typedef struct _drm_i915_sarea {
261 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
262 int last_upload; /* last time texture was uploaded */
263 int last_enqueue; /* last time a buffer was enqueued */
264 int last_dispatch; /* age of the most recently dispatched buffer */
265 int ctxOwner; /* last context to upload state */
267 int pf_enabled; /* is pageflipping allowed? */
269 int pf_current_page; /* which buffer is being displayed? */
270 int perf_boxes; /* performance boxes to be displayed */
271 int width, height; /* screen size in pixels */
273 drm_handle_t front_handle;
277 drm_handle_t back_handle;
281 drm_handle_t depth_handle;
285 drm_handle_t tex_handle;
288 int log_tex_granularity;
290 int rotation; /* 0, 90, 180 or 270 */
294 int virtualX, virtualY;
296 unsigned int front_tiled;
297 unsigned int back_tiled;
298 unsigned int depth_tiled;
299 unsigned int rotated_tiled;
300 unsigned int rotated2_tiled;
311 /* fill out some space for old userspace triple buffer */
312 drm_handle_t unused_handle;
313 __u32 unused1, unused2, unused3;
315 /* buffer object handles for static buffers. May change
316 * over the lifetime of the client.
318 __u32 front_bo_handle;
319 __u32 back_bo_handle;
320 __u32 unused_bo_handle;
321 __u32 depth_bo_handle;
325 /* due to userspace building against these headers we need some compat here */
326 #define planeA_x pipeA_x
327 #define planeA_y pipeA_y
328 #define planeA_w pipeA_w
329 #define planeA_h pipeA_h
330 #define planeB_x pipeB_x
331 #define planeB_y pipeB_y
332 #define planeB_w pipeB_w
333 #define planeB_h pipeB_h
335 /* Flags for perf_boxes
337 #define I915_BOX_RING_EMPTY 0x1
338 #define I915_BOX_FLIP 0x2
339 #define I915_BOX_WAIT 0x4
340 #define I915_BOX_TEXTURE_LOAD 0x8
341 #define I915_BOX_LOST_CONTEXT 0x10
344 * i915 specific ioctls.
346 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
347 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
348 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
350 #define DRM_I915_INIT 0x00
351 #define DRM_I915_FLUSH 0x01
352 #define DRM_I915_FLIP 0x02
353 #define DRM_I915_BATCHBUFFER 0x03
354 #define DRM_I915_IRQ_EMIT 0x04
355 #define DRM_I915_IRQ_WAIT 0x05
356 #define DRM_I915_GETPARAM 0x06
357 #define DRM_I915_SETPARAM 0x07
358 #define DRM_I915_ALLOC 0x08
359 #define DRM_I915_FREE 0x09
360 #define DRM_I915_INIT_HEAP 0x0a
361 #define DRM_I915_CMDBUFFER 0x0b
362 #define DRM_I915_DESTROY_HEAP 0x0c
363 #define DRM_I915_SET_VBLANK_PIPE 0x0d
364 #define DRM_I915_GET_VBLANK_PIPE 0x0e
365 #define DRM_I915_VBLANK_SWAP 0x0f
366 #define DRM_I915_HWS_ADDR 0x11
367 #define DRM_I915_GEM_INIT 0x13
368 #define DRM_I915_GEM_EXECBUFFER 0x14
369 #define DRM_I915_GEM_PIN 0x15
370 #define DRM_I915_GEM_UNPIN 0x16
371 #define DRM_I915_GEM_BUSY 0x17
372 #define DRM_I915_GEM_THROTTLE 0x18
373 #define DRM_I915_GEM_ENTERVT 0x19
374 #define DRM_I915_GEM_LEAVEVT 0x1a
375 #define DRM_I915_GEM_CREATE 0x1b
376 #define DRM_I915_GEM_PREAD 0x1c
377 #define DRM_I915_GEM_PWRITE 0x1d
378 #define DRM_I915_GEM_MMAP 0x1e
379 #define DRM_I915_GEM_SET_DOMAIN 0x1f
380 #define DRM_I915_GEM_SW_FINISH 0x20
381 #define DRM_I915_GEM_SET_TILING 0x21
382 #define DRM_I915_GEM_GET_TILING 0x22
383 #define DRM_I915_GEM_GET_APERTURE 0x23
384 #define DRM_I915_GEM_MMAP_GTT 0x24
385 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
386 #define DRM_I915_GEM_MADVISE 0x26
387 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
388 #define DRM_I915_OVERLAY_ATTRS 0x28
389 #define DRM_I915_GEM_EXECBUFFER2 0x29
390 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
391 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
392 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
393 #define DRM_I915_GEM_WAIT 0x2c
394 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
395 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
396 #define DRM_I915_GEM_SET_CACHING 0x2f
397 #define DRM_I915_GEM_GET_CACHING 0x30
398 #define DRM_I915_REG_READ 0x31
399 #define DRM_I915_GET_RESET_STATS 0x32
400 #define DRM_I915_GEM_USERPTR 0x33
401 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
402 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
403 #define DRM_I915_PERF_OPEN 0x36
404 #define DRM_I915_PERF_ADD_CONFIG 0x37
405 #define DRM_I915_PERF_REMOVE_CONFIG 0x38
406 #define DRM_I915_QUERY 0x39
407 #define DRM_I915_GEM_VM_CREATE 0x3a
408 #define DRM_I915_GEM_VM_DESTROY 0x3b
409 /* Must be kept compact -- no holes */
411 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
412 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
413 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
414 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
415 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
416 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
417 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
418 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
419 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
420 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
421 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
422 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
423 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
424 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
425 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
426 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
427 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
428 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
429 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
430 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
431 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
432 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
433 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
434 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
435 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
436 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
437 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
438 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
439 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
440 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
441 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
442 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
443 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
444 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
445 #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)
446 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
447 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
448 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
449 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
450 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
451 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
452 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
453 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
454 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
455 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
456 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
457 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
458 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
459 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
460 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
461 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
462 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
463 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
464 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
465 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
466 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
467 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
468 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
469 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
470 #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
471 #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
473 /* Allow drivers to submit batchbuffers directly to hardware, relying
474 * on the security mechanisms provided by hardware.
476 typedef struct drm_i915_batchbuffer {
477 int start; /* agp offset */
478 int used; /* nr bytes in use */
479 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
480 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
481 int num_cliprects; /* mulitpass with multiple cliprects? */
482 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
483 } drm_i915_batchbuffer_t;
485 /* As above, but pass a pointer to userspace buffer which can be
486 * validated by the kernel prior to sending to hardware.
488 typedef struct _drm_i915_cmdbuffer {
489 char __user *buf; /* pointer to userspace command buffer */
490 int sz; /* nr bytes in buf */
491 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
492 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
493 int num_cliprects; /* mulitpass with multiple cliprects? */
494 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
495 } drm_i915_cmdbuffer_t;
497 /* Userspace can request & wait on irq's:
499 typedef struct drm_i915_irq_emit {
501 } drm_i915_irq_emit_t;
503 typedef struct drm_i915_irq_wait {
505 } drm_i915_irq_wait_t;
508 * Different modes of per-process Graphics Translation Table,
509 * see I915_PARAM_HAS_ALIASING_PPGTT
511 #define I915_GEM_PPGTT_NONE 0
512 #define I915_GEM_PPGTT_ALIASING 1
513 #define I915_GEM_PPGTT_FULL 2
515 /* Ioctl to query kernel params:
517 #define I915_PARAM_IRQ_ACTIVE 1
518 #define I915_PARAM_ALLOW_BATCHBUFFER 2
519 #define I915_PARAM_LAST_DISPATCH 3
520 #define I915_PARAM_CHIPSET_ID 4
521 #define I915_PARAM_HAS_GEM 5
522 #define I915_PARAM_NUM_FENCES_AVAIL 6
523 #define I915_PARAM_HAS_OVERLAY 7
524 #define I915_PARAM_HAS_PAGEFLIPPING 8
525 #define I915_PARAM_HAS_EXECBUF2 9
526 #define I915_PARAM_HAS_BSD 10
527 #define I915_PARAM_HAS_BLT 11
528 #define I915_PARAM_HAS_RELAXED_FENCING 12
529 #define I915_PARAM_HAS_COHERENT_RINGS 13
530 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
531 #define I915_PARAM_HAS_RELAXED_DELTA 15
532 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
533 #define I915_PARAM_HAS_LLC 17
534 #define I915_PARAM_HAS_ALIASING_PPGTT 18
535 #define I915_PARAM_HAS_WAIT_TIMEOUT 19
536 #define I915_PARAM_HAS_SEMAPHORES 20
537 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
538 #define I915_PARAM_HAS_VEBOX 22
539 #define I915_PARAM_HAS_SECURE_BATCHES 23
540 #define I915_PARAM_HAS_PINNED_BATCHES 24
541 #define I915_PARAM_HAS_EXEC_NO_RELOC 25
542 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
543 #define I915_PARAM_HAS_WT 27
544 #define I915_PARAM_CMD_PARSER_VERSION 28
545 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
546 #define I915_PARAM_MMAP_VERSION 30
547 #define I915_PARAM_HAS_BSD2 31
548 #define I915_PARAM_REVISION 32
549 #define I915_PARAM_SUBSLICE_TOTAL 33
550 #define I915_PARAM_EU_TOTAL 34
551 #define I915_PARAM_HAS_GPU_RESET 35
552 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
553 #define I915_PARAM_HAS_EXEC_SOFTPIN 37
554 #define I915_PARAM_HAS_POOLED_EU 38
555 #define I915_PARAM_MIN_EU_IN_POOL 39
556 #define I915_PARAM_MMAP_GTT_VERSION 40
559 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
560 * priorities and the driver will attempt to execute batches in priority order.
561 * The param returns a capability bitmask, nonzero implies that the scheduler
562 * is enabled, with different features present according to the mask.
564 * The initial priority for each batch is supplied by the context and is
565 * controlled via I915_CONTEXT_PARAM_PRIORITY.
567 #define I915_PARAM_HAS_SCHEDULER 41
568 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
569 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
570 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
571 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
572 #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
574 #define I915_PARAM_HUC_STATUS 42
576 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
577 * synchronisation with implicit fencing on individual objects.
578 * See EXEC_OBJECT_ASYNC.
580 #define I915_PARAM_HAS_EXEC_ASYNC 43
582 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
583 * both being able to pass in a sync_file fd to wait upon before executing,
584 * and being able to return a new sync_file fd that is signaled when the
585 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
587 #define I915_PARAM_HAS_EXEC_FENCE 44
589 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
590 * user specified bufffers for post-mortem debugging of GPU hangs. See
591 * EXEC_OBJECT_CAPTURE.
593 #define I915_PARAM_HAS_EXEC_CAPTURE 45
595 #define I915_PARAM_SLICE_MASK 46
597 /* Assuming it's uniform for each slice, this queries the mask of subslices
598 * per-slice for this system.
600 #define I915_PARAM_SUBSLICE_MASK 47
603 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
604 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
606 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
608 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
609 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
611 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
614 * Query whether every context (both per-file default and user created) is
615 * isolated (insofar as HW supports). If this parameter is not true, then
616 * freshly created contexts may inherit values from an existing context,
617 * rather than default HW values. If true, it also ensures (insofar as HW
618 * supports) that all state set by this context will not leak to any other
621 * As not every engine across every gen support contexts, the returned
622 * value reports the support of context isolation for individual engines by
623 * returning a bitmask of each engine class set to true if that class supports
626 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50
628 /* Frequency of the command streamer timestamps given by the *_TIMESTAMP
629 * registers. This used to be fixed per platform but from CNL onwards, this
630 * might vary depending on the parts.
632 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
635 * Once upon a time we supposed that writes through the GGTT would be
636 * immediately in physical memory (once flushed out of the CPU path). However,
637 * on a few different processors and chipsets, this is not necessarily the case
638 * as the writes appear to be buffered internally. Thus a read of the backing
639 * storage (physical memory) via a different path (with different physical tags
640 * to the indirect write via the GGTT) will see stale values from before
641 * the GGTT write. Inside the kernel, we can for the most part keep track of
642 * the different read/write domains in use (e.g. set-domain), but the assumption
643 * of coherency is baked into the ABI, hence reporting its true state in this
646 * Reports true when writes via mmap_gtt are immediately visible following an
647 * lfence to flush the WCB.
649 * Reports false when writes via mmap_gtt are indeterminately delayed in an in
650 * internal buffer and are _not_ immediately visible to third parties accessing
651 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
652 * communications channel when reporting false is strongly disadvised.
654 #define I915_PARAM_MMAP_GTT_COHERENT 52
657 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
658 * execution through use of explicit fence support.
659 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
661 #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
664 * Revision of the i915-perf uAPI. The value returned helps determine what
665 * i915-perf features are available. See drm_i915_perf_property_id.
667 #define I915_PARAM_PERF_REVISION 54
669 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
670 * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See
671 * I915_EXEC_USE_EXTENSIONS.
673 #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
675 /* Must be kept compact -- no holes and well documented */
677 typedef struct drm_i915_getparam {
680 * WARNING: Using pointers instead of fixed-size u64 means we need to write
681 * compat32 code. Don't repeat this mistake.
684 } drm_i915_getparam_t;
686 /* Ioctl to set kernel params:
688 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
689 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
690 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
691 #define I915_SETPARAM_NUM_USED_FENCES 4
692 /* Must be kept compact -- no holes */
694 typedef struct drm_i915_setparam {
697 } drm_i915_setparam_t;
699 /* A memory manager for regions of shared memory:
701 #define I915_MEM_REGION_AGP 1
703 typedef struct drm_i915_mem_alloc {
707 int __user *region_offset; /* offset from start of fb or agp */
708 } drm_i915_mem_alloc_t;
710 typedef struct drm_i915_mem_free {
713 } drm_i915_mem_free_t;
715 typedef struct drm_i915_mem_init_heap {
719 } drm_i915_mem_init_heap_t;
721 /* Allow memory manager to be torn down and re-initialized (eg on
724 typedef struct drm_i915_mem_destroy_heap {
726 } drm_i915_mem_destroy_heap_t;
728 /* Allow X server to configure which pipes to monitor for vblank signals
730 #define DRM_I915_VBLANK_PIPE_A 1
731 #define DRM_I915_VBLANK_PIPE_B 2
733 typedef struct drm_i915_vblank_pipe {
735 } drm_i915_vblank_pipe_t;
737 /* Schedule buffer swap at given vertical blank:
739 typedef struct drm_i915_vblank_swap {
740 drm_drawable_t drawable;
741 enum drm_vblank_seq_type seqtype;
742 unsigned int sequence;
743 } drm_i915_vblank_swap_t;
745 typedef struct drm_i915_hws_addr {
747 } drm_i915_hws_addr_t;
749 struct drm_i915_gem_init {
751 * Beginning offset in the GTT to be managed by the DRM memory
756 * Ending offset in the GTT to be managed by the DRM memory
762 struct drm_i915_gem_create {
764 * Requested size for the object.
766 * The (page-aligned) allocated size for the object will be returned.
770 * Returned handle for the object.
772 * Object handles are nonzero.
778 struct drm_i915_gem_pread {
779 /** Handle for the object being read. */
782 /** Offset into the object to read from */
784 /** Length of data to read */
787 * Pointer to write the data into.
789 * This is a fixed-size type for 32/64 compatibility.
794 struct drm_i915_gem_pwrite {
795 /** Handle for the object being written to. */
798 /** Offset into the object to write to */
800 /** Length of data to write */
803 * Pointer to read the data from.
805 * This is a fixed-size type for 32/64 compatibility.
810 struct drm_i915_gem_mmap {
811 /** Handle for the object being mapped. */
814 /** Offset in the object to map. */
817 * Length of data to map.
819 * The value will be page-aligned.
823 * Returned pointer the data was mapped at.
825 * This is a fixed-size type for 32/64 compatibility.
830 * Flags for extended behaviour.
832 * Added in version 2.
835 #define I915_MMAP_WC 0x1
838 struct drm_i915_gem_mmap_gtt {
839 /** Handle for the object being mapped. */
843 * Fake offset to use for subsequent mmap call
845 * This is a fixed-size type for 32/64 compatibility.
850 struct drm_i915_gem_mmap_offset {
851 /** Handle for the object being mapped. */
855 * Fake offset to use for subsequent mmap call
857 * This is a fixed-size type for 32/64 compatibility.
862 * Flags for extended behaviour.
864 * It is mandatory that one of the MMAP_OFFSET types
865 * (GTT, WC, WB, UC, etc) should be included.
868 #define I915_MMAP_OFFSET_GTT 0
869 #define I915_MMAP_OFFSET_WC 1
870 #define I915_MMAP_OFFSET_WB 2
871 #define I915_MMAP_OFFSET_UC 3
874 * Zero-terminated chain of extensions.
876 * No current extensions defined; mbz.
881 struct drm_i915_gem_set_domain {
882 /** Handle for the object */
885 /** New read domains */
888 /** New write domain */
892 struct drm_i915_gem_sw_finish {
893 /** Handle for the object */
897 struct drm_i915_gem_relocation_entry {
899 * Handle of the buffer being pointed to by this relocation entry.
901 * It's appealing to make this be an index into the mm_validate_entry
902 * list to refer to the buffer, but this allows the driver to create
903 * a relocation list for state buffers and not re-write it per
904 * exec using the buffer.
909 * Value to be added to the offset of the target buffer to make up
910 * the relocation entry.
914 /** Offset in the buffer the relocation entry will be written into */
918 * Offset value of the target buffer that the relocation entry was last
921 * If the buffer has the same offset as last time, we can skip syncing
922 * and writing the relocation. This value is written back out by
923 * the execbuffer ioctl when the relocation is written.
925 __u64 presumed_offset;
928 * Target memory domains read by this operation.
933 * Target memory domains written by this operation.
935 * Note that only one domain may be written by the whole
936 * execbuffer operation, so that where there are conflicts,
937 * the application will get -EINVAL back.
943 * Intel memory domains
945 * Most of these just align with the various caches in
946 * the system and are used to flush and invalidate as
947 * objects end up cached in different domains.
950 #define I915_GEM_DOMAIN_CPU 0x00000001
951 /** Render cache, used by 2D and 3D drawing */
952 #define I915_GEM_DOMAIN_RENDER 0x00000002
953 /** Sampler cache, used by texture engine */
954 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
955 /** Command queue, used to load batch buffers */
956 #define I915_GEM_DOMAIN_COMMAND 0x00000008
957 /** Instruction cache, used by shader programs */
958 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
959 /** Vertex address cache */
960 #define I915_GEM_DOMAIN_VERTEX 0x00000020
961 /** GTT domain - aperture and scanout */
962 #define I915_GEM_DOMAIN_GTT 0x00000040
963 /** WC domain - uncached access */
964 #define I915_GEM_DOMAIN_WC 0x00000080
967 struct drm_i915_gem_exec_object {
969 * User's handle for a buffer to be bound into the GTT for this
974 /** Number of relocations to be performed on this buffer */
975 __u32 relocation_count;
977 * Pointer to array of struct drm_i915_gem_relocation_entry containing
978 * the relocations to be performed in this buffer.
982 /** Required alignment in graphics aperture */
986 * Returned value of the updated offset of the object, for future
987 * presumed_offset writes.
992 /* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */
993 struct drm_i915_gem_execbuffer {
995 * List of buffers to be validated with their relocations to be
996 * performend on them.
998 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
1000 * These buffers must be listed in an order such that all relocations
1001 * a buffer is performing refer to buffers that have already appeared
1002 * in the validate list.
1007 /** Offset in the batchbuffer to start execution from. */
1008 __u32 batch_start_offset;
1009 /** Bytes used in batchbuffer from batch_start_offset */
1013 __u32 num_cliprects;
1014 /** This is a struct drm_clip_rect *cliprects */
1015 __u64 cliprects_ptr;
1018 struct drm_i915_gem_exec_object2 {
1020 * User's handle for a buffer to be bound into the GTT for this
1025 /** Number of relocations to be performed on this buffer */
1026 __u32 relocation_count;
1028 * Pointer to array of struct drm_i915_gem_relocation_entry containing
1029 * the relocations to be performed in this buffer.
1033 /** Required alignment in graphics aperture */
1037 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
1038 * the user with the GTT offset at which this object will be pinned.
1039 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
1040 * presumed_offset of the object.
1041 * During execbuffer2 the kernel populates it with the value of the
1042 * current GTT offset of the object, for future presumed_offset writes.
1046 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
1047 #define EXEC_OBJECT_NEEDS_GTT (1<<1)
1048 #define EXEC_OBJECT_WRITE (1<<2)
1049 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
1050 #define EXEC_OBJECT_PINNED (1<<4)
1051 #define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
1052 /* The kernel implicitly tracks GPU activity on all GEM objects, and
1053 * synchronises operations with outstanding rendering. This includes
1054 * rendering on other devices if exported via dma-buf. However, sometimes
1055 * this tracking is too coarse and the user knows better. For example,
1056 * if the object is split into non-overlapping ranges shared between different
1057 * clients or engines (i.e. suballocating objects), the implicit tracking
1058 * by kernel assumes that each operation affects the whole object rather
1059 * than an individual range, causing needless synchronisation between clients.
1060 * The kernel will also forgo any CPU cache flushes prior to rendering from
1061 * the object as the client is expected to be also handling such domain
1064 * The kernel maintains the implicit tracking in order to manage resources
1065 * used by the GPU - this flag only disables the synchronisation prior to
1066 * rendering with this object in this execbuf.
1068 * Opting out of implicit synhronisation requires the user to do its own
1069 * explicit tracking to avoid rendering corruption. See, for example,
1070 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
1072 #define EXEC_OBJECT_ASYNC (1<<6)
1073 /* Request that the contents of this execobject be copied into the error
1074 * state upon a GPU hang involving this batch for post-mortem debugging.
1075 * These buffers are recorded in no particular order as "user" in
1076 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
1077 * if the kernel supports this flag.
1079 #define EXEC_OBJECT_CAPTURE (1<<7)
1080 /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
1081 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
1091 struct drm_i915_gem_exec_fence {
1093 * User's handle for a drm_syncobj to wait on or signal.
1097 #define I915_EXEC_FENCE_WAIT (1<<0)
1098 #define I915_EXEC_FENCE_SIGNAL (1<<1)
1099 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
1104 * See drm_i915_gem_execbuffer_ext_timeline_fences.
1106 #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
1109 * This structure describes an array of drm_syncobj and associated points for
1110 * timeline variants of drm_syncobj. It is invalid to append this structure to
1111 * the execbuf if I915_EXEC_FENCE_ARRAY is set.
1113 struct drm_i915_gem_execbuffer_ext_timeline_fences {
1114 struct i915_user_extension base;
1117 * Number of element in the handles_ptr & value_ptr arrays.
1122 * Pointer to an array of struct drm_i915_gem_exec_fence of length
1128 * Pointer to an array of u64 values of length fence_count. Values
1129 * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline
1130 * drm_syncobj is invalid as it turns a drm_syncobj into a binary one.
1135 struct drm_i915_gem_execbuffer2 {
1137 * List of gem_exec_object2 structs
1142 /** Offset in the batchbuffer to start execution from. */
1143 __u32 batch_start_offset;
1144 /** Bytes used in batchbuffer from batch_start_offset */
1148 __u32 num_cliprects;
1150 * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
1151 * & I915_EXEC_USE_EXTENSIONS are not set.
1153 * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
1154 * of struct drm_i915_gem_exec_fence and num_cliprects is the length
1157 * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
1158 * single struct i915_user_extension and num_cliprects is 0.
1160 __u64 cliprects_ptr;
1161 #define I915_EXEC_RING_MASK (0x3f)
1162 #define I915_EXEC_DEFAULT (0<<0)
1163 #define I915_EXEC_RENDER (1<<0)
1164 #define I915_EXEC_BSD (2<<0)
1165 #define I915_EXEC_BLT (3<<0)
1166 #define I915_EXEC_VEBOX (4<<0)
1168 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
1169 * Gen6+ only supports relative addressing to dynamic state (default) and
1170 * absolute addressing.
1172 * These flags are ignored for the BSD and BLT rings.
1174 #define I915_EXEC_CONSTANTS_MASK (3<<6)
1175 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
1176 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
1177 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
1179 __u64 rsvd1; /* now used for context info */
1183 /** Resets the SO write offset registers for transform feedback on gen7. */
1184 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
1186 /** Request a privileged ("secure") batch buffer. Note only available for
1187 * DRM_ROOT_ONLY | DRM_MASTER processes.
1189 #define I915_EXEC_SECURE (1<<9)
1191 /** Inform the kernel that the batch is and will always be pinned. This
1192 * negates the requirement for a workaround to be performed to avoid
1193 * an incoherent CS (such as can be found on 830/845). If this flag is
1194 * not passed, the kernel will endeavour to make sure the batch is
1195 * coherent with the CS before execution. If this flag is passed,
1196 * userspace assumes the responsibility for ensuring the same.
1198 #define I915_EXEC_IS_PINNED (1<<10)
1200 /** Provide a hint to the kernel that the command stream and auxiliary
1201 * state buffers already holds the correct presumed addresses and so the
1202 * relocation process may be skipped if no buffers need to be moved in
1203 * preparation for the execbuffer.
1205 #define I915_EXEC_NO_RELOC (1<<11)
1207 /** Use the reloc.handle as an index into the exec object array rather
1208 * than as the per-file handle.
1210 #define I915_EXEC_HANDLE_LUT (1<<12)
1212 /** Used for switching BSD rings on the platforms with two BSD rings */
1213 #define I915_EXEC_BSD_SHIFT (13)
1214 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
1215 /* default ping-pong mode */
1216 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
1217 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
1218 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
1220 /** Tell the kernel that the batchbuffer is processed by
1221 * the resource streamer.
1223 #define I915_EXEC_RESOURCE_STREAMER (1<<15)
1225 /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
1226 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1229 * Returns -EINVAL if the sync_file fd cannot be found.
1231 #define I915_EXEC_FENCE_IN (1<<16)
1233 /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
1234 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
1235 * to the caller, and it should be close() after use. (The fd is a regular
1236 * file descriptor and will be cleaned up on process termination. It holds
1237 * a reference to the request, but nothing else.)
1239 * The sync_file fd can be combined with other sync_file and passed either
1240 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
1241 * will only occur after this request completes), or to other devices.
1243 * Using I915_EXEC_FENCE_OUT requires use of
1244 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
1245 * back to userspace. Failure to do so will cause the out-fence to always
1246 * be reported as zero, and the real fence fd to be leaked.
1248 #define I915_EXEC_FENCE_OUT (1<<17)
1251 * Traditionally the execbuf ioctl has only considered the final element in
1252 * the execobject[] to be the executable batch. Often though, the client
1253 * will known the batch object prior to construction and being able to place
1254 * it into the execobject[] array first can simplify the relocation tracking.
1255 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
1256 * execobject[] as the * batch instead (the default is to use the last
1259 #define I915_EXEC_BATCH_FIRST (1<<18)
1261 /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
1262 * define an array of i915_gem_exec_fence structures which specify a set of
1263 * dma fences to wait upon or signal.
1265 #define I915_EXEC_FENCE_ARRAY (1<<19)
1268 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
1269 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1272 * Returns -EINVAL if the sync_file fd cannot be found.
1274 #define I915_EXEC_FENCE_SUBMIT (1 << 20)
1277 * Setting I915_EXEC_USE_EXTENSIONS implies that
1278 * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
1279 * list of i915_user_extension. Each i915_user_extension node is the base of a
1280 * larger structure. The list of supported structures are listed in the
1281 * drm_i915_gem_execbuffer_ext enum.
1283 #define I915_EXEC_USE_EXTENSIONS (1 << 21)
1285 #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))
1287 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1288 #define i915_execbuffer2_set_context_id(eb2, context) \
1289 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
1290 #define i915_execbuffer2_get_context_id(eb2) \
1291 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
1293 struct drm_i915_gem_pin {
1294 /** Handle of the buffer to be pinned. */
1298 /** alignment required within the aperture */
1301 /** Returned GTT offset of the buffer. */
1305 struct drm_i915_gem_unpin {
1306 /** Handle of the buffer to be unpinned. */
1311 struct drm_i915_gem_busy {
1312 /** Handle of the buffer to check for busy */
1315 /** Return busy status
1317 * A return of 0 implies that the object is idle (after
1318 * having flushed any pending activity), and a non-zero return that
1319 * the object is still in-flight on the GPU. (The GPU has not yet
1320 * signaled completion for all pending requests that reference the
1321 * object.) An object is guaranteed to become idle eventually (so
1322 * long as no new GPU commands are executed upon it). Due to the
1323 * asynchronous nature of the hardware, an object reported
1324 * as busy may become idle before the ioctl is completed.
1326 * Furthermore, if the object is busy, which engine is busy is only
1327 * provided as a guide and only indirectly by reporting its class
1328 * (there may be more than one engine in each class). There are race
1329 * conditions which prevent the report of which engines are busy from
1330 * being always accurate. However, the converse is not true. If the
1331 * object is idle, the result of the ioctl, that all engines are idle,
1334 * The returned dword is split into two fields to indicate both
1335 * the engine classess on which the object is being read, and the
1336 * engine class on which it is currently being written (if any).
1338 * The low word (bits 0:15) indicate if the object is being written
1339 * to by any engine (there can only be one, as the GEM implicit
1340 * synchronisation rules force writes to be serialised). Only the
1341 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1342 * 1 not 0 etc) for the last write is reported.
1344 * The high word (bits 16:31) are a bitmask of which engines classes
1345 * are currently reading from the object. Multiple engines may be
1346 * reading from the object simultaneously.
1348 * The value of each engine class is the same as specified in the
1349 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
1350 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1351 * reported as active itself. Some hardware may have parallel
1352 * execution engines, e.g. multiple media engines, which are
1353 * mapped to the same class identifier and so are not separately
1354 * reported for busyness.
1357 * Only the boolean result of this query is reliable; that is whether
1358 * the object is idle or busy. The report of which engines are busy
1359 * should be only used as a heuristic.
1367 * GPU access is not coherent with cpu caches. Default for machines without an
1370 #define I915_CACHING_NONE 0
1372 * I915_CACHING_CACHED
1374 * GPU access is coherent with cpu caches and furthermore the data is cached in
1375 * last-level caches shared between cpu cores and the gpu GT. Default on
1376 * machines with HAS_LLC.
1378 #define I915_CACHING_CACHED 1
1380 * I915_CACHING_DISPLAY
1382 * Special GPU caching mode which is coherent with the scanout engines.
1383 * Transparently falls back to I915_CACHING_NONE on platforms where no special
1384 * cache mode (like write-through or gfdt flushing) is available. The kernel
1385 * automatically sets this mode when using a buffer as a scanout target.
1386 * Userspace can manually set this mode to avoid a costly stall and clflush in
1387 * the hotpath of drawing the first frame.
1389 #define I915_CACHING_DISPLAY 2
1391 struct drm_i915_gem_caching {
1393 * Handle of the buffer to set/get the caching level of. */
1397 * Cacheing level to apply or return value
1399 * bits0-15 are for generic caching control (i.e. the above defined
1400 * values). bits16-31 are reserved for platform-specific variations
1401 * (e.g. l3$ caching on gen7). */
1405 #define I915_TILING_NONE 0
1406 #define I915_TILING_X 1
1407 #define I915_TILING_Y 2
1408 #define I915_TILING_LAST I915_TILING_Y
1410 #define I915_BIT_6_SWIZZLE_NONE 0
1411 #define I915_BIT_6_SWIZZLE_9 1
1412 #define I915_BIT_6_SWIZZLE_9_10 2
1413 #define I915_BIT_6_SWIZZLE_9_11 3
1414 #define I915_BIT_6_SWIZZLE_9_10_11 4
1415 /* Not seen by userland */
1416 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
1417 /* Seen by userland. */
1418 #define I915_BIT_6_SWIZZLE_9_17 6
1419 #define I915_BIT_6_SWIZZLE_9_10_17 7
1421 struct drm_i915_gem_set_tiling {
1422 /** Handle of the buffer to have its tiling state updated */
1426 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1429 * This value is to be set on request, and will be updated by the
1430 * kernel on successful return with the actual chosen tiling layout.
1432 * The tiling mode may be demoted to I915_TILING_NONE when the system
1433 * has bit 6 swizzling that can't be managed correctly by GEM.
1435 * Buffer contents become undefined when changing tiling_mode.
1440 * Stride in bytes for the object when in I915_TILING_X or
1446 * Returned address bit 6 swizzling required for CPU access through
1452 struct drm_i915_gem_get_tiling {
1453 /** Handle of the buffer to get tiling state for. */
1457 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1463 * Returned address bit 6 swizzling required for CPU access through
1469 * Returned address bit 6 swizzling required for CPU access through
1470 * mmap mapping whilst bound.
1472 __u32 phys_swizzle_mode;
1475 struct drm_i915_gem_get_aperture {
1476 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1480 * Available space in the aperture used by i915_gem_execbuffer, in
1483 __u64 aper_available_size;
1486 struct drm_i915_get_pipe_from_crtc_id {
1487 /** ID of CRTC being requested **/
1490 /** pipe of requested CRTC **/
1494 #define I915_MADV_WILLNEED 0
1495 #define I915_MADV_DONTNEED 1
1496 #define __I915_MADV_PURGED 2 /* internal state */
1498 struct drm_i915_gem_madvise {
1499 /** Handle of the buffer to change the backing store advice */
1502 /* Advice: either the buffer will be needed again in the near future,
1503 * or wont be and could be discarded under memory pressure.
1507 /** Whether the backing store still exists. */
1512 #define I915_OVERLAY_TYPE_MASK 0xff
1513 #define I915_OVERLAY_YUV_PLANAR 0x01
1514 #define I915_OVERLAY_YUV_PACKED 0x02
1515 #define I915_OVERLAY_RGB 0x03
1517 #define I915_OVERLAY_DEPTH_MASK 0xff00
1518 #define I915_OVERLAY_RGB24 0x1000
1519 #define I915_OVERLAY_RGB16 0x2000
1520 #define I915_OVERLAY_RGB15 0x3000
1521 #define I915_OVERLAY_YUV422 0x0100
1522 #define I915_OVERLAY_YUV411 0x0200
1523 #define I915_OVERLAY_YUV420 0x0300
1524 #define I915_OVERLAY_YUV410 0x0400
1526 #define I915_OVERLAY_SWAP_MASK 0xff0000
1527 #define I915_OVERLAY_NO_SWAP 0x000000
1528 #define I915_OVERLAY_UV_SWAP 0x010000
1529 #define I915_OVERLAY_Y_SWAP 0x020000
1530 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1532 #define I915_OVERLAY_FLAGS_MASK 0xff000000
1533 #define I915_OVERLAY_ENABLE 0x01000000
1535 struct drm_intel_overlay_put_image {
1536 /* various flags and src format description */
1538 /* source picture description */
1540 /* stride values and offsets are in bytes, buffer relative */
1541 __u16 stride_Y; /* stride for packed formats */
1543 __u32 offset_Y; /* offset for packet formats */
1549 /* to compensate the scaling factors for partially covered surfaces */
1550 __u16 src_scan_width;
1551 __u16 src_scan_height;
1552 /* output crtc description */
1561 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1562 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1563 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1564 struct drm_intel_overlay_attrs {
1579 * Intel sprite handling
1581 * Color keying works with a min/mask/max tuple. Both source and destination
1582 * color keying is allowed.
1585 * Sprite pixels within the min & max values, masked against the color channels
1586 * specified in the mask field, will be transparent. All other pixels will
1587 * be displayed on top of the primary plane. For RGB surfaces, only the min
1588 * and mask fields will be used; ranged compares are not allowed.
1590 * Destination keying:
1591 * Primary plane pixels that match the min value, masked against the color
1592 * channels specified in the mask field, will be replaced by corresponding
1593 * pixels from the sprite plane.
1595 * Note that source & destination keying are exclusive; only one can be
1596 * active on a given plane.
1599 #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set
1600 * flags==0 to disable colorkeying.
1602 #define I915_SET_COLORKEY_DESTINATION (1<<1)
1603 #define I915_SET_COLORKEY_SOURCE (1<<2)
1604 struct drm_intel_sprite_colorkey {
1612 struct drm_i915_gem_wait {
1613 /** Handle of BO we shall wait on */
1616 /** Number of nanoseconds to wait, Returns time remaining. */
1620 struct drm_i915_gem_context_create {
1621 __u32 ctx_id; /* output: id of new context*/
1625 struct drm_i915_gem_context_create_ext {
1626 __u32 ctx_id; /* output: id of new context*/
1628 #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
1629 #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
1630 #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
1631 (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
1635 struct drm_i915_gem_context_param {
1639 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1640 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1641 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1642 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1643 #define I915_CONTEXT_PARAM_BANNABLE 0x5
1644 #define I915_CONTEXT_PARAM_PRIORITY 0x6
1645 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1646 #define I915_CONTEXT_DEFAULT_PRIORITY 0
1647 #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1649 * When using the following param, value should be a pointer to
1650 * drm_i915_gem_context_param_sseu.
1652 #define I915_CONTEXT_PARAM_SSEU 0x7
1655 * Not all clients may want to attempt automatic recover of a context after
1656 * a hang (for example, some clients may only submit very small incremental
1657 * batches relying on known logical state of previous batches which will never
1658 * recover correctly and each attempt will hang), and so would prefer that
1659 * the context is forever banned instead.
1661 * If set to false (0), after a reset, subsequent (and in flight) rendering
1662 * from this context is discarded, and the client will need to create a new
1663 * context to use instead.
1665 * If set to true (1), the kernel will automatically attempt to recover the
1666 * context by skipping the hanging batch and executing the next batch starting
1667 * from the default context state (discarding the incomplete logical context
1668 * state lost due to the reset).
1670 * On creation, all new contexts are marked as recoverable.
1672 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1675 * The id of the associated virtual memory address space (ppGTT) of
1676 * this context. Can be retrieved and passed to another context
1677 * (on the same fd) for both to use the same ppGTT and so share
1678 * address layouts, and avoid reloading the page tables on context
1679 * switches between themselves.
1681 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
1683 #define I915_CONTEXT_PARAM_VM 0x9
1686 * I915_CONTEXT_PARAM_ENGINES:
1688 * Bind this context to operate on this subset of available engines. Henceforth,
1689 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
1690 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
1691 * and upwards. Slots 0...N are filled in using the specified (class, instance).
1693 * engine_class: I915_ENGINE_CLASS_INVALID,
1694 * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
1695 * to specify a gap in the array that can be filled in later, e.g. by a
1696 * virtual engine used for load balancing.
1698 * Setting the number of engines bound to the context to 0, by passing a zero
1699 * sized argument, will revert back to default settings.
1701 * See struct i915_context_param_engines.
1704 * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
1705 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
1707 #define I915_CONTEXT_PARAM_ENGINES 0xa
1710 * I915_CONTEXT_PARAM_PERSISTENCE:
1712 * Allow the context and active rendering to survive the process until
1713 * completion. Persistence allows fire-and-forget clients to queue up a
1714 * bunch of work, hand the output over to a display server and then quit.
1715 * If the context is marked as not persistent, upon closing (either via
1716 * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
1717 * or process termination), the context and any outstanding requests will be
1718 * cancelled (and exported fences for cancelled requests marked as -EIO).
1720 * By default, new contexts allow persistence.
1722 #define I915_CONTEXT_PARAM_PERSISTENCE 0xb
1725 * I915_CONTEXT_PARAM_RINGSIZE:
1727 * Sets the size of the CS ringbuffer to use for logical ring contexts. This
1728 * applies a limit of how many batches can be queued to HW before the caller
1729 * is blocked due to lack of space for more commands.
1731 * Only reliably possible to be set prior to first use, i.e. during
1732 * construction. At any later point, the current execution must be flushed as
1733 * the ring can only be changed while the context is idle. Note, the ringsize
1734 * can be specified as a constructor property, see
1735 * I915_CONTEXT_CREATE_EXT_SETPARAM, but can also be set later if required.
1737 * Only applies to the current set of engine and lost when those engines
1738 * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
1740 * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
1741 * Default is 16 KiB.
1743 #define I915_CONTEXT_PARAM_RINGSIZE 0xc
1744 /* Must be kept compact -- no holes and well documented */
1750 * Context SSEU programming
1752 * It may be necessary for either functional or performance reason to configure
1753 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
1756 * This is done by configuring SSEU configuration using the below
1757 * @struct drm_i915_gem_context_param_sseu for every supported engine which
1758 * userspace intends to use.
1760 * Not all GPUs or engines support this functionality in which case an error
1761 * code -ENODEV will be returned.
1763 * Also, flexibility of possible SSEU configuration permutations varies between
1764 * GPU generations and software imposed limitations. Requesting such a
1765 * combination will return an error code of -EINVAL.
1767 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
1768 * favour of a single global setting.
1770 struct drm_i915_gem_context_param_sseu {
1772 * Engine class & instance to be configured or queried.
1774 struct i915_engine_class_instance engine;
1777 * Unknown flags must be cleared to zero.
1780 #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
1783 * Mask of slices to enable for the context. Valid values are a subset
1784 * of the bitmask value returned for I915_PARAM_SLICE_MASK.
1789 * Mask of subslices to enable for the context. Valid values are a
1790 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
1792 __u64 subslice_mask;
1795 * Minimum/Maximum number of EUs to enable per subslice for the
1796 * context. min_eus_per_subslice must be inferior or equal to
1797 * max_eus_per_subslice.
1799 __u16 min_eus_per_subslice;
1800 __u16 max_eus_per_subslice;
1803 * Unused for now. Must be cleared to zero.
1809 * i915_context_engines_load_balance:
1811 * Enable load balancing across this set of engines.
1813 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
1814 * used will proxy the execbuffer request onto one of the set of engines
1815 * in such a way as to distribute the load evenly across the set.
1817 * The set of engines must be compatible (e.g. the same HW class) as they
1818 * will share the same logical GPU context and ring.
1820 * To intermix rendering with the virtual engine and direct rendering onto
1821 * the backing engines (bypassing the load balancing proxy), the context must
1822 * be defined to use a single timeline for all engines.
1824 struct i915_context_engines_load_balance {
1825 struct i915_user_extension base;
1829 __u32 flags; /* all undefined flags must be zero */
1831 __u64 mbz64; /* reserved for future use; must be zero */
1833 struct i915_engine_class_instance engines[0];
1834 } __attribute__((packed));
1836 #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
1837 struct i915_user_extension base; \
1838 __u16 engine_index; \
1839 __u16 num_siblings; \
1842 struct i915_engine_class_instance engines[N__]; \
1843 } __attribute__((packed)) name__
1846 * i915_context_engines_bond:
1848 * Constructed bonded pairs for execution within a virtual engine.
1850 * All engines are equal, but some are more equal than others. Given
1851 * the distribution of resources in the HW, it may be preferable to run
1852 * a request on a given subset of engines in parallel to a request on a
1853 * specific engine. We enable this selection of engines within a virtual
1854 * engine by specifying bonding pairs, for any given master engine we will
1855 * only execute on one of the corresponding siblings within the virtual engine.
1857 * To execute a request in parallel on the master engine and a sibling requires
1858 * coordination with a I915_EXEC_FENCE_SUBMIT.
1860 struct i915_context_engines_bond {
1861 struct i915_user_extension base;
1863 struct i915_engine_class_instance master;
1865 __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
1868 __u64 flags; /* all undefined flags must be zero */
1869 __u64 mbz64[4]; /* reserved for future use; must be zero */
1871 struct i915_engine_class_instance engines[0];
1872 } __attribute__((packed));
1874 #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
1875 struct i915_user_extension base; \
1876 struct i915_engine_class_instance master; \
1877 __u16 virtual_index; \
1881 struct i915_engine_class_instance engines[N__]; \
1882 } __attribute__((packed)) name__
1884 struct i915_context_param_engines {
1885 __u64 extensions; /* linked chain of extension blocks, 0 terminates */
1886 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
1887 #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
1888 struct i915_engine_class_instance engines[0];
1889 } __attribute__((packed));
1891 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
1893 struct i915_engine_class_instance engines[N__]; \
1894 } __attribute__((packed)) name__
1896 struct drm_i915_gem_context_create_ext_setparam {
1897 #define I915_CONTEXT_CREATE_EXT_SETPARAM 0
1898 struct i915_user_extension base;
1899 struct drm_i915_gem_context_param param;
1902 struct drm_i915_gem_context_create_ext_clone {
1903 #define I915_CONTEXT_CREATE_EXT_CLONE 1
1904 struct i915_user_extension base;
1907 #define I915_CONTEXT_CLONE_ENGINES (1u << 0)
1908 #define I915_CONTEXT_CLONE_FLAGS (1u << 1)
1909 #define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
1910 #define I915_CONTEXT_CLONE_SSEU (1u << 3)
1911 #define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
1912 #define I915_CONTEXT_CLONE_VM (1u << 5)
1913 #define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
1917 struct drm_i915_gem_context_destroy {
1923 * DRM_I915_GEM_VM_CREATE -
1925 * Create a new virtual memory address space (ppGTT) for use within a context
1926 * on the same file. Extensions can be provided to configure exactly how the
1927 * address space is setup upon creation.
1929 * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
1930 * returned in the outparam @id.
1932 * No flags are defined, with all bits reserved and must be zero.
1934 * An extension chain maybe provided, starting with @extensions, and terminated
1935 * by the @next_extension being 0. Currently, no extensions are defined.
1937 * DRM_I915_GEM_VM_DESTROY -
1939 * Destroys a previously created VM id, specified in @id.
1941 * No extensions or flags are allowed currently, and so must be zero.
1943 struct drm_i915_gem_vm_control {
1949 struct drm_i915_reg_read {
1952 * For 64bit wide registers where the upper 32bits don't immediately
1953 * follow the lower 32bits, the offset of the lower 32bits must
1957 #define I915_REG_READ_8B_WA (1ul << 0)
1959 __u64 val; /* Return value */
1964 * Render engine timestamp - 0x2358 + 64bit - gen7+
1965 * - Note this register returns an invalid value if using the default
1966 * single instruction 8byte read, in order to workaround that pass
1967 * flag I915_REG_READ_8B_WA in offset field.
1971 struct drm_i915_reset_stats {
1975 /* All resets since boot/module reload, for all contexts */
1978 /* Number of batches lost when active in GPU, for this context */
1981 /* Number of batches lost pending for execution, for this context */
1982 __u32 batch_pending;
1987 struct drm_i915_gem_userptr {
1991 #define I915_USERPTR_READ_ONLY 0x1
1992 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1994 * Returned handle for the object.
1996 * Object handles are nonzero.
2001 enum drm_i915_oa_format {
2002 I915_OA_FORMAT_A13 = 1, /* HSW only */
2003 I915_OA_FORMAT_A29, /* HSW only */
2004 I915_OA_FORMAT_A13_B8_C8, /* HSW only */
2005 I915_OA_FORMAT_B4_C8, /* HSW only */
2006 I915_OA_FORMAT_A45_B8_C8, /* HSW only */
2007 I915_OA_FORMAT_B4_C8_A16, /* HSW only */
2008 I915_OA_FORMAT_C4_B8, /* HSW+ */
2012 I915_OA_FORMAT_A12_B8_C8,
2013 I915_OA_FORMAT_A32u40_A4u32_B8_C8,
2015 I915_OA_FORMAT_MAX /* non-ABI */
2018 enum drm_i915_perf_property_id {
2020 * Open the stream for a specific context handle (as used with
2021 * execbuffer2). A stream opened for a specific context this way
2022 * won't typically require root privileges.
2024 * This property is available in perf revision 1.
2026 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
2029 * A value of 1 requests the inclusion of raw OA unit reports as
2030 * part of stream samples.
2032 * This property is available in perf revision 1.
2034 DRM_I915_PERF_PROP_SAMPLE_OA,
2037 * The value specifies which set of OA unit metrics should be
2038 * configured, defining the contents of any OA unit reports.
2040 * This property is available in perf revision 1.
2042 DRM_I915_PERF_PROP_OA_METRICS_SET,
2045 * The value specifies the size and layout of OA unit reports.
2047 * This property is available in perf revision 1.
2049 DRM_I915_PERF_PROP_OA_FORMAT,
2052 * Specifying this property implicitly requests periodic OA unit
2053 * sampling and (at least on Haswell) the sampling frequency is derived
2054 * from this exponent as follows:
2056 * 80ns * 2^(period_exponent + 1)
2058 * This property is available in perf revision 1.
2060 DRM_I915_PERF_PROP_OA_EXPONENT,
2063 * Specifying this property is only valid when specify a context to
2064 * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
2065 * will hold preemption of the particular context we want to gather
2066 * performance data about. The execbuf2 submissions must include a
2067 * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
2069 * This property is available in perf revision 3.
2071 DRM_I915_PERF_PROP_HOLD_PREEMPTION,
2074 * Specifying this pins all contexts to the specified SSEU power
2075 * configuration for the duration of the recording.
2077 * This parameter's value is a pointer to a struct
2078 * drm_i915_gem_context_param_sseu.
2080 * This property is available in perf revision 4.
2082 DRM_I915_PERF_PROP_GLOBAL_SSEU,
2085 * This optional parameter specifies the timer interval in nanoseconds
2086 * at which the i915 driver will check the OA buffer for available data.
2087 * Minimum allowed value is 100 microseconds. A default value is used by
2088 * the driver if this parameter is not specified. Note that larger timer
2089 * values will reduce cpu consumption during OA perf captures. However,
2090 * excessively large values would potentially result in OA buffer
2091 * overwrites as captures reach end of the OA buffer.
2093 * This property is available in perf revision 5.
2095 DRM_I915_PERF_PROP_POLL_OA_PERIOD,
2097 DRM_I915_PERF_PROP_MAX /* non-ABI */
2100 struct drm_i915_perf_open_param {
2102 #define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
2103 #define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
2104 #define I915_PERF_FLAG_DISABLED (1<<2)
2106 /** The number of u64 (id, value) pairs */
2107 __u32 num_properties;
2110 * Pointer to array of u64 (id, value) pairs configuring the stream
2113 __u64 properties_ptr;
2117 * Enable data capture for a stream that was either opened in a disabled state
2118 * via I915_PERF_FLAG_DISABLED or was later disabled via
2119 * I915_PERF_IOCTL_DISABLE.
2121 * It is intended to be cheaper to disable and enable a stream than it may be
2122 * to close and re-open a stream with the same configuration.
2124 * It's undefined whether any pending data for the stream will be lost.
2126 * This ioctl is available in perf revision 1.
2128 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
2131 * Disable data capture for a stream.
2133 * It is an error to try and read a stream that is disabled.
2135 * This ioctl is available in perf revision 1.
2137 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
2140 * Change metrics_set captured by a stream.
2142 * If the stream is bound to a specific context, the configuration change
2143 * will performed inline with that context such that it takes effect before
2144 * the next execbuf submission.
2146 * Returns the previously bound metrics set id, or a negative error code.
2148 * This ioctl is available in perf revision 2.
2150 #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
2153 * Common to all i915 perf records
2155 struct drm_i915_perf_record_header {
2161 enum drm_i915_perf_record_type {
2164 * Samples are the work horse record type whose contents are extensible
2165 * and defined when opening an i915 perf stream based on the given
2168 * Boolean properties following the naming convention
2169 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
2172 * The order of these sample properties given by userspace has no
2173 * affect on the ordering of data within a sample. The order is
2177 * struct drm_i915_perf_record_header header;
2179 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
2182 DRM_I915_PERF_RECORD_SAMPLE = 1,
2185 * Indicates that one or more OA reports were not written by the
2186 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
2187 * command collides with periodic sampling - which would be more likely
2188 * at higher sampling frequencies.
2190 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
2193 * An error occurred that resulted in all pending OA reports being lost.
2195 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
2197 DRM_I915_PERF_RECORD_MAX /* non-ABI */
2201 * Structure to upload perf dynamic configuration into the kernel.
2203 struct drm_i915_perf_oa_config {
2204 /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
2208 __u32 n_boolean_regs;
2212 * These fields are pointers to tuples of u32 values (register address,
2213 * value). For example the expected length of the buffer pointed by
2214 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
2217 __u64 boolean_regs_ptr;
2218 __u64 flex_regs_ptr;
2222 * struct drm_i915_query_item - An individual query for the kernel to process.
2224 * The behaviour is determined by the @query_id. Note that exactly what
2225 * @data_ptr is also depends on the specific @query_id.
2227 struct drm_i915_query_item {
2228 /** @query_id: The id for this query */
2230 #define DRM_I915_QUERY_TOPOLOGY_INFO 1
2231 #define DRM_I915_QUERY_ENGINE_INFO 2
2232 #define DRM_I915_QUERY_PERF_CONFIG 3
2233 /* Must be kept compact -- no holes and well documented */
2238 * When set to zero by userspace, this is filled with the size of the
2239 * data to be written at the @data_ptr pointer. The kernel sets this
2240 * value to a negative value to signal an error on a particular query
2248 * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
2250 * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
2253 * - DRM_I915_QUERY_PERF_CONFIG_LIST
2254 * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
2255 * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
2258 #define DRM_I915_QUERY_PERF_CONFIG_LIST 1
2259 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
2260 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
2265 * Data will be written at the location pointed by @data_ptr when the
2266 * value of @length matches the length of the data to be written by the
2273 * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the
2274 * kernel to fill out.
2276 * Note that this is generally a two step process for each struct
2277 * drm_i915_query_item in the array:
2279 * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct
2280 * drm_i915_query_item, with &drm_i915_query_item.length set to zero. The
2281 * kernel will then fill in the size, in bytes, which tells userspace how
2282 * memory it needs to allocate for the blob(say for an array of properties).
2284 * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the
2285 * &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that
2286 * the &drm_i915_query_item.length should still be the same as what the
2287 * kernel previously set. At this point the kernel can fill in the blob.
2289 * Note that for some query items it can make sense for userspace to just pass
2290 * in a buffer/blob equal to or larger than the required size. In this case only
2291 * a single ioctl call is needed. For some smaller query items this can work
2295 struct drm_i915_query {
2296 /** @num_items: The number of elements in the @items_ptr array */
2300 * @flags: Unused for now. Must be cleared to zero.
2307 * Pointer to an array of struct drm_i915_query_item. The number of
2308 * array elements is @num_items.
2314 * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
2316 * data: contains the 3 pieces of information :
2318 * - the slice mask with one bit per slice telling whether a slice is
2319 * available. The availability of slice X can be queried with the following
2322 * (data[X / 8] >> (X % 8)) & 1
2324 * - the subslice mask for each slice with one bit per subslice telling
2325 * whether a subslice is available. Gen12 has dual-subslices, which are
2326 * similar to two gen11 subslices. For gen12, this array represents dual-
2327 * subslices. The availability of subslice Y in slice X can be queried
2328 * with the following formula :
2330 * (data[subslice_offset +
2331 * X * subslice_stride +
2332 * Y / 8] >> (Y % 8)) & 1
2334 * - the EU mask for each subslice in each slice with one bit per EU telling
2335 * whether an EU is available. The availability of EU Z in subslice Y in
2336 * slice X can be queried with the following formula :
2339 * (X * max_subslices + Y) * eu_stride +
2340 * Z / 8] >> (Z % 8)) & 1
2342 struct drm_i915_query_topology_info {
2344 * Unused for now. Must be cleared to zero.
2349 __u16 max_subslices;
2350 __u16 max_eus_per_subslice;
2353 * Offset in data[] at which the subslice masks are stored.
2355 __u16 subslice_offset;
2358 * Stride at which each of the subslice masks for each slice are
2361 __u16 subslice_stride;
2364 * Offset in data[] at which the EU masks are stored.
2369 * Stride at which each of the EU masks for each subslice are stored.
2377 * struct drm_i915_engine_info
2379 * Describes one engine and it's capabilities as known to the driver.
2381 struct drm_i915_engine_info {
2382 /** @engine: Engine class and instance. */
2383 struct i915_engine_class_instance engine;
2385 /** @rsvd0: Reserved field. */
2388 /** @flags: Engine flags. */
2391 /** @capabilities: Capabilities of this engine. */
2393 #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
2394 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
2396 /** @rsvd1: Reserved fields. */
2401 * struct drm_i915_query_engine_info
2403 * Engine info query enumerates all engines known to the driver by filling in
2404 * an array of struct drm_i915_engine_info structures.
2406 struct drm_i915_query_engine_info {
2407 /** @num_engines: Number of struct drm_i915_engine_info structs following. */
2413 /** @engines: Marker for drm_i915_engine_info structures. */
2414 struct drm_i915_engine_info engines[];
2418 * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
2420 struct drm_i915_query_perf_config {
2423 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
2424 * this fields to the number of configurations available.
2429 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
2430 * i915 will use the value in this field as configuration
2431 * identifier to decide what data to write into config_ptr.
2436 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
2437 * i915 will use the value in this field as configuration
2438 * identifier to decide what data to write into config_ptr.
2440 * String formatted like "%08x-%04x-%04x-%04x-%012x"
2446 * Unused for now. Must be cleared to zero.
2451 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
2452 * write an array of __u64 of configuration identifiers.
2454 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
2455 * write a struct drm_i915_perf_oa_config. If the following fields of
2456 * drm_i915_perf_oa_config are set not set to 0, i915 will write into
2457 * the associated pointers the values of submitted when the
2458 * configuration was created :
2467 #if defined(__cplusplus)
2471 #endif /* _UAPI_I915_DRM_H_ */