2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #ifndef _UAPI_I915_DRM_H_
28 #define _UAPI_I915_DRM_H_
32 /* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
37 * DOC: uevents generated by i915 on it's device node
39 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
40 * event from the gpu l3 cache. Additional information supplied is ROW,
41 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
42 * track of these events and if a specific cache-line seems to have a
43 * persistent error remap it with the l3 remapping tool supplied in
44 * intel-gpu-tools. The value supplied with the event is always 1.
46 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
47 * hangcheck. The error detection event is a good indicator of when things
48 * began to go badly. The value supplied with the event is a 1 upon error
49 * detection, and a 0 upon reset completion, signifying no more error
50 * exists. NOTE: Disabling hangcheck or reset via module parameter will
51 * cause the related events to not be seen.
53 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
54 * the GPU. The value supplied with the event is always 1. NOTE: Disable
55 * reset via module parameter will cause this event to not be seen.
57 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
58 #define I915_ERROR_UEVENT "ERROR"
59 #define I915_RESET_UEVENT "RESET"
61 /* Each region is a minimum of 16k, and there are at most 255 of them.
63 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
64 * of chars for next/prev indices */
65 #define I915_LOG_MIN_TEX_REGION_SIZE 14
67 typedef struct _drm_i915_init {
70 I915_CLEANUP_DMA = 0x02,
71 I915_RESUME_DMA = 0x03
73 unsigned int mmio_offset;
74 int sarea_priv_offset;
75 unsigned int ring_start;
76 unsigned int ring_end;
77 unsigned int ring_size;
78 unsigned int front_offset;
79 unsigned int back_offset;
80 unsigned int depth_offset;
84 unsigned int pitch_bits;
85 unsigned int back_pitch;
86 unsigned int depth_pitch;
91 typedef struct _drm_i915_sarea {
92 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
93 int last_upload; /* last time texture was uploaded */
94 int last_enqueue; /* last time a buffer was enqueued */
95 int last_dispatch; /* age of the most recently dispatched buffer */
96 int ctxOwner; /* last context to upload state */
98 int pf_enabled; /* is pageflipping allowed? */
100 int pf_current_page; /* which buffer is being displayed? */
101 int perf_boxes; /* performance boxes to be displayed */
102 int width, height; /* screen size in pixels */
104 drm_handle_t front_handle;
108 drm_handle_t back_handle;
112 drm_handle_t depth_handle;
116 drm_handle_t tex_handle;
119 int log_tex_granularity;
121 int rotation; /* 0, 90, 180 or 270 */
125 int virtualX, virtualY;
127 unsigned int front_tiled;
128 unsigned int back_tiled;
129 unsigned int depth_tiled;
130 unsigned int rotated_tiled;
131 unsigned int rotated2_tiled;
142 /* fill out some space for old userspace triple buffer */
143 drm_handle_t unused_handle;
144 __u32 unused1, unused2, unused3;
146 /* buffer object handles for static buffers. May change
147 * over the lifetime of the client.
149 __u32 front_bo_handle;
150 __u32 back_bo_handle;
151 __u32 unused_bo_handle;
152 __u32 depth_bo_handle;
156 /* due to userspace building against these headers we need some compat here */
157 #define planeA_x pipeA_x
158 #define planeA_y pipeA_y
159 #define planeA_w pipeA_w
160 #define planeA_h pipeA_h
161 #define planeB_x pipeB_x
162 #define planeB_y pipeB_y
163 #define planeB_w pipeB_w
164 #define planeB_h pipeB_h
166 /* Flags for perf_boxes
168 #define I915_BOX_RING_EMPTY 0x1
169 #define I915_BOX_FLIP 0x2
170 #define I915_BOX_WAIT 0x4
171 #define I915_BOX_TEXTURE_LOAD 0x8
172 #define I915_BOX_LOST_CONTEXT 0x10
174 /* I915 specific ioctls
175 * The device specific ioctl range is 0x40 to 0x79.
177 #define DRM_I915_INIT 0x00
178 #define DRM_I915_FLUSH 0x01
179 #define DRM_I915_FLIP 0x02
180 #define DRM_I915_BATCHBUFFER 0x03
181 #define DRM_I915_IRQ_EMIT 0x04
182 #define DRM_I915_IRQ_WAIT 0x05
183 #define DRM_I915_GETPARAM 0x06
184 #define DRM_I915_SETPARAM 0x07
185 #define DRM_I915_ALLOC 0x08
186 #define DRM_I915_FREE 0x09
187 #define DRM_I915_INIT_HEAP 0x0a
188 #define DRM_I915_CMDBUFFER 0x0b
189 #define DRM_I915_DESTROY_HEAP 0x0c
190 #define DRM_I915_SET_VBLANK_PIPE 0x0d
191 #define DRM_I915_GET_VBLANK_PIPE 0x0e
192 #define DRM_I915_VBLANK_SWAP 0x0f
193 #define DRM_I915_HWS_ADDR 0x11
194 #define DRM_I915_GEM_INIT 0x13
195 #define DRM_I915_GEM_EXECBUFFER 0x14
196 #define DRM_I915_GEM_PIN 0x15
197 #define DRM_I915_GEM_UNPIN 0x16
198 #define DRM_I915_GEM_BUSY 0x17
199 #define DRM_I915_GEM_THROTTLE 0x18
200 #define DRM_I915_GEM_ENTERVT 0x19
201 #define DRM_I915_GEM_LEAVEVT 0x1a
202 #define DRM_I915_GEM_CREATE 0x1b
203 #define DRM_I915_GEM_PREAD 0x1c
204 #define DRM_I915_GEM_PWRITE 0x1d
205 #define DRM_I915_GEM_MMAP 0x1e
206 #define DRM_I915_GEM_SET_DOMAIN 0x1f
207 #define DRM_I915_GEM_SW_FINISH 0x20
208 #define DRM_I915_GEM_SET_TILING 0x21
209 #define DRM_I915_GEM_GET_TILING 0x22
210 #define DRM_I915_GEM_GET_APERTURE 0x23
211 #define DRM_I915_GEM_MMAP_GTT 0x24
212 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
213 #define DRM_I915_GEM_MADVISE 0x26
214 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
215 #define DRM_I915_OVERLAY_ATTRS 0x28
216 #define DRM_I915_GEM_EXECBUFFER2 0x29
217 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
218 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
219 #define DRM_I915_GEM_WAIT 0x2c
220 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
221 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
222 #define DRM_I915_GEM_SET_CACHING 0x2f
223 #define DRM_I915_GEM_GET_CACHING 0x30
224 #define DRM_I915_REG_READ 0x31
225 #define DRM_I915_GET_RESET_STATS 0x32
227 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
228 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
229 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
230 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
231 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
232 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
233 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
234 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
235 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
236 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
237 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
238 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
239 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
240 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
241 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
242 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
243 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
244 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
245 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
246 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
247 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
248 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
249 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
250 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
251 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
252 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
253 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
254 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
255 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
256 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
257 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
258 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
259 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
260 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
261 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
262 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
263 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
264 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
265 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
266 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
267 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
268 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
269 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
270 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
271 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
272 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
273 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
274 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
275 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
277 /* Allow drivers to submit batchbuffers directly to hardware, relying
278 * on the security mechanisms provided by hardware.
280 typedef struct drm_i915_batchbuffer {
281 int start; /* agp offset */
282 int used; /* nr bytes in use */
283 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
284 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
285 int num_cliprects; /* mulitpass with multiple cliprects? */
286 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
287 } drm_i915_batchbuffer_t;
289 /* As above, but pass a pointer to userspace buffer which can be
290 * validated by the kernel prior to sending to hardware.
292 typedef struct _drm_i915_cmdbuffer {
293 char __user *buf; /* pointer to userspace command buffer */
294 int sz; /* nr bytes in buf */
295 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
296 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
297 int num_cliprects; /* mulitpass with multiple cliprects? */
298 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
299 } drm_i915_cmdbuffer_t;
301 /* Userspace can request & wait on irq's:
303 typedef struct drm_i915_irq_emit {
305 } drm_i915_irq_emit_t;
307 typedef struct drm_i915_irq_wait {
309 } drm_i915_irq_wait_t;
311 /* Ioctl to query kernel params:
313 #define I915_PARAM_IRQ_ACTIVE 1
314 #define I915_PARAM_ALLOW_BATCHBUFFER 2
315 #define I915_PARAM_LAST_DISPATCH 3
316 #define I915_PARAM_CHIPSET_ID 4
317 #define I915_PARAM_HAS_GEM 5
318 #define I915_PARAM_NUM_FENCES_AVAIL 6
319 #define I915_PARAM_HAS_OVERLAY 7
320 #define I915_PARAM_HAS_PAGEFLIPPING 8
321 #define I915_PARAM_HAS_EXECBUF2 9
322 #define I915_PARAM_HAS_BSD 10
323 #define I915_PARAM_HAS_BLT 11
324 #define I915_PARAM_HAS_RELAXED_FENCING 12
325 #define I915_PARAM_HAS_COHERENT_RINGS 13
326 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
327 #define I915_PARAM_HAS_RELAXED_DELTA 15
328 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
329 #define I915_PARAM_HAS_LLC 17
330 #define I915_PARAM_HAS_ALIASING_PPGTT 18
331 #define I915_PARAM_HAS_WAIT_TIMEOUT 19
332 #define I915_PARAM_HAS_SEMAPHORES 20
333 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
334 #define I915_PARAM_HAS_VEBOX 22
335 #define I915_PARAM_HAS_SECURE_BATCHES 23
336 #define I915_PARAM_HAS_PINNED_BATCHES 24
337 #define I915_PARAM_HAS_EXEC_NO_RELOC 25
338 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
339 #define I915_PARAM_HAS_WT 27
340 #define I915_PARAM_HAS_FULL_PPGTT 28
342 typedef struct drm_i915_getparam {
345 } drm_i915_getparam_t;
347 /* Ioctl to set kernel params:
349 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
350 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
351 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
352 #define I915_SETPARAM_NUM_USED_FENCES 4
354 typedef struct drm_i915_setparam {
357 } drm_i915_setparam_t;
359 /* A memory manager for regions of shared memory:
361 #define I915_MEM_REGION_AGP 1
363 typedef struct drm_i915_mem_alloc {
367 int __user *region_offset; /* offset from start of fb or agp */
368 } drm_i915_mem_alloc_t;
370 typedef struct drm_i915_mem_free {
373 } drm_i915_mem_free_t;
375 typedef struct drm_i915_mem_init_heap {
379 } drm_i915_mem_init_heap_t;
381 /* Allow memory manager to be torn down and re-initialized (eg on
384 typedef struct drm_i915_mem_destroy_heap {
386 } drm_i915_mem_destroy_heap_t;
388 /* Allow X server to configure which pipes to monitor for vblank signals
390 #define DRM_I915_VBLANK_PIPE_A 1
391 #define DRM_I915_VBLANK_PIPE_B 2
393 typedef struct drm_i915_vblank_pipe {
395 } drm_i915_vblank_pipe_t;
397 /* Schedule buffer swap at given vertical blank:
399 typedef struct drm_i915_vblank_swap {
400 drm_drawable_t drawable;
401 enum drm_vblank_seq_type seqtype;
402 unsigned int sequence;
403 } drm_i915_vblank_swap_t;
405 typedef struct drm_i915_hws_addr {
407 } drm_i915_hws_addr_t;
409 struct drm_i915_gem_init {
411 * Beginning offset in the GTT to be managed by the DRM memory
416 * Ending offset in the GTT to be managed by the DRM memory
422 struct drm_i915_gem_create {
424 * Requested size for the object.
426 * The (page-aligned) allocated size for the object will be returned.
430 * Returned handle for the object.
432 * Object handles are nonzero.
438 struct drm_i915_gem_pread {
439 /** Handle for the object being read. */
442 /** Offset into the object to read from */
444 /** Length of data to read */
447 * Pointer to write the data into.
449 * This is a fixed-size type for 32/64 compatibility.
454 struct drm_i915_gem_pwrite {
455 /** Handle for the object being written to. */
458 /** Offset into the object to write to */
460 /** Length of data to write */
463 * Pointer to read the data from.
465 * This is a fixed-size type for 32/64 compatibility.
470 struct drm_i915_gem_mmap {
471 /** Handle for the object being mapped. */
474 /** Offset in the object to map. */
477 * Length of data to map.
479 * The value will be page-aligned.
483 * Returned pointer the data was mapped at.
485 * This is a fixed-size type for 32/64 compatibility.
490 struct drm_i915_gem_mmap_gtt {
491 /** Handle for the object being mapped. */
495 * Fake offset to use for subsequent mmap call
497 * This is a fixed-size type for 32/64 compatibility.
502 struct drm_i915_gem_set_domain {
503 /** Handle for the object */
506 /** New read domains */
509 /** New write domain */
513 struct drm_i915_gem_sw_finish {
514 /** Handle for the object */
518 struct drm_i915_gem_relocation_entry {
520 * Handle of the buffer being pointed to by this relocation entry.
522 * It's appealing to make this be an index into the mm_validate_entry
523 * list to refer to the buffer, but this allows the driver to create
524 * a relocation list for state buffers and not re-write it per
525 * exec using the buffer.
530 * Value to be added to the offset of the target buffer to make up
531 * the relocation entry.
535 /** Offset in the buffer the relocation entry will be written into */
539 * Offset value of the target buffer that the relocation entry was last
542 * If the buffer has the same offset as last time, we can skip syncing
543 * and writing the relocation. This value is written back out by
544 * the execbuffer ioctl when the relocation is written.
546 __u64 presumed_offset;
549 * Target memory domains read by this operation.
554 * Target memory domains written by this operation.
556 * Note that only one domain may be written by the whole
557 * execbuffer operation, so that where there are conflicts,
558 * the application will get -EINVAL back.
564 * Intel memory domains
566 * Most of these just align with the various caches in
567 * the system and are used to flush and invalidate as
568 * objects end up cached in different domains.
571 #define I915_GEM_DOMAIN_CPU 0x00000001
572 /** Render cache, used by 2D and 3D drawing */
573 #define I915_GEM_DOMAIN_RENDER 0x00000002
574 /** Sampler cache, used by texture engine */
575 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
576 /** Command queue, used to load batch buffers */
577 #define I915_GEM_DOMAIN_COMMAND 0x00000008
578 /** Instruction cache, used by shader programs */
579 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
580 /** Vertex address cache */
581 #define I915_GEM_DOMAIN_VERTEX 0x00000020
582 /** GTT domain - aperture and scanout */
583 #define I915_GEM_DOMAIN_GTT 0x00000040
586 struct drm_i915_gem_exec_object {
588 * User's handle for a buffer to be bound into the GTT for this
593 /** Number of relocations to be performed on this buffer */
594 __u32 relocation_count;
596 * Pointer to array of struct drm_i915_gem_relocation_entry containing
597 * the relocations to be performed in this buffer.
601 /** Required alignment in graphics aperture */
605 * Returned value of the updated offset of the object, for future
606 * presumed_offset writes.
611 struct drm_i915_gem_execbuffer {
613 * List of buffers to be validated with their relocations to be
614 * performend on them.
616 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
618 * These buffers must be listed in an order such that all relocations
619 * a buffer is performing refer to buffers that have already appeared
620 * in the validate list.
625 /** Offset in the batchbuffer to start execution from. */
626 __u32 batch_start_offset;
627 /** Bytes used in batchbuffer from batch_start_offset */
632 /** This is a struct drm_clip_rect *cliprects */
636 struct drm_i915_gem_exec_object2 {
638 * User's handle for a buffer to be bound into the GTT for this
643 /** Number of relocations to be performed on this buffer */
644 __u32 relocation_count;
646 * Pointer to array of struct drm_i915_gem_relocation_entry containing
647 * the relocations to be performed in this buffer.
651 /** Required alignment in graphics aperture */
655 * Returned value of the updated offset of the object, for future
656 * presumed_offset writes.
660 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
661 #define EXEC_OBJECT_NEEDS_GTT (1<<1)
662 #define EXEC_OBJECT_WRITE (1<<2)
663 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
670 struct drm_i915_gem_execbuffer2 {
672 * List of gem_exec_object2 structs
677 /** Offset in the batchbuffer to start execution from. */
678 __u32 batch_start_offset;
679 /** Bytes used in batchbuffer from batch_start_offset */
684 /** This is a struct drm_clip_rect *cliprects */
686 #define I915_EXEC_RING_MASK (7<<0)
687 #define I915_EXEC_DEFAULT (0<<0)
688 #define I915_EXEC_RENDER (1<<0)
689 #define I915_EXEC_BSD (2<<0)
690 #define I915_EXEC_BLT (3<<0)
691 #define I915_EXEC_VEBOX (4<<0)
693 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
694 * Gen6+ only supports relative addressing to dynamic state (default) and
695 * absolute addressing.
697 * These flags are ignored for the BSD and BLT rings.
699 #define I915_EXEC_CONSTANTS_MASK (3<<6)
700 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
701 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
702 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
704 __u64 rsvd1; /* now used for context info */
708 /** Resets the SO write offset registers for transform feedback on gen7. */
709 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
711 /** Request a privileged ("secure") batch buffer. Note only available for
712 * DRM_ROOT_ONLY | DRM_MASTER processes.
714 #define I915_EXEC_SECURE (1<<9)
716 /** Inform the kernel that the batch is and will always be pinned. This
717 * negates the requirement for a workaround to be performed to avoid
718 * an incoherent CS (such as can be found on 830/845). If this flag is
719 * not passed, the kernel will endeavour to make sure the batch is
720 * coherent with the CS before execution. If this flag is passed,
721 * userspace assumes the responsibility for ensuring the same.
723 #define I915_EXEC_IS_PINNED (1<<10)
725 /** Provide a hint to the kernel that the command stream and auxilliary
726 * state buffers already holds the correct presumed addresses and so the
727 * relocation process may be skipped if no buffers need to be moved in
728 * preparation for the execbuffer.
730 #define I915_EXEC_NO_RELOC (1<<11)
732 /** Use the reloc.handle as an index into the exec object array rather
733 * than as the per-file handle.
735 #define I915_EXEC_HANDLE_LUT (1<<12)
737 #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
739 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
740 #define i915_execbuffer2_set_context_id(eb2, context) \
741 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
742 #define i915_execbuffer2_get_context_id(eb2) \
743 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
745 struct drm_i915_gem_pin {
746 /** Handle of the buffer to be pinned. */
750 /** alignment required within the aperture */
753 /** Returned GTT offset of the buffer. */
757 struct drm_i915_gem_unpin {
758 /** Handle of the buffer to be unpinned. */
763 struct drm_i915_gem_busy {
764 /** Handle of the buffer to check for busy */
767 /** Return busy status (1 if busy, 0 if idle).
768 * The high word is used to indicate on which rings the object
770 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
778 * GPU access is not coherent with cpu caches. Default for machines without an
781 #define I915_CACHING_NONE 0
783 * I915_CACHING_CACHED
785 * GPU access is coherent with cpu caches and furthermore the data is cached in
786 * last-level caches shared between cpu cores and the gpu GT. Default on
787 * machines with HAS_LLC.
789 #define I915_CACHING_CACHED 1
791 * I915_CACHING_DISPLAY
793 * Special GPU caching mode which is coherent with the scanout engines.
794 * Transparently falls back to I915_CACHING_NONE on platforms where no special
795 * cache mode (like write-through or gfdt flushing) is available. The kernel
796 * automatically sets this mode when using a buffer as a scanout target.
797 * Userspace can manually set this mode to avoid a costly stall and clflush in
798 * the hotpath of drawing the first frame.
800 #define I915_CACHING_DISPLAY 2
802 struct drm_i915_gem_caching {
804 * Handle of the buffer to set/get the caching level of. */
808 * Cacheing level to apply or return value
810 * bits0-15 are for generic caching control (i.e. the above defined
811 * values). bits16-31 are reserved for platform-specific variations
812 * (e.g. l3$ caching on gen7). */
816 #define I915_TILING_NONE 0
817 #define I915_TILING_X 1
818 #define I915_TILING_Y 2
820 #define I915_BIT_6_SWIZZLE_NONE 0
821 #define I915_BIT_6_SWIZZLE_9 1
822 #define I915_BIT_6_SWIZZLE_9_10 2
823 #define I915_BIT_6_SWIZZLE_9_11 3
824 #define I915_BIT_6_SWIZZLE_9_10_11 4
825 /* Not seen by userland */
826 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
827 /* Seen by userland. */
828 #define I915_BIT_6_SWIZZLE_9_17 6
829 #define I915_BIT_6_SWIZZLE_9_10_17 7
831 struct drm_i915_gem_set_tiling {
832 /** Handle of the buffer to have its tiling state updated */
836 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
839 * This value is to be set on request, and will be updated by the
840 * kernel on successful return with the actual chosen tiling layout.
842 * The tiling mode may be demoted to I915_TILING_NONE when the system
843 * has bit 6 swizzling that can't be managed correctly by GEM.
845 * Buffer contents become undefined when changing tiling_mode.
850 * Stride in bytes for the object when in I915_TILING_X or
856 * Returned address bit 6 swizzling required for CPU access through
862 struct drm_i915_gem_get_tiling {
863 /** Handle of the buffer to get tiling state for. */
867 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
873 * Returned address bit 6 swizzling required for CPU access through
879 struct drm_i915_gem_get_aperture {
880 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
884 * Available space in the aperture used by i915_gem_execbuffer, in
887 __u64 aper_available_size;
890 struct drm_i915_get_pipe_from_crtc_id {
891 /** ID of CRTC being requested **/
894 /** pipe of requested CRTC **/
898 #define I915_MADV_WILLNEED 0
899 #define I915_MADV_DONTNEED 1
900 #define __I915_MADV_PURGED 2 /* internal state */
902 struct drm_i915_gem_madvise {
903 /** Handle of the buffer to change the backing store advice */
906 /* Advice: either the buffer will be needed again in the near future,
907 * or wont be and could be discarded under memory pressure.
911 /** Whether the backing store still exists. */
916 #define I915_OVERLAY_TYPE_MASK 0xff
917 #define I915_OVERLAY_YUV_PLANAR 0x01
918 #define I915_OVERLAY_YUV_PACKED 0x02
919 #define I915_OVERLAY_RGB 0x03
921 #define I915_OVERLAY_DEPTH_MASK 0xff00
922 #define I915_OVERLAY_RGB24 0x1000
923 #define I915_OVERLAY_RGB16 0x2000
924 #define I915_OVERLAY_RGB15 0x3000
925 #define I915_OVERLAY_YUV422 0x0100
926 #define I915_OVERLAY_YUV411 0x0200
927 #define I915_OVERLAY_YUV420 0x0300
928 #define I915_OVERLAY_YUV410 0x0400
930 #define I915_OVERLAY_SWAP_MASK 0xff0000
931 #define I915_OVERLAY_NO_SWAP 0x000000
932 #define I915_OVERLAY_UV_SWAP 0x010000
933 #define I915_OVERLAY_Y_SWAP 0x020000
934 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
936 #define I915_OVERLAY_FLAGS_MASK 0xff000000
937 #define I915_OVERLAY_ENABLE 0x01000000
939 struct drm_intel_overlay_put_image {
940 /* various flags and src format description */
942 /* source picture description */
944 /* stride values and offsets are in bytes, buffer relative */
945 __u16 stride_Y; /* stride for packed formats */
947 __u32 offset_Y; /* offset for packet formats */
953 /* to compensate the scaling factors for partially covered surfaces */
954 __u16 src_scan_width;
955 __u16 src_scan_height;
956 /* output crtc description */
965 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
966 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
967 struct drm_intel_overlay_attrs {
982 * Intel sprite handling
984 * Color keying works with a min/mask/max tuple. Both source and destination
985 * color keying is allowed.
988 * Sprite pixels within the min & max values, masked against the color channels
989 * specified in the mask field, will be transparent. All other pixels will
990 * be displayed on top of the primary plane. For RGB surfaces, only the min
991 * and mask fields will be used; ranged compares are not allowed.
993 * Destination keying:
994 * Primary plane pixels that match the min value, masked against the color
995 * channels specified in the mask field, will be replaced by corresponding
996 * pixels from the sprite plane.
998 * Note that source & destination keying are exclusive; only one can be
999 * active on a given plane.
1002 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
1003 #define I915_SET_COLORKEY_DESTINATION (1<<1)
1004 #define I915_SET_COLORKEY_SOURCE (1<<2)
1005 struct drm_intel_sprite_colorkey {
1013 struct drm_i915_gem_wait {
1014 /** Handle of BO we shall wait on */
1017 /** Number of nanoseconds to wait, Returns time remaining. */
1021 struct drm_i915_gem_context_create {
1022 /* output: id of new context*/
1027 struct drm_i915_gem_context_destroy {
1032 struct drm_i915_reg_read {
1034 __u64 val; /* Return value */
1037 struct drm_i915_reset_stats {
1041 /* All resets since boot/module reload, for all contexts */
1044 /* Number of batches lost when active in GPU, for this context */
1047 /* Number of batches lost pending for execution, for this context */
1048 __u32 batch_pending;
1053 #endif /* _UAPI_I915_DRM_H_ */