2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #ifndef _UAPI_I915_DRM_H_
28 #define _UAPI_I915_DRM_H_
32 #if defined(__cplusplus)
36 /* Please note that modifications to all structs defined here are
37 * subject to backwards-compatibility constraints.
41 * DOC: uevents generated by i915 on it's device node
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
44 * event from the gpu l3 cache. Additional information supplied is ROW,
45 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
46 * track of these events and if a specific cache-line seems to have a
47 * persistent error remap it with the l3 remapping tool supplied in
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
51 * hangcheck. The error detection event is a good indicator of when things
52 * began to go badly. The value supplied with the event is a 1 upon error
53 * detection, and a 0 upon reset completion, signifying no more error
54 * exists. NOTE: Disabling hangcheck or reset via module parameter will
55 * cause the related events to not be seen.
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58 * GPU. The value supplied with the event is always 1. NOTE: Disable
59 * reset via module parameter will cause this event to not be seen.
61 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62 #define I915_ERROR_UEVENT "ERROR"
63 #define I915_RESET_UEVENT "RESET"
66 * i915_user_extension: Base class for defining a chain of extensions
68 * Many interfaces need to grow over time. In most cases we can simply
69 * extend the struct and have userspace pass in more data. Another option,
70 * as demonstrated by Vulkan's approach to providing extensions for forward
71 * and backward compatibility, is to use a list of optional structs to
72 * provide those extra details.
74 * The key advantage to using an extension chain is that it allows us to
75 * redefine the interface more easily than an ever growing struct of
76 * increasing complexity, and for large parts of that interface to be
77 * entirely optional. The downside is more pointer chasing; chasing across
78 * the __user boundary with pointers encapsulated inside u64.
80 struct i915_user_extension {
83 __u32 flags; /* All undefined bits must be zero. */
84 __u32 rsvd[4]; /* Reserved for future use; must be zero. */
88 * MOCS indexes used for GPU surfaces, defining the cacheability of the
89 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
91 enum i915_mocs_table_index {
93 * Not cached anywhere, coherency between CPU and GPU accesses is
98 * Cacheability and coherency controlled by the kernel automatically
99 * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
100 * usage of the surface (used for display scanout or not).
104 * Cached in all GPU caches available on the platform.
105 * Coherency between CPU and GPU accesses to the surface is not
106 * guaranteed without extra synchronization.
112 * Different engines serve different roles, and there may be more than one
113 * engine serving each role. enum drm_i915_gem_engine_class provides a
114 * classification of the role of the engine, which may be used when requesting
115 * operations to be performed on a certain subset of engines, or for providing
116 * information about that group.
118 enum drm_i915_gem_engine_class {
119 I915_ENGINE_CLASS_RENDER = 0,
120 I915_ENGINE_CLASS_COPY = 1,
121 I915_ENGINE_CLASS_VIDEO = 2,
122 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
124 /* should be kept compact */
126 I915_ENGINE_CLASS_INVALID = -1
130 * There may be more than one engine fulfilling any role within the system.
131 * Each engine of a class is given a unique instance number and therefore
132 * any engine can be specified by its class:instance tuplet. APIs that allow
133 * access to any engine in the system will use struct i915_engine_class_instance
134 * for this identification.
136 struct i915_engine_class_instance {
137 __u16 engine_class; /* see enum drm_i915_gem_engine_class */
138 __u16 engine_instance;
139 #define I915_ENGINE_CLASS_INVALID_NONE -1
140 #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
144 * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
148 enum drm_i915_pmu_engine_sample {
149 I915_SAMPLE_BUSY = 0,
150 I915_SAMPLE_WAIT = 1,
154 #define I915_PMU_SAMPLE_BITS (4)
155 #define I915_PMU_SAMPLE_MASK (0xf)
156 #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
157 #define I915_PMU_CLASS_SHIFT \
158 (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
160 #define __I915_PMU_ENGINE(class, instance, sample) \
161 ((class) << I915_PMU_CLASS_SHIFT | \
162 (instance) << I915_PMU_SAMPLE_BITS | \
165 #define I915_PMU_ENGINE_BUSY(class, instance) \
166 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
168 #define I915_PMU_ENGINE_WAIT(class, instance) \
169 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
171 #define I915_PMU_ENGINE_SEMA(class, instance) \
172 __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
174 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
176 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
177 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
178 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
179 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
180 #define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)
182 #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
184 /* Each region is a minimum of 16k, and there are at most 255 of them.
186 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
187 * of chars for next/prev indices */
188 #define I915_LOG_MIN_TEX_REGION_SIZE 14
190 typedef struct _drm_i915_init {
192 I915_INIT_DMA = 0x01,
193 I915_CLEANUP_DMA = 0x02,
194 I915_RESUME_DMA = 0x03
196 unsigned int mmio_offset;
197 int sarea_priv_offset;
198 unsigned int ring_start;
199 unsigned int ring_end;
200 unsigned int ring_size;
201 unsigned int front_offset;
202 unsigned int back_offset;
203 unsigned int depth_offset;
207 unsigned int pitch_bits;
208 unsigned int back_pitch;
209 unsigned int depth_pitch;
211 unsigned int chipset;
214 typedef struct _drm_i915_sarea {
215 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
216 int last_upload; /* last time texture was uploaded */
217 int last_enqueue; /* last time a buffer was enqueued */
218 int last_dispatch; /* age of the most recently dispatched buffer */
219 int ctxOwner; /* last context to upload state */
221 int pf_enabled; /* is pageflipping allowed? */
223 int pf_current_page; /* which buffer is being displayed? */
224 int perf_boxes; /* performance boxes to be displayed */
225 int width, height; /* screen size in pixels */
227 drm_handle_t front_handle;
231 drm_handle_t back_handle;
235 drm_handle_t depth_handle;
239 drm_handle_t tex_handle;
242 int log_tex_granularity;
244 int rotation; /* 0, 90, 180 or 270 */
248 int virtualX, virtualY;
250 unsigned int front_tiled;
251 unsigned int back_tiled;
252 unsigned int depth_tiled;
253 unsigned int rotated_tiled;
254 unsigned int rotated2_tiled;
265 /* fill out some space for old userspace triple buffer */
266 drm_handle_t unused_handle;
267 __u32 unused1, unused2, unused3;
269 /* buffer object handles for static buffers. May change
270 * over the lifetime of the client.
272 __u32 front_bo_handle;
273 __u32 back_bo_handle;
274 __u32 unused_bo_handle;
275 __u32 depth_bo_handle;
279 /* due to userspace building against these headers we need some compat here */
280 #define planeA_x pipeA_x
281 #define planeA_y pipeA_y
282 #define planeA_w pipeA_w
283 #define planeA_h pipeA_h
284 #define planeB_x pipeB_x
285 #define planeB_y pipeB_y
286 #define planeB_w pipeB_w
287 #define planeB_h pipeB_h
289 /* Flags for perf_boxes
291 #define I915_BOX_RING_EMPTY 0x1
292 #define I915_BOX_FLIP 0x2
293 #define I915_BOX_WAIT 0x4
294 #define I915_BOX_TEXTURE_LOAD 0x8
295 #define I915_BOX_LOST_CONTEXT 0x10
298 * i915 specific ioctls.
300 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
301 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
302 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
304 #define DRM_I915_INIT 0x00
305 #define DRM_I915_FLUSH 0x01
306 #define DRM_I915_FLIP 0x02
307 #define DRM_I915_BATCHBUFFER 0x03
308 #define DRM_I915_IRQ_EMIT 0x04
309 #define DRM_I915_IRQ_WAIT 0x05
310 #define DRM_I915_GETPARAM 0x06
311 #define DRM_I915_SETPARAM 0x07
312 #define DRM_I915_ALLOC 0x08
313 #define DRM_I915_FREE 0x09
314 #define DRM_I915_INIT_HEAP 0x0a
315 #define DRM_I915_CMDBUFFER 0x0b
316 #define DRM_I915_DESTROY_HEAP 0x0c
317 #define DRM_I915_SET_VBLANK_PIPE 0x0d
318 #define DRM_I915_GET_VBLANK_PIPE 0x0e
319 #define DRM_I915_VBLANK_SWAP 0x0f
320 #define DRM_I915_HWS_ADDR 0x11
321 #define DRM_I915_GEM_INIT 0x13
322 #define DRM_I915_GEM_EXECBUFFER 0x14
323 #define DRM_I915_GEM_PIN 0x15
324 #define DRM_I915_GEM_UNPIN 0x16
325 #define DRM_I915_GEM_BUSY 0x17
326 #define DRM_I915_GEM_THROTTLE 0x18
327 #define DRM_I915_GEM_ENTERVT 0x19
328 #define DRM_I915_GEM_LEAVEVT 0x1a
329 #define DRM_I915_GEM_CREATE 0x1b
330 #define DRM_I915_GEM_PREAD 0x1c
331 #define DRM_I915_GEM_PWRITE 0x1d
332 #define DRM_I915_GEM_MMAP 0x1e
333 #define DRM_I915_GEM_SET_DOMAIN 0x1f
334 #define DRM_I915_GEM_SW_FINISH 0x20
335 #define DRM_I915_GEM_SET_TILING 0x21
336 #define DRM_I915_GEM_GET_TILING 0x22
337 #define DRM_I915_GEM_GET_APERTURE 0x23
338 #define DRM_I915_GEM_MMAP_GTT 0x24
339 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
340 #define DRM_I915_GEM_MADVISE 0x26
341 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
342 #define DRM_I915_OVERLAY_ATTRS 0x28
343 #define DRM_I915_GEM_EXECBUFFER2 0x29
344 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
345 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
346 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
347 #define DRM_I915_GEM_WAIT 0x2c
348 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
349 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
350 #define DRM_I915_GEM_SET_CACHING 0x2f
351 #define DRM_I915_GEM_GET_CACHING 0x30
352 #define DRM_I915_REG_READ 0x31
353 #define DRM_I915_GET_RESET_STATS 0x32
354 #define DRM_I915_GEM_USERPTR 0x33
355 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
356 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
357 #define DRM_I915_PERF_OPEN 0x36
358 #define DRM_I915_PERF_ADD_CONFIG 0x37
359 #define DRM_I915_PERF_REMOVE_CONFIG 0x38
360 #define DRM_I915_QUERY 0x39
361 #define DRM_I915_GEM_VM_CREATE 0x3a
362 #define DRM_I915_GEM_VM_DESTROY 0x3b
363 /* Must be kept compact -- no holes */
365 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
366 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
367 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
368 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
369 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
370 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
371 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
372 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
373 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
374 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
375 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
376 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
377 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
378 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
379 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
380 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
381 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
382 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
383 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
384 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
385 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
386 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
387 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
388 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
389 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
390 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
391 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
392 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
393 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
394 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
395 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
396 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
397 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
398 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
399 #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)
400 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
401 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
402 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
403 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
404 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
405 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
406 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
407 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
408 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
409 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
410 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
411 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
412 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
413 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
414 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
415 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
416 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
417 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
418 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
419 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
420 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
421 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
422 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
423 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
424 #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
425 #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
427 /* Allow drivers to submit batchbuffers directly to hardware, relying
428 * on the security mechanisms provided by hardware.
430 typedef struct drm_i915_batchbuffer {
431 int start; /* agp offset */
432 int used; /* nr bytes in use */
433 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
434 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
435 int num_cliprects; /* mulitpass with multiple cliprects? */
436 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
437 } drm_i915_batchbuffer_t;
439 /* As above, but pass a pointer to userspace buffer which can be
440 * validated by the kernel prior to sending to hardware.
442 typedef struct _drm_i915_cmdbuffer {
443 char __user *buf; /* pointer to userspace command buffer */
444 int sz; /* nr bytes in buf */
445 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
446 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
447 int num_cliprects; /* mulitpass with multiple cliprects? */
448 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
449 } drm_i915_cmdbuffer_t;
451 /* Userspace can request & wait on irq's:
453 typedef struct drm_i915_irq_emit {
455 } drm_i915_irq_emit_t;
457 typedef struct drm_i915_irq_wait {
459 } drm_i915_irq_wait_t;
462 * Different modes of per-process Graphics Translation Table,
463 * see I915_PARAM_HAS_ALIASING_PPGTT
465 #define I915_GEM_PPGTT_NONE 0
466 #define I915_GEM_PPGTT_ALIASING 1
467 #define I915_GEM_PPGTT_FULL 2
469 /* Ioctl to query kernel params:
471 #define I915_PARAM_IRQ_ACTIVE 1
472 #define I915_PARAM_ALLOW_BATCHBUFFER 2
473 #define I915_PARAM_LAST_DISPATCH 3
474 #define I915_PARAM_CHIPSET_ID 4
475 #define I915_PARAM_HAS_GEM 5
476 #define I915_PARAM_NUM_FENCES_AVAIL 6
477 #define I915_PARAM_HAS_OVERLAY 7
478 #define I915_PARAM_HAS_PAGEFLIPPING 8
479 #define I915_PARAM_HAS_EXECBUF2 9
480 #define I915_PARAM_HAS_BSD 10
481 #define I915_PARAM_HAS_BLT 11
482 #define I915_PARAM_HAS_RELAXED_FENCING 12
483 #define I915_PARAM_HAS_COHERENT_RINGS 13
484 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
485 #define I915_PARAM_HAS_RELAXED_DELTA 15
486 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
487 #define I915_PARAM_HAS_LLC 17
488 #define I915_PARAM_HAS_ALIASING_PPGTT 18
489 #define I915_PARAM_HAS_WAIT_TIMEOUT 19
490 #define I915_PARAM_HAS_SEMAPHORES 20
491 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
492 #define I915_PARAM_HAS_VEBOX 22
493 #define I915_PARAM_HAS_SECURE_BATCHES 23
494 #define I915_PARAM_HAS_PINNED_BATCHES 24
495 #define I915_PARAM_HAS_EXEC_NO_RELOC 25
496 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
497 #define I915_PARAM_HAS_WT 27
498 #define I915_PARAM_CMD_PARSER_VERSION 28
499 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
500 #define I915_PARAM_MMAP_VERSION 30
501 #define I915_PARAM_HAS_BSD2 31
502 #define I915_PARAM_REVISION 32
503 #define I915_PARAM_SUBSLICE_TOTAL 33
504 #define I915_PARAM_EU_TOTAL 34
505 #define I915_PARAM_HAS_GPU_RESET 35
506 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
507 #define I915_PARAM_HAS_EXEC_SOFTPIN 37
508 #define I915_PARAM_HAS_POOLED_EU 38
509 #define I915_PARAM_MIN_EU_IN_POOL 39
510 #define I915_PARAM_MMAP_GTT_VERSION 40
513 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
514 * priorities and the driver will attempt to execute batches in priority order.
515 * The param returns a capability bitmask, nonzero implies that the scheduler
516 * is enabled, with different features present according to the mask.
518 * The initial priority for each batch is supplied by the context and is
519 * controlled via I915_CONTEXT_PARAM_PRIORITY.
521 #define I915_PARAM_HAS_SCHEDULER 41
522 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
523 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
524 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
525 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
526 #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
528 #define I915_PARAM_HUC_STATUS 42
530 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
531 * synchronisation with implicit fencing on individual objects.
532 * See EXEC_OBJECT_ASYNC.
534 #define I915_PARAM_HAS_EXEC_ASYNC 43
536 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
537 * both being able to pass in a sync_file fd to wait upon before executing,
538 * and being able to return a new sync_file fd that is signaled when the
539 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
541 #define I915_PARAM_HAS_EXEC_FENCE 44
543 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
544 * user specified bufffers for post-mortem debugging of GPU hangs. See
545 * EXEC_OBJECT_CAPTURE.
547 #define I915_PARAM_HAS_EXEC_CAPTURE 45
549 #define I915_PARAM_SLICE_MASK 46
551 /* Assuming it's uniform for each slice, this queries the mask of subslices
552 * per-slice for this system.
554 #define I915_PARAM_SUBSLICE_MASK 47
557 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
558 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
560 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
562 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
563 * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
565 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
568 * Query whether every context (both per-file default and user created) is
569 * isolated (insofar as HW supports). If this parameter is not true, then
570 * freshly created contexts may inherit values from an existing context,
571 * rather than default HW values. If true, it also ensures (insofar as HW
572 * supports) that all state set by this context will not leak to any other
575 * As not every engine across every gen support contexts, the returned
576 * value reports the support of context isolation for individual engines by
577 * returning a bitmask of each engine class set to true if that class supports
580 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50
582 /* Frequency of the command streamer timestamps given by the *_TIMESTAMP
583 * registers. This used to be fixed per platform but from CNL onwards, this
584 * might vary depending on the parts.
586 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
589 * Once upon a time we supposed that writes through the GGTT would be
590 * immediately in physical memory (once flushed out of the CPU path). However,
591 * on a few different processors and chipsets, this is not necessarily the case
592 * as the writes appear to be buffered internally. Thus a read of the backing
593 * storage (physical memory) via a different path (with different physical tags
594 * to the indirect write via the GGTT) will see stale values from before
595 * the GGTT write. Inside the kernel, we can for the most part keep track of
596 * the different read/write domains in use (e.g. set-domain), but the assumption
597 * of coherency is baked into the ABI, hence reporting its true state in this
600 * Reports true when writes via mmap_gtt are immediately visible following an
601 * lfence to flush the WCB.
603 * Reports false when writes via mmap_gtt are indeterminately delayed in an in
604 * internal buffer and are _not_ immediately visible to third parties accessing
605 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
606 * communications channel when reporting false is strongly disadvised.
608 #define I915_PARAM_MMAP_GTT_COHERENT 52
611 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
612 * execution through use of explicit fence support.
613 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
615 #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
618 * Revision of the i915-perf uAPI. The value returned helps determine what
619 * i915-perf features are available. See drm_i915_perf_property_id.
621 #define I915_PARAM_PERF_REVISION 54
623 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
624 * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See
625 * I915_EXEC_USE_EXTENSIONS.
627 #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
629 /* Must be kept compact -- no holes and well documented */
631 typedef struct drm_i915_getparam {
634 * WARNING: Using pointers instead of fixed-size u64 means we need to write
635 * compat32 code. Don't repeat this mistake.
638 } drm_i915_getparam_t;
640 /* Ioctl to set kernel params:
642 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
643 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
644 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
645 #define I915_SETPARAM_NUM_USED_FENCES 4
646 /* Must be kept compact -- no holes */
648 typedef struct drm_i915_setparam {
651 } drm_i915_setparam_t;
653 /* A memory manager for regions of shared memory:
655 #define I915_MEM_REGION_AGP 1
657 typedef struct drm_i915_mem_alloc {
661 int __user *region_offset; /* offset from start of fb or agp */
662 } drm_i915_mem_alloc_t;
664 typedef struct drm_i915_mem_free {
667 } drm_i915_mem_free_t;
669 typedef struct drm_i915_mem_init_heap {
673 } drm_i915_mem_init_heap_t;
675 /* Allow memory manager to be torn down and re-initialized (eg on
678 typedef struct drm_i915_mem_destroy_heap {
680 } drm_i915_mem_destroy_heap_t;
682 /* Allow X server to configure which pipes to monitor for vblank signals
684 #define DRM_I915_VBLANK_PIPE_A 1
685 #define DRM_I915_VBLANK_PIPE_B 2
687 typedef struct drm_i915_vblank_pipe {
689 } drm_i915_vblank_pipe_t;
691 /* Schedule buffer swap at given vertical blank:
693 typedef struct drm_i915_vblank_swap {
694 drm_drawable_t drawable;
695 enum drm_vblank_seq_type seqtype;
696 unsigned int sequence;
697 } drm_i915_vblank_swap_t;
699 typedef struct drm_i915_hws_addr {
701 } drm_i915_hws_addr_t;
703 struct drm_i915_gem_init {
705 * Beginning offset in the GTT to be managed by the DRM memory
710 * Ending offset in the GTT to be managed by the DRM memory
716 struct drm_i915_gem_create {
718 * Requested size for the object.
720 * The (page-aligned) allocated size for the object will be returned.
724 * Returned handle for the object.
726 * Object handles are nonzero.
732 struct drm_i915_gem_pread {
733 /** Handle for the object being read. */
736 /** Offset into the object to read from */
738 /** Length of data to read */
741 * Pointer to write the data into.
743 * This is a fixed-size type for 32/64 compatibility.
748 struct drm_i915_gem_pwrite {
749 /** Handle for the object being written to. */
752 /** Offset into the object to write to */
754 /** Length of data to write */
757 * Pointer to read the data from.
759 * This is a fixed-size type for 32/64 compatibility.
764 struct drm_i915_gem_mmap {
765 /** Handle for the object being mapped. */
768 /** Offset in the object to map. */
771 * Length of data to map.
773 * The value will be page-aligned.
777 * Returned pointer the data was mapped at.
779 * This is a fixed-size type for 32/64 compatibility.
784 * Flags for extended behaviour.
786 * Added in version 2.
789 #define I915_MMAP_WC 0x1
792 struct drm_i915_gem_mmap_gtt {
793 /** Handle for the object being mapped. */
797 * Fake offset to use for subsequent mmap call
799 * This is a fixed-size type for 32/64 compatibility.
804 struct drm_i915_gem_mmap_offset {
805 /** Handle for the object being mapped. */
809 * Fake offset to use for subsequent mmap call
811 * This is a fixed-size type for 32/64 compatibility.
816 * Flags for extended behaviour.
818 * It is mandatory that one of the MMAP_OFFSET types
819 * (GTT, WC, WB, UC, etc) should be included.
822 #define I915_MMAP_OFFSET_GTT 0
823 #define I915_MMAP_OFFSET_WC 1
824 #define I915_MMAP_OFFSET_WB 2
825 #define I915_MMAP_OFFSET_UC 3
828 * Zero-terminated chain of extensions.
830 * No current extensions defined; mbz.
835 struct drm_i915_gem_set_domain {
836 /** Handle for the object */
839 /** New read domains */
842 /** New write domain */
846 struct drm_i915_gem_sw_finish {
847 /** Handle for the object */
851 struct drm_i915_gem_relocation_entry {
853 * Handle of the buffer being pointed to by this relocation entry.
855 * It's appealing to make this be an index into the mm_validate_entry
856 * list to refer to the buffer, but this allows the driver to create
857 * a relocation list for state buffers and not re-write it per
858 * exec using the buffer.
863 * Value to be added to the offset of the target buffer to make up
864 * the relocation entry.
868 /** Offset in the buffer the relocation entry will be written into */
872 * Offset value of the target buffer that the relocation entry was last
875 * If the buffer has the same offset as last time, we can skip syncing
876 * and writing the relocation. This value is written back out by
877 * the execbuffer ioctl when the relocation is written.
879 __u64 presumed_offset;
882 * Target memory domains read by this operation.
887 * Target memory domains written by this operation.
889 * Note that only one domain may be written by the whole
890 * execbuffer operation, so that where there are conflicts,
891 * the application will get -EINVAL back.
897 * Intel memory domains
899 * Most of these just align with the various caches in
900 * the system and are used to flush and invalidate as
901 * objects end up cached in different domains.
904 #define I915_GEM_DOMAIN_CPU 0x00000001
905 /** Render cache, used by 2D and 3D drawing */
906 #define I915_GEM_DOMAIN_RENDER 0x00000002
907 /** Sampler cache, used by texture engine */
908 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
909 /** Command queue, used to load batch buffers */
910 #define I915_GEM_DOMAIN_COMMAND 0x00000008
911 /** Instruction cache, used by shader programs */
912 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
913 /** Vertex address cache */
914 #define I915_GEM_DOMAIN_VERTEX 0x00000020
915 /** GTT domain - aperture and scanout */
916 #define I915_GEM_DOMAIN_GTT 0x00000040
917 /** WC domain - uncached access */
918 #define I915_GEM_DOMAIN_WC 0x00000080
921 struct drm_i915_gem_exec_object {
923 * User's handle for a buffer to be bound into the GTT for this
928 /** Number of relocations to be performed on this buffer */
929 __u32 relocation_count;
931 * Pointer to array of struct drm_i915_gem_relocation_entry containing
932 * the relocations to be performed in this buffer.
936 /** Required alignment in graphics aperture */
940 * Returned value of the updated offset of the object, for future
941 * presumed_offset writes.
946 struct drm_i915_gem_execbuffer {
948 * List of buffers to be validated with their relocations to be
949 * performend on them.
951 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
953 * These buffers must be listed in an order such that all relocations
954 * a buffer is performing refer to buffers that have already appeared
955 * in the validate list.
960 /** Offset in the batchbuffer to start execution from. */
961 __u32 batch_start_offset;
962 /** Bytes used in batchbuffer from batch_start_offset */
967 /** This is a struct drm_clip_rect *cliprects */
971 struct drm_i915_gem_exec_object2 {
973 * User's handle for a buffer to be bound into the GTT for this
978 /** Number of relocations to be performed on this buffer */
979 __u32 relocation_count;
981 * Pointer to array of struct drm_i915_gem_relocation_entry containing
982 * the relocations to be performed in this buffer.
986 /** Required alignment in graphics aperture */
990 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
991 * the user with the GTT offset at which this object will be pinned.
992 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
993 * presumed_offset of the object.
994 * During execbuffer2 the kernel populates it with the value of the
995 * current GTT offset of the object, for future presumed_offset writes.
999 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
1000 #define EXEC_OBJECT_NEEDS_GTT (1<<1)
1001 #define EXEC_OBJECT_WRITE (1<<2)
1002 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
1003 #define EXEC_OBJECT_PINNED (1<<4)
1004 #define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
1005 /* The kernel implicitly tracks GPU activity on all GEM objects, and
1006 * synchronises operations with outstanding rendering. This includes
1007 * rendering on other devices if exported via dma-buf. However, sometimes
1008 * this tracking is too coarse and the user knows better. For example,
1009 * if the object is split into non-overlapping ranges shared between different
1010 * clients or engines (i.e. suballocating objects), the implicit tracking
1011 * by kernel assumes that each operation affects the whole object rather
1012 * than an individual range, causing needless synchronisation between clients.
1013 * The kernel will also forgo any CPU cache flushes prior to rendering from
1014 * the object as the client is expected to be also handling such domain
1017 * The kernel maintains the implicit tracking in order to manage resources
1018 * used by the GPU - this flag only disables the synchronisation prior to
1019 * rendering with this object in this execbuf.
1021 * Opting out of implicit synhronisation requires the user to do its own
1022 * explicit tracking to avoid rendering corruption. See, for example,
1023 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
1025 #define EXEC_OBJECT_ASYNC (1<<6)
1026 /* Request that the contents of this execobject be copied into the error
1027 * state upon a GPU hang involving this batch for post-mortem debugging.
1028 * These buffers are recorded in no particular order as "user" in
1029 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
1030 * if the kernel supports this flag.
1032 #define EXEC_OBJECT_CAPTURE (1<<7)
1033 /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
1034 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
1044 struct drm_i915_gem_exec_fence {
1046 * User's handle for a drm_syncobj to wait on or signal.
1050 #define I915_EXEC_FENCE_WAIT (1<<0)
1051 #define I915_EXEC_FENCE_SIGNAL (1<<1)
1052 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
1057 * See drm_i915_gem_execbuffer_ext_timeline_fences.
1059 #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
1062 * This structure describes an array of drm_syncobj and associated points for
1063 * timeline variants of drm_syncobj. It is invalid to append this structure to
1064 * the execbuf if I915_EXEC_FENCE_ARRAY is set.
1066 struct drm_i915_gem_execbuffer_ext_timeline_fences {
1067 struct i915_user_extension base;
1070 * Number of element in the handles_ptr & value_ptr arrays.
1075 * Pointer to an array of struct drm_i915_gem_exec_fence of length
1081 * Pointer to an array of u64 values of length fence_count. Values
1082 * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline
1083 * drm_syncobj is invalid as it turns a drm_syncobj into a binary one.
1088 struct drm_i915_gem_execbuffer2 {
1090 * List of gem_exec_object2 structs
1095 /** Offset in the batchbuffer to start execution from. */
1096 __u32 batch_start_offset;
1097 /** Bytes used in batchbuffer from batch_start_offset */
1101 __u32 num_cliprects;
1103 * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
1104 * & I915_EXEC_USE_EXTENSIONS are not set.
1106 * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
1107 * of struct drm_i915_gem_exec_fence and num_cliprects is the length
1110 * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
1111 * single struct i915_user_extension and num_cliprects is 0.
1113 __u64 cliprects_ptr;
1114 #define I915_EXEC_RING_MASK (0x3f)
1115 #define I915_EXEC_DEFAULT (0<<0)
1116 #define I915_EXEC_RENDER (1<<0)
1117 #define I915_EXEC_BSD (2<<0)
1118 #define I915_EXEC_BLT (3<<0)
1119 #define I915_EXEC_VEBOX (4<<0)
1121 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
1122 * Gen6+ only supports relative addressing to dynamic state (default) and
1123 * absolute addressing.
1125 * These flags are ignored for the BSD and BLT rings.
1127 #define I915_EXEC_CONSTANTS_MASK (3<<6)
1128 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
1129 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
1130 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
1132 __u64 rsvd1; /* now used for context info */
1136 /** Resets the SO write offset registers for transform feedback on gen7. */
1137 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
1139 /** Request a privileged ("secure") batch buffer. Note only available for
1140 * DRM_ROOT_ONLY | DRM_MASTER processes.
1142 #define I915_EXEC_SECURE (1<<9)
1144 /** Inform the kernel that the batch is and will always be pinned. This
1145 * negates the requirement for a workaround to be performed to avoid
1146 * an incoherent CS (such as can be found on 830/845). If this flag is
1147 * not passed, the kernel will endeavour to make sure the batch is
1148 * coherent with the CS before execution. If this flag is passed,
1149 * userspace assumes the responsibility for ensuring the same.
1151 #define I915_EXEC_IS_PINNED (1<<10)
1153 /** Provide a hint to the kernel that the command stream and auxiliary
1154 * state buffers already holds the correct presumed addresses and so the
1155 * relocation process may be skipped if no buffers need to be moved in
1156 * preparation for the execbuffer.
1158 #define I915_EXEC_NO_RELOC (1<<11)
1160 /** Use the reloc.handle as an index into the exec object array rather
1161 * than as the per-file handle.
1163 #define I915_EXEC_HANDLE_LUT (1<<12)
1165 /** Used for switching BSD rings on the platforms with two BSD rings */
1166 #define I915_EXEC_BSD_SHIFT (13)
1167 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
1168 /* default ping-pong mode */
1169 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
1170 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
1171 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
1173 /** Tell the kernel that the batchbuffer is processed by
1174 * the resource streamer.
1176 #define I915_EXEC_RESOURCE_STREAMER (1<<15)
1178 /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
1179 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1182 * Returns -EINVAL if the sync_file fd cannot be found.
1184 #define I915_EXEC_FENCE_IN (1<<16)
1186 /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
1187 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
1188 * to the caller, and it should be close() after use. (The fd is a regular
1189 * file descriptor and will be cleaned up on process termination. It holds
1190 * a reference to the request, but nothing else.)
1192 * The sync_file fd can be combined with other sync_file and passed either
1193 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
1194 * will only occur after this request completes), or to other devices.
1196 * Using I915_EXEC_FENCE_OUT requires use of
1197 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
1198 * back to userspace. Failure to do so will cause the out-fence to always
1199 * be reported as zero, and the real fence fd to be leaked.
1201 #define I915_EXEC_FENCE_OUT (1<<17)
1204 * Traditionally the execbuf ioctl has only considered the final element in
1205 * the execobject[] to be the executable batch. Often though, the client
1206 * will known the batch object prior to construction and being able to place
1207 * it into the execobject[] array first can simplify the relocation tracking.
1208 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
1209 * execobject[] as the * batch instead (the default is to use the last
1212 #define I915_EXEC_BATCH_FIRST (1<<18)
1214 /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
1215 * define an array of i915_gem_exec_fence structures which specify a set of
1216 * dma fences to wait upon or signal.
1218 #define I915_EXEC_FENCE_ARRAY (1<<19)
1221 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
1222 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
1225 * Returns -EINVAL if the sync_file fd cannot be found.
1227 #define I915_EXEC_FENCE_SUBMIT (1 << 20)
1230 * Setting I915_EXEC_USE_EXTENSIONS implies that
1231 * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
1232 * list of i915_user_extension. Each i915_user_extension node is the base of a
1233 * larger structure. The list of supported structures are listed in the
1234 * drm_i915_gem_execbuffer_ext enum.
1236 #define I915_EXEC_USE_EXTENSIONS (1 << 21)
1238 #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))
1240 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1241 #define i915_execbuffer2_set_context_id(eb2, context) \
1242 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
1243 #define i915_execbuffer2_get_context_id(eb2) \
1244 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
1246 struct drm_i915_gem_pin {
1247 /** Handle of the buffer to be pinned. */
1251 /** alignment required within the aperture */
1254 /** Returned GTT offset of the buffer. */
1258 struct drm_i915_gem_unpin {
1259 /** Handle of the buffer to be unpinned. */
1264 struct drm_i915_gem_busy {
1265 /** Handle of the buffer to check for busy */
1268 /** Return busy status
1270 * A return of 0 implies that the object is idle (after
1271 * having flushed any pending activity), and a non-zero return that
1272 * the object is still in-flight on the GPU. (The GPU has not yet
1273 * signaled completion for all pending requests that reference the
1274 * object.) An object is guaranteed to become idle eventually (so
1275 * long as no new GPU commands are executed upon it). Due to the
1276 * asynchronous nature of the hardware, an object reported
1277 * as busy may become idle before the ioctl is completed.
1279 * Furthermore, if the object is busy, which engine is busy is only
1280 * provided as a guide and only indirectly by reporting its class
1281 * (there may be more than one engine in each class). There are race
1282 * conditions which prevent the report of which engines are busy from
1283 * being always accurate. However, the converse is not true. If the
1284 * object is idle, the result of the ioctl, that all engines are idle,
1287 * The returned dword is split into two fields to indicate both
1288 * the engine classess on which the object is being read, and the
1289 * engine class on which it is currently being written (if any).
1291 * The low word (bits 0:15) indicate if the object is being written
1292 * to by any engine (there can only be one, as the GEM implicit
1293 * synchronisation rules force writes to be serialised). Only the
1294 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
1295 * 1 not 0 etc) for the last write is reported.
1297 * The high word (bits 16:31) are a bitmask of which engines classes
1298 * are currently reading from the object. Multiple engines may be
1299 * reading from the object simultaneously.
1301 * The value of each engine class is the same as specified in the
1302 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
1303 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1304 * reported as active itself. Some hardware may have parallel
1305 * execution engines, e.g. multiple media engines, which are
1306 * mapped to the same class identifier and so are not separately
1307 * reported for busyness.
1310 * Only the boolean result of this query is reliable; that is whether
1311 * the object is idle or busy. The report of which engines are busy
1312 * should be only used as a heuristic.
1320 * GPU access is not coherent with cpu caches. Default for machines without an
1323 #define I915_CACHING_NONE 0
1325 * I915_CACHING_CACHED
1327 * GPU access is coherent with cpu caches and furthermore the data is cached in
1328 * last-level caches shared between cpu cores and the gpu GT. Default on
1329 * machines with HAS_LLC.
1331 #define I915_CACHING_CACHED 1
1333 * I915_CACHING_DISPLAY
1335 * Special GPU caching mode which is coherent with the scanout engines.
1336 * Transparently falls back to I915_CACHING_NONE on platforms where no special
1337 * cache mode (like write-through or gfdt flushing) is available. The kernel
1338 * automatically sets this mode when using a buffer as a scanout target.
1339 * Userspace can manually set this mode to avoid a costly stall and clflush in
1340 * the hotpath of drawing the first frame.
1342 #define I915_CACHING_DISPLAY 2
1344 struct drm_i915_gem_caching {
1346 * Handle of the buffer to set/get the caching level of. */
1350 * Cacheing level to apply or return value
1352 * bits0-15 are for generic caching control (i.e. the above defined
1353 * values). bits16-31 are reserved for platform-specific variations
1354 * (e.g. l3$ caching on gen7). */
1358 #define I915_TILING_NONE 0
1359 #define I915_TILING_X 1
1360 #define I915_TILING_Y 2
1361 #define I915_TILING_LAST I915_TILING_Y
1363 #define I915_BIT_6_SWIZZLE_NONE 0
1364 #define I915_BIT_6_SWIZZLE_9 1
1365 #define I915_BIT_6_SWIZZLE_9_10 2
1366 #define I915_BIT_6_SWIZZLE_9_11 3
1367 #define I915_BIT_6_SWIZZLE_9_10_11 4
1368 /* Not seen by userland */
1369 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
1370 /* Seen by userland. */
1371 #define I915_BIT_6_SWIZZLE_9_17 6
1372 #define I915_BIT_6_SWIZZLE_9_10_17 7
1374 struct drm_i915_gem_set_tiling {
1375 /** Handle of the buffer to have its tiling state updated */
1379 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1382 * This value is to be set on request, and will be updated by the
1383 * kernel on successful return with the actual chosen tiling layout.
1385 * The tiling mode may be demoted to I915_TILING_NONE when the system
1386 * has bit 6 swizzling that can't be managed correctly by GEM.
1388 * Buffer contents become undefined when changing tiling_mode.
1393 * Stride in bytes for the object when in I915_TILING_X or
1399 * Returned address bit 6 swizzling required for CPU access through
1405 struct drm_i915_gem_get_tiling {
1406 /** Handle of the buffer to get tiling state for. */
1410 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
1416 * Returned address bit 6 swizzling required for CPU access through
1422 * Returned address bit 6 swizzling required for CPU access through
1423 * mmap mapping whilst bound.
1425 __u32 phys_swizzle_mode;
1428 struct drm_i915_gem_get_aperture {
1429 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
1433 * Available space in the aperture used by i915_gem_execbuffer, in
1436 __u64 aper_available_size;
1439 struct drm_i915_get_pipe_from_crtc_id {
1440 /** ID of CRTC being requested **/
1443 /** pipe of requested CRTC **/
1447 #define I915_MADV_WILLNEED 0
1448 #define I915_MADV_DONTNEED 1
1449 #define __I915_MADV_PURGED 2 /* internal state */
1451 struct drm_i915_gem_madvise {
1452 /** Handle of the buffer to change the backing store advice */
1455 /* Advice: either the buffer will be needed again in the near future,
1456 * or wont be and could be discarded under memory pressure.
1460 /** Whether the backing store still exists. */
1465 #define I915_OVERLAY_TYPE_MASK 0xff
1466 #define I915_OVERLAY_YUV_PLANAR 0x01
1467 #define I915_OVERLAY_YUV_PACKED 0x02
1468 #define I915_OVERLAY_RGB 0x03
1470 #define I915_OVERLAY_DEPTH_MASK 0xff00
1471 #define I915_OVERLAY_RGB24 0x1000
1472 #define I915_OVERLAY_RGB16 0x2000
1473 #define I915_OVERLAY_RGB15 0x3000
1474 #define I915_OVERLAY_YUV422 0x0100
1475 #define I915_OVERLAY_YUV411 0x0200
1476 #define I915_OVERLAY_YUV420 0x0300
1477 #define I915_OVERLAY_YUV410 0x0400
1479 #define I915_OVERLAY_SWAP_MASK 0xff0000
1480 #define I915_OVERLAY_NO_SWAP 0x000000
1481 #define I915_OVERLAY_UV_SWAP 0x010000
1482 #define I915_OVERLAY_Y_SWAP 0x020000
1483 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1485 #define I915_OVERLAY_FLAGS_MASK 0xff000000
1486 #define I915_OVERLAY_ENABLE 0x01000000
1488 struct drm_intel_overlay_put_image {
1489 /* various flags and src format description */
1491 /* source picture description */
1493 /* stride values and offsets are in bytes, buffer relative */
1494 __u16 stride_Y; /* stride for packed formats */
1496 __u32 offset_Y; /* offset for packet formats */
1502 /* to compensate the scaling factors for partially covered surfaces */
1503 __u16 src_scan_width;
1504 __u16 src_scan_height;
1505 /* output crtc description */
1514 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1515 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1516 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1517 struct drm_intel_overlay_attrs {
1532 * Intel sprite handling
1534 * Color keying works with a min/mask/max tuple. Both source and destination
1535 * color keying is allowed.
1538 * Sprite pixels within the min & max values, masked against the color channels
1539 * specified in the mask field, will be transparent. All other pixels will
1540 * be displayed on top of the primary plane. For RGB surfaces, only the min
1541 * and mask fields will be used; ranged compares are not allowed.
1543 * Destination keying:
1544 * Primary plane pixels that match the min value, masked against the color
1545 * channels specified in the mask field, will be replaced by corresponding
1546 * pixels from the sprite plane.
1548 * Note that source & destination keying are exclusive; only one can be
1549 * active on a given plane.
1552 #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set
1553 * flags==0 to disable colorkeying.
1555 #define I915_SET_COLORKEY_DESTINATION (1<<1)
1556 #define I915_SET_COLORKEY_SOURCE (1<<2)
1557 struct drm_intel_sprite_colorkey {
1565 struct drm_i915_gem_wait {
1566 /** Handle of BO we shall wait on */
1569 /** Number of nanoseconds to wait, Returns time remaining. */
1573 struct drm_i915_gem_context_create {
1574 __u32 ctx_id; /* output: id of new context*/
1578 struct drm_i915_gem_context_create_ext {
1579 __u32 ctx_id; /* output: id of new context*/
1581 #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
1582 #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
1583 #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
1584 (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
1588 struct drm_i915_gem_context_param {
1592 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1593 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1594 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1595 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1596 #define I915_CONTEXT_PARAM_BANNABLE 0x5
1597 #define I915_CONTEXT_PARAM_PRIORITY 0x6
1598 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1599 #define I915_CONTEXT_DEFAULT_PRIORITY 0
1600 #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1602 * When using the following param, value should be a pointer to
1603 * drm_i915_gem_context_param_sseu.
1605 #define I915_CONTEXT_PARAM_SSEU 0x7
1608 * Not all clients may want to attempt automatic recover of a context after
1609 * a hang (for example, some clients may only submit very small incremental
1610 * batches relying on known logical state of previous batches which will never
1611 * recover correctly and each attempt will hang), and so would prefer that
1612 * the context is forever banned instead.
1614 * If set to false (0), after a reset, subsequent (and in flight) rendering
1615 * from this context is discarded, and the client will need to create a new
1616 * context to use instead.
1618 * If set to true (1), the kernel will automatically attempt to recover the
1619 * context by skipping the hanging batch and executing the next batch starting
1620 * from the default context state (discarding the incomplete logical context
1621 * state lost due to the reset).
1623 * On creation, all new contexts are marked as recoverable.
1625 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8
1628 * The id of the associated virtual memory address space (ppGTT) of
1629 * this context. Can be retrieved and passed to another context
1630 * (on the same fd) for both to use the same ppGTT and so share
1631 * address layouts, and avoid reloading the page tables on context
1632 * switches between themselves.
1634 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
1636 #define I915_CONTEXT_PARAM_VM 0x9
1639 * I915_CONTEXT_PARAM_ENGINES:
1641 * Bind this context to operate on this subset of available engines. Henceforth,
1642 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
1643 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
1644 * and upwards. Slots 0...N are filled in using the specified (class, instance).
1646 * engine_class: I915_ENGINE_CLASS_INVALID,
1647 * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
1648 * to specify a gap in the array that can be filled in later, e.g. by a
1649 * virtual engine used for load balancing.
1651 * Setting the number of engines bound to the context to 0, by passing a zero
1652 * sized argument, will revert back to default settings.
1654 * See struct i915_context_param_engines.
1657 * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
1658 * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
1660 #define I915_CONTEXT_PARAM_ENGINES 0xa
1663 * I915_CONTEXT_PARAM_PERSISTENCE:
1665 * Allow the context and active rendering to survive the process until
1666 * completion. Persistence allows fire-and-forget clients to queue up a
1667 * bunch of work, hand the output over to a display server and then quit.
1668 * If the context is marked as not persistent, upon closing (either via
1669 * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
1670 * or process termination), the context and any outstanding requests will be
1671 * cancelled (and exported fences for cancelled requests marked as -EIO).
1673 * By default, new contexts allow persistence.
1675 #define I915_CONTEXT_PARAM_PERSISTENCE 0xb
1678 * I915_CONTEXT_PARAM_RINGSIZE:
1680 * Sets the size of the CS ringbuffer to use for logical ring contexts. This
1681 * applies a limit of how many batches can be queued to HW before the caller
1682 * is blocked due to lack of space for more commands.
1684 * Only reliably possible to be set prior to first use, i.e. during
1685 * construction. At any later point, the current execution must be flushed as
1686 * the ring can only be changed while the context is idle. Note, the ringsize
1687 * can be specified as a constructor property, see
1688 * I915_CONTEXT_CREATE_EXT_SETPARAM, but can also be set later if required.
1690 * Only applies to the current set of engine and lost when those engines
1691 * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
1693 * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
1694 * Default is 16 KiB.
1696 #define I915_CONTEXT_PARAM_RINGSIZE 0xc
1697 /* Must be kept compact -- no holes and well documented */
1703 * Context SSEU programming
1705 * It may be necessary for either functional or performance reason to configure
1706 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
1709 * This is done by configuring SSEU configuration using the below
1710 * @struct drm_i915_gem_context_param_sseu for every supported engine which
1711 * userspace intends to use.
1713 * Not all GPUs or engines support this functionality in which case an error
1714 * code -ENODEV will be returned.
1716 * Also, flexibility of possible SSEU configuration permutations varies between
1717 * GPU generations and software imposed limitations. Requesting such a
1718 * combination will return an error code of -EINVAL.
1720 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
1721 * favour of a single global setting.
1723 struct drm_i915_gem_context_param_sseu {
1725 * Engine class & instance to be configured or queried.
1727 struct i915_engine_class_instance engine;
1730 * Unknown flags must be cleared to zero.
1733 #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
1736 * Mask of slices to enable for the context. Valid values are a subset
1737 * of the bitmask value returned for I915_PARAM_SLICE_MASK.
1742 * Mask of subslices to enable for the context. Valid values are a
1743 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
1745 __u64 subslice_mask;
1748 * Minimum/Maximum number of EUs to enable per subslice for the
1749 * context. min_eus_per_subslice must be inferior or equal to
1750 * max_eus_per_subslice.
1752 __u16 min_eus_per_subslice;
1753 __u16 max_eus_per_subslice;
1756 * Unused for now. Must be cleared to zero.
1762 * i915_context_engines_load_balance:
1764 * Enable load balancing across this set of engines.
1766 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
1767 * used will proxy the execbuffer request onto one of the set of engines
1768 * in such a way as to distribute the load evenly across the set.
1770 * The set of engines must be compatible (e.g. the same HW class) as they
1771 * will share the same logical GPU context and ring.
1773 * To intermix rendering with the virtual engine and direct rendering onto
1774 * the backing engines (bypassing the load balancing proxy), the context must
1775 * be defined to use a single timeline for all engines.
1777 struct i915_context_engines_load_balance {
1778 struct i915_user_extension base;
1782 __u32 flags; /* all undefined flags must be zero */
1784 __u64 mbz64; /* reserved for future use; must be zero */
1786 struct i915_engine_class_instance engines[0];
1787 } __attribute__((packed));
1789 #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
1790 struct i915_user_extension base; \
1791 __u16 engine_index; \
1792 __u16 num_siblings; \
1795 struct i915_engine_class_instance engines[N__]; \
1796 } __attribute__((packed)) name__
1799 * i915_context_engines_bond:
1801 * Constructed bonded pairs for execution within a virtual engine.
1803 * All engines are equal, but some are more equal than others. Given
1804 * the distribution of resources in the HW, it may be preferable to run
1805 * a request on a given subset of engines in parallel to a request on a
1806 * specific engine. We enable this selection of engines within a virtual
1807 * engine by specifying bonding pairs, for any given master engine we will
1808 * only execute on one of the corresponding siblings within the virtual engine.
1810 * To execute a request in parallel on the master engine and a sibling requires
1811 * coordination with a I915_EXEC_FENCE_SUBMIT.
1813 struct i915_context_engines_bond {
1814 struct i915_user_extension base;
1816 struct i915_engine_class_instance master;
1818 __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
1821 __u64 flags; /* all undefined flags must be zero */
1822 __u64 mbz64[4]; /* reserved for future use; must be zero */
1824 struct i915_engine_class_instance engines[0];
1825 } __attribute__((packed));
1827 #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
1828 struct i915_user_extension base; \
1829 struct i915_engine_class_instance master; \
1830 __u16 virtual_index; \
1834 struct i915_engine_class_instance engines[N__]; \
1835 } __attribute__((packed)) name__
1837 struct i915_context_param_engines {
1838 __u64 extensions; /* linked chain of extension blocks, 0 terminates */
1839 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
1840 #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
1841 struct i915_engine_class_instance engines[0];
1842 } __attribute__((packed));
1844 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
1846 struct i915_engine_class_instance engines[N__]; \
1847 } __attribute__((packed)) name__
1849 struct drm_i915_gem_context_create_ext_setparam {
1850 #define I915_CONTEXT_CREATE_EXT_SETPARAM 0
1851 struct i915_user_extension base;
1852 struct drm_i915_gem_context_param param;
1855 struct drm_i915_gem_context_create_ext_clone {
1856 #define I915_CONTEXT_CREATE_EXT_CLONE 1
1857 struct i915_user_extension base;
1860 #define I915_CONTEXT_CLONE_ENGINES (1u << 0)
1861 #define I915_CONTEXT_CLONE_FLAGS (1u << 1)
1862 #define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
1863 #define I915_CONTEXT_CLONE_SSEU (1u << 3)
1864 #define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
1865 #define I915_CONTEXT_CLONE_VM (1u << 5)
1866 #define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
1870 struct drm_i915_gem_context_destroy {
1876 * DRM_I915_GEM_VM_CREATE -
1878 * Create a new virtual memory address space (ppGTT) for use within a context
1879 * on the same file. Extensions can be provided to configure exactly how the
1880 * address space is setup upon creation.
1882 * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
1883 * returned in the outparam @id.
1885 * No flags are defined, with all bits reserved and must be zero.
1887 * An extension chain maybe provided, starting with @extensions, and terminated
1888 * by the @next_extension being 0. Currently, no extensions are defined.
1890 * DRM_I915_GEM_VM_DESTROY -
1892 * Destroys a previously created VM id, specified in @id.
1894 * No extensions or flags are allowed currently, and so must be zero.
1896 struct drm_i915_gem_vm_control {
1902 struct drm_i915_reg_read {
1905 * For 64bit wide registers where the upper 32bits don't immediately
1906 * follow the lower 32bits, the offset of the lower 32bits must
1910 #define I915_REG_READ_8B_WA (1ul << 0)
1912 __u64 val; /* Return value */
1917 * Render engine timestamp - 0x2358 + 64bit - gen7+
1918 * - Note this register returns an invalid value if using the default
1919 * single instruction 8byte read, in order to workaround that pass
1920 * flag I915_REG_READ_8B_WA in offset field.
1924 struct drm_i915_reset_stats {
1928 /* All resets since boot/module reload, for all contexts */
1931 /* Number of batches lost when active in GPU, for this context */
1934 /* Number of batches lost pending for execution, for this context */
1935 __u32 batch_pending;
1940 struct drm_i915_gem_userptr {
1944 #define I915_USERPTR_READ_ONLY 0x1
1945 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1947 * Returned handle for the object.
1949 * Object handles are nonzero.
1954 enum drm_i915_oa_format {
1955 I915_OA_FORMAT_A13 = 1, /* HSW only */
1956 I915_OA_FORMAT_A29, /* HSW only */
1957 I915_OA_FORMAT_A13_B8_C8, /* HSW only */
1958 I915_OA_FORMAT_B4_C8, /* HSW only */
1959 I915_OA_FORMAT_A45_B8_C8, /* HSW only */
1960 I915_OA_FORMAT_B4_C8_A16, /* HSW only */
1961 I915_OA_FORMAT_C4_B8, /* HSW+ */
1965 I915_OA_FORMAT_A12_B8_C8,
1966 I915_OA_FORMAT_A32u40_A4u32_B8_C8,
1968 I915_OA_FORMAT_MAX /* non-ABI */
1971 enum drm_i915_perf_property_id {
1973 * Open the stream for a specific context handle (as used with
1974 * execbuffer2). A stream opened for a specific context this way
1975 * won't typically require root privileges.
1977 * This property is available in perf revision 1.
1979 DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1982 * A value of 1 requests the inclusion of raw OA unit reports as
1983 * part of stream samples.
1985 * This property is available in perf revision 1.
1987 DRM_I915_PERF_PROP_SAMPLE_OA,
1990 * The value specifies which set of OA unit metrics should be
1991 * configured, defining the contents of any OA unit reports.
1993 * This property is available in perf revision 1.
1995 DRM_I915_PERF_PROP_OA_METRICS_SET,
1998 * The value specifies the size and layout of OA unit reports.
2000 * This property is available in perf revision 1.
2002 DRM_I915_PERF_PROP_OA_FORMAT,
2005 * Specifying this property implicitly requests periodic OA unit
2006 * sampling and (at least on Haswell) the sampling frequency is derived
2007 * from this exponent as follows:
2009 * 80ns * 2^(period_exponent + 1)
2011 * This property is available in perf revision 1.
2013 DRM_I915_PERF_PROP_OA_EXPONENT,
2016 * Specifying this property is only valid when specify a context to
2017 * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
2018 * will hold preemption of the particular context we want to gather
2019 * performance data about. The execbuf2 submissions must include a
2020 * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
2022 * This property is available in perf revision 3.
2024 DRM_I915_PERF_PROP_HOLD_PREEMPTION,
2027 * Specifying this pins all contexts to the specified SSEU power
2028 * configuration for the duration of the recording.
2030 * This parameter's value is a pointer to a struct
2031 * drm_i915_gem_context_param_sseu.
2033 * This property is available in perf revision 4.
2035 DRM_I915_PERF_PROP_GLOBAL_SSEU,
2038 * This optional parameter specifies the timer interval in nanoseconds
2039 * at which the i915 driver will check the OA buffer for available data.
2040 * Minimum allowed value is 100 microseconds. A default value is used by
2041 * the driver if this parameter is not specified. Note that larger timer
2042 * values will reduce cpu consumption during OA perf captures. However,
2043 * excessively large values would potentially result in OA buffer
2044 * overwrites as captures reach end of the OA buffer.
2046 * This property is available in perf revision 5.
2048 DRM_I915_PERF_PROP_POLL_OA_PERIOD,
2050 DRM_I915_PERF_PROP_MAX /* non-ABI */
2053 struct drm_i915_perf_open_param {
2055 #define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
2056 #define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
2057 #define I915_PERF_FLAG_DISABLED (1<<2)
2059 /** The number of u64 (id, value) pairs */
2060 __u32 num_properties;
2063 * Pointer to array of u64 (id, value) pairs configuring the stream
2066 __u64 properties_ptr;
2070 * Enable data capture for a stream that was either opened in a disabled state
2071 * via I915_PERF_FLAG_DISABLED or was later disabled via
2072 * I915_PERF_IOCTL_DISABLE.
2074 * It is intended to be cheaper to disable and enable a stream than it may be
2075 * to close and re-open a stream with the same configuration.
2077 * It's undefined whether any pending data for the stream will be lost.
2079 * This ioctl is available in perf revision 1.
2081 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
2084 * Disable data capture for a stream.
2086 * It is an error to try and read a stream that is disabled.
2088 * This ioctl is available in perf revision 1.
2090 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
2093 * Change metrics_set captured by a stream.
2095 * If the stream is bound to a specific context, the configuration change
2096 * will performed inline with that context such that it takes effect before
2097 * the next execbuf submission.
2099 * Returns the previously bound metrics set id, or a negative error code.
2101 * This ioctl is available in perf revision 2.
2103 #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
2106 * Common to all i915 perf records
2108 struct drm_i915_perf_record_header {
2114 enum drm_i915_perf_record_type {
2117 * Samples are the work horse record type whose contents are extensible
2118 * and defined when opening an i915 perf stream based on the given
2121 * Boolean properties following the naming convention
2122 * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
2125 * The order of these sample properties given by userspace has no
2126 * affect on the ordering of data within a sample. The order is
2130 * struct drm_i915_perf_record_header header;
2132 * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
2135 DRM_I915_PERF_RECORD_SAMPLE = 1,
2138 * Indicates that one or more OA reports were not written by the
2139 * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
2140 * command collides with periodic sampling - which would be more likely
2141 * at higher sampling frequencies.
2143 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
2146 * An error occurred that resulted in all pending OA reports being lost.
2148 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
2150 DRM_I915_PERF_RECORD_MAX /* non-ABI */
2154 * Structure to upload perf dynamic configuration into the kernel.
2156 struct drm_i915_perf_oa_config {
2157 /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
2161 __u32 n_boolean_regs;
2165 * These fields are pointers to tuples of u32 values (register address,
2166 * value). For example the expected length of the buffer pointed by
2167 * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
2170 __u64 boolean_regs_ptr;
2171 __u64 flex_regs_ptr;
2174 struct drm_i915_query_item {
2176 #define DRM_I915_QUERY_TOPOLOGY_INFO 1
2177 #define DRM_I915_QUERY_ENGINE_INFO 2
2178 #define DRM_I915_QUERY_PERF_CONFIG 3
2179 /* Must be kept compact -- no holes and well documented */
2182 * When set to zero by userspace, this is filled with the size of the
2183 * data to be written at the data_ptr pointer. The kernel sets this
2184 * value to a negative value to signal an error on a particular query
2190 * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
2192 * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
2194 * - DRM_I915_QUERY_PERF_CONFIG_LIST
2195 * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
2196 * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
2199 #define DRM_I915_QUERY_PERF_CONFIG_LIST 1
2200 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
2201 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
2204 * Data will be written at the location pointed by data_ptr when the
2205 * value of length matches the length of the data to be written by the
2211 struct drm_i915_query {
2215 * Unused for now. Must be cleared to zero.
2220 * This points to an array of num_items drm_i915_query_item structures.
2226 * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
2228 * data: contains the 3 pieces of information :
2230 * - the slice mask with one bit per slice telling whether a slice is
2231 * available. The availability of slice X can be queried with the following
2234 * (data[X / 8] >> (X % 8)) & 1
2236 * - the subslice mask for each slice with one bit per subslice telling
2237 * whether a subslice is available. Gen12 has dual-subslices, which are
2238 * similar to two gen11 subslices. For gen12, this array represents dual-
2239 * subslices. The availability of subslice Y in slice X can be queried
2240 * with the following formula :
2242 * (data[subslice_offset +
2243 * X * subslice_stride +
2244 * Y / 8] >> (Y % 8)) & 1
2246 * - the EU mask for each subslice in each slice with one bit per EU telling
2247 * whether an EU is available. The availability of EU Z in subslice Y in
2248 * slice X can be queried with the following formula :
2251 * (X * max_subslices + Y) * eu_stride +
2252 * Z / 8] >> (Z % 8)) & 1
2254 struct drm_i915_query_topology_info {
2256 * Unused for now. Must be cleared to zero.
2261 __u16 max_subslices;
2262 __u16 max_eus_per_subslice;
2265 * Offset in data[] at which the subslice masks are stored.
2267 __u16 subslice_offset;
2270 * Stride at which each of the subslice masks for each slice are
2273 __u16 subslice_stride;
2276 * Offset in data[] at which the EU masks are stored.
2281 * Stride at which each of the EU masks for each subslice are stored.
2289 * struct drm_i915_engine_info
2291 * Describes one engine and it's capabilities as known to the driver.
2293 struct drm_i915_engine_info {
2294 /** Engine class and instance. */
2295 struct i915_engine_class_instance engine;
2297 /** Reserved field. */
2300 /** Engine flags. */
2303 /** Capabilities of this engine. */
2305 #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
2306 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
2308 /** Reserved fields. */
2313 * struct drm_i915_query_engine_info
2315 * Engine info query enumerates all engines known to the driver by filling in
2316 * an array of struct drm_i915_engine_info structures.
2318 struct drm_i915_query_engine_info {
2319 /** Number of struct drm_i915_engine_info structs following. */
2325 /** Marker for drm_i915_engine_info structures. */
2326 struct drm_i915_engine_info engines[];
2330 * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
2332 struct drm_i915_query_perf_config {
2335 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
2336 * this fields to the number of configurations available.
2341 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
2342 * i915 will use the value in this field as configuration
2343 * identifier to decide what data to write into config_ptr.
2348 * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
2349 * i915 will use the value in this field as configuration
2350 * identifier to decide what data to write into config_ptr.
2352 * String formatted like "%08x-%04x-%04x-%04x-%012x"
2358 * Unused for now. Must be cleared to zero.
2363 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
2364 * write an array of __u64 of configuration identifiers.
2366 * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
2367 * write a struct drm_i915_perf_oa_config. If the following fields of
2368 * drm_i915_perf_oa_config are set not set to 0, i915 will write into
2369 * the associated pointers the values of submitted when the
2370 * configuration was created :
2379 #if defined(__cplusplus)
2383 #endif /* _UAPI_I915_DRM_H_ */