1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2014 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #ifndef __AMDGPU_DRM_H__
33 #define __AMDGPU_DRM_H__
37 #if defined(__cplusplus)
41 #define DRM_AMDGPU_GEM_CREATE 0x00
42 #define DRM_AMDGPU_GEM_MMAP 0x01
43 #define DRM_AMDGPU_CTX 0x02
44 #define DRM_AMDGPU_BO_LIST 0x03
45 #define DRM_AMDGPU_CS 0x04
46 #define DRM_AMDGPU_INFO 0x05
47 #define DRM_AMDGPU_GEM_METADATA 0x06
48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49 #define DRM_AMDGPU_GEM_VA 0x08
50 #define DRM_AMDGPU_WAIT_CS 0x09
51 #define DRM_AMDGPU_GEM_OP 0x10
52 #define DRM_AMDGPU_GEM_USERPTR 0x11
53 #define DRM_AMDGPU_WAIT_FENCES 0x12
54 #define DRM_AMDGPU_VM 0x13
55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56 #define DRM_AMDGPU_SCHED 0x15
58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
79 * Memory in this pool could be swapped out to disk if there is pressure.
81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
83 * pages of system memory, allows GPU access system memory in a linezrized
86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
87 * carved out by the BIOS.
89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
90 * across shader threads.
92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
93 * execution of all the waves on a device.
95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
98 #define AMDGPU_GEM_DOMAIN_CPU 0x1
99 #define AMDGPU_GEM_DOMAIN_GTT 0x2
100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
101 #define AMDGPU_GEM_DOMAIN_GDS 0x8
102 #define AMDGPU_GEM_DOMAIN_GWS 0x10
103 #define AMDGPU_GEM_DOMAIN_OA 0x20
104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
105 AMDGPU_GEM_DOMAIN_GTT | \
106 AMDGPU_GEM_DOMAIN_VRAM | \
107 AMDGPU_GEM_DOMAIN_GDS | \
108 AMDGPU_GEM_DOMAIN_GWS | \
109 AMDGPU_GEM_DOMAIN_OA)
111 /* Flag that CPU access will be required for the case of VRAM domain */
112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
113 /* Flag that CPU access will not work, this VRAM domain is invisible */
114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
115 /* Flag that USWC attributes should be used for GTT */
116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
117 /* Flag that the memory should be in VRAM and cleared */
118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
119 /* Flag that create shadow bo(GTT) while allocating vram bo */
120 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
121 /* Flag that allocating the BO should use linear VRAM */
122 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
123 /* Flag that BO is always valid in this VM */
124 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
125 /* Flag that BO sharing will be explicitly synchronized */
126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype
128 * for the second page onward should be set to NC.
130 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
132 struct drm_amdgpu_gem_create_in {
133 /** the requested memory size */
135 /** physical start_addr alignment in bytes for some HW requirements */
137 /** the requested memory domains */
139 /** allocation flags */
143 struct drm_amdgpu_gem_create_out {
144 /** returned GEM object handle */
149 union drm_amdgpu_gem_create {
150 struct drm_amdgpu_gem_create_in in;
151 struct drm_amdgpu_gem_create_out out;
154 /** Opcode to create new residency list. */
155 #define AMDGPU_BO_LIST_OP_CREATE 0
156 /** Opcode to destroy previously created residency list */
157 #define AMDGPU_BO_LIST_OP_DESTROY 1
158 /** Opcode to update resource information in the list */
159 #define AMDGPU_BO_LIST_OP_UPDATE 2
161 struct drm_amdgpu_bo_list_in {
162 /** Type of operation */
164 /** Handle of list or 0 if we want to create one */
166 /** Number of BOs in list */
168 /** Size of each element describing BO */
170 /** Pointer to array describing BOs */
174 struct drm_amdgpu_bo_list_entry {
177 /** New (if specified) BO priority to be used during migration */
181 struct drm_amdgpu_bo_list_out {
182 /** Handle of resource list */
187 union drm_amdgpu_bo_list {
188 struct drm_amdgpu_bo_list_in in;
189 struct drm_amdgpu_bo_list_out out;
192 /* context related */
193 #define AMDGPU_CTX_OP_ALLOC_CTX 1
194 #define AMDGPU_CTX_OP_FREE_CTX 2
195 #define AMDGPU_CTX_OP_QUERY_STATE 3
196 #define AMDGPU_CTX_OP_QUERY_STATE2 4
198 /* GPU reset status */
199 #define AMDGPU_CTX_NO_RESET 0
200 /* this the context caused it */
201 #define AMDGPU_CTX_GUILTY_RESET 1
202 /* some other context caused it */
203 #define AMDGPU_CTX_INNOCENT_RESET 2
205 #define AMDGPU_CTX_UNKNOWN_RESET 3
207 /* indicate gpu reset occured after ctx created */
208 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
209 /* indicate vram lost occured after ctx created */
210 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
211 /* indicate some job from this context once cause gpu hang */
212 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
213 /* indicate some errors are detected by RAS */
214 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
215 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
217 /* Context priority level */
218 #define AMDGPU_CTX_PRIORITY_UNSET -2048
219 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
220 #define AMDGPU_CTX_PRIORITY_LOW -512
221 #define AMDGPU_CTX_PRIORITY_NORMAL 0
223 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
224 * CAP_SYS_NICE or DRM_MASTER
226 #define AMDGPU_CTX_PRIORITY_HIGH 512
227 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
229 struct drm_amdgpu_ctx_in {
230 /** AMDGPU_CTX_OP_* */
232 /** For future use, no flags defined so far */
235 /** AMDGPU_CTX_PRIORITY_* */
239 union drm_amdgpu_ctx_out {
246 /** For future use, no flags defined so far */
248 /** Number of resets caused by this context so far. */
250 /** Reset status since the last call of the ioctl. */
255 union drm_amdgpu_ctx {
256 struct drm_amdgpu_ctx_in in;
257 union drm_amdgpu_ctx_out out;
261 #define AMDGPU_VM_OP_RESERVE_VMID 1
262 #define AMDGPU_VM_OP_UNRESERVE_VMID 2
264 struct drm_amdgpu_vm_in {
265 /** AMDGPU_VM_OP_* */
270 struct drm_amdgpu_vm_out {
271 /** For future use, no flags defined so far */
275 union drm_amdgpu_vm {
276 struct drm_amdgpu_vm_in in;
277 struct drm_amdgpu_vm_out out;
281 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
282 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
284 struct drm_amdgpu_sched_in {
285 /* AMDGPU_SCHED_OP_* */
288 /** AMDGPU_CTX_PRIORITY_* */
293 union drm_amdgpu_sched {
294 struct drm_amdgpu_sched_in in;
298 * This is not a reliable API and you should expect it to fail for any
299 * number of reasons and have fallback path that do not use userptr to
300 * perform any operation.
302 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
303 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
304 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
305 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
307 struct drm_amdgpu_gem_userptr {
310 /* AMDGPU_GEM_USERPTR_* */
312 /* Resulting GEM handle */
317 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
318 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
319 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
320 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
321 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
322 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
323 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
324 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
325 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
326 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
327 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
328 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
329 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
330 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
331 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
332 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21
333 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3
335 /* GFX9 and later: */
336 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
337 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
338 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
339 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
340 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
341 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
342 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
343 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
345 /* Set/Get helpers for tiling flags. */
346 #define AMDGPU_TILING_SET(field, value) \
347 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
348 #define AMDGPU_TILING_GET(value, field) \
349 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
351 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
352 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
354 /** The same structure is shared for input/output */
355 struct drm_amdgpu_gem_metadata {
356 /** GEM Object handle */
358 /** Do we want get or set metadata */
361 /** For future use, no flags defined so far */
363 /** family specific tiling info */
365 __u32 data_size_bytes;
370 struct drm_amdgpu_gem_mmap_in {
371 /** the GEM object handle */
376 struct drm_amdgpu_gem_mmap_out {
377 /** mmap offset from the vma offset manager */
381 union drm_amdgpu_gem_mmap {
382 struct drm_amdgpu_gem_mmap_in in;
383 struct drm_amdgpu_gem_mmap_out out;
386 struct drm_amdgpu_gem_wait_idle_in {
387 /** GEM object handle */
389 /** For future use, no flags defined so far */
391 /** Absolute timeout to wait */
395 struct drm_amdgpu_gem_wait_idle_out {
396 /** BO status: 0 - BO is idle, 1 - BO is busy */
398 /** Returned current memory domain */
402 union drm_amdgpu_gem_wait_idle {
403 struct drm_amdgpu_gem_wait_idle_in in;
404 struct drm_amdgpu_gem_wait_idle_out out;
407 struct drm_amdgpu_wait_cs_in {
408 /* Command submission handle
409 * handle equals 0 means none to wait for
410 * handle equals ~0ull means wait for the latest sequence number
413 /** Absolute timeout to wait */
421 struct drm_amdgpu_wait_cs_out {
422 /** CS status: 0 - CS completed, 1 - CS still busy */
426 union drm_amdgpu_wait_cs {
427 struct drm_amdgpu_wait_cs_in in;
428 struct drm_amdgpu_wait_cs_out out;
431 struct drm_amdgpu_fence {
439 struct drm_amdgpu_wait_fences_in {
440 /** This points to uint64_t * which points to fences */
447 struct drm_amdgpu_wait_fences_out {
449 __u32 first_signaled;
452 union drm_amdgpu_wait_fences {
453 struct drm_amdgpu_wait_fences_in in;
454 struct drm_amdgpu_wait_fences_out out;
457 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
458 #define AMDGPU_GEM_OP_SET_PLACEMENT 1
460 /* Sets or returns a value associated with a buffer. */
461 struct drm_amdgpu_gem_op {
462 /** GEM object handle */
464 /** AMDGPU_GEM_OP_* */
466 /** Input or return value */
470 #define AMDGPU_VA_OP_MAP 1
471 #define AMDGPU_VA_OP_UNMAP 2
472 #define AMDGPU_VA_OP_CLEAR 3
473 #define AMDGPU_VA_OP_REPLACE 4
475 /* Delay the page table update till the next CS */
476 #define AMDGPU_VM_DELAY_UPDATE (1 << 0)
479 /* readable mapping */
480 #define AMDGPU_VM_PAGE_READABLE (1 << 1)
481 /* writable mapping */
482 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
483 /* executable mapping, new for VI */
484 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
485 /* partially resident texture */
486 #define AMDGPU_VM_PAGE_PRT (1 << 4)
487 /* MTYPE flags use bit 5 to 8 */
488 #define AMDGPU_VM_MTYPE_MASK (0xf << 5)
489 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
490 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
491 /* Use NC MTYPE instead of default MTYPE */
492 #define AMDGPU_VM_MTYPE_NC (1 << 5)
493 /* Use WC MTYPE instead of default MTYPE */
494 #define AMDGPU_VM_MTYPE_WC (2 << 5)
495 /* Use CC MTYPE instead of default MTYPE */
496 #define AMDGPU_VM_MTYPE_CC (3 << 5)
497 /* Use UC MTYPE instead of default MTYPE */
498 #define AMDGPU_VM_MTYPE_UC (4 << 5)
500 struct drm_amdgpu_gem_va {
501 /** GEM object handle */
504 /** AMDGPU_VA_OP_* */
506 /** AMDGPU_VM_PAGE_* */
508 /** va address to assign . Must be correctly aligned.*/
510 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
512 /** Specify mapping size. Must be correctly aligned. */
516 #define AMDGPU_HW_IP_GFX 0
517 #define AMDGPU_HW_IP_COMPUTE 1
518 #define AMDGPU_HW_IP_DMA 2
519 #define AMDGPU_HW_IP_UVD 3
520 #define AMDGPU_HW_IP_VCE 4
521 #define AMDGPU_HW_IP_UVD_ENC 5
522 #define AMDGPU_HW_IP_VCN_DEC 6
523 #define AMDGPU_HW_IP_VCN_ENC 7
524 #define AMDGPU_HW_IP_VCN_JPEG 8
525 #define AMDGPU_HW_IP_NUM 9
527 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
529 #define AMDGPU_CHUNK_ID_IB 0x01
530 #define AMDGPU_CHUNK_ID_FENCE 0x02
531 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
532 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
533 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
534 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
535 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
536 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
537 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
539 struct drm_amdgpu_cs_chunk {
545 struct drm_amdgpu_cs_in {
546 /** Rendering context id */
548 /** Handle of resource list associated with CS */
549 __u32 bo_list_handle;
552 /** this points to __u64 * which point to cs chunks */
556 struct drm_amdgpu_cs_out {
560 union drm_amdgpu_cs {
561 struct drm_amdgpu_cs_in in;
562 struct drm_amdgpu_cs_out out;
565 /* Specify flags to be used for IB */
567 /* This IB should be submitted to CE */
568 #define AMDGPU_IB_FLAG_CE (1<<0)
570 /* Preamble flag, which means the IB could be dropped if no context switch */
571 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
573 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
574 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
576 /* The IB fence should do the L2 writeback but not invalidate any shader
577 * caches (L2/vL1/sL1/I$). */
578 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
580 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
581 * This will reset wave ID counters for the IB.
583 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
585 struct drm_amdgpu_cs_chunk_ib {
587 /** AMDGPU_IB_FLAG_* */
589 /** Virtual address to begin IB execution */
591 /** Size of submission */
593 /** HW IP to submit to */
595 /** HW IP index of the same type to submit to */
597 /** Ring index to submit to */
601 struct drm_amdgpu_cs_chunk_dep {
609 struct drm_amdgpu_cs_chunk_fence {
614 struct drm_amdgpu_cs_chunk_sem {
618 struct drm_amdgpu_cs_chunk_syncobj {
624 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
625 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
626 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
628 union drm_amdgpu_fence_to_handle {
630 struct drm_amdgpu_fence fence;
639 struct drm_amdgpu_cs_chunk_data {
641 struct drm_amdgpu_cs_chunk_ib ib_data;
642 struct drm_amdgpu_cs_chunk_fence fence_data;
647 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
650 #define AMDGPU_IDS_FLAGS_FUSION 0x1
651 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
653 /* indicate if acceleration can be working */
654 #define AMDGPU_INFO_ACCEL_WORKING 0x00
655 /* get the crtc_id from the mode object id? */
656 #define AMDGPU_INFO_CRTC_FROM_ID 0x01
657 /* query hw IP info */
658 #define AMDGPU_INFO_HW_IP_INFO 0x02
659 /* query hw IP instance count for the specified type */
660 #define AMDGPU_INFO_HW_IP_COUNT 0x03
661 /* timestamp for GL_ARB_timer_query */
662 #define AMDGPU_INFO_TIMESTAMP 0x05
663 /* Query the firmware version */
664 #define AMDGPU_INFO_FW_VERSION 0x0e
665 /* Subquery id: Query VCE firmware version */
666 #define AMDGPU_INFO_FW_VCE 0x1
667 /* Subquery id: Query UVD firmware version */
668 #define AMDGPU_INFO_FW_UVD 0x2
669 /* Subquery id: Query GMC firmware version */
670 #define AMDGPU_INFO_FW_GMC 0x03
671 /* Subquery id: Query GFX ME firmware version */
672 #define AMDGPU_INFO_FW_GFX_ME 0x04
673 /* Subquery id: Query GFX PFP firmware version */
674 #define AMDGPU_INFO_FW_GFX_PFP 0x05
675 /* Subquery id: Query GFX CE firmware version */
676 #define AMDGPU_INFO_FW_GFX_CE 0x06
677 /* Subquery id: Query GFX RLC firmware version */
678 #define AMDGPU_INFO_FW_GFX_RLC 0x07
679 /* Subquery id: Query GFX MEC firmware version */
680 #define AMDGPU_INFO_FW_GFX_MEC 0x08
681 /* Subquery id: Query SMC firmware version */
682 #define AMDGPU_INFO_FW_SMC 0x0a
683 /* Subquery id: Query SDMA firmware version */
684 #define AMDGPU_INFO_FW_SDMA 0x0b
685 /* Subquery id: Query PSP SOS firmware version */
686 #define AMDGPU_INFO_FW_SOS 0x0c
687 /* Subquery id: Query PSP ASD firmware version */
688 #define AMDGPU_INFO_FW_ASD 0x0d
689 /* Subquery id: Query VCN firmware version */
690 #define AMDGPU_INFO_FW_VCN 0x0e
691 /* Subquery id: Query GFX RLC SRLC firmware version */
692 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
693 /* Subquery id: Query GFX RLC SRLG firmware version */
694 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
695 /* Subquery id: Query GFX RLC SRLS firmware version */
696 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
697 /* Subquery id: Query DMCU firmware version */
698 #define AMDGPU_INFO_FW_DMCU 0x12
699 #define AMDGPU_INFO_FW_TA 0x13
700 /* number of bytes moved for TTM migration */
701 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
702 /* the used VRAM size */
703 #define AMDGPU_INFO_VRAM_USAGE 0x10
704 /* the used GTT size */
705 #define AMDGPU_INFO_GTT_USAGE 0x11
706 /* Information about GDS, etc. resource configuration */
707 #define AMDGPU_INFO_GDS_CONFIG 0x13
708 /* Query information about VRAM and GTT domains */
709 #define AMDGPU_INFO_VRAM_GTT 0x14
710 /* Query information about register in MMR address space*/
711 #define AMDGPU_INFO_READ_MMR_REG 0x15
712 /* Query information about device: rev id, family, etc. */
713 #define AMDGPU_INFO_DEV_INFO 0x16
714 /* visible vram usage */
715 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
716 /* number of TTM buffer evictions */
717 #define AMDGPU_INFO_NUM_EVICTIONS 0x18
718 /* Query memory about VRAM and GTT domains */
719 #define AMDGPU_INFO_MEMORY 0x19
720 /* Query vce clock table */
721 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
722 /* Query vbios related information */
723 #define AMDGPU_INFO_VBIOS 0x1B
724 /* Subquery id: Query vbios size */
725 #define AMDGPU_INFO_VBIOS_SIZE 0x1
726 /* Subquery id: Query vbios image */
727 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
728 /* Query UVD handles */
729 #define AMDGPU_INFO_NUM_HANDLES 0x1C
730 /* Query sensor related information */
731 #define AMDGPU_INFO_SENSOR 0x1D
732 /* Subquery id: Query GPU shader clock */
733 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
734 /* Subquery id: Query GPU memory clock */
735 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
736 /* Subquery id: Query GPU temperature */
737 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
738 /* Subquery id: Query GPU load */
739 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
740 /* Subquery id: Query average GPU power */
741 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
742 /* Subquery id: Query northbridge voltage */
743 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
744 /* Subquery id: Query graphics voltage */
745 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
746 /* Subquery id: Query GPU stable pstate shader clock */
747 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
748 /* Subquery id: Query GPU stable pstate memory clock */
749 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
750 /* Number of VRAM page faults on CPU access. */
751 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
752 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
753 /* query ras mask of enabled features*/
754 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
756 /* RAS MASK: UMC (VRAM) */
757 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
759 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
761 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
762 /* RAS MASK: MMHUB */
763 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
764 /* RAS MASK: ATHUB */
765 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
767 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
769 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
771 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
773 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
775 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
777 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
779 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
781 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
783 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
785 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
786 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
787 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
788 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
790 struct drm_amdgpu_query_fw {
791 /** AMDGPU_INFO_FW_* */
794 * Index of the IP if there are more IPs of
799 * Index of the engine. Whether this is used depends
800 * on the firmware type. (e.g. MEC, SDMA)
806 /* Input structure for the INFO ioctl */
807 struct drm_amdgpu_info {
808 /* Where the return value will be stored */
809 __u64 return_pointer;
810 /* The size of the return value. Just like "size" in "snprintf",
811 * it limits how many bytes the kernel can write. */
813 /* The query request id. */
823 /** AMDGPU_HW_IP_* */
826 * Index of the IP if there are more IPs of the same
827 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
834 /** number of registers to read */
837 /** For future use, no flags defined so far */
841 struct drm_amdgpu_query_fw query_fw;
854 struct drm_amdgpu_info_gds {
855 /** GDS GFX partition size */
856 __u32 gds_gfx_partition_size;
857 /** GDS compute partition size */
858 __u32 compute_partition_size;
859 /** total GDS memory size */
860 __u32 gds_total_size;
861 /** GWS size per GFX partition */
862 __u32 gws_per_gfx_partition;
863 /** GSW size per compute partition */
864 __u32 gws_per_compute_partition;
865 /** OA size per GFX partition */
866 __u32 oa_per_gfx_partition;
867 /** OA size per compute partition */
868 __u32 oa_per_compute_partition;
872 struct drm_amdgpu_info_vram_gtt {
874 __u64 vram_cpu_accessible_size;
878 struct drm_amdgpu_heap_info {
879 /** max. physical memory */
880 __u64 total_heap_size;
882 /** Theoretical max. available memory in the given heap */
883 __u64 usable_heap_size;
886 * Number of bytes allocated in the heap. This includes all processes
887 * and private allocations in the kernel. It changes when new buffers
888 * are allocated, freed, and moved. It cannot be larger than
894 * Theoretical possible max. size of buffer which
895 * could be allocated in the given heap
897 __u64 max_allocation;
900 struct drm_amdgpu_memory_info {
901 struct drm_amdgpu_heap_info vram;
902 struct drm_amdgpu_heap_info cpu_accessible_vram;
903 struct drm_amdgpu_heap_info gtt;
906 struct drm_amdgpu_info_firmware {
911 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
912 #define AMDGPU_VRAM_TYPE_GDDR1 1
913 #define AMDGPU_VRAM_TYPE_DDR2 2
914 #define AMDGPU_VRAM_TYPE_GDDR3 3
915 #define AMDGPU_VRAM_TYPE_GDDR4 4
916 #define AMDGPU_VRAM_TYPE_GDDR5 5
917 #define AMDGPU_VRAM_TYPE_HBM 6
918 #define AMDGPU_VRAM_TYPE_DDR3 7
919 #define AMDGPU_VRAM_TYPE_DDR4 8
920 #define AMDGPU_VRAM_TYPE_GDDR6 9
922 struct drm_amdgpu_info_device {
925 /** Internal chip revision: A0, A1, etc.) */
928 /** Revision id in PCI Config space */
931 __u32 num_shader_engines;
932 __u32 num_shader_arrays_per_engine;
934 __u32 gpu_counter_freq;
935 __u64 max_engine_clock;
936 __u64 max_memory_clock;
938 __u32 cu_active_number;
939 /* NOTE: cu_ao_mask is INVALID, DON'T use it */
941 __u32 cu_bitmap[4][4];
942 /** Render backend pipe mask. One render backend is CB+DB. */
943 __u32 enabled_rb_pipes_mask;
945 __u32 num_hw_gfx_contexts;
948 /** Starting virtual address for UMDs. */
949 __u64 virtual_address_offset;
950 /** The maximum virtual address */
951 __u64 virtual_address_max;
952 /** Required alignment of virtual addresses. */
953 __u32 virtual_address_alignment;
954 /** Page table entry - fragment size */
955 __u32 pte_fragment_size;
956 __u32 gart_page_size;
957 /** constant engine ram size*/
959 /** video memory type info*/
961 /** video memory bit width*/
962 __u32 vram_bit_width;
963 /* vce harvesting instance */
964 __u32 vce_harvest_config;
965 /* gfx double offchip LDS buffers */
966 __u32 gc_double_offchip_lds_buf;
967 /* NGG Primitive Buffer */
968 __u64 prim_buf_gpu_addr;
969 /* NGG Position Buffer */
970 __u64 pos_buf_gpu_addr;
971 /* NGG Control Sideband */
972 __u64 cntl_sb_buf_gpu_addr;
973 /* NGG Parameter Cache */
974 __u64 param_buf_gpu_addr;
977 __u32 cntl_sb_buf_size;
978 __u32 param_buf_size;
980 __u32 wave_front_size;
981 /* shader visible vgprs*/
982 __u32 num_shader_visible_vgprs;
983 /* CU per shader array*/
985 /* number of tcc blocks*/
986 __u32 num_tcc_blocks;
987 /* gs vgt table depth*/
988 __u32 gs_vgt_table_depth;
989 /* gs primitive buffer depth*/
990 __u32 gs_prim_buffer_depth;
991 /* max gs wavefront per vgt*/
992 __u32 max_gs_waves_per_vgt;
994 /* always on cu bitmap */
995 __u32 cu_ao_bitmap[4][4];
996 /** Starting high virtual address for UMDs. */
997 __u64 high_va_offset;
998 /** The maximum high virtual address */
1000 /* gfx10 pa_sc_tile_steering_override */
1001 __u32 pa_sc_tile_steering_override;
1004 struct drm_amdgpu_info_hw_ip {
1005 /** Version of h/w IP */
1006 __u32 hw_ip_version_major;
1007 __u32 hw_ip_version_minor;
1009 __u64 capabilities_flags;
1010 /** command buffer address start alignment*/
1011 __u32 ib_start_alignment;
1012 /** command buffer size alignment*/
1013 __u32 ib_size_alignment;
1014 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
1015 __u32 available_rings;
1019 struct drm_amdgpu_info_num_handles {
1020 /** Max handles as supported by firmware for UVD */
1021 __u32 uvd_max_handles;
1022 /** Handles currently in use for UVD */
1023 __u32 uvd_used_handles;
1026 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
1028 struct drm_amdgpu_info_vce_clock_table_entry {
1038 struct drm_amdgpu_info_vce_clock_table {
1039 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
1040 __u32 num_valid_entries;
1045 * Supported GPU families
1047 #define AMDGPU_FAMILY_UNKNOWN 0
1048 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
1049 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
1050 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
1051 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
1052 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
1053 #define AMDGPU_FAMILY_AI 141 /* Vega10 */
1054 #define AMDGPU_FAMILY_RV 142 /* Raven */
1055 #define AMDGPU_FAMILY_NV 143 /* Navi10 */
1057 #if defined(__cplusplus)