1 /* SPDX-License-Identifier: GPL-2.0 */
6 #ifndef __SOUND_HDAUDIO_H
7 #define __SOUND_HDAUDIO_H
9 #include <linux/device.h>
10 #include <linux/interrupt.h>
12 #include <linux/io-64-nonatomic-lo-hi.h>
13 #include <linux/iopoll.h>
14 #include <linux/pci.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/timecounter.h>
17 #include <sound/core.h>
18 #include <sound/pcm.h>
19 #include <sound/memalloc.h>
20 #include <sound/hda_verbs.h>
21 #include <drm/i915_component.h>
24 typedef u16 hda_nid_t;
30 struct hdac_widget_tree;
36 extern const struct bus_type snd_hda_bus_type;
44 unsigned int elem_size;
45 unsigned int alloc_align;
50 * HD-audio codec base device
56 unsigned int addr; /* codec address */
57 struct list_head list; /* list point for bus codec_list */
59 hda_nid_t afg; /* AFG node id */
60 hda_nid_t mfg; /* MFG node id */
63 unsigned int vendor_id;
64 unsigned int subsystem_id;
65 unsigned int revision_id;
66 unsigned int afg_function_id;
67 unsigned int mfg_function_id;
68 unsigned int afg_unsol:1;
69 unsigned int mfg_unsol:1;
71 unsigned int power_caps; /* FG power caps */
73 const char *vendor_name; /* codec vendor name */
74 const char *chip_name; /* codec chip name */
76 /* verb exec op override */
77 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd,
78 unsigned int flags, unsigned int *res);
81 unsigned int num_nodes;
82 hda_nid_t start_nid, end_nid;
85 atomic_t in_pm; /* suspend/resume being performed */
88 struct mutex widget_lock;
89 struct hdac_widget_tree *widgets;
92 struct regmap *regmap;
93 struct mutex regmap_lock;
94 struct snd_array vendor_verbs;
95 bool lazy_cache:1; /* don't wake up for writes */
96 bool caps_overwriting:1; /* caps overwrite being in process */
97 bool cache_coef:1; /* cache COEF read/write too */
98 unsigned int registered:1; /* codec was registered */
101 /* device/driver type used for matching */
109 SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */
110 SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */
111 SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */
116 HDA_INPUT, HDA_OUTPUT
119 #define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev)
121 int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus,
122 const char *name, unsigned int addr);
123 void snd_hdac_device_exit(struct hdac_device *dev);
124 int snd_hdac_device_register(struct hdac_device *codec);
125 void snd_hdac_device_unregister(struct hdac_device *codec);
126 int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name);
127 int snd_hdac_codec_modalias(const struct hdac_device *hdac, char *buf, size_t size);
129 int snd_hdac_refresh_widgets(struct hdac_device *codec);
131 int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid,
132 unsigned int verb, unsigned int parm, unsigned int *res);
133 int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm,
135 int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid,
137 int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid,
138 unsigned int parm, unsigned int val);
139 int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,
140 hda_nid_t *conn_list, int max_conns);
141 int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,
142 hda_nid_t *start_id);
143 unsigned int snd_hdac_stream_format_bits(snd_pcm_format_t format, snd_pcm_subformat_t subformat,
144 unsigned int maxbits);
145 unsigned int snd_hdac_stream_format(unsigned int channels, unsigned int bits, unsigned int rate);
146 unsigned int snd_hdac_spdif_stream_format(unsigned int channels, unsigned int bits,
147 unsigned int rate, unsigned short spdif_ctls);
148 int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,
149 u32 *ratesp, u64 *formatsp, u32 *subformatsp,
151 bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,
152 unsigned int format);
154 int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid,
155 int flags, unsigned int verb, unsigned int parm);
156 int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid,
157 int flags, unsigned int verb, unsigned int parm);
158 bool snd_hdac_check_power_state(struct hdac_device *hdac,
159 hda_nid_t nid, unsigned int target_state);
160 unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac,
161 hda_nid_t nid, unsigned int target_state);
163 * snd_hdac_read_parm - read a codec parameter
164 * @codec: the codec object
165 * @nid: NID to read a parameter
166 * @parm: parameter to read
168 * Returns -1 for error. If you need to distinguish the error more
169 * strictly, use _snd_hdac_read_parm() directly.
171 static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid,
176 return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val;
180 int snd_hdac_power_up(struct hdac_device *codec);
181 int snd_hdac_power_down(struct hdac_device *codec);
182 int snd_hdac_power_up_pm(struct hdac_device *codec);
183 int snd_hdac_power_down_pm(struct hdac_device *codec);
184 int snd_hdac_keep_power_up(struct hdac_device *codec);
186 /* call this at entering into suspend/resume callbacks in codec driver */
187 static inline void snd_hdac_enter_pm(struct hdac_device *codec)
189 atomic_inc(&codec->in_pm);
192 /* call this at leaving from suspend/resume callbacks in codec driver */
193 static inline void snd_hdac_leave_pm(struct hdac_device *codec)
195 atomic_dec(&codec->in_pm);
198 static inline bool snd_hdac_is_in_pm(struct hdac_device *codec)
200 return atomic_read(&codec->in_pm);
203 static inline bool snd_hdac_is_power_on(struct hdac_device *codec)
205 return !pm_runtime_suspended(&codec->dev);
208 static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; }
209 static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; }
210 static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; }
211 static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; }
212 static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; }
213 static inline void snd_hdac_enter_pm(struct hdac_device *codec) {}
214 static inline void snd_hdac_leave_pm(struct hdac_device *codec) {}
215 static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; }
216 static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; }
220 * HD-audio codec base driver
223 struct device_driver driver;
225 const struct hda_device_id *id_table;
226 int (*match)(struct hdac_device *dev, struct hdac_driver *drv);
227 void (*unsol_event)(struct hdac_device *dev, unsigned int event);
229 /* fields used by ext bus APIs */
230 int (*probe)(struct hdac_device *dev);
231 int (*remove)(struct hdac_device *dev);
232 void (*shutdown)(struct hdac_device *dev);
235 #define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)
237 const struct hda_device_id *
238 hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv);
243 struct hdac_bus_ops {
244 /* send a single command */
245 int (*command)(struct hdac_bus *bus, unsigned int cmd);
246 /* get a response from the last command */
247 int (*get_response)(struct hdac_bus *bus, unsigned int addr,
249 /* notify of codec link power-up/down */
250 void (*link_power)(struct hdac_device *hdev, bool enable);
254 * ops used for ASoC HDA codec drivers
256 struct hdac_ext_bus_ops {
257 int (*hdev_attach)(struct hdac_device *hdev);
258 int (*hdev_detach)(struct hdac_device *hdev);
261 #define HDA_UNSOL_QUEUE_SIZE 64
262 #define HDA_MAX_CODECS 8 /* limit by controller side */
267 * Each CORB entry is 4byte, RIRB is 8byte
270 __le32 *buf; /* virtual address of CORB/RIRB buffer */
271 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
272 unsigned short rp, wp; /* RIRB read/write pointers */
273 int cmds[HDA_MAX_CODECS]; /* number of pending requests */
274 u32 res[HDA_MAX_CODECS]; /* last read value */
278 * HD-audio bus base driver
280 * @ppcap: pp capabilities pointer
281 * @spbcap: SPIB capabilities pointer
282 * @mlcap: MultiLink capabilities pointer
283 * @gtscap: gts capabilities pointer
284 * @drsmcap: dma resume capabilities pointer
285 * @num_streams: streams supported
286 * @idx: HDA link index
287 * @hlink_list: link list of HDA links
288 * @lock: lock for link and display power mgmt
289 * @cmd_dma_state: state of cmd DMAs: CORB and RIRB
293 const struct hdac_bus_ops *ops;
294 const struct hdac_ext_bus_ops *ext_ops;
298 void __iomem *remap_addr;
302 void __iomem *spbcap;
304 void __iomem *gtscap;
305 void __iomem *drsmcap;
307 /* codec linked list */
308 struct list_head codec_list;
309 unsigned int num_codecs;
311 /* link caddr -> codec */
312 struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
314 /* unsolicited event queue */
315 u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
316 unsigned int unsol_rp, unsol_wp;
317 struct work_struct unsol_work;
319 /* bit flags of detected codecs */
320 unsigned long codec_mask;
322 /* bit flags of powered codecs */
323 unsigned long codec_powered;
328 unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */
329 wait_queue_head_t rirb_wq;
331 /* CORB/RIRB and position buffers */
332 struct snd_dma_buffer rb;
333 struct snd_dma_buffer posbuf;
334 int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */
336 /* hdac_stream linked list */
337 struct list_head stream_list;
339 /* operation state */
340 bool chip_init:1; /* h/w initialized */
343 bool aligned_mmio:1; /* aligned MMIO access */
344 bool sync_write:1; /* sync after verb write */
345 bool use_posbuf:1; /* use position buffer */
346 bool snoop:1; /* enable snooping */
347 bool align_bdle_4k:1; /* BDLE align 4K boundary */
348 bool reverse_assign:1; /* assign devices in reverse order */
349 bool corbrp_self_clear:1; /* CORBRP clears itself after reset */
351 bool needs_damn_long_delay:1;
352 bool not_use_interrupts:1; /* prohibiting the RIRB IRQ */
353 bool access_sdnctl_in_dword:1; /* accessing the sdnctl register by dword */
357 int bdl_pos_adj; /* BDL position adjustment */
359 /* delay time in us for dma stop */
360 unsigned int dma_stop_delay;
364 struct mutex cmd_mutex;
367 /* DRM component interface */
368 struct drm_audio_component *audio_component;
369 long display_power_status;
370 unsigned long display_power_active;
372 /* parameters required for enhanced capabilities */
376 /* link management */
377 struct list_head hlink_list;
380 /* factor used to derive STRIPE control value */
381 unsigned int sdo_limit;
384 int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
385 const struct hdac_bus_ops *ops);
386 void snd_hdac_bus_exit(struct hdac_bus *bus);
387 int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
388 unsigned int cmd, unsigned int *res);
390 void snd_hdac_codec_link_up(struct hdac_device *codec);
391 void snd_hdac_codec_link_down(struct hdac_device *codec);
393 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
394 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
396 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus);
398 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);
399 void snd_hdac_bus_stop_chip(struct hdac_bus *bus);
400 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);
401 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);
402 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);
403 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);
404 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset);
405 void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable);
407 void snd_hdac_bus_update_rirb(struct hdac_bus *bus);
408 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
409 void (*ack)(struct hdac_bus *,
410 struct hdac_stream *));
412 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);
413 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);
415 #ifdef CONFIG_SND_HDA_ALIGNED_MMIO
416 unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask);
417 void snd_hdac_aligned_write(unsigned int val, void __iomem *addr,
419 #define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio
421 #define snd_hdac_aligned_mmio(bus) false
422 #define snd_hdac_aligned_read(addr, mask) 0
423 #define snd_hdac_aligned_write(val, addr, mask) do {} while (0)
426 static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr,
429 if (snd_hdac_aligned_mmio(bus))
430 snd_hdac_aligned_write(val, addr, 0xff);
435 static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr,
438 if (snd_hdac_aligned_mmio(bus))
439 snd_hdac_aligned_write(val, addr, 0xffff);
444 static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr)
446 return snd_hdac_aligned_mmio(bus) ?
447 snd_hdac_aligned_read(addr, 0xff) : readb(addr);
450 static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr)
452 return snd_hdac_aligned_mmio(bus) ?
453 snd_hdac_aligned_read(addr, 0xffff) : readw(addr);
456 #define snd_hdac_reg_writel(bus, addr, val) writel(val, addr)
457 #define snd_hdac_reg_readl(bus, addr) readl(addr)
458 #define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr)
459 #define snd_hdac_reg_readq(bus, addr) readq(addr)
462 * macros for easy use
464 #define _snd_hdac_chip_writeb(chip, reg, value) \
465 snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value)
466 #define _snd_hdac_chip_readb(chip, reg) \
467 snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg))
468 #define _snd_hdac_chip_writew(chip, reg, value) \
469 snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value)
470 #define _snd_hdac_chip_readw(chip, reg) \
471 snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg))
472 #define _snd_hdac_chip_writel(chip, reg, value) \
473 snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value)
474 #define _snd_hdac_chip_readl(chip, reg) \
475 snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg))
477 /* read/write a register, pass without AZX_REG_ prefix */
478 #define snd_hdac_chip_writel(chip, reg, value) \
479 _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value)
480 #define snd_hdac_chip_writew(chip, reg, value) \
481 _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value)
482 #define snd_hdac_chip_writeb(chip, reg, value) \
483 _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value)
484 #define snd_hdac_chip_readl(chip, reg) \
485 _snd_hdac_chip_readl(chip, AZX_REG_ ## reg)
486 #define snd_hdac_chip_readw(chip, reg) \
487 _snd_hdac_chip_readw(chip, AZX_REG_ ## reg)
488 #define snd_hdac_chip_readb(chip, reg) \
489 _snd_hdac_chip_readb(chip, AZX_REG_ ## reg)
491 /* update a register, pass without AZX_REG_ prefix */
492 #define snd_hdac_chip_updatel(chip, reg, mask, val) \
493 snd_hdac_chip_writel(chip, reg, \
494 (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))
495 #define snd_hdac_chip_updatew(chip, reg, mask, val) \
496 snd_hdac_chip_writew(chip, reg, \
497 (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val))
498 #define snd_hdac_chip_updateb(chip, reg, mask, val) \
499 snd_hdac_chip_writeb(chip, reg, \
500 (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))
502 /* update register macro */
503 #define snd_hdac_updatel(addr, reg, mask, val) \
504 writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg)
506 #define snd_hdac_updatew(addr, reg, mask, val) \
507 writew(((readw(addr + reg) & ~(mask)) | (val)), addr + reg)
513 struct hdac_bus *bus;
514 struct snd_dma_buffer bdl; /* BDL buffer */
515 __le32 *posbuf; /* position buffer pointer */
516 int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */
518 unsigned int bufsize; /* size of the play buffer in bytes */
519 unsigned int period_bytes; /* size of the period in bytes */
520 unsigned int frags; /* number for period in the play buffer */
521 unsigned int fifo_size; /* FIFO size */
523 void __iomem *sd_addr; /* stream descriptor pointer */
525 void __iomem *spib_addr; /* software position in buffers stream pointer */
526 void __iomem *fifo_addr; /* software position Max fifos stream pointer */
528 void __iomem *dpibr_addr; /* DMA position in buffer resume pointer */
529 u32 dpib; /* DMA position in buffer */
530 u32 lpib; /* Linear position in buffer */
532 u32 sd_int_sta_mask; /* stream int status mask */
535 struct snd_pcm_substream *substream; /* assigned substream,
538 struct snd_compr_stream *cstream;
539 unsigned int format_val; /* format value to be set in the
540 * controller and the codec
542 unsigned char stream_tag; /* assigned stream */
543 unsigned char index; /* stream index */
544 int assigned_key; /* last device# key assigned to */
549 bool no_period_wakeup:1;
551 bool stripe:1; /* apply stripe control */
555 unsigned long start_wallclk; /* start + minimum wallclk */
556 unsigned long period_wallclk; /* wallclk for period */
557 struct timecounter tc;
558 struct cyclecounter cc;
559 int delay_negative_threshold;
561 struct list_head list;
562 #ifdef CONFIG_SND_HDA_DSP_LOADER
563 /* DSP access mutex */
564 struct mutex dsp_mutex;
568 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
569 int idx, int direction, int tag);
570 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
571 struct snd_pcm_substream *substream);
572 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev);
573 void snd_hdac_stream_release(struct hdac_stream *azx_dev);
574 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
575 int dir, int stream_tag);
577 int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading);
578 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);
579 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);
580 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
581 unsigned int format_val);
582 void snd_hdac_stream_start(struct hdac_stream *azx_dev);
583 void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
584 void snd_hdac_stop_streams(struct hdac_bus *bus);
585 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus);
586 void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
587 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
588 unsigned int streams, unsigned int reg);
589 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
590 unsigned int streams);
591 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
592 unsigned int streams);
593 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
594 struct snd_pcm_substream *substream);
596 void snd_hdac_stream_spbcap_enable(struct hdac_bus *chip,
597 bool enable, int index);
598 int snd_hdac_stream_set_spib(struct hdac_bus *bus,
599 struct hdac_stream *azx_dev, u32 value);
600 int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
601 struct hdac_stream *azx_dev);
602 void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
603 bool enable, int index);
604 int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev);
605 int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
606 struct hdac_stream *azx_dev, u32 value);
607 int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value);
610 * macros for easy use
612 /* read/write a register, pass without AZX_REG_ prefix */
613 #define snd_hdac_stream_writel(dev, reg, value) \
614 snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
615 #define snd_hdac_stream_writew(dev, reg, value) \
616 snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
617 #define snd_hdac_stream_writeb(dev, reg, value) \
618 snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
619 #define snd_hdac_stream_readl(dev, reg) \
620 snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
621 #define snd_hdac_stream_readw(dev, reg) \
622 snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
623 #define snd_hdac_stream_readb(dev, reg) \
624 snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
625 #define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \
626 read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \
627 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
628 #define snd_hdac_stream_readw_poll(dev, reg, val, cond, delay_us, timeout_us) \
629 read_poll_timeout_atomic(snd_hdac_reg_readw, val, cond, delay_us, timeout_us, \
630 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
631 #define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \
632 read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \
633 false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
635 /* update a register, pass without AZX_REG_ prefix */
636 #define snd_hdac_stream_updatel(dev, reg, mask, val) \
637 snd_hdac_stream_writel(dev, reg, \
638 (snd_hdac_stream_readl(dev, reg) & \
640 #define snd_hdac_stream_updatew(dev, reg, mask, val) \
641 snd_hdac_stream_writew(dev, reg, \
642 (snd_hdac_stream_readw(dev, reg) & \
644 #define snd_hdac_stream_updateb(dev, reg, mask, val) \
645 snd_hdac_stream_writeb(dev, reg, \
646 (snd_hdac_stream_readb(dev, reg) & \
649 #ifdef CONFIG_SND_HDA_DSP_LOADER
650 /* DSP lock helpers */
651 #define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
652 #define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
653 #define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
654 #define snd_hdac_stream_is_locked(dev) ((dev)->locked)
655 /* DSP loader helpers */
656 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
657 unsigned int byte_size, struct snd_dma_buffer *bufp);
658 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);
659 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
660 struct snd_dma_buffer *dmab);
661 #else /* CONFIG_SND_HDA_DSP_LOADER */
662 #define snd_hdac_dsp_lock_init(dev) do {} while (0)
663 #define snd_hdac_dsp_lock(dev) do {} while (0)
664 #define snd_hdac_dsp_unlock(dev) do {} while (0)
665 #define snd_hdac_stream_is_locked(dev) 0
668 snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
669 unsigned int byte_size, struct snd_dma_buffer *bufp)
674 static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
678 static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
679 struct snd_dma_buffer *dmab)
682 #endif /* CONFIG_SND_HDA_DSP_LOADER */
686 * generic array helpers
688 void *snd_array_new(struct snd_array *array);
689 void snd_array_free(struct snd_array *array);
690 static inline void snd_array_init(struct snd_array *array, unsigned int size,
693 array->elem_size = size;
694 array->alloc_align = align;
697 static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
699 return array->list + idx * array->elem_size;
702 static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
704 return (unsigned long)(ptr - array->list) / array->elem_size;
707 /* a helper macro to iterate for each snd_array element */
708 #define snd_array_for_each(array, idx, ptr) \
709 for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \
710 (ptr) = snd_array_elem(array, ++(idx)))
716 #define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \
717 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \
718 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_2) }, \
719 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_3) }, \
720 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BDW) }, \
724 #define HDA_CONTROLLER_IS_APL(pci) (pci_match_id((struct pci_device_id []){ \
725 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_APL) }, \
729 #define HDA_CONTROLLER_IN_GPU(pci) (pci_match_id((struct pci_device_id []){ \
730 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG1) }, \
731 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_0) }, \
732 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_1) }, \
733 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_2) }, \
735 }, pci) || HDA_CONTROLLER_IS_HSW(pci))
737 #endif /* __SOUND_HDAUDIO_H */