1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
14 /* Port Group IDs (PGID) are masks of destination ports.
16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
17 * frame, and forwards the frame to the ports that are present in the logical
20 * These PGID lookups are:
21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
22 * which the switch selects a destination PGID:
23 * - The {DMAC, VID} is present in the MAC table. In that case, the
24 * destination PGID is given by the DEST_IDX field of the MAC table entry
26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
27 * frame is disseminated as being either unicast, multicast or broadcast,
28 * and according to that, the destination PGID is chosen as being the
29 * value contained by ANA_FLOODING_FLD_UNICAST,
30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
31 * The destination PGID can be an unicast set: the first PGIDs, 0 to
32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
34 * a physical port and has a single bit set in the destination ports mask:
35 * that corresponding to the port number itself. In contrast, a multicast
36 * PGID will have potentially more than one single bit set in the destination
38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
39 * dissects each frame and generates a 4-bit Link Aggregation Code which is
40 * used for this second PGID table lookup. The goal of link aggregation is to
41 * hash multiple flows within the same LAG on to different destination ports.
42 * The first lookup will result in a PGID with all the LAG members present in
43 * the destination ports mask, and the second lookup, by Link Aggregation
44 * Code, will ensure that each flow gets forwarded only to a single port out
45 * of that mask (there are no duplicates).
46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
47 * is indexed with the ingress port (plus 80). These PGIDs answer the
48 * question "is port i allowed to forward traffic to port j?" If yes, then
49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
53 /* Reserve some destination PGIDs at the end of the range:
54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
55 * of the switch port net devices, towards the CPU port module.
56 * PGID_UC: the flooding destinations for unknown unicast traffic.
57 * PGID_MC: the flooding destinations for non-IP multicast traffic.
58 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
59 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
60 * PGID_BC: the flooding destinations for broadcast traffic.
65 #define PGID_MCIPV4 61
66 #define PGID_MCIPV6 62
69 #define for_each_unicast_dest_pgid(ocelot, pgid) \
71 (pgid) < (ocelot)->num_phys_ports; \
74 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \
75 for ((pgid) = (ocelot)->num_phys_ports + 1; \
79 #define for_each_aggr_pgid(ocelot, pgid) \
80 for ((pgid) = PGID_AGGR; \
84 /* Aggregation PGIDs, one per Link Aggregation Code */
87 /* Source PGIDs, one per physical port */
90 #define IFH_TAG_TYPE_C 0
91 #define IFH_TAG_TYPE_S 1
93 #define IFH_REW_OP_NOOP 0x0
94 #define IFH_REW_OP_DSCP 0x1
95 #define IFH_REW_OP_ONE_STEP_PTP 0x2
96 #define IFH_REW_OP_TWO_STEP_PTP 0x3
97 #define IFH_REW_OP_ORIGIN_PTP 0x5
99 #define OCELOT_NUM_TC 8
101 #define OCELOT_SPEED_2500 0
102 #define OCELOT_SPEED_1000 1
103 #define OCELOT_SPEED_100 2
104 #define OCELOT_SPEED_10 3
106 #define OCELOT_PTP_PINS_NUM 4
108 #define TARGET_OFFSET 24
109 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
110 #define REG(reg, offset) [reg & REG_MASK] = offset
112 #define REG_RESERVED_ADDR 0xffffffff
113 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
115 #define OCELOT_MRP_CPUQ 7
134 ANA_ADVLEARN = ANA << TARGET_OFFSET,
139 ANA_STORMLIMIT_BURST,
158 ANA_TABLES_STREAMDATA,
159 ANA_TABLES_MACACCESS,
161 ANA_TABLES_VLANACCESS,
163 ANA_TABLES_ISDXACCESS,
166 ANA_TABLES_PTP_ID_HIGH,
167 ANA_TABLES_PTP_ID_LOW,
168 ANA_TABLES_STREAMACCESS,
169 ANA_TABLES_STREAMTIDX,
170 ANA_TABLES_SEQ_HISTORY,
172 ANA_TABLES_SFID_MASK,
173 ANA_TABLES_SFIDACCESS,
183 ANA_SG_GCL_GS_CONFIG,
184 ANA_SG_GCL_TI_CONFIG,
192 ANA_PORT_VCAP_S1_KEY_CFG,
193 ANA_PORT_VCAP_S2_CFG,
194 ANA_PORT_PCP_DEI_MAP,
195 ANA_PORT_CPU_FWD_CFG,
196 ANA_PORT_CPU_FWD_BPDU_CFG,
197 ANA_PORT_CPU_FWD_GARP_CFG,
198 ANA_PORT_CPU_FWD_CCM_CFG,
202 ANA_PORT_PTP_DLY1_CFG,
203 ANA_PORT_PTP_DLY2_CFG,
217 ANA_VCAP_RNG_TYPE_CFG,
218 ANA_VCAP_RNG_VAL_CFG,
233 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
245 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
246 QSYS_SWITCH_PORT_MODE,
258 QSYS_TIMED_FRAME_ENTRY,
261 QSYS_TFRM_TIMER_CFG_1,
262 QSYS_TFRM_TIMER_CFG_2,
263 QSYS_TFRM_TIMER_CFG_3,
264 QSYS_TFRM_TIMER_CFG_4,
265 QSYS_TFRM_TIMER_CFG_5,
266 QSYS_TFRM_TIMER_CFG_6,
267 QSYS_TFRM_TIMER_CFG_7,
268 QSYS_TFRM_TIMER_CFG_8,
296 QSYS_TAS_PARAM_CFG_CTRL,
298 QSYS_PARAM_CFG_REG_1,
299 QSYS_PARAM_CFG_REG_2,
300 QSYS_PARAM_CFG_REG_3,
301 QSYS_PARAM_CFG_REG_4,
302 QSYS_PARAM_CFG_REG_5,
305 QSYS_PARAM_STATUS_REG_1,
306 QSYS_PARAM_STATUS_REG_2,
307 QSYS_PARAM_STATUS_REG_3,
308 QSYS_PARAM_STATUS_REG_4,
309 QSYS_PARAM_STATUS_REG_5,
310 QSYS_PARAM_STATUS_REG_6,
311 QSYS_PARAM_STATUS_REG_7,
312 QSYS_PARAM_STATUS_REG_8,
313 QSYS_PARAM_STATUS_REG_9,
314 QSYS_GCL_STATUS_REG_1,
315 QSYS_GCL_STATUS_REG_2,
316 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
320 REW_PCP_DEI_QOS_MAP_CFG,
324 REW_DSCP_REMAP_DP1_CFG,
329 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
330 SYS_COUNT_RX_UNICAST,
331 SYS_COUNT_RX_MULTICAST,
332 SYS_COUNT_RX_BROADCAST,
334 SYS_COUNT_RX_FRAGMENTS,
335 SYS_COUNT_RX_JABBERS,
336 SYS_COUNT_RX_CRC_ALIGN_ERRS,
337 SYS_COUNT_RX_SYM_ERRS,
340 SYS_COUNT_RX_128_255,
341 SYS_COUNT_RX_256_1023,
342 SYS_COUNT_RX_1024_1526,
343 SYS_COUNT_RX_1527_MAX,
345 SYS_COUNT_RX_CONTROL,
347 SYS_COUNT_RX_CLASSIFIED_DROPS,
349 SYS_COUNT_TX_UNICAST,
350 SYS_COUNT_TX_MULTICAST,
351 SYS_COUNT_TX_BROADCAST,
352 SYS_COUNT_TX_COLLISION,
357 SYS_COUNT_TX_128_511,
358 SYS_COUNT_TX_512_1023,
359 SYS_COUNT_TX_1024_1526,
360 SYS_COUNT_TX_1527_MAX,
371 SYS_REW_MAC_HIGH_CFG,
373 SYS_TIMESTAMP_OFFSET,
395 PTP_PIN_CFG = PTP << TARGET_OFFSET,
399 PTP_PIN_WF_HIGH_PERIOD,
400 PTP_PIN_WF_LOW_PERIOD,
403 PTP_CLK_CFG_ADJ_FREQ,
404 GCB_SOFT_RST = GCB << TARGET_OFFSET,
408 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
423 DEV_MAC_FC_MAC_LOW_CFG,
424 DEV_MAC_FC_MAC_HIGH_CFG,
435 PCS1G_ANEG_NP_STATUS,
441 PCS1G_LPI_WAKE_ERROR_CNT,
443 PCS1G_TSTPAT_MODE_CFG,
446 DEV_PCS_FX100_STATUS,
449 enum ocelot_regfield {
450 ANA_ADVLEARN_VLAN_CHK,
451 ANA_ADVLEARN_LEARN_MIRROR,
452 ANA_ANEVENTS_FLOOD_DISCARD,
453 ANA_ANEVENTS_MSTI_DROP,
454 ANA_ANEVENTS_ACLKILL,
455 ANA_ANEVENTS_ACLUSED,
456 ANA_ANEVENTS_AUTOAGE,
457 ANA_ANEVENTS_VS2TTL1,
458 ANA_ANEVENTS_STORM_DROP,
459 ANA_ANEVENTS_LEARN_DROP,
460 ANA_ANEVENTS_AGED_ENTRY,
461 ANA_ANEVENTS_CPU_LEARN_FAILED,
462 ANA_ANEVENTS_AUTO_LEARN_FAILED,
463 ANA_ANEVENTS_LEARN_REMOVE,
464 ANA_ANEVENTS_AUTO_LEARNED,
465 ANA_ANEVENTS_AUTO_MOVED,
466 ANA_ANEVENTS_DROPPED,
467 ANA_ANEVENTS_CLASSIFIED_DROP,
468 ANA_ANEVENTS_CLASSIFIED_COPY,
469 ANA_ANEVENTS_VLAN_DISCARD,
470 ANA_ANEVENTS_FWD_DISCARD,
471 ANA_ANEVENTS_MULTICAST_FLOOD,
472 ANA_ANEVENTS_UNICAST_FLOOD,
473 ANA_ANEVENTS_DEST_KNOWN,
474 ANA_ANEVENTS_BUCKET3_MATCH,
475 ANA_ANEVENTS_BUCKET2_MATCH,
476 ANA_ANEVENTS_BUCKET1_MATCH,
477 ANA_ANEVENTS_BUCKET0_MATCH,
478 ANA_ANEVENTS_CPU_OPERATION,
479 ANA_ANEVENTS_DMAC_LOOKUP,
480 ANA_ANEVENTS_SMAC_LOOKUP,
481 ANA_ANEVENTS_SEQ_GEN_ERR_0,
482 ANA_ANEVENTS_SEQ_GEN_ERR_1,
483 ANA_TABLES_MACACCESS_B_DOM,
484 ANA_TABLES_MACTINDX_BUCKET,
485 ANA_TABLES_MACTINDX_M_INDEX,
486 QSYS_SWITCH_PORT_MODE_PORT_ENA,
487 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG,
488 QSYS_SWITCH_PORT_MODE_YEL_RSRVD,
489 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,
490 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA,
491 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE,
492 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
493 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
494 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
495 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
496 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
497 SYS_PORT_MODE_DATA_WO_TS,
498 SYS_PORT_MODE_INCL_INJ_HDR,
499 SYS_PORT_MODE_INCL_XTR_HDR,
500 SYS_PORT_MODE_INCL_HDR_ERR,
501 SYS_RESET_CFG_CORE_ENA,
502 SYS_RESET_CFG_MEM_ENA,
503 SYS_RESET_CFG_MEM_INIT,
504 GCB_SOFT_RST_SWC_RST,
505 GCB_MIIM_MII_STATUS_PENDING,
506 GCB_MIIM_MII_STATUS_BUSY,
507 SYS_PAUSE_CFG_PAUSE_START,
508 SYS_PAUSE_CFG_PAUSE_STOP,
509 SYS_PAUSE_CFG_PAUSE_ENA,
515 VCAP_CORE_UPDATE_CTRL,
517 /* VCAP_CORE_CACHE */
518 VCAP_CACHE_ENTRY_DAT,
520 VCAP_CACHE_ACTION_DAT,
525 VCAP_CONST_ENTRY_WIDTH,
526 VCAP_CONST_ENTRY_CNT,
527 VCAP_CONST_ENTRY_SWCNT,
528 VCAP_CONST_ENTRY_TG_WIDTH,
529 VCAP_CONST_ACTION_DEF_CNT,
530 VCAP_CONST_ACTION_WIDTH,
531 VCAP_CONST_CNT_WIDTH,
536 enum ocelot_ptp_pins {
544 struct ocelot_stat_layout {
546 char name[ETH_GSTRING_LEN];
549 enum ocelot_tag_prefix {
550 OCELOT_TAG_PREFIX_DISABLED = 0,
551 OCELOT_TAG_PREFIX_NONE,
552 OCELOT_TAG_PREFIX_SHORT,
553 OCELOT_TAG_PREFIX_LONG,
559 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
560 int (*netdev_to_port)(struct net_device *dev);
561 int (*reset)(struct ocelot *ocelot);
562 u16 (*wm_enc)(u16 value);
563 u16 (*wm_dec)(u16 value);
564 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse);
567 struct ocelot_vcap_block {
568 struct list_head rules;
584 enum ocelot_sb_pool {
591 struct ocelot *ocelot;
593 struct regmap *target;
596 /* VLAN that untagged frames are classified to, on ingress */
597 struct ocelot_vlan pvid_vlan;
598 /* The VLAN ID that will be transmitted as untagged, on egress */
599 struct ocelot_vlan native_vlan;
602 struct sk_buff_head tx_skbs;
604 spinlock_t ts_id_lock;
606 phy_interface_t phy_mode;
609 bool is_dsa_8021q_cpu;
612 struct net_device *bond;
618 struct devlink *devlink;
619 struct devlink_port *devlink_ports;
621 const struct ocelot_ops *ops;
622 struct regmap *targets[TARGET_MAX];
623 struct regmap_field *regfields[REGFIELD_MAX];
624 const u32 *const *map;
625 const struct ocelot_stat_layout *stats_layout;
626 unsigned int num_stats;
628 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM];
629 int packet_buffer_size;
633 struct net_device *hw_bridge_dev;
637 struct ocelot_port **ports;
639 u8 base_mac[ETH_ALEN];
641 /* Keep track of the vlan port masks */
642 u32 vlan_mask[VLAN_N_VID];
644 /* Switches like VSC9959 have flooding per traffic class */
645 int num_flooding_pgids;
647 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
648 * the CPU is located after the physical ports (at the
649 * num_phys_ports index).
655 enum ocelot_tag_prefix npi_inj_prefix;
656 enum ocelot_tag_prefix npi_xtr_prefix;
658 struct list_head multicast;
659 struct list_head pgids;
661 struct list_head dummy_rules;
662 struct ocelot_vcap_block block[3];
663 struct vcap_props *vcap;
665 /* Workqueue to check statistics for overflow with its lock */
666 struct mutex stats_lock;
668 struct delayed_work stats_work;
669 struct workqueue_struct *stats_queue;
671 struct workqueue_struct *owq;
674 struct ptp_clock *ptp_clock;
675 struct ptp_clock_info ptp_info;
676 struct hwtstamp_config hwtstamp_config;
677 /* Protects the PTP interface state */
678 struct mutex ptp_lock;
679 /* Protects the PTP clock */
680 spinlock_t ptp_clock_lock;
681 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM];
683 #if IS_ENABLED(CONFIG_BRIDGE_MRP)
685 struct net_device *mrp_p_port;
686 struct net_device *mrp_s_port;
690 struct ocelot_policer {
691 u32 rate; /* kilobit per second */
692 u32 burst; /* bytes */
695 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
696 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
697 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
698 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
700 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
701 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
702 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
703 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
705 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
706 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
707 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
708 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
710 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
711 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
712 #define ocelot_fields_write(ocelot, id, reg, val) regmap_fields_write((ocelot)->regfields[(reg)], (id), (val))
713 #define ocelot_fields_read(ocelot, id, reg, val) regmap_fields_read((ocelot)->regfields[(reg)], (id), (val))
715 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \
716 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
717 #define ocelot_target_read_gix(ocelot, target, reg, gi) \
718 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi))
719 #define ocelot_target_read_rix(ocelot, target, reg, ri) \
720 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri))
721 #define ocelot_target_read(ocelot, target, reg) \
722 __ocelot_target_read_ix(ocelot, target, reg, 0)
724 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \
725 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
726 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \
727 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi))
728 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \
729 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri))
730 #define ocelot_target_write(ocelot, target, val, reg) \
731 __ocelot_target_write_ix(ocelot, target, val, reg, 0)
734 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
735 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
736 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg);
737 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
738 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
739 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
741 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
742 u32 reg, u32 offset);
743 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
744 u32 val, u32 reg, u32 offset);
747 #if IS_ENABLED(CONFIG_MSCC_OCELOT_SWITCH_LIB)
749 bool ocelot_can_inject(struct ocelot *ocelot, int grp);
750 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
751 u32 rew_op, struct sk_buff *skb);
752 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb);
753 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp);
757 static inline bool ocelot_can_inject(struct ocelot *ocelot, int grp)
762 static inline void ocelot_port_inject_frame(struct ocelot *ocelot, int port,
768 static inline int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp,
769 struct sk_buff **skb)
774 static inline void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
780 /* Hardware initialization */
781 int ocelot_regfields_init(struct ocelot *ocelot,
782 const struct reg_field *const regfields);
783 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
784 int ocelot_init(struct ocelot *ocelot);
785 void ocelot_deinit(struct ocelot *ocelot);
786 void ocelot_init_port(struct ocelot *ocelot, int port);
787 void ocelot_deinit_port(struct ocelot *ocelot, int port);
790 void ocelot_port_enable(struct ocelot *ocelot, int port,
791 struct phy_device *phy);
792 void ocelot_port_disable(struct ocelot *ocelot, int port);
793 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
794 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
795 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
796 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
797 struct ethtool_ts_info *info);
798 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
799 int ocelot_port_flush(struct ocelot *ocelot, int port);
800 void ocelot_adjust_link(struct ocelot *ocelot, int port,
801 struct phy_device *phydev);
802 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled);
803 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
804 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot);
805 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
806 struct switchdev_brport_flags val);
807 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
808 struct switchdev_brport_flags val);
809 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
810 struct net_device *bridge);
811 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
812 struct net_device *bridge);
813 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
814 dsa_fdb_dump_cb_t *cb, void *data);
815 int ocelot_fdb_add(struct ocelot *ocelot, int port,
816 const unsigned char *addr, u16 vid);
817 int ocelot_fdb_del(struct ocelot *ocelot, int port,
818 const unsigned char *addr, u16 vid);
819 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
821 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
823 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
824 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
825 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
826 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,
827 struct sk_buff *clone);
828 void ocelot_get_txtstamp(struct ocelot *ocelot);
829 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
830 int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
831 int ocelot_port_policer_add(struct ocelot *ocelot, int port,
832 struct ocelot_policer *pol);
833 int ocelot_port_policer_del(struct ocelot *ocelot, int port);
834 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
835 struct flow_cls_offload *f, bool ingress);
836 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
837 struct flow_cls_offload *f, bool ingress);
838 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
839 struct flow_cls_offload *f, bool ingress);
840 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
841 const struct switchdev_obj_port_mdb *mdb);
842 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
843 const struct switchdev_obj_port_mdb *mdb);
844 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
845 struct net_device *bond,
846 struct netdev_lag_upper_info *info);
847 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
848 struct net_device *bond);
849 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active);
851 int ocelot_devlink_sb_register(struct ocelot *ocelot);
852 void ocelot_devlink_sb_unregister(struct ocelot *ocelot);
853 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index,
855 struct devlink_sb_pool_info *pool_info);
856 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index,
857 u16 pool_index, u32 size,
858 enum devlink_sb_threshold_type threshold_type,
859 struct netlink_ext_ack *extack);
860 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port,
861 unsigned int sb_index, u16 pool_index,
863 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port,
864 unsigned int sb_index, u16 pool_index,
865 u32 threshold, struct netlink_ext_ack *extack);
866 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port,
867 unsigned int sb_index, u16 tc_index,
868 enum devlink_sb_pool_type pool_type,
869 u16 *p_pool_index, u32 *p_threshold);
870 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port,
871 unsigned int sb_index, u16 tc_index,
872 enum devlink_sb_pool_type pool_type,
873 u16 pool_index, u32 threshold,
874 struct netlink_ext_ack *extack);
875 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index);
876 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index);
877 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port,
878 unsigned int sb_index, u16 pool_index,
879 u32 *p_cur, u32 *p_max);
880 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port,
881 unsigned int sb_index, u16 tc_index,
882 enum devlink_sb_pool_type pool_type,
883 u32 *p_cur, u32 *p_max);
885 #if IS_ENABLED(CONFIG_BRIDGE_MRP)
886 int ocelot_mrp_add(struct ocelot *ocelot, int port,
887 const struct switchdev_obj_mrp *mrp);
888 int ocelot_mrp_del(struct ocelot *ocelot, int port,
889 const struct switchdev_obj_mrp *mrp);
890 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
891 const struct switchdev_obj_ring_role_mrp *mrp);
892 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
893 const struct switchdev_obj_ring_role_mrp *mrp);
895 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port,
896 const struct switchdev_obj_mrp *mrp)
901 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port,
902 const struct switchdev_obj_mrp *mrp)
908 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
909 const struct switchdev_obj_ring_role_mrp *mrp)
915 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
916 const struct switchdev_obj_ring_role_mrp *mrp)