1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
14 /* Port Group IDs (PGID) are masks of destination ports.
16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
17 * frame, and forwards the frame to the ports that are present in the logical
20 * These PGID lookups are:
21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
22 * which the switch selects a destination PGID:
23 * - The {DMAC, VID} is present in the MAC table. In that case, the
24 * destination PGID is given by the DEST_IDX field of the MAC table entry
26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
27 * frame is disseminated as being either unicast, multicast or broadcast,
28 * and according to that, the destination PGID is chosen as being the
29 * value contained by ANA_FLOODING_FLD_UNICAST,
30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
31 * The destination PGID can be an unicast set: the first PGIDs, 0 to
32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
34 * a physical port and has a single bit set in the destination ports mask:
35 * that corresponding to the port number itself. In contrast, a multicast
36 * PGID will have potentially more than one single bit set in the destination
38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
39 * dissects each frame and generates a 4-bit Link Aggregation Code which is
40 * used for this second PGID table lookup. The goal of link aggregation is to
41 * hash multiple flows within the same LAG on to different destination ports.
42 * The first lookup will result in a PGID with all the LAG members present in
43 * the destination ports mask, and the second lookup, by Link Aggregation
44 * Code, will ensure that each flow gets forwarded only to a single port out
45 * of that mask (there are no duplicates).
46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
47 * is indexed with the ingress port (plus 80). These PGIDs answer the
48 * question "is port i allowed to forward traffic to port j?" If yes, then
49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
53 /* Reserve some destination PGIDs at the end of the range:
54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
55 * of the switch port net devices, towards the CPU port module.
56 * PGID_UC: the flooding destinations for unknown unicast traffic.
57 * PGID_MC: the flooding destinations for broadcast and non-IP multicast
59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
65 #define PGID_MCIPV4 62
66 #define PGID_MCIPV6 63
68 #define for_each_unicast_dest_pgid(ocelot, pgid) \
70 (pgid) < (ocelot)->num_phys_ports; \
73 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \
74 for ((pgid) = (ocelot)->num_phys_ports + 1; \
78 #define for_each_aggr_pgid(ocelot, pgid) \
79 for ((pgid) = PGID_AGGR; \
83 /* Aggregation PGIDs, one per Link Aggregation Code */
86 /* Source PGIDs, one per physical port */
89 #define IFH_INJ_BYPASS BIT(31)
90 #define IFH_INJ_POP_CNT_DISABLE (3 << 28)
92 #define IFH_TAG_TYPE_C 0
93 #define IFH_TAG_TYPE_S 1
95 #define IFH_REW_OP_NOOP 0x0
96 #define IFH_REW_OP_DSCP 0x1
97 #define IFH_REW_OP_ONE_STEP_PTP 0x2
98 #define IFH_REW_OP_TWO_STEP_PTP 0x3
99 #define IFH_REW_OP_ORIGIN_PTP 0x5
101 #define OCELOT_TAG_LEN 16
102 #define OCELOT_SHORT_PREFIX_LEN 4
103 #define OCELOT_LONG_PREFIX_LEN 16
104 #define OCELOT_TOTAL_TAG_LEN (OCELOT_SHORT_PREFIX_LEN + OCELOT_TAG_LEN)
106 #define OCELOT_SPEED_2500 0
107 #define OCELOT_SPEED_1000 1
108 #define OCELOT_SPEED_100 2
109 #define OCELOT_SPEED_10 3
111 #define OCELOT_PTP_PINS_NUM 4
113 #define TARGET_OFFSET 24
114 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
115 #define REG(reg, offset) [reg & REG_MASK] = offset
117 #define REG_RESERVED_ADDR 0xffffffff
118 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
137 ANA_ADVLEARN = ANA << TARGET_OFFSET,
142 ANA_STORMLIMIT_BURST,
161 ANA_TABLES_STREAMDATA,
162 ANA_TABLES_MACACCESS,
164 ANA_TABLES_VLANACCESS,
166 ANA_TABLES_ISDXACCESS,
169 ANA_TABLES_PTP_ID_HIGH,
170 ANA_TABLES_PTP_ID_LOW,
171 ANA_TABLES_STREAMACCESS,
172 ANA_TABLES_STREAMTIDX,
173 ANA_TABLES_SEQ_HISTORY,
175 ANA_TABLES_SFID_MASK,
176 ANA_TABLES_SFIDACCESS,
186 ANA_SG_GCL_GS_CONFIG,
187 ANA_SG_GCL_TI_CONFIG,
195 ANA_PORT_VCAP_S1_KEY_CFG,
196 ANA_PORT_VCAP_S2_CFG,
197 ANA_PORT_PCP_DEI_MAP,
198 ANA_PORT_CPU_FWD_CFG,
199 ANA_PORT_CPU_FWD_BPDU_CFG,
200 ANA_PORT_CPU_FWD_GARP_CFG,
201 ANA_PORT_CPU_FWD_CCM_CFG,
205 ANA_PORT_PTP_DLY1_CFG,
206 ANA_PORT_PTP_DLY2_CFG,
220 ANA_VCAP_RNG_TYPE_CFG,
221 ANA_VCAP_RNG_VAL_CFG,
236 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
248 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
249 QSYS_SWITCH_PORT_MODE,
261 QSYS_TIMED_FRAME_ENTRY,
264 QSYS_TFRM_TIMER_CFG_1,
265 QSYS_TFRM_TIMER_CFG_2,
266 QSYS_TFRM_TIMER_CFG_3,
267 QSYS_TFRM_TIMER_CFG_4,
268 QSYS_TFRM_TIMER_CFG_5,
269 QSYS_TFRM_TIMER_CFG_6,
270 QSYS_TFRM_TIMER_CFG_7,
271 QSYS_TFRM_TIMER_CFG_8,
299 QSYS_TAS_PARAM_CFG_CTRL,
301 QSYS_PARAM_CFG_REG_1,
302 QSYS_PARAM_CFG_REG_2,
303 QSYS_PARAM_CFG_REG_3,
304 QSYS_PARAM_CFG_REG_4,
305 QSYS_PARAM_CFG_REG_5,
308 QSYS_PARAM_STATUS_REG_1,
309 QSYS_PARAM_STATUS_REG_2,
310 QSYS_PARAM_STATUS_REG_3,
311 QSYS_PARAM_STATUS_REG_4,
312 QSYS_PARAM_STATUS_REG_5,
313 QSYS_PARAM_STATUS_REG_6,
314 QSYS_PARAM_STATUS_REG_7,
315 QSYS_PARAM_STATUS_REG_8,
316 QSYS_PARAM_STATUS_REG_9,
317 QSYS_GCL_STATUS_REG_1,
318 QSYS_GCL_STATUS_REG_2,
319 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
323 REW_PCP_DEI_QOS_MAP_CFG,
327 REW_DSCP_REMAP_DP1_CFG,
332 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
333 SYS_COUNT_RX_UNICAST,
334 SYS_COUNT_RX_MULTICAST,
335 SYS_COUNT_RX_BROADCAST,
337 SYS_COUNT_RX_FRAGMENTS,
338 SYS_COUNT_RX_JABBERS,
339 SYS_COUNT_RX_CRC_ALIGN_ERRS,
340 SYS_COUNT_RX_SYM_ERRS,
343 SYS_COUNT_RX_128_255,
344 SYS_COUNT_RX_256_1023,
345 SYS_COUNT_RX_1024_1526,
346 SYS_COUNT_RX_1527_MAX,
348 SYS_COUNT_RX_CONTROL,
350 SYS_COUNT_RX_CLASSIFIED_DROPS,
352 SYS_COUNT_TX_UNICAST,
353 SYS_COUNT_TX_MULTICAST,
354 SYS_COUNT_TX_BROADCAST,
355 SYS_COUNT_TX_COLLISION,
360 SYS_COUNT_TX_128_511,
361 SYS_COUNT_TX_512_1023,
362 SYS_COUNT_TX_1024_1526,
363 SYS_COUNT_TX_1527_MAX,
374 SYS_REW_MAC_HIGH_CFG,
376 SYS_TIMESTAMP_OFFSET,
398 PTP_PIN_CFG = PTP << TARGET_OFFSET,
402 PTP_PIN_WF_HIGH_PERIOD,
403 PTP_PIN_WF_LOW_PERIOD,
406 PTP_CLK_CFG_ADJ_FREQ,
407 GCB_SOFT_RST = GCB << TARGET_OFFSET,
411 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
426 DEV_MAC_FC_MAC_LOW_CFG,
427 DEV_MAC_FC_MAC_HIGH_CFG,
438 PCS1G_ANEG_NP_STATUS,
444 PCS1G_LPI_WAKE_ERROR_CNT,
446 PCS1G_TSTPAT_MODE_CFG,
449 DEV_PCS_FX100_STATUS,
452 enum ocelot_regfield {
453 ANA_ADVLEARN_VLAN_CHK,
454 ANA_ADVLEARN_LEARN_MIRROR,
455 ANA_ANEVENTS_FLOOD_DISCARD,
456 ANA_ANEVENTS_MSTI_DROP,
457 ANA_ANEVENTS_ACLKILL,
458 ANA_ANEVENTS_ACLUSED,
459 ANA_ANEVENTS_AUTOAGE,
460 ANA_ANEVENTS_VS2TTL1,
461 ANA_ANEVENTS_STORM_DROP,
462 ANA_ANEVENTS_LEARN_DROP,
463 ANA_ANEVENTS_AGED_ENTRY,
464 ANA_ANEVENTS_CPU_LEARN_FAILED,
465 ANA_ANEVENTS_AUTO_LEARN_FAILED,
466 ANA_ANEVENTS_LEARN_REMOVE,
467 ANA_ANEVENTS_AUTO_LEARNED,
468 ANA_ANEVENTS_AUTO_MOVED,
469 ANA_ANEVENTS_DROPPED,
470 ANA_ANEVENTS_CLASSIFIED_DROP,
471 ANA_ANEVENTS_CLASSIFIED_COPY,
472 ANA_ANEVENTS_VLAN_DISCARD,
473 ANA_ANEVENTS_FWD_DISCARD,
474 ANA_ANEVENTS_MULTICAST_FLOOD,
475 ANA_ANEVENTS_UNICAST_FLOOD,
476 ANA_ANEVENTS_DEST_KNOWN,
477 ANA_ANEVENTS_BUCKET3_MATCH,
478 ANA_ANEVENTS_BUCKET2_MATCH,
479 ANA_ANEVENTS_BUCKET1_MATCH,
480 ANA_ANEVENTS_BUCKET0_MATCH,
481 ANA_ANEVENTS_CPU_OPERATION,
482 ANA_ANEVENTS_DMAC_LOOKUP,
483 ANA_ANEVENTS_SMAC_LOOKUP,
484 ANA_ANEVENTS_SEQ_GEN_ERR_0,
485 ANA_ANEVENTS_SEQ_GEN_ERR_1,
486 ANA_TABLES_MACACCESS_B_DOM,
487 ANA_TABLES_MACTINDX_BUCKET,
488 ANA_TABLES_MACTINDX_M_INDEX,
489 QSYS_SWITCH_PORT_MODE_PORT_ENA,
490 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG,
491 QSYS_SWITCH_PORT_MODE_YEL_RSRVD,
492 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,
493 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA,
494 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE,
495 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
496 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
497 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
498 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
499 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
500 SYS_PORT_MODE_DATA_WO_TS,
501 SYS_PORT_MODE_INCL_INJ_HDR,
502 SYS_PORT_MODE_INCL_XTR_HDR,
503 SYS_PORT_MODE_INCL_HDR_ERR,
504 SYS_RESET_CFG_CORE_ENA,
505 SYS_RESET_CFG_MEM_ENA,
506 SYS_RESET_CFG_MEM_INIT,
507 GCB_SOFT_RST_SWC_RST,
508 GCB_MIIM_MII_STATUS_PENDING,
509 GCB_MIIM_MII_STATUS_BUSY,
510 SYS_PAUSE_CFG_PAUSE_START,
511 SYS_PAUSE_CFG_PAUSE_STOP,
512 SYS_PAUSE_CFG_PAUSE_ENA,
518 VCAP_CORE_UPDATE_CTRL,
520 /* VCAP_CORE_CACHE */
521 VCAP_CACHE_ENTRY_DAT,
523 VCAP_CACHE_ACTION_DAT,
528 VCAP_CONST_ENTRY_WIDTH,
529 VCAP_CONST_ENTRY_CNT,
530 VCAP_CONST_ENTRY_SWCNT,
531 VCAP_CONST_ENTRY_TG_WIDTH,
532 VCAP_CONST_ACTION_DEF_CNT,
533 VCAP_CONST_ACTION_WIDTH,
534 VCAP_CONST_CNT_WIDTH,
539 enum ocelot_ptp_pins {
547 struct ocelot_stat_layout {
549 char name[ETH_GSTRING_LEN];
552 enum ocelot_tag_prefix {
553 OCELOT_TAG_PREFIX_DISABLED = 0,
554 OCELOT_TAG_PREFIX_NONE,
555 OCELOT_TAG_PREFIX_SHORT,
556 OCELOT_TAG_PREFIX_LONG,
562 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
563 int (*netdev_to_port)(struct net_device *dev);
564 int (*reset)(struct ocelot *ocelot);
565 u16 (*wm_enc)(u16 value);
568 struct ocelot_vcap_block {
569 struct list_head rules;
580 struct ocelot *ocelot;
582 struct regmap *target;
585 /* VLAN that untagged frames are classified to, on ingress */
586 struct ocelot_vlan pvid_vlan;
587 /* The VLAN ID that will be transmitted as untagged, on egress */
588 struct ocelot_vlan native_vlan;
591 struct sk_buff_head tx_skbs;
593 spinlock_t ts_id_lock;
595 phy_interface_t phy_mode;
603 const struct ocelot_ops *ops;
604 struct regmap *targets[TARGET_MAX];
605 struct regmap_field *regfields[REGFIELD_MAX];
606 const u32 *const *map;
607 const struct ocelot_stat_layout *stats_layout;
608 unsigned int num_stats;
613 struct net_device *hw_bridge_dev;
617 struct ocelot_port **ports;
619 u8 base_mac[ETH_ALEN];
621 /* Keep track of the vlan port masks */
622 u32 vlan_mask[VLAN_N_VID];
624 /* Switches like VSC9959 have flooding per traffic class */
625 int num_flooding_pgids;
627 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
628 * the CPU is located after the physical ports (at the
629 * num_phys_ports index).
635 enum ocelot_tag_prefix inj_prefix;
636 enum ocelot_tag_prefix xtr_prefix;
640 struct list_head multicast;
641 struct list_head pgids;
643 struct list_head dummy_rules;
644 struct ocelot_vcap_block block[3];
645 struct vcap_props *vcap;
647 /* Workqueue to check statistics for overflow with its lock */
648 struct mutex stats_lock;
650 struct delayed_work stats_work;
651 struct workqueue_struct *stats_queue;
653 struct workqueue_struct *owq;
656 struct ptp_clock *ptp_clock;
657 struct ptp_clock_info ptp_info;
658 struct hwtstamp_config hwtstamp_config;
659 /* Protects the PTP interface state */
660 struct mutex ptp_lock;
661 /* Protects the PTP clock */
662 spinlock_t ptp_clock_lock;
663 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM];
666 struct ocelot_policer {
667 u32 rate; /* kilobit per second */
668 u32 burst; /* bytes */
671 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
672 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
673 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
674 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
676 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
677 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
678 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
679 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
681 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
682 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
683 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
684 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
686 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
687 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
688 #define ocelot_fields_write(ocelot, id, reg, val) regmap_fields_write((ocelot)->regfields[(reg)], (id), (val))
689 #define ocelot_fields_read(ocelot, id, reg, val) regmap_fields_read((ocelot)->regfields[(reg)], (id), (val))
691 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \
692 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
693 #define ocelot_target_read_gix(ocelot, target, reg, gi) \
694 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi))
695 #define ocelot_target_read_rix(ocelot, target, reg, ri) \
696 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri))
697 #define ocelot_target_read(ocelot, target, reg) \
698 __ocelot_target_read_ix(ocelot, target, reg, 0)
700 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \
701 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
702 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \
703 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi))
704 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \
705 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri))
706 #define ocelot_target_write(ocelot, target, val, reg) \
707 __ocelot_target_write_ix(ocelot, target, val, reg, 0)
710 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
711 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
712 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg);
713 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
714 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
715 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
717 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
718 u32 reg, u32 offset);
719 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
720 u32 val, u32 reg, u32 offset);
722 /* Hardware initialization */
723 int ocelot_regfields_init(struct ocelot *ocelot,
724 const struct reg_field *const regfields);
725 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
726 int ocelot_init(struct ocelot *ocelot);
727 void ocelot_deinit(struct ocelot *ocelot);
728 void ocelot_init_port(struct ocelot *ocelot, int port);
729 void ocelot_deinit_port(struct ocelot *ocelot, int port);
732 void ocelot_port_enable(struct ocelot *ocelot, int port,
733 struct phy_device *phy);
734 void ocelot_port_disable(struct ocelot *ocelot, int port);
735 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
736 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
737 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
738 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
739 struct ethtool_ts_info *info);
740 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
741 int ocelot_port_flush(struct ocelot *ocelot, int port);
742 void ocelot_adjust_link(struct ocelot *ocelot, int port,
743 struct phy_device *phydev);
744 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled,
745 struct switchdev_trans *trans);
746 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
747 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
748 struct net_device *bridge);
749 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
750 struct net_device *bridge);
751 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
752 dsa_fdb_dump_cb_t *cb, void *data);
753 int ocelot_fdb_add(struct ocelot *ocelot, int port,
754 const unsigned char *addr, u16 vid);
755 int ocelot_fdb_del(struct ocelot *ocelot, int port,
756 const unsigned char *addr, u16 vid);
757 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
759 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
761 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
762 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
763 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
764 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,
765 struct sk_buff *clone);
766 void ocelot_get_txtstamp(struct ocelot *ocelot);
767 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
768 int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
769 int ocelot_port_policer_add(struct ocelot *ocelot, int port,
770 struct ocelot_policer *pol);
771 int ocelot_port_policer_del(struct ocelot *ocelot, int port);
772 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
773 struct flow_cls_offload *f, bool ingress);
774 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
775 struct flow_cls_offload *f, bool ingress);
776 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
777 struct flow_cls_offload *f, bool ingress);
778 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
779 const struct switchdev_obj_port_mdb *mdb);
780 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
781 const struct switchdev_obj_port_mdb *mdb);