1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
14 /* Port Group IDs (PGID) are masks of destination ports.
16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
17 * frame, and forwards the frame to the ports that are present in the logical
20 * These PGID lookups are:
21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
22 * which the switch selects a destination PGID:
23 * - The {DMAC, VID} is present in the MAC table. In that case, the
24 * destination PGID is given by the DEST_IDX field of the MAC table entry
26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
27 * frame is disseminated as being either unicast, multicast or broadcast,
28 * and according to that, the destination PGID is chosen as being the
29 * value contained by ANA_FLOODING_FLD_UNICAST,
30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
31 * The destination PGID can be an unicast set: the first PGIDs, 0 to
32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
34 * a physical port and has a single bit set in the destination ports mask:
35 * that corresponding to the port number itself. In contrast, a multicast
36 * PGID will have potentially more than one single bit set in the destination
38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
39 * dissects each frame and generates a 4-bit Link Aggregation Code which is
40 * used for this second PGID table lookup. The goal of link aggregation is to
41 * hash multiple flows within the same LAG on to different destination ports.
42 * The first lookup will result in a PGID with all the LAG members present in
43 * the destination ports mask, and the second lookup, by Link Aggregation
44 * Code, will ensure that each flow gets forwarded only to a single port out
45 * of that mask (there are no duplicates).
46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
47 * is indexed with the ingress port (plus 80). These PGIDs answer the
48 * question "is port i allowed to forward traffic to port j?" If yes, then
49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
53 /* Reserve some destination PGIDs at the end of the range:
54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
55 * of the switch port net devices, towards the CPU port module.
56 * PGID_UC: the flooding destinations for unknown unicast traffic.
57 * PGID_MC: the flooding destinations for broadcast and non-IP multicast
59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
65 #define PGID_MCIPV4 62
66 #define PGID_MCIPV6 63
68 #define for_each_unicast_dest_pgid(ocelot, pgid) \
70 (pgid) < (ocelot)->num_phys_ports; \
73 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \
74 for ((pgid) = (ocelot)->num_phys_ports + 1; \
78 #define for_each_aggr_pgid(ocelot, pgid) \
79 for ((pgid) = PGID_AGGR; \
83 /* Aggregation PGIDs, one per Link Aggregation Code */
86 /* Source PGIDs, one per physical port */
89 #define IFH_INJ_BYPASS BIT(31)
90 #define IFH_INJ_POP_CNT_DISABLE (3 << 28)
92 #define IFH_TAG_TYPE_C 0
93 #define IFH_TAG_TYPE_S 1
95 #define IFH_REW_OP_NOOP 0x0
96 #define IFH_REW_OP_DSCP 0x1
97 #define IFH_REW_OP_ONE_STEP_PTP 0x2
98 #define IFH_REW_OP_TWO_STEP_PTP 0x3
99 #define IFH_REW_OP_ORIGIN_PTP 0x5
101 #define OCELOT_TAG_LEN 16
102 #define OCELOT_SHORT_PREFIX_LEN 4
103 #define OCELOT_LONG_PREFIX_LEN 16
105 #define OCELOT_SPEED_2500 0
106 #define OCELOT_SPEED_1000 1
107 #define OCELOT_SPEED_100 2
108 #define OCELOT_SPEED_10 3
110 #define OCELOT_PTP_PINS_NUM 4
112 #define TARGET_OFFSET 24
113 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
114 #define REG(reg, offset) [reg & REG_MASK] = offset
116 #define REG_RESERVED_ADDR 0xffffffff
117 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
134 ANA_ADVLEARN = ANA << TARGET_OFFSET,
139 ANA_STORMLIMIT_BURST,
158 ANA_TABLES_STREAMDATA,
159 ANA_TABLES_MACACCESS,
161 ANA_TABLES_VLANACCESS,
163 ANA_TABLES_ISDXACCESS,
166 ANA_TABLES_PTP_ID_HIGH,
167 ANA_TABLES_PTP_ID_LOW,
168 ANA_TABLES_STREAMACCESS,
169 ANA_TABLES_STREAMTIDX,
170 ANA_TABLES_SEQ_HISTORY,
172 ANA_TABLES_SFID_MASK,
173 ANA_TABLES_SFIDACCESS,
183 ANA_SG_GCL_GS_CONFIG,
184 ANA_SG_GCL_TI_CONFIG,
192 ANA_PORT_VCAP_S1_KEY_CFG,
193 ANA_PORT_VCAP_S2_CFG,
194 ANA_PORT_PCP_DEI_MAP,
195 ANA_PORT_CPU_FWD_CFG,
196 ANA_PORT_CPU_FWD_BPDU_CFG,
197 ANA_PORT_CPU_FWD_GARP_CFG,
198 ANA_PORT_CPU_FWD_CCM_CFG,
202 ANA_PORT_PTP_DLY1_CFG,
203 ANA_PORT_PTP_DLY2_CFG,
217 ANA_VCAP_RNG_TYPE_CFG,
218 ANA_VCAP_RNG_VAL_CFG,
233 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
245 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
246 QSYS_SWITCH_PORT_MODE,
258 QSYS_TIMED_FRAME_ENTRY,
261 QSYS_TFRM_TIMER_CFG_1,
262 QSYS_TFRM_TIMER_CFG_2,
263 QSYS_TFRM_TIMER_CFG_3,
264 QSYS_TFRM_TIMER_CFG_4,
265 QSYS_TFRM_TIMER_CFG_5,
266 QSYS_TFRM_TIMER_CFG_6,
267 QSYS_TFRM_TIMER_CFG_7,
268 QSYS_TFRM_TIMER_CFG_8,
296 QSYS_TAS_PARAM_CFG_CTRL,
298 QSYS_PARAM_CFG_REG_1,
299 QSYS_PARAM_CFG_REG_2,
300 QSYS_PARAM_CFG_REG_3,
301 QSYS_PARAM_CFG_REG_4,
302 QSYS_PARAM_CFG_REG_5,
305 QSYS_PARAM_STATUS_REG_1,
306 QSYS_PARAM_STATUS_REG_2,
307 QSYS_PARAM_STATUS_REG_3,
308 QSYS_PARAM_STATUS_REG_4,
309 QSYS_PARAM_STATUS_REG_5,
310 QSYS_PARAM_STATUS_REG_6,
311 QSYS_PARAM_STATUS_REG_7,
312 QSYS_PARAM_STATUS_REG_8,
313 QSYS_PARAM_STATUS_REG_9,
314 QSYS_GCL_STATUS_REG_1,
315 QSYS_GCL_STATUS_REG_2,
316 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
320 REW_PCP_DEI_QOS_MAP_CFG,
324 REW_DSCP_REMAP_DP1_CFG,
329 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
330 SYS_COUNT_RX_UNICAST,
331 SYS_COUNT_RX_MULTICAST,
332 SYS_COUNT_RX_BROADCAST,
334 SYS_COUNT_RX_FRAGMENTS,
335 SYS_COUNT_RX_JABBERS,
336 SYS_COUNT_RX_CRC_ALIGN_ERRS,
337 SYS_COUNT_RX_SYM_ERRS,
340 SYS_COUNT_RX_128_255,
341 SYS_COUNT_RX_256_1023,
342 SYS_COUNT_RX_1024_1526,
343 SYS_COUNT_RX_1527_MAX,
345 SYS_COUNT_RX_CONTROL,
347 SYS_COUNT_RX_CLASSIFIED_DROPS,
349 SYS_COUNT_TX_UNICAST,
350 SYS_COUNT_TX_MULTICAST,
351 SYS_COUNT_TX_BROADCAST,
352 SYS_COUNT_TX_COLLISION,
357 SYS_COUNT_TX_128_511,
358 SYS_COUNT_TX_512_1023,
359 SYS_COUNT_TX_1024_1526,
360 SYS_COUNT_TX_1527_MAX,
371 SYS_REW_MAC_HIGH_CFG,
373 SYS_TIMESTAMP_OFFSET,
395 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
402 PTP_PIN_CFG = PTP << TARGET_OFFSET,
406 PTP_PIN_WF_HIGH_PERIOD,
407 PTP_PIN_WF_LOW_PERIOD,
410 PTP_CLK_CFG_ADJ_FREQ,
411 GCB_SOFT_RST = GCB << TARGET_OFFSET,
412 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
427 DEV_MAC_FC_MAC_LOW_CFG,
428 DEV_MAC_FC_MAC_HIGH_CFG,
439 PCS1G_ANEG_NP_STATUS,
445 PCS1G_LPI_WAKE_ERROR_CNT,
447 PCS1G_TSTPAT_MODE_CFG,
450 DEV_PCS_FX100_STATUS,
453 enum ocelot_regfield {
454 ANA_ADVLEARN_VLAN_CHK,
455 ANA_ADVLEARN_LEARN_MIRROR,
456 ANA_ANEVENTS_FLOOD_DISCARD,
457 ANA_ANEVENTS_MSTI_DROP,
458 ANA_ANEVENTS_ACLKILL,
459 ANA_ANEVENTS_ACLUSED,
460 ANA_ANEVENTS_AUTOAGE,
461 ANA_ANEVENTS_VS2TTL1,
462 ANA_ANEVENTS_STORM_DROP,
463 ANA_ANEVENTS_LEARN_DROP,
464 ANA_ANEVENTS_AGED_ENTRY,
465 ANA_ANEVENTS_CPU_LEARN_FAILED,
466 ANA_ANEVENTS_AUTO_LEARN_FAILED,
467 ANA_ANEVENTS_LEARN_REMOVE,
468 ANA_ANEVENTS_AUTO_LEARNED,
469 ANA_ANEVENTS_AUTO_MOVED,
470 ANA_ANEVENTS_DROPPED,
471 ANA_ANEVENTS_CLASSIFIED_DROP,
472 ANA_ANEVENTS_CLASSIFIED_COPY,
473 ANA_ANEVENTS_VLAN_DISCARD,
474 ANA_ANEVENTS_FWD_DISCARD,
475 ANA_ANEVENTS_MULTICAST_FLOOD,
476 ANA_ANEVENTS_UNICAST_FLOOD,
477 ANA_ANEVENTS_DEST_KNOWN,
478 ANA_ANEVENTS_BUCKET3_MATCH,
479 ANA_ANEVENTS_BUCKET2_MATCH,
480 ANA_ANEVENTS_BUCKET1_MATCH,
481 ANA_ANEVENTS_BUCKET0_MATCH,
482 ANA_ANEVENTS_CPU_OPERATION,
483 ANA_ANEVENTS_DMAC_LOOKUP,
484 ANA_ANEVENTS_SMAC_LOOKUP,
485 ANA_ANEVENTS_SEQ_GEN_ERR_0,
486 ANA_ANEVENTS_SEQ_GEN_ERR_1,
487 ANA_TABLES_MACACCESS_B_DOM,
488 ANA_TABLES_MACTINDX_BUCKET,
489 ANA_TABLES_MACTINDX_M_INDEX,
490 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
491 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
492 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
493 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
494 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
495 SYS_RESET_CFG_CORE_ENA,
496 SYS_RESET_CFG_MEM_ENA,
497 SYS_RESET_CFG_MEM_INIT,
498 GCB_SOFT_RST_SWC_RST,
502 enum ocelot_ptp_pins {
510 struct ocelot_stat_layout {
512 char name[ETH_GSTRING_LEN];
515 enum ocelot_tag_prefix {
516 OCELOT_TAG_PREFIX_DISABLED = 0,
517 OCELOT_TAG_PREFIX_NONE,
518 OCELOT_TAG_PREFIX_SHORT,
519 OCELOT_TAG_PREFIX_LONG,
525 int (*reset)(struct ocelot *ocelot);
528 struct ocelot_vcap_block {
529 struct list_head rules;
535 struct ocelot *ocelot;
537 struct regmap *target;
541 /* Ingress default VLAN (pvid) */
544 /* Egress default VLAN (vid) */
548 struct sk_buff_head tx_skbs;
551 phy_interface_t phy_mode;
557 const struct ocelot_ops *ops;
558 struct regmap *targets[TARGET_MAX];
559 struct regmap_field *regfields[REGFIELD_MAX];
560 const u32 *const *map;
561 const struct ocelot_stat_layout *stats_layout;
562 unsigned int num_stats;
567 struct net_device *hw_bridge_dev;
571 struct ocelot_port **ports;
573 u8 base_mac[ETH_ALEN];
575 /* Keep track of the vlan port masks */
576 u32 vlan_mask[VLAN_N_VID];
578 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
579 * the CPU is located after the physical ports (at the
580 * num_phys_ports index).
586 enum ocelot_tag_prefix inj_prefix;
587 enum ocelot_tag_prefix xtr_prefix;
591 struct list_head multicast;
593 struct ocelot_vcap_block block;
595 const struct vcap_field *vcap_is2_keys;
596 const struct vcap_field *vcap_is2_actions;
597 const struct vcap_props *vcap;
599 /* Workqueue to check statistics for overflow with its lock */
600 struct mutex stats_lock;
602 struct delayed_work stats_work;
603 struct workqueue_struct *stats_queue;
606 struct ptp_clock *ptp_clock;
607 struct ptp_clock_info ptp_info;
608 struct hwtstamp_config hwtstamp_config;
609 /* Protects the PTP interface state */
610 struct mutex ptp_lock;
611 /* Protects the PTP clock */
612 spinlock_t ptp_clock_lock;
613 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM];
616 struct ocelot_policer {
617 u32 rate; /* kilobit per second */
618 u32 burst; /* bytes */
621 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
622 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
623 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
624 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
626 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
627 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
628 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
629 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
631 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
632 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
633 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
634 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
637 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
638 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
639 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
640 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
641 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
644 /* Hardware initialization */
645 int ocelot_regfields_init(struct ocelot *ocelot,
646 const struct reg_field *const regfields);
647 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
648 void ocelot_configure_cpu(struct ocelot *ocelot, int npi,
649 enum ocelot_tag_prefix injection,
650 enum ocelot_tag_prefix extraction);
651 int ocelot_init(struct ocelot *ocelot);
652 void ocelot_deinit(struct ocelot *ocelot);
653 void ocelot_init_port(struct ocelot *ocelot, int port);
656 void ocelot_port_enable(struct ocelot *ocelot, int port,
657 struct phy_device *phy);
658 void ocelot_port_disable(struct ocelot *ocelot, int port);
659 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
660 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
661 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
662 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
663 struct ethtool_ts_info *info);
664 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
665 void ocelot_adjust_link(struct ocelot *ocelot, int port,
666 struct phy_device *phydev);
667 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
669 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
670 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
671 struct net_device *bridge);
672 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
673 struct net_device *bridge);
674 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
675 dsa_fdb_dump_cb_t *cb, void *data);
676 int ocelot_fdb_add(struct ocelot *ocelot, int port,
677 const unsigned char *addr, u16 vid);
678 int ocelot_fdb_del(struct ocelot *ocelot, int port,
679 const unsigned char *addr, u16 vid);
680 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
682 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
683 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
684 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
685 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port,
686 struct sk_buff *skb);
687 void ocelot_get_txtstamp(struct ocelot *ocelot);
688 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
689 int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
690 int ocelot_port_policer_add(struct ocelot *ocelot, int port,
691 struct ocelot_policer *pol);
692 int ocelot_port_policer_del(struct ocelot *ocelot, int port);
693 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
694 struct flow_cls_offload *f, bool ingress);
695 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
696 struct flow_cls_offload *f, bool ingress);
697 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
698 struct flow_cls_offload *f, bool ingress);
699 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
700 const struct switchdev_obj_port_mdb *mdb);
701 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
702 const struct switchdev_obj_port_mdb *mdb);