2 * Microsemi Switchtec PCIe Driver
3 * Copyright (c) 2017, Microsemi Corporation
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 #include <linux/pci.h>
20 #include <linux/cdev.h>
22 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
23 #define SWITCHTEC_MAX_PFF_CSR 48
25 #define SWITCHTEC_EVENT_OCCURRED BIT(0)
26 #define SWITCHTEC_EVENT_CLEAR BIT(0)
27 #define SWITCHTEC_EVENT_EN_LOG BIT(1)
28 #define SWITCHTEC_EVENT_EN_CLI BIT(2)
29 #define SWITCHTEC_EVENT_EN_IRQ BIT(3)
30 #define SWITCHTEC_EVENT_FATAL BIT(4)
32 #define SWITCHTEC_DMA_MRPC_EN BIT(0)
34 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
35 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
36 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
37 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
38 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
39 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
40 SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
41 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
45 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
46 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
57 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
58 SWITCHTEC_MRPC_STATUS_DONE = 2,
59 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
60 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
63 struct sw_event_regs {
64 u64 event_report_ctrl;
66 u64 part_event_bitmap;
70 u32 stack_error_event_hdr;
71 u32 stack_error_event_data;
73 u32 ppu_error_event_hdr;
74 u32 ppu_error_event_data;
76 u32 isp_error_event_hdr;
77 u32 isp_error_event_data;
79 u32 sys_reset_event_hdr;
89 u32 twi_mrpc_comp_hdr;
90 u32 twi_mrpc_comp_data;
92 u32 twi_mrpc_comp_async_hdr;
93 u32 twi_mrpc_comp_async_data;
95 u32 cli_mrpc_comp_hdr;
96 u32 cli_mrpc_comp_data;
98 u32 cli_mrpc_comp_async_hdr;
99 u32 cli_mrpc_comp_async_data;
101 u32 gpio_interrupt_hdr;
102 u32 gpio_interrupt_data;
110 SWITCHTEC_CFG0_RUNNING = 0x04,
111 SWITCHTEC_CFG1_RUNNING = 0x05,
112 SWITCHTEC_IMG0_RUNNING = 0x03,
113 SWITCHTEC_IMG1_RUNNING = 0x07,
116 struct sys_info_regs {
119 u32 firmware_version;
121 u32 vendor_table_revision;
122 u32 table_format_version;
124 u32 cfg_file_fmt_version;
130 char product_revision[4];
131 char component_vendor[8];
133 u8 component_revision;
136 struct flash_info_regs {
137 u32 flash_part_map_upd_idx;
139 struct active_partition_info {
145 struct active_partition_info active_cfg;
146 struct active_partition_info inactive_img;
147 struct active_partition_info inactive_cfg;
151 struct partition_info {
156 struct partition_info cfg1;
157 struct partition_info img0;
158 struct partition_info img1;
159 struct partition_info nvlog;
160 struct partition_info vendor[8];
164 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
165 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
166 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
169 struct ntb_info_regs {
177 struct nt_partition_info {
180 u32 target_part_high;
185 struct part_cfg_regs {
192 u32 dsp_pff_inst_id[47];
194 u16 vep_vector_number;
195 u16 usp_vector_number;
196 u32 port_event_bitmap;
198 u32 part_event_summary;
201 u32 part_reset_data[5];
203 u32 mrpc_comp_data[5];
204 u32 mrpc_comp_async_hdr;
205 u32 mrpc_comp_async_data[5];
207 u32 dyn_binding_data[5];
212 NTB_CTRL_PART_OP_LOCK = 0x1,
213 NTB_CTRL_PART_OP_CFG = 0x2,
214 NTB_CTRL_PART_OP_RESET = 0x3,
216 NTB_CTRL_PART_STATUS_NORMAL = 0x1,
217 NTB_CTRL_PART_STATUS_LOCKED = 0x2,
218 NTB_CTRL_PART_STATUS_LOCKING = 0x3,
219 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
220 NTB_CTRL_PART_STATUS_RESETTING = 0x5,
222 NTB_CTRL_BAR_VALID = 1 << 0,
223 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
224 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
226 NTB_CTRL_REQ_ID_EN = 1 << 0,
228 NTB_CTRL_LUT_EN = 1 << 0,
230 NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
233 struct ntb_ctrl_regs {
234 u32 partition_status;
239 u16 lut_table_entries;
240 u16 lut_table_offset;
242 u16 req_id_table_size;
243 u16 req_id_table_offset;
252 u32 req_id_table[256];
257 #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
258 #define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
260 struct ntb_dbmsg_regs {
290 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
291 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
292 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
293 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
296 struct pff_csr_regs {
308 u32 pci_subsystem_id;
309 u32 pci_expansion_rom;
313 u32 pci_cap_region[48];
314 u32 pcie_cap_region[448];
315 u32 indirect_gas_window[128];
316 u32 indirect_gas_window_off;
318 u32 pff_event_summary;
321 u32 aer_in_p2p_data[5];
323 u32 aer_in_vep_data[5];
334 u32 threshold_data[5];
336 u32 power_mgmt_data[5];
337 u32 tlp_throttling_hdr;
338 u32 tlp_throttling_data[5];
340 u32 force_speed_data[5];
341 u32 credit_timeout_hdr;
342 u32 credit_timeout_data[5];
344 u32 link_state_data[5];
348 struct switchtec_ntb;
350 struct dma_mrpc_output {
355 u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
358 struct switchtec_dev {
359 struct pci_dev *pdev;
366 char pff_local[SWITCHTEC_MAX_PFF_CSR];
369 struct mrpc_regs __iomem *mmio_mrpc;
370 struct sw_event_regs __iomem *mmio_sw_event;
371 struct sys_info_regs __iomem *mmio_sys_info;
372 struct flash_info_regs __iomem *mmio_flash_info;
373 struct ntb_info_regs __iomem *mmio_ntb;
374 struct part_cfg_regs __iomem *mmio_part_cfg;
375 struct part_cfg_regs __iomem *mmio_part_cfg_all;
376 struct pff_csr_regs __iomem *mmio_pff_csr;
379 * The mrpc mutex must be held when accessing the other
380 * mrpc_ fields, alive flag and stuser->state field
382 struct mutex mrpc_mutex;
383 struct list_head mrpc_queue;
385 struct work_struct mrpc_work;
386 struct delayed_work mrpc_timeout;
389 wait_queue_head_t event_wq;
392 struct work_struct link_event_work;
393 void (*link_notifier)(struct switchtec_dev *stdev);
394 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
396 struct switchtec_ntb *sndev;
398 struct dma_mrpc_output *dma_mrpc;
399 dma_addr_t dma_mrpc_dma_addr;
402 static inline struct switchtec_dev *to_stdev(struct device *dev)
404 return container_of(dev, struct switchtec_dev, dev);
407 extern struct class *switchtec_class;