1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
7 #include <linux/mod_devicetable.h>
12 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
14 /* SDW Broadcast Device Number */
15 #define SDW_BROADCAST_DEV_NUM 15
17 /* SDW Enumeration Device Number */
18 #define SDW_ENUM_DEV_NUM 0
20 /* SDW Group Device Numbers */
21 #define SDW_GROUP12_DEV_NUM 12
22 #define SDW_GROUP13_DEV_NUM 13
24 /* SDW Master Device Number, not supported yet */
25 #define SDW_MASTER_DEV_NUM 14
27 #define SDW_NUM_DEV_ID_REGISTERS 6
28 /* frame shape defines */
31 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
32 * fill hole with 0, one more dummy entry is added
34 #define SDW_FRAME_ROWS 24
35 #define SDW_FRAME_COLS 8
36 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
38 #define SDW_FRAME_CTRL_BITS 48
39 #define SDW_MAX_DEVICES 11
41 #define SDW_VALID_PORT_RANGE(n) ((n) <= 14 && (n) >= 1)
44 SDW_PORT_DIRN_SINK = 0,
50 * constants for flow control, ports and transport
52 * these are bit masks as devices can have multiple capabilities
56 * flow modes for SDW port. These can be isochronous, tx controlled,
57 * rx controlled or async
59 #define SDW_PORT_FLOW_MODE_ISOCH 0
60 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0)
61 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1)
62 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0)
64 /* sample packaging for block. It can be per port or per channel */
65 #define SDW_BLOCK_PACKG_PER_PORT BIT(0)
66 #define SDW_BLOCK_PACKG_PER_CH BIT(1)
69 * enum sdw_slave_status - Slave status
70 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
71 * @SDW_SLAVE_ATTACHED: Slave is attached with bus.
72 * @SDW_SLAVE_ALERT: Some alert condition on the Slave
73 * @SDW_SLAVE_RESERVED: Reserved for future use
75 enum sdw_slave_status {
76 SDW_SLAVE_UNATTACHED = 0,
77 SDW_SLAVE_ATTACHED = 1,
79 SDW_SLAVE_RESERVED = 3,
83 * enum sdw_clk_stop_type: clock stop operations
85 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
86 * @SDW_CLK_POST_PREPARE: post clock stop prepare
87 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
88 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
90 enum sdw_clk_stop_type {
91 SDW_CLK_PRE_PREPARE = 0,
93 SDW_CLK_PRE_DEPREPARE,
94 SDW_CLK_POST_DEPREPARE,
98 * enum sdw_command_response - Command response as defined by SDW spec
99 * @SDW_CMD_OK: cmd was successful
100 * @SDW_CMD_IGNORED: cmd was ignored
101 * @SDW_CMD_FAIL: cmd was NACKed
102 * @SDW_CMD_TIMEOUT: cmd timedout
103 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above
105 * NOTE: The enum is different than actual Spec as response in the Spec is
106 * combination of ACK/NAK bits
108 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec
110 enum sdw_command_response {
115 SDW_CMD_FAIL_OTHER = 4,
118 /* block group count enum */
119 enum sdw_dpn_grouping {
120 SDW_BLK_GRP_CNT_1 = 0,
121 SDW_BLK_GRP_CNT_2 = 1,
122 SDW_BLK_GRP_CNT_3 = 2,
123 SDW_BLK_GRP_CNT_4 = 3,
127 * enum sdw_stream_type: data stream type
129 * @SDW_STREAM_PCM: PCM data stream
130 * @SDW_STREAM_PDM: PDM data stream
132 * spec doesn't define this, but is used in implementation
134 enum sdw_stream_type {
140 * enum sdw_data_direction: Data direction
142 * @SDW_DATA_DIR_RX: Data into Port
143 * @SDW_DATA_DIR_TX: Data out of Port
145 enum sdw_data_direction {
151 * enum sdw_port_data_mode: Data Port mode
153 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received
155 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of
156 * logic 1. The encoding will result in signal transitions at every bitslot
158 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of
159 * logic 0. The encoding will result in no signal transitions
160 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce
161 * a pseudo random data pattern that is transferred
163 enum sdw_port_data_mode {
164 SDW_PORT_DATA_MODE_NORMAL = 0,
165 SDW_PORT_DATA_MODE_STATIC_1 = 1,
166 SDW_PORT_DATA_MODE_STATIC_0 = 2,
167 SDW_PORT_DATA_MODE_PRBS = 3,
171 * SDW properties, defined in MIPI DisCo spec v1.0
173 enum sdw_clk_stop_reset_behave {
174 SDW_CLK_STOP_KEEP_STATUS = 1,
178 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
180 * @SDW_P15_READ_IGNORED: Read is ignored
181 * @SDW_P15_CMD_OK: Command is ok
183 enum sdw_p15_behave {
184 SDW_P15_READ_IGNORED = 0,
189 * enum sdw_dpn_type - Data port types
190 * @SDW_DPN_FULL: Full Data Port is supported
191 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec.
192 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3
193 * are not implemented.
194 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec.
195 * DPN_SampleCtrl2, DPN_HCtrl are not implemented.
204 * enum sdw_clk_stop_mode - Clock Stop modes
205 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
207 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
208 * not capable of continuing operation seamlessly when the clock restarts
210 enum sdw_clk_stop_mode {
211 SDW_CLK_STOP_MODE0 = 0,
212 SDW_CLK_STOP_MODE1 = 1,
216 * struct sdw_dp0_prop - DP0 properties
217 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
219 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
221 * @num_words: number of wordlengths supported
222 * @words: wordlengths supported
223 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady
225 * @simple_ch_prep_sm: If channel prepare sequence is required
226 * @imp_def_interrupts: If set, each bit corresponds to support for
227 * implementation-defined interrupts
229 * The wordlengths are specified by Spec as max, min AND number of
230 * discrete values, implementation can define based on the wordlengths they
233 struct sdw_dp0_prop {
238 bool BRA_flow_controlled;
239 bool simple_ch_prep_sm;
240 bool imp_def_interrupts;
244 * struct sdw_dpn_audio_mode - Audio mode properties for DPn
245 * @bus_min_freq: Minimum bus frequency, in Hz
246 * @bus_max_freq: Maximum bus frequency, in Hz
247 * @bus_num_freq: Number of discrete frequencies supported
248 * @bus_freq: Discrete bus frequencies, in Hz
249 * @min_freq: Minimum sampling frequency, in Hz
250 * @max_freq: Maximum sampling bus frequency, in Hz
251 * @num_freq: Number of discrete sampling frequency supported
252 * @freq: Discrete sampling frequencies, in Hz
253 * @prep_ch_behave: Specifies the dependencies between Channel Prepare
254 * sequence and bus clock configuration
255 * If 0, Channel Prepare can happen at any Bus clock rate
256 * If 1, Channel Prepare sequence shall happen only after Bus clock is
257 * changed to a frequency supported by this mode or compatible modes
258 * described by the next field
259 * @glitchless: Bitmap describing possible glitchless transitions from this
260 * Audio Mode to other Audio Modes
262 struct sdw_dpn_audio_mode {
276 * struct sdw_dpn_prop - Data Port DPn properties
278 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
280 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
282 * @num_words: Number of discrete supported wordlengths
283 * @words: Discrete supported wordlength
284 * @type: Data port type. Full, Simplified or Reduced
285 * @max_grouping: Maximum number of samples that can be grouped together for
287 * @simple_ch_prep_sm: If the port supports simplified channel prepare state
289 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
290 * @imp_def_interrupts: If set, each bit corresponds to support for
291 * implementation-defined interrupts
292 * @max_ch: Maximum channels supported
293 * @min_ch: Minimum channels supported
294 * @num_ch: Number of discrete channels supported
295 * @ch: Discrete channels supported
296 * @num_ch_combinations: Number of channel combinations supported
297 * @ch_combinations: Channel combinations supported
298 * @modes: SDW mode supported
299 * @max_async_buffer: Number of samples that this port can buffer in
301 * @block_pack_mode: Type of block port mode supported
302 * @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register
303 * @port_encoding: Payload Channel Sample encoding schemes supported
304 * @audio_modes: Audio modes supported
306 struct sdw_dpn_prop {
312 enum sdw_dpn_type type;
314 bool simple_ch_prep_sm;
316 u32 imp_def_interrupts;
321 u32 num_ch_combinations;
322 u32 *ch_combinations;
324 u32 max_async_buffer;
325 bool block_pack_mode;
326 bool read_only_wordlength;
328 struct sdw_dpn_audio_mode *audio_modes;
332 * struct sdw_slave_prop - SoundWire Slave properties
333 * @mipi_revision: Spec version of the implementation
334 * @wake_capable: Wake-up events are supported
335 * @test_mode_capable: If test mode is supported
336 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
337 * @simple_clk_stop_capable: Simple clock mode is supported
338 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
339 * Machine transitions, in milliseconds
340 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
341 * transitions, in milliseconds
342 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare
343 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
344 * @high_PHY_capable: Slave is HighPHY capable
345 * @paging_support: Slave implements paging registers SCP_AddrPage1 and
347 * @bank_delay_support: Slave implements bank delay/bridge support registers
348 * SCP_BankDelay and SCP_NextFrame
349 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
351 * @lane_control_support: Slave supports lane control
352 * @master_count: Number of Masters present on this Slave
353 * @source_ports: Bitmap identifying source ports
354 * @sink_ports: Bitmap identifying sink ports
355 * @dp0_prop: Data Port 0 properties
356 * @src_dpn_prop: Source Data Port N properties
357 * @sink_dpn_prop: Sink Data Port N properties
359 struct sdw_slave_prop {
362 bool test_mode_capable;
364 bool simple_clk_stop_capable;
365 u32 clk_stop_timeout;
367 enum sdw_clk_stop_reset_behave reset_behave;
368 bool high_PHY_capable;
370 bool bank_delay_support;
371 enum sdw_p15_behave p15_behave;
372 bool lane_control_support;
376 struct sdw_dp0_prop *dp0_prop;
377 struct sdw_dpn_prop *src_dpn_prop;
378 struct sdw_dpn_prop *sink_dpn_prop;
382 * struct sdw_master_prop - Master properties
383 * @revision: MIPI spec version of the implementation
384 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
385 * @max_clk_freq: Maximum Bus clock frequency, in Hz
386 * @num_clk_gears: Number of clock gears supported
387 * @clk_gears: Clock gears supported
388 * @num_clk_freq: Number of clock frequencies supported, in Hz
389 * @clk_freq: Clock frequencies supported, in Hz
390 * @default_frame_rate: Controller default Frame rate, in Hz
391 * @default_row: Number of rows
392 * @default_col: Number of columns
393 * @dynamic_frame: Dynamic frame shape supported
394 * @err_threshold: Number of times that software may retry sending a single
396 * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
397 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux
399 struct sdw_master_prop {
407 u32 default_frame_rate;
416 int sdw_master_read_prop(struct sdw_bus *bus);
417 int sdw_slave_read_prop(struct sdw_slave *slave);
420 * SDW Slave Structures and APIs
423 #define SDW_IGNORED_UNIQUE_ID 0xFF
426 * struct sdw_slave_id - Slave ID
427 * @mfg_id: MIPI Manufacturer ID
428 * @part_id: Device Part ID
429 * @class_id: MIPI Class ID, unused now.
430 * Currently a placeholder in MIPI SoundWire Spec
431 * @unique_id: Device unique ID
432 * @sdw_version: SDW version implemented
434 * The order of the IDs here does not follow the DisCo spec definitions
436 struct sdw_slave_id {
445 * Helper macros to extract the MIPI-defined IDs
448 * Register Bit Contents
449 * DevId_0 [7:4] 47:44 sdw_version
450 * DevId_0 [3:0] 43:40 unique_id
451 * DevId_1 39:32 mfg_id [15:8]
452 * DevId_2 31:24 mfg_id [7:0]
453 * DevId_3 23:16 part_id [15:8]
454 * DevId_4 15:08 part_id [7:0]
455 * DevId_5 07:00 class_id
457 * The MIPI DisCo for SoundWire defines in addition the link_id as bits 51:48
460 #define SDW_DISCO_LINK_ID(adr) (((adr) >> 48) & GENMASK(3, 0))
461 #define SDW_VERSION(adr) (((adr) >> 44) & GENMASK(3, 0))
462 #define SDW_UNIQUE_ID(adr) (((adr) >> 40) & GENMASK(3, 0))
463 #define SDW_MFG_ID(adr) (((adr) >> 24) & GENMASK(15, 0))
464 #define SDW_PART_ID(adr) (((adr) >> 8) & GENMASK(15, 0))
465 #define SDW_CLASS_ID(adr) ((adr) & GENMASK(7, 0))
468 * struct sdw_slave_intr_status - Slave interrupt status
469 * @control_port: control port status
470 * @port: data port status
472 struct sdw_slave_intr_status {
478 * sdw_reg_bank - SoundWire register banks
479 * @SDW_BANK0: Soundwire register bank 0
480 * @SDW_BANK1: Soundwire register bank 1
488 * struct sdw_bus_conf: Bus configuration
490 * @clk_freq: Clock frequency, in Hz
491 * @num_rows: Number of rows in frame
492 * @num_cols: Number of columns in frame
493 * @bank: Next register bank
495 struct sdw_bus_conf {
496 unsigned int clk_freq;
497 unsigned int num_rows;
498 unsigned int num_cols;
503 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
506 * @ch_mask: Active channel mask
507 * @prepare: Prepare (true) /de-prepare (false) channel
508 * @bank: Register bank, which bank Slave/Master driver should program for
509 * implementation defined registers. This is always updated to next_bank
510 * value read from bus params.
513 struct sdw_prepare_ch {
515 unsigned int ch_mask;
521 * enum sdw_port_prep_ops: Prepare operations for Data Port
523 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
524 * @SDW_OPS_PORT_PREP: Prepare operation for the Port
525 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
527 enum sdw_port_prep_ops {
528 SDW_OPS_PORT_PRE_PREP = 0,
529 SDW_OPS_PORT_PREP = 1,
530 SDW_OPS_PORT_POST_PREP = 2,
534 * struct sdw_bus_params: Structure holding bus configuration
536 * @curr_bank: Current bank in use (BANK0/BANK1)
537 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
539 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
540 * @curr_dr_freq: Current double rate clock frequency, in Hz
541 * @bandwidth: Current bandwidth
542 * @col: Active columns
545 struct sdw_bus_params {
546 enum sdw_reg_bank curr_bank;
547 enum sdw_reg_bank next_bank;
548 unsigned int max_dr_freq;
549 unsigned int curr_dr_freq;
550 unsigned int bandwidth;
556 * struct sdw_slave_ops: Slave driver callback ops
558 * @read_prop: Read Slave properties
559 * @interrupt_callback: Device interrupt notification (invoked in thread
561 * @update_status: Update Slave status
562 * @bus_config: Update the bus config for Slave
563 * @port_prep: Prepare the port with parameters
565 struct sdw_slave_ops {
566 int (*read_prop)(struct sdw_slave *sdw);
567 int (*interrupt_callback)(struct sdw_slave *slave,
568 struct sdw_slave_intr_status *status);
569 int (*update_status)(struct sdw_slave *slave,
570 enum sdw_slave_status status);
571 int (*bus_config)(struct sdw_slave *slave,
572 struct sdw_bus_params *params);
573 int (*port_prep)(struct sdw_slave *slave,
574 struct sdw_prepare_ch *prepare_ch,
575 enum sdw_port_prep_ops pre_ops);
576 int (*get_clk_stop_mode)(struct sdw_slave *slave);
577 int (*clk_stop)(struct sdw_slave *slave,
578 enum sdw_clk_stop_mode mode,
579 enum sdw_clk_stop_type type);
584 * struct sdw_slave - SoundWire Slave
585 * @id: MIPI device ID
587 * @status: Status reported by the Slave
589 * @ops: Slave callback ops
590 * @prop: Slave properties
591 * @debugfs: Slave debugfs
592 * @node: node for bus list
593 * @port_ready: Port ready completion flag for each Slave port
594 * @dev_num: Current Device Number, values can be 0 or dev_num_sticky
595 * @dev_num_sticky: one-time static Device Number assigned by Bus
596 * @probed: boolean tracking driver state
597 * @probe_complete: completion utility to control potential races
598 * on startup between driver probe/initialization and SoundWire
599 * Slave state changes/implementation-defined interrupts
600 * @enumeration_complete: completion utility to control potential races
601 * on startup between device enumeration and read/write access to the
603 * @initialization_complete: completion utility to control potential races
604 * on startup between device enumeration and settings being restored
605 * @unattach_request: mask field to keep track why the Slave re-attached and
606 * was re-initialized. This is useful to deal with potential race conditions
607 * between the Master suspending and the codec resuming, and make sure that
608 * when the Master triggered a reset the Slave is properly enumerated and
612 struct sdw_slave_id id;
614 enum sdw_slave_status status;
616 const struct sdw_slave_ops *ops;
617 struct sdw_slave_prop prop;
618 #ifdef CONFIG_DEBUG_FS
619 struct dentry *debugfs;
621 struct list_head node;
622 struct completion *port_ready;
623 enum sdw_clk_stop_mode curr_clk_stop_mode;
627 struct completion probe_complete;
628 struct completion enumeration_complete;
629 struct completion initialization_complete;
630 u32 unattach_request;
633 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
638 int (*probe)(struct sdw_slave *sdw,
639 const struct sdw_device_id *id);
640 int (*remove)(struct sdw_slave *sdw);
641 void (*shutdown)(struct sdw_slave *sdw);
643 const struct sdw_device_id *id_table;
644 const struct sdw_slave_ops *ops;
646 struct device_driver driver;
649 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \
650 { .mfg_id = (_mfg_id), .part_id = (_part_id), \
651 .driver_data = (unsigned long)(_drv_data) }
653 int sdw_handle_slave_status(struct sdw_bus *bus,
654 enum sdw_slave_status status[]);
657 * SDW master structures and APIs
661 * struct sdw_port_params: Data Port parameters
664 * @bps: Word length of the Port
665 * @flow_mode: Port Data flow mode
666 * @data_mode: Test modes or normal mode
668 * This is used to program the Data Port based on Data Port stream
671 struct sdw_port_params {
674 unsigned int flow_mode;
675 unsigned int data_mode;
679 * struct sdw_transport_params: Data Port Transport Parameters
681 * @blk_grp_ctrl_valid: Port implements block group control
683 * @blk_grp_ctrl: Block group control value
684 * @sample_interval: Sample interval
685 * @offset1: Blockoffset of the payload data
686 * @offset2: Blockoffset of the payload data
687 * @hstart: Horizontal start of the payload data
688 * @hstop: Horizontal stop of the payload data
689 * @blk_pkg_mode: Block per channel or block per port
690 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
691 * data lane is supported in bus
693 * This is used to program the Data Port based on Data Port transport
694 * parameters. All these parameters are banked and can be modified
695 * during a bank switch without any artifacts in audio stream.
697 struct sdw_transport_params {
698 bool blk_grp_ctrl_valid;
699 unsigned int port_num;
700 unsigned int blk_grp_ctrl;
701 unsigned int sample_interval;
702 unsigned int offset1;
703 unsigned int offset2;
706 unsigned int blk_pkg_mode;
707 unsigned int lane_ctrl;
711 * struct sdw_enable_ch: Enable/disable Data Port channel
714 * @ch_mask: Active channel mask
715 * @enable: Enable (true) /disable (false) channel
717 struct sdw_enable_ch {
718 unsigned int port_num;
719 unsigned int ch_mask;
724 * struct sdw_master_port_ops: Callback functions from bus to Master
725 * driver to set Master Data ports.
727 * @dpn_set_port_params: Set the Port parameters for the Master Port.
729 * @dpn_set_port_transport_params: Set transport parameters for the Master
730 * Port. Mandatory callback
731 * @dpn_port_prep: Port prepare operations for the Master Data Port.
732 * @dpn_port_enable_ch: Enable the channels of Master Port.
734 struct sdw_master_port_ops {
735 int (*dpn_set_port_params)(struct sdw_bus *bus,
736 struct sdw_port_params *port_params,
738 int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
739 struct sdw_transport_params *transport_params,
740 enum sdw_reg_bank bank);
741 int (*dpn_port_prep)(struct sdw_bus *bus,
742 struct sdw_prepare_ch *prepare_ch);
743 int (*dpn_port_enable_ch)(struct sdw_bus *bus,
744 struct sdw_enable_ch *enable_ch, unsigned int bank);
750 * struct sdw_defer - SDW deffered message
751 * @length: message length
752 * @complete: message completion
757 struct completion complete;
762 * struct sdw_master_ops - Master driver ops
763 * @read_prop: Read Master properties
764 * @xfer_msg: Transfer message callback
765 * @xfer_msg_defer: Defer version of transfer message callback
766 * @reset_page_addr: Reset the SCP page address registers
767 * @set_bus_conf: Set the bus configuration
768 * @pre_bank_switch: Callback for pre bank switch
769 * @post_bank_switch: Callback for post bank switch
771 struct sdw_master_ops {
772 int (*read_prop)(struct sdw_bus *bus);
774 enum sdw_command_response (*xfer_msg)
775 (struct sdw_bus *bus, struct sdw_msg *msg);
776 enum sdw_command_response (*xfer_msg_defer)
777 (struct sdw_bus *bus, struct sdw_msg *msg,
778 struct sdw_defer *defer);
779 enum sdw_command_response (*reset_page_addr)
780 (struct sdw_bus *bus, unsigned int dev_num);
781 int (*set_bus_conf)(struct sdw_bus *bus,
782 struct sdw_bus_params *params);
783 int (*pre_bank_switch)(struct sdw_bus *bus);
784 int (*post_bank_switch)(struct sdw_bus *bus);
789 * struct sdw_bus - SoundWire bus
790 * @dev: Master linux device
791 * @link_id: Link id number, can be 0 to N, unique for each Master
792 * @slaves: list of Slaves on this bus
793 * @assigned: Bitmap for Slave device numbers.
794 * Bit set implies used number, bit clear implies unused number.
795 * @bus_lock: bus lock
796 * @msg_lock: message lock
797 * @compute_params: points to Bus resource management implementation
798 * @ops: Master callback ops
799 * @port_ops: Master port callback ops
800 * @params: Current bus parameters
801 * @prop: Master properties
802 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
803 * is used to compute and program bus bandwidth, clock, frame shape,
804 * transport and port parameters
805 * @debugfs: Bus debugfs
806 * @defer_msg: Defer message
807 * @clk_stop_timeout: Clock stop timeout computed
808 * @bank_switch_timeout: Bank switch timeout computed
809 * @multi_link: Store bus property that indicates if multi links
810 * are supported. This flag is populated by drivers after reading
811 * appropriate firmware (ACPI/DT).
815 unsigned int link_id;
816 struct list_head slaves;
817 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
818 struct mutex bus_lock;
819 struct mutex msg_lock;
820 int (*compute_params)(struct sdw_bus *bus);
821 const struct sdw_master_ops *ops;
822 const struct sdw_master_port_ops *port_ops;
823 struct sdw_bus_params params;
824 struct sdw_master_prop prop;
825 struct list_head m_rt_list;
826 #ifdef CONFIG_DEBUG_FS
827 struct dentry *debugfs;
829 struct sdw_defer defer_msg;
830 unsigned int clk_stop_timeout;
831 u32 bank_switch_timeout;
835 int sdw_add_bus_master(struct sdw_bus *bus);
836 void sdw_delete_bus_master(struct sdw_bus *bus);
839 * sdw_port_config: Master or Slave Port configuration
842 * @ch_mask: channels mask for port
844 struct sdw_port_config {
846 unsigned int ch_mask;
850 * sdw_stream_config: Master or Slave stream configuration
852 * @frame_rate: Audio frame rate of the stream, in Hz
853 * @ch_count: Channel count of the stream
854 * @bps: Number of bits per audio sample
855 * @direction: Data direction
856 * @type: Stream type PCM or PDM
858 struct sdw_stream_config {
859 unsigned int frame_rate;
860 unsigned int ch_count;
862 enum sdw_data_direction direction;
863 enum sdw_stream_type type;
867 * sdw_stream_state: Stream states
869 * @SDW_STREAM_ALLOCATED: New stream allocated.
870 * @SDW_STREAM_CONFIGURED: Stream configured
871 * @SDW_STREAM_PREPARED: Stream prepared
872 * @SDW_STREAM_ENABLED: Stream enabled
873 * @SDW_STREAM_DISABLED: Stream disabled
874 * @SDW_STREAM_DEPREPARED: Stream de-prepared
875 * @SDW_STREAM_RELEASED: Stream released
877 enum sdw_stream_state {
878 SDW_STREAM_ALLOCATED = 0,
879 SDW_STREAM_CONFIGURED = 1,
880 SDW_STREAM_PREPARED = 2,
881 SDW_STREAM_ENABLED = 3,
882 SDW_STREAM_DISABLED = 4,
883 SDW_STREAM_DEPREPARED = 5,
884 SDW_STREAM_RELEASED = 6,
888 * sdw_stream_params: Stream parameters
890 * @rate: Sampling frequency, in Hz
891 * @ch_count: Number of channels
892 * @bps: bits per channel sample
894 struct sdw_stream_params {
896 unsigned int ch_count;
901 * sdw_stream_runtime: Runtime stream parameters
903 * @name: SoundWire stream name
904 * @params: Stream parameters
905 * @state: Current state of the stream
906 * @type: Stream type PCM or PDM
907 * @master_list: List of Master runtime(s) in this stream.
908 * master_list can contain only one m_rt per Master instance
910 * @m_rt_count: Count of Master runtime(s) in this stream
912 struct sdw_stream_runtime {
914 struct sdw_stream_params params;
915 enum sdw_stream_state state;
916 enum sdw_stream_type type;
917 struct list_head master_list;
921 struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name);
922 void sdw_release_stream(struct sdw_stream_runtime *stream);
923 int sdw_stream_add_master(struct sdw_bus *bus,
924 struct sdw_stream_config *stream_config,
925 struct sdw_port_config *port_config,
926 unsigned int num_ports,
927 struct sdw_stream_runtime *stream);
928 int sdw_stream_add_slave(struct sdw_slave *slave,
929 struct sdw_stream_config *stream_config,
930 struct sdw_port_config *port_config,
931 unsigned int num_ports,
932 struct sdw_stream_runtime *stream);
933 int sdw_stream_remove_master(struct sdw_bus *bus,
934 struct sdw_stream_runtime *stream);
935 int sdw_stream_remove_slave(struct sdw_slave *slave,
936 struct sdw_stream_runtime *stream);
937 int sdw_prepare_stream(struct sdw_stream_runtime *stream);
938 int sdw_enable_stream(struct sdw_stream_runtime *stream);
939 int sdw_disable_stream(struct sdw_stream_runtime *stream);
940 int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
941 int sdw_bus_prep_clk_stop(struct sdw_bus *bus);
942 int sdw_bus_clk_stop(struct sdw_bus *bus);
943 int sdw_bus_exit_clk_stop(struct sdw_bus *bus);
945 /* messaging and data APIs */
947 int sdw_read(struct sdw_slave *slave, u32 addr);
948 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
949 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
950 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
952 #endif /* __SOUNDWIRE_H */