include/linux/regulator/pca9450.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /* Copyright 2020 NXP. */
   3
   4 #ifndef __LINUX_REG_PCA9450_H__
   5 #define __LINUX_REG_PCA9450_H__
   6
   7 #include <linux/regmap.h>
   8
   9 enum pca9450_chip_type {
  10         PCA9450_TYPE_PCA9450A = 0,
  11         PCA9450_TYPE_PCA9450BC,
  12         PCA9450_TYPE_AMOUNT,
  13 };
  14
  15 enum {
  16         PCA9450_BUCK1 = 0,
  17         PCA9450_BUCK2,
  18         PCA9450_BUCK3,
  19         PCA9450_BUCK4,
  20         PCA9450_BUCK5,
  21         PCA9450_BUCK6,
  22         PCA9450_LDO1,
  23         PCA9450_LDO2,
  24         PCA9450_LDO3,
  25         PCA9450_LDO4,
  26         PCA9450_LDO5,
  27         PCA9450_REGULATOR_CNT,
  28 };
  29
  30 enum {
  31         PCA9450_DVS_LEVEL_RUN = 0,
  32         PCA9450_DVS_LEVEL_STANDBY,
  33         PCA9450_DVS_LEVEL_MAX,
  34 };
  35
  36 #define PCA9450_BUCK1_VOLTAGE_NUM       0x80
  37 #define PCA9450_BUCK2_VOLTAGE_NUM       0x80
  38 #define PCA9450_BUCK3_VOLTAGE_NUM       0x80
  39 #define PCA9450_BUCK4_VOLTAGE_NUM       0x80
  40
  41 #define PCA9450_BUCK5_VOLTAGE_NUM       0x80
  42 #define PCA9450_BUCK6_VOLTAGE_NUM       0x80
  43
  44 #define PCA9450_LDO1_VOLTAGE_NUM        0x08
  45 #define PCA9450_LDO2_VOLTAGE_NUM        0x08
  46 #define PCA9450_LDO3_VOLTAGE_NUM        0x20
  47 #define PCA9450_LDO4_VOLTAGE_NUM        0x20
  48 #define PCA9450_LDO5_VOLTAGE_NUM        0x10
  49
  50 enum {
  51         PCA9450_REG_DEV_ID          = 0x00,
  52         PCA9450_REG_INT1            = 0x01,
  53         PCA9450_REG_INT1_MSK        = 0x02,
  54         PCA9450_REG_STATUS1         = 0x03,
  55         PCA9450_REG_STATUS2         = 0x04,
  56         PCA9450_REG_PWRON_STAT      = 0x05,
  57         PCA9450_REG_SWRST           = 0x06,
  58         PCA9450_REG_PWRCTRL         = 0x07,
  59         PCA9450_REG_RESET_CTRL      = 0x08,
  60         PCA9450_REG_CONFIG1         = 0x09,
  61         PCA9450_REG_CONFIG2         = 0x0A,
  62         PCA9450_REG_BUCK123_DVS     = 0x0C,
  63         PCA9450_REG_BUCK1OUT_LIMIT  = 0x0D,
  64         PCA9450_REG_BUCK2OUT_LIMIT  = 0x0E,
  65         PCA9450_REG_BUCK3OUT_LIMIT  = 0x0F,
  66         PCA9450_REG_BUCK1CTRL       = 0x10,
  67         PCA9450_REG_BUCK1OUT_DVS0   = 0x11,
  68         PCA9450_REG_BUCK1OUT_DVS1   = 0x12,
  69         PCA9450_REG_BUCK2CTRL       = 0x13,
  70         PCA9450_REG_BUCK2OUT_DVS0   = 0x14,
  71         PCA9450_REG_BUCK2OUT_DVS1   = 0x15,
  72         PCA9450_REG_BUCK3CTRL       = 0x16,
  73         PCA9450_REG_BUCK3OUT_DVS0   = 0x17,
  74         PCA9450_REG_BUCK3OUT_DVS1   = 0x18,
  75         PCA9450_REG_BUCK4CTRL       = 0x19,
  76         PCA9450_REG_BUCK4OUT        = 0x1A,
  77         PCA9450_REG_BUCK5CTRL       = 0x1B,
  78         PCA9450_REG_BUCK5OUT        = 0x1C,
  79         PCA9450_REG_BUCK6CTRL       = 0x1D,
  80         PCA9450_REG_BUCK6OUT        = 0x1E,
  81         PCA9450_REG_LDO_AD_CTRL     = 0x20,
  82         PCA9450_REG_LDO1CTRL        = 0x21,
  83         PCA9450_REG_LDO2CTRL        = 0x22,
  84         PCA9450_REG_LDO3CTRL        = 0x23,
  85         PCA9450_REG_LDO4CTRL        = 0x24,
  86         PCA9450_REG_LDO5CTRL_L      = 0x25,
  87         PCA9450_REG_LDO5CTRL_H      = 0x26,
  88         PCA9450_REG_LOADSW_CTRL     = 0x2A,
  89         PCA9450_REG_VRFLT1_STS      = 0x2B,
  90         PCA9450_REG_VRFLT2_STS      = 0x2C,
  91         PCA9450_REG_VRFLT1_MASK     = 0x2D,
  92         PCA9450_REG_VRFLT2_MASK     = 0x2E,
  93         PCA9450_MAX_REGISTER        = 0x2F,
  94 };
  95
  96 /* PCA9450 BUCK ENMODE bits */
  97 #define BUCK_ENMODE_OFF                 0x00
  98 #define BUCK_ENMODE_ONREQ               0x01
  99 #define BUCK_ENMODE_ONREQ_STBYREQ       0x02
 100 #define BUCK_ENMODE_ON                  0x03
 101
 102 /* PCA9450_REG_BUCK1_CTRL bits */
 103 #define BUCK1_RAMP_MASK                 0xC0
 104 #define BUCK1_RAMP_25MV                 0x0
 105 #define BUCK1_RAMP_12P5MV               0x1
 106 #define BUCK1_RAMP_6P25MV               0x2
 107 #define BUCK1_RAMP_3P125MV              0x3
 108 #define BUCK1_DVS_CTRL                  0x10
 109 #define BUCK1_AD                        0x08
 110 #define BUCK1_FPWM                      0x04
 111 #define BUCK1_ENMODE_MASK               0x03
 112
 113 /* PCA9450_REG_BUCK2_CTRL bits */
 114 #define BUCK2_RAMP_MASK                 0xC0
 115 #define BUCK2_RAMP_25MV                 0x0
 116 #define BUCK2_RAMP_12P5MV               0x1
 117 #define BUCK2_RAMP_6P25MV               0x2
 118 #define BUCK2_RAMP_3P125MV              0x3
 119 #define BUCK2_DVS_CTRL                  0x10
 120 #define BUCK2_AD                        0x08
 121 #define BUCK2_FPWM                      0x04
 122 #define BUCK2_ENMODE_MASK               0x03
 123
 124 /* PCA9450_REG_BUCK3_CTRL bits */
 125 #define BUCK3_RAMP_MASK                 0xC0
 126 #define BUCK3_RAMP_25MV                 0x0
 127 #define BUCK3_RAMP_12P5MV               0x1
 128 #define BUCK3_RAMP_6P25MV               0x2
 129 #define BUCK3_RAMP_3P125MV              0x3
 130 #define BUCK3_DVS_CTRL                  0x10
 131 #define BUCK3_AD                        0x08
 132 #define BUCK3_FPWM                      0x04
 133 #define BUCK3_ENMODE_MASK               0x03
 134
 135 /* PCA9450_REG_BUCK4_CTRL bits */
 136 #define BUCK4_AD                        0x08
 137 #define BUCK4_FPWM                      0x04
 138 #define BUCK4_ENMODE_MASK               0x03
 139
 140 /* PCA9450_REG_BUCK5_CTRL bits */
 141 #define BUCK5_AD                        0x08
 142 #define BUCK5_FPWM                      0x04
 143 #define BUCK5_ENMODE_MASK               0x03
 144
 145 /* PCA9450_REG_BUCK6_CTRL bits */
 146 #define BUCK6_AD                        0x08
 147 #define BUCK6_FPWM                      0x04
 148 #define BUCK6_ENMODE_MASK               0x03
 149
 150 /* PCA9450_BUCK1OUT_DVS0 bits */
 151 #define BUCK1OUT_DVS0_MASK              0x7F
 152 #define BUCK1OUT_DVS0_DEFAULT           0x14
 153
 154 /* PCA9450_BUCK1OUT_DVS1 bits */
 155 #define BUCK1OUT_DVS1_MASK              0x7F
 156 #define BUCK1OUT_DVS1_DEFAULT           0x14
 157
 158 /* PCA9450_BUCK2OUT_DVS0 bits */
 159 #define BUCK2OUT_DVS0_MASK              0x7F
 160 #define BUCK2OUT_DVS0_DEFAULT           0x14
 161
 162 /* PCA9450_BUCK2OUT_DVS1 bits */
 163 #define BUCK2OUT_DVS1_MASK              0x7F
 164 #define BUCK2OUT_DVS1_DEFAULT           0x14
 165
 166 /* PCA9450_BUCK3OUT_DVS0 bits */
 167 #define BUCK3OUT_DVS0_MASK              0x7F
 168 #define BUCK3OUT_DVS0_DEFAULT           0x14
 169
 170 /* PCA9450_BUCK3OUT_DVS1 bits */
 171 #define BUCK3OUT_DVS1_MASK              0x7F
 172 #define BUCK3OUT_DVS1_DEFAULT           0x14
 173
 174 /* PCA9450_REG_BUCK4OUT bits */
 175 #define BUCK4OUT_MASK                   0x7F
 176 #define BUCK4OUT_DEFAULT                0x6C
 177
 178 /* PCA9450_REG_BUCK5OUT bits */
 179 #define BUCK5OUT_MASK                   0x7F
 180 #define BUCK5OUT_DEFAULT                0x30
 181
 182 /* PCA9450_REG_BUCK6OUT bits */
 183 #define BUCK6OUT_MASK                   0x7F
 184 #define BUCK6OUT_DEFAULT                0x14
 185
 186 /* PCA9450_REG_LDO1_VOLT bits */
 187 #define LDO1_EN_MASK                    0xC0
 188 #define LDO1OUT_MASK                    0x07
 189
 190 /* PCA9450_REG_LDO2_VOLT bits */
 191 #define LDO2_EN_MASK                    0xC0
 192 #define LDO2OUT_MASK                    0x07
 193
 194 /* PCA9450_REG_LDO3_VOLT bits */
 195 #define LDO3_EN_MASK                    0xC0
 196 #define LDO3OUT_MASK                    0x0F
 197
 198 /* PCA9450_REG_LDO4_VOLT bits */
 199 #define LDO4_EN_MASK                    0xC0
 200 #define LDO4OUT_MASK                    0x0F
 201
 202 /* PCA9450_REG_LDO5_VOLT bits */
 203 #define LDO5L_EN_MASK                   0xC0
 204 #define LDO5LOUT_MASK                   0x0F
 205
 206 #define LDO5H_EN_MASK                   0xC0
 207 #define LDO5HOUT_MASK                   0x0F
 208
 209 /* PCA9450_REG_IRQ bits */
 210 #define IRQ_PWRON                       0x80
 211 #define IRQ_WDOGB                       0x40
 212 #define IRQ_RSVD                        0x20
 213 #define IRQ_VR_FLT1                     0x10
 214 #define IRQ_VR_FLT2                     0x08
 215 #define IRQ_LOWVSYS                     0x04
 216 #define IRQ_THERM_105                   0x02
 217 #define IRQ_THERM_125                   0x01
 218
 219 /* PCA9450_REG_RESET_CTRL bits */
 220 #define WDOG_B_CFG_MASK                 0xC0
 221 #define WDOG_B_CFG_NONE                 0x00
 222 #define WDOG_B_CFG_WARM                 0x40
 223 #define WDOG_B_CFG_COLD_LDO12           0x80
 224 #define WDOG_B_CFG_COLD                 0xC0
 225
 226 #endif /* __LINUX_REG_PCA9450_H__ */