1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <linux/interrupt.h>
38 #include <linux/netdevice.h>
39 #include <linux/pci.h>
40 #include <linux/skbuff.h>
41 #include <asm/byteorder.h>
43 #include <linux/compiler.h>
44 #include <linux/kernel.h>
45 #include <linux/list.h>
46 #include <linux/slab.h>
47 #include <linux/qed/common_hsi.h>
48 #include <linux/qed/qed_chain.h>
49 #include <linux/io-64-nonatomic-lo-hi.h>
51 enum dcbx_protocol_type {
55 DCBX_PROTOCOL_ROCE_V2,
57 DCBX_MAX_PROTOCOL_TYPE
60 #define QED_ROCE_PROTOCOL_INDEX (3)
62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
63 #define QED_LLDP_PORT_ID_STAT_LEN 4
64 #define QED_DCBX_MAX_APP_PROTOCOL 32
65 #define QED_MAX_PFC_PRIORITIES 8
66 #define QED_DCBX_DSCP_SIZE 64
68 struct qed_dcbx_lldp_remote {
69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
77 struct qed_dcbx_lldp_local {
78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
82 struct qed_dcbx_app_prio {
90 struct qed_dbcx_pfc_params {
93 u8 prio[QED_MAX_PFC_PRIORITIES];
97 enum qed_dcbx_sf_ieee_type {
98 QED_DCBX_SF_IEEE_ETHTYPE,
99 QED_DCBX_SF_IEEE_TCP_PORT,
100 QED_DCBX_SF_IEEE_UDP_PORT,
101 QED_DCBX_SF_IEEE_TCP_UDP_PORT
104 struct qed_app_entry {
106 enum qed_dcbx_sf_ieee_type sf_ieee;
110 enum dcbx_protocol_type proto_type;
113 struct qed_dcbx_params {
114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
126 struct qed_dbcx_pfc_params pfc;
130 struct qed_dcbx_admin_params {
131 struct qed_dcbx_params params;
135 struct qed_dcbx_remote_params {
136 struct qed_dcbx_params params;
140 struct qed_dcbx_operational_params {
141 struct qed_dcbx_app_prio app_prio;
142 struct qed_dcbx_params params;
151 struct qed_dcbx_get {
152 struct qed_dcbx_operational_params operational;
153 struct qed_dcbx_lldp_remote lldp_remote;
154 struct qed_dcbx_lldp_local lldp_local;
155 struct qed_dcbx_remote_params remote;
156 struct qed_dcbx_admin_params local;
159 enum qed_nvm_images {
160 QED_NVM_IMAGE_ISCSI_CFG,
161 QED_NVM_IMAGE_FCOE_CFG,
162 QED_NVM_IMAGE_NVM_CFG1,
163 QED_NVM_IMAGE_DEFAULT_CFG,
164 QED_NVM_IMAGE_NVM_META,
167 struct qed_link_eee_params {
169 #define QED_EEE_1G_ADV BIT(0)
170 #define QED_EEE_10G_ADV BIT(1)
172 /* Capabilities are represented using QED_EEE_*_ADV values */
185 struct qed_mfw_tlv_eth {
187 bool lso_maxoff_size_set;
189 bool lso_minseg_size_set;
193 bool tx_descr_size_set;
195 bool rx_descr_size_set;
199 bool tcp4_offloads_set;
201 bool tcp6_offloads_set;
203 bool tx_descr_qdepth_set;
205 bool rx_descr_qdepth_set;
207 #define QED_MFW_TLV_IOV_OFFLOAD_NONE (0)
208 #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1)
209 #define QED_MFW_TLV_IOV_OFFLOAD_VEB (2)
210 #define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3)
211 bool iov_offload_set;
217 bool num_txqs_full_set;
219 bool num_rxqs_full_set;
222 #define QED_MFW_TLV_TIME_SIZE 14
223 struct qed_mfw_tlv_time {
233 struct qed_mfw_tlv_fcoe {
235 bool scsi_timeout_set;
249 bool num_npiv_ids_set;
251 bool switch_name_set;
253 bool switch_portnum_set;
255 bool switch_portid_set;
257 bool vendor_name_set;
259 bool switch_model_set;
260 u8 switch_fw_version[8];
261 bool switch_fw_version_set;
267 #define QED_MFW_TLV_PORT_STATE_OFFLINE (0)
268 #define QED_MFW_TLV_PORT_STATE_LOOP (1)
269 #define QED_MFW_TLV_PORT_STATE_P2P (2)
270 #define QED_MFW_TLV_PORT_STATE_FABRIC (3)
272 u16 fip_tx_descr_size;
273 bool fip_tx_descr_size_set;
274 u16 fip_rx_descr_size;
275 bool fip_rx_descr_size_set;
277 bool link_failures_set;
278 u8 fcoe_boot_progress;
279 bool fcoe_boot_progress_set;
285 bool fcoe_txq_depth_set;
287 bool fcoe_rxq_depth_set;
289 bool fcoe_rx_frames_set;
291 bool fcoe_rx_bytes_set;
293 bool fcoe_tx_frames_set;
295 bool fcoe_tx_bytes_set;
298 u32 crc_err_src_fcid[5];
299 bool crc_err_src_fcid_set[5];
300 struct qed_mfw_tlv_time crc_err[5];
306 bool primtive_err_set;
308 bool disparity_err_set;
309 u16 code_violation_err;
310 bool code_violation_err_set;
312 bool flogi_param_set[4];
313 struct qed_mfw_tlv_time flogi_tstamp;
314 u32 flogi_acc_param[4];
315 bool flogi_acc_param_set[4];
316 struct qed_mfw_tlv_time flogi_acc_tstamp;
319 struct qed_mfw_tlv_time flogi_rjt_tstamp;
332 u32 plogi_dst_fcid[5];
333 bool plogi_dst_fcid_set[5];
334 struct qed_mfw_tlv_time plogi_tstamp[5];
335 u32 plogi_acc_src_fcid[5];
336 bool plogi_acc_src_fcid_set[5];
337 struct qed_mfw_tlv_time plogi_acc_tstamp[5];
344 u32 plogo_src_fcid[5];
345 bool plogo_src_fcid_set[5];
346 struct qed_mfw_tlv_time plogo_tstamp[5];
358 bool rx_abts_acc_set;
360 bool rx_abts_rjt_set;
361 u32 abts_dst_fcid[5];
362 bool abts_dst_fcid_set[5];
363 struct qed_mfw_tlv_time abts_tstamp[5];
366 u32 rx_rscn_nport[4];
367 bool rx_rscn_nport_set[4];
371 bool abort_task_sets_set;
395 bool scsi_cond_met_set;
400 u8 scsi_inter_cond_met;
401 bool scsi_inter_cond_met_set;
402 u8 scsi_rsv_conflicts;
403 bool scsi_rsv_conflicts_set;
405 bool scsi_tsk_full_set;
407 bool scsi_aca_active_set;
409 bool scsi_tsk_abort_set;
411 bool scsi_rx_chk_set[5];
412 struct qed_mfw_tlv_time scsi_chk_tstamp[5];
415 struct qed_mfw_tlv_iscsi {
417 bool target_llmnr_set;
419 bool header_digest_set;
421 bool data_digest_set;
423 #define QED_MFW_TLV_AUTH_METHOD_NONE (1)
424 #define QED_MFW_TLV_AUTH_METHOD_CHAP (2)
425 #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3)
426 bool auth_method_set;
427 u16 boot_taget_portal;
428 bool boot_taget_portal_set;
432 bool tx_desc_size_set;
434 bool rx_desc_size_set;
436 bool boot_progress_set;
438 bool tx_desc_qdepth_set;
440 bool rx_desc_qdepth_set;
451 enum qed_db_rec_width {
456 enum qed_db_rec_space {
461 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
462 (void __iomem *)(reg_addr))
464 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
466 #define DIRECT_REG_WR64(reg_addr, val) writeq((u32)val, \
467 (void __iomem *)(reg_addr))
469 #define QED_COALESCE_MAX 0x1FF
470 #define QED_DEFAULT_RX_USECS 12
471 #define QED_DEFAULT_TX_USECS 48
476 struct qed_eth_pf_params {
477 /* The following parameters are used during HW-init
478 * and these parameters need to be passed as arguments
479 * to update_pf_params routine invoked before slowpath start
483 /* per-VF number of CIDs */
485 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32)
487 /* To enable arfs, previous to HW-init a positive number needs to be
488 * set [as filters require allocated searcher ILT memory].
489 * This will set the maximal number of configured steering-filters.
491 u32 num_arfs_filters;
494 struct qed_fcoe_pf_params {
495 /* The following parameters are used during protocol-init */
496 u64 glbl_q_params_addr;
497 u64 bdq_pbl_base_addr[2];
499 /* The following parameters are used during HW-init
500 * and these parameters need to be passed as arguments
501 * to update_pf_params routine invoked before slowpath start
506 /* The following parameters are used during protocol-init */
507 u16 sq_num_pbl_pages;
510 u16 cmdq_num_entries;
511 u16 rq_buffer_log_size;
514 u16 bdq_xoff_threshold[2];
515 u16 bdq_xon_threshold[2];
517 u8 num_cqs; /* num of global CQs */
523 u8 bdq_pbl_num_entries[2];
526 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
527 struct qed_iscsi_pf_params {
528 u64 glbl_q_params_addr;
529 u64 bdq_pbl_base_addr[3];
531 u16 cmdq_num_entries;
535 /* The following parameters are used during HW-init
536 * and these parameters need to be passed as arguments
537 * to update_pf_params routine invoked before slowpath start
542 /* The following parameters are used during protocol-init */
543 u16 half_way_close_timeout;
544 u16 bdq_xoff_threshold[3];
545 u16 bdq_xon_threshold[3];
546 u16 cmdq_xoff_threshold;
547 u16 cmdq_xon_threshold;
550 u8 num_sq_pages_in_ring;
551 u8 num_r2tq_pages_in_ring;
552 u8 num_uhq_pages_in_ring;
564 u8 soc_num_of_blocks_log;
565 u8 bdq_pbl_num_entries[3];
568 struct qed_rdma_pf_params {
569 /* Supplied to QED during resource allocation (may affect the ILT and
572 u32 min_dpis; /* number of requested DPIs */
573 u32 num_qps; /* number of requested Queue Pairs */
574 u32 num_srqs; /* number of requested SRQ */
575 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
576 u8 gl_pi; /* protocol index */
578 /* Will allocate rate limiters to be used with QPs */
582 struct qed_pf_params {
583 struct qed_eth_pf_params eth_pf_params;
584 struct qed_fcoe_pf_params fcoe_pf_params;
585 struct qed_iscsi_pf_params iscsi_pf_params;
586 struct qed_rdma_pf_params rdma_pf_params;
597 struct status_block_e4 *sb_virt;
599 u32 sb_ack; /* Last given ack */
601 void __iomem *igu_addr;
603 #define QED_SB_INFO_INIT 0x1
604 #define QED_SB_INFO_SETUP 0x2
606 struct qed_dev *cdev;
614 struct qed_dev_info {
615 unsigned long pci_mem_start;
616 unsigned long pci_mem_end;
617 unsigned int pci_irq;
630 #define QED_MFW_VERSION_0_MASK 0x000000FF
631 #define QED_MFW_VERSION_0_OFFSET 0
632 #define QED_MFW_VERSION_1_MASK 0x0000FF00
633 #define QED_MFW_VERSION_1_OFFSET 8
634 #define QED_MFW_VERSION_2_MASK 0x00FF0000
635 #define QED_MFW_VERSION_2_OFFSET 16
636 #define QED_MFW_VERSION_3_MASK 0xFF000000
637 #define QED_MFW_VERSION_3_OFFSET 24
640 bool b_inter_pf_switch;
650 #define QED_MBI_VERSION_0_MASK 0x000000FF
651 #define QED_MBI_VERSION_0_OFFSET 0
652 #define QED_MBI_VERSION_1_MASK 0x0000FF00
653 #define QED_MBI_VERSION_1_OFFSET 8
654 #define QED_MBI_VERSION_2_MASK 0x00FF0000
655 #define QED_MBI_VERSION_2_OFFSET 16
657 enum qed_dev_type dev_type;
659 /* Output parameters for qede */
668 QED_SB_TYPE_L2_QUEUE,
679 enum qed_link_mode_bits {
680 QED_LM_FIBRE_BIT = BIT(0),
681 QED_LM_Autoneg_BIT = BIT(1),
682 QED_LM_Asym_Pause_BIT = BIT(2),
683 QED_LM_Pause_BIT = BIT(3),
684 QED_LM_1000baseT_Full_BIT = BIT(4),
685 QED_LM_10000baseT_Full_BIT = BIT(5),
686 QED_LM_10000baseKR_Full_BIT = BIT(6),
687 QED_LM_20000baseKR2_Full_BIT = BIT(7),
688 QED_LM_25000baseKR_Full_BIT = BIT(8),
689 QED_LM_40000baseLR4_Full_BIT = BIT(9),
690 QED_LM_50000baseKR2_Full_BIT = BIT(10),
691 QED_LM_100000baseKR4_Full_BIT = BIT(11),
692 QED_LM_2500baseX_Full_BIT = BIT(12),
693 QED_LM_Backplane_BIT = BIT(13),
694 QED_LM_1000baseKX_Full_BIT = BIT(14),
695 QED_LM_10000baseKX4_Full_BIT = BIT(15),
696 QED_LM_10000baseR_FEC_BIT = BIT(16),
697 QED_LM_40000baseKR4_Full_BIT = BIT(17),
698 QED_LM_40000baseCR4_Full_BIT = BIT(18),
699 QED_LM_40000baseSR4_Full_BIT = BIT(19),
700 QED_LM_25000baseCR_Full_BIT = BIT(20),
701 QED_LM_25000baseSR_Full_BIT = BIT(21),
702 QED_LM_50000baseCR2_Full_BIT = BIT(22),
703 QED_LM_100000baseSR4_Full_BIT = BIT(23),
704 QED_LM_100000baseCR4_Full_BIT = BIT(24),
705 QED_LM_100000baseLR4_ER4_Full_BIT = BIT(25),
706 QED_LM_50000baseSR2_Full_BIT = BIT(26),
707 QED_LM_1000baseX_Full_BIT = BIT(27),
708 QED_LM_10000baseCR_Full_BIT = BIT(28),
709 QED_LM_10000baseSR_Full_BIT = BIT(29),
710 QED_LM_10000baseLR_Full_BIT = BIT(30),
711 QED_LM_10000baseLRM_Full_BIT = BIT(31),
715 struct qed_link_params {
718 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
719 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
720 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
721 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
722 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
723 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
728 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
729 #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
730 #define QED_LINK_PAUSE_TX_ENABLE BIT(2)
732 #define QED_LINK_LOOPBACK_NONE BIT(0)
733 #define QED_LINK_LOOPBACK_INT_PHY BIT(1)
734 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
735 #define QED_LINK_LOOPBACK_EXT BIT(3)
736 #define QED_LINK_LOOPBACK_MAC BIT(4)
738 struct qed_link_eee_params eee;
741 struct qed_link_output {
744 /* In QED_LM_* defs */
749 u32 speed; /* In Mb/s */
750 u8 duplex; /* In DUPLEX defs */
751 u8 port; /* In PORT defs */
755 /* EEE - capability & param */
759 struct qed_link_eee_params eee;
762 struct qed_probe_params {
763 enum qed_protocol protocol;
770 #define QED_DRV_VER_STR_SIZE 12
771 struct qed_slowpath_params {
777 u8 name[QED_DRV_VER_STR_SIZE];
780 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
782 struct qed_int_info {
783 struct msix_entry *msix;
786 /* This should be updated by the protocol driver */
790 struct qed_generic_tlvs {
791 #define QED_TLV_IP_CSUM BIT(0)
792 #define QED_TLV_LSO BIT(1)
794 #define QED_TLV_MAC_COUNT 3
795 u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
798 #define QED_I2C_DEV_ADDR_A0 0xA0
799 #define QED_I2C_DEV_ADDR_A2 0xA2
801 #define QED_NVM_SIGNATURE 0x12435687
803 enum qed_nvm_flash_cmd {
804 QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
805 QED_NVM_FLASH_CMD_FILE_START = 0x3,
806 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
807 QED_NVM_FLASH_CMD_NVM_MAX,
810 struct qed_common_cb_ops {
811 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
812 void (*link_update)(void *dev,
813 struct qed_link_output *link);
814 void (*schedule_recovery_handler)(void *dev);
815 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
816 void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
817 void (*get_protocol_tlv_data)(void *dev, void *data);
820 struct qed_selftest_ops {
822 * @brief selftest_interrupt - Perform interrupt test
826 * @return 0 on success, error otherwise.
828 int (*selftest_interrupt)(struct qed_dev *cdev);
831 * @brief selftest_memory - Perform memory test
835 * @return 0 on success, error otherwise.
837 int (*selftest_memory)(struct qed_dev *cdev);
840 * @brief selftest_register - Perform register test
844 * @return 0 on success, error otherwise.
846 int (*selftest_register)(struct qed_dev *cdev);
849 * @brief selftest_clock - Perform clock test
853 * @return 0 on success, error otherwise.
855 int (*selftest_clock)(struct qed_dev *cdev);
858 * @brief selftest_nvram - Perform nvram test
862 * @return 0 on success, error otherwise.
864 int (*selftest_nvram) (struct qed_dev *cdev);
867 struct qed_common_ops {
868 struct qed_selftest_ops *selftest;
870 struct qed_dev* (*probe)(struct pci_dev *dev,
871 struct qed_probe_params *params);
873 void (*remove)(struct qed_dev *cdev);
875 int (*set_power_state)(struct qed_dev *cdev,
878 void (*set_name) (struct qed_dev *cdev, char name[]);
880 /* Client drivers need to make this call before slowpath_start.
881 * PF params required for the call before slowpath_start is
882 * documented within the qed_pf_params structure definition.
884 void (*update_pf_params)(struct qed_dev *cdev,
885 struct qed_pf_params *params);
886 int (*slowpath_start)(struct qed_dev *cdev,
887 struct qed_slowpath_params *params);
889 int (*slowpath_stop)(struct qed_dev *cdev);
891 /* Requests to use `cnt' interrupts for fastpath.
892 * upon success, returns number of interrupts allocated for fastpath.
894 int (*set_fp_int)(struct qed_dev *cdev,
897 /* Fills `info' with pointers required for utilizing interrupts */
898 int (*get_fp_int)(struct qed_dev *cdev,
899 struct qed_int_info *info);
901 u32 (*sb_init)(struct qed_dev *cdev,
902 struct qed_sb_info *sb_info,
904 dma_addr_t sb_phy_addr,
906 enum qed_sb_type type);
908 u32 (*sb_release)(struct qed_dev *cdev,
909 struct qed_sb_info *sb_info,
911 enum qed_sb_type type);
913 void (*simd_handler_config)(struct qed_dev *cdev,
916 void (*handler)(void *));
918 void (*simd_handler_clean)(struct qed_dev *cdev,
920 int (*dbg_grc)(struct qed_dev *cdev,
921 void *buffer, u32 *num_dumped_bytes);
923 int (*dbg_grc_size)(struct qed_dev *cdev);
925 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
927 int (*dbg_all_data_size) (struct qed_dev *cdev);
930 * @brief can_link_change - can the instance change the link or not
934 * @return true if link-change is allowed, false otherwise.
936 bool (*can_link_change)(struct qed_dev *cdev);
939 * @brief set_link - set links according to params
942 * @param params - values used to override the default link configuration
944 * @return 0 on success, error otherwise.
946 int (*set_link)(struct qed_dev *cdev,
947 struct qed_link_params *params);
950 * @brief get_link - returns the current link state.
953 * @param if_link - structure to be filled with current link configuration.
955 void (*get_link)(struct qed_dev *cdev,
956 struct qed_link_output *if_link);
959 * @brief - drains chip in case Tx completions fail to arrive due to pause.
963 int (*drain)(struct qed_dev *cdev);
966 * @brief update_msglvl - update module debug level
972 void (*update_msglvl)(struct qed_dev *cdev,
976 int (*chain_alloc)(struct qed_dev *cdev,
977 enum qed_chain_use_mode intended_use,
978 enum qed_chain_mode mode,
979 enum qed_chain_cnt_type cnt_type,
982 struct qed_chain *p_chain,
983 struct qed_chain_ext_pbl *ext_pbl);
985 void (*chain_free)(struct qed_dev *cdev,
986 struct qed_chain *p_chain);
989 * @brief nvm_flash - Flash nvm data.
992 * @param name - file containing the data
994 * @return 0 on success, error otherwise.
996 int (*nvm_flash)(struct qed_dev *cdev, const char *name);
999 * @brief nvm_get_image - reads an entire image from nvram
1002 * @param type - type of the request nvram image
1003 * @param buf - preallocated buffer to fill with the image
1004 * @param len - length of the allocated buffer
1006 * @return 0 on success, error otherwise
1008 int (*nvm_get_image)(struct qed_dev *cdev,
1009 enum qed_nvm_images type, u8 *buf, u16 len);
1012 * @brief set_coalesce - Configure Rx coalesce value in usec
1015 * @param rx_coal - Rx coalesce value in usec
1016 * @param tx_coal - Tx coalesce value in usec
1017 * @param qid - Queue index
1018 * @param sb_id - Status Block Id
1020 * @return 0 on success, error otherwise.
1022 int (*set_coalesce)(struct qed_dev *cdev,
1023 u16 rx_coal, u16 tx_coal, void *handle);
1026 * @brief set_led - Configure LED mode
1029 * @param mode - LED mode
1031 * @return 0 on success, error otherwise.
1033 int (*set_led)(struct qed_dev *cdev,
1034 enum qed_led_mode mode);
1036 * @brief db_recovery_add - add doorbell information to the doorbell
1037 * recovery mechanism.
1040 * @param db_addr - doorbell address
1041 * @param db_data - address of where db_data is stored
1042 * @param db_is_32b - doorbell is 32b pr 64b
1043 * @param db_is_user - doorbell recovery addresses are user or kernel space
1045 int (*db_recovery_add)(struct qed_dev *cdev,
1046 void __iomem *db_addr,
1048 enum qed_db_rec_width db_width,
1049 enum qed_db_rec_space db_space);
1052 * @brief db_recovery_del - remove doorbell information from the doorbell
1053 * recovery mechanism. db_data serves as key (db_addr is not unique).
1056 * @param db_addr - doorbell address
1057 * @param db_data - address where db_data is stored. Serves as key for the
1060 int (*db_recovery_del)(struct qed_dev *cdev,
1061 void __iomem *db_addr, void *db_data);
1064 * @brief recovery_process - Trigger a recovery process
1068 * @return 0 on success, error otherwise.
1070 int (*recovery_process)(struct qed_dev *cdev);
1073 * @brief recovery_prolog - Execute the prolog operations of a recovery process
1077 * @return 0 on success, error otherwise.
1079 int (*recovery_prolog)(struct qed_dev *cdev);
1082 * @brief update_drv_state - API to inform the change in the driver state.
1088 int (*update_drv_state)(struct qed_dev *cdev, bool active);
1091 * @brief update_mac - API to inform the change in the mac address
1097 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
1100 * @brief update_mtu - API to inform the change in the mtu
1106 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
1109 * @brief update_wol - update of changes in the WoL configuration
1112 * @param enabled - true iff WoL should be enabled.
1114 int (*update_wol) (struct qed_dev *cdev, bool enabled);
1117 * @brief read_module_eeprom
1120 * @param buf - buffer
1121 * @param dev_addr - PHY device memory region
1122 * @param offset - offset into eeprom contents to be read
1123 * @param len - buffer length, i.e., max bytes to be read
1125 int (*read_module_eeprom)(struct qed_dev *cdev,
1126 char *buf, u8 dev_addr, u32 offset, u32 len);
1129 * @brief get_affin_hwfn_idx
1133 u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
1136 #define MASK_FIELD(_name, _value) \
1137 ((_value) &= (_name ## _MASK))
1139 #define FIELD_VALUE(_name, _value) \
1140 ((_value & _name ## _MASK) << _name ## _SHIFT)
1142 #define SET_FIELD(value, name, flag) \
1144 (value) &= ~(name ## _MASK << name ## _SHIFT); \
1145 (value) |= (((u64)flag) << (name ## _SHIFT)); \
1148 #define GET_FIELD(value, name) \
1149 (((value) >> (name ## _SHIFT)) & name ## _MASK)
1151 /* Debug print definitions */
1152 #define DP_ERR(cdev, fmt, ...) \
1154 pr_err("[%s:%d(%s)]" fmt, \
1155 __func__, __LINE__, \
1156 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1160 #define DP_NOTICE(cdev, fmt, ...) \
1162 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1163 pr_notice("[%s:%d(%s)]" fmt, \
1164 __func__, __LINE__, \
1165 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1171 #define DP_INFO(cdev, fmt, ...) \
1173 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
1174 pr_notice("[%s:%d(%s)]" fmt, \
1175 __func__, __LINE__, \
1176 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1181 #define DP_VERBOSE(cdev, module, fmt, ...) \
1183 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
1184 ((cdev)->dp_module & module))) { \
1185 pr_notice("[%s:%d(%s)]" fmt, \
1186 __func__, __LINE__, \
1187 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1193 QED_LEVEL_VERBOSE = 0x0,
1194 QED_LEVEL_INFO = 0x1,
1195 QED_LEVEL_NOTICE = 0x2,
1196 QED_LEVEL_ERR = 0x3,
1199 #define QED_LOG_LEVEL_SHIFT (30)
1200 #define QED_LOG_VERBOSE_MASK (0x3fffffff)
1201 #define QED_LOG_INFO_MASK (0x40000000)
1202 #define QED_LOG_NOTICE_MASK (0x80000000)
1205 QED_MSG_SPQ = 0x10000,
1206 QED_MSG_STATS = 0x20000,
1207 QED_MSG_DCB = 0x40000,
1208 QED_MSG_IOV = 0x80000,
1209 QED_MSG_SP = 0x100000,
1210 QED_MSG_STORAGE = 0x200000,
1211 QED_MSG_CXT = 0x800000,
1212 QED_MSG_LL2 = 0x1000000,
1213 QED_MSG_ILT = 0x2000000,
1214 QED_MSG_RDMA = 0x4000000,
1215 QED_MSG_DEBUG = 0x8000000,
1216 /* to be added...up to 0x8000000 */
1225 struct qed_eth_stats_common {
1226 u64 no_buff_discards;
1227 u64 packet_too_big_discard;
1235 u64 mftag_filter_discards;
1236 u64 mac_filter_discards;
1237 u64 gft_filter_drop;
1244 u64 tx_err_drop_pkts;
1245 u64 tpa_coalesced_pkts;
1246 u64 tpa_coalesced_events;
1248 u64 tpa_not_coalesced_pkts;
1249 u64 tpa_coalesced_bytes;
1252 u64 rx_64_byte_packets;
1253 u64 rx_65_to_127_byte_packets;
1254 u64 rx_128_to_255_byte_packets;
1255 u64 rx_256_to_511_byte_packets;
1256 u64 rx_512_to_1023_byte_packets;
1257 u64 rx_1024_to_1518_byte_packets;
1259 u64 rx_mac_crtl_frames;
1260 u64 rx_pause_frames;
1262 u64 rx_align_errors;
1263 u64 rx_carrier_errors;
1264 u64 rx_oversize_packets;
1266 u64 rx_undersize_packets;
1268 u64 tx_64_byte_packets;
1269 u64 tx_65_to_127_byte_packets;
1270 u64 tx_128_to_255_byte_packets;
1271 u64 tx_256_to_511_byte_packets;
1272 u64 tx_512_to_1023_byte_packets;
1273 u64 tx_1024_to_1518_byte_packets;
1274 u64 tx_pause_frames;
1279 u64 rx_mac_uc_packets;
1280 u64 rx_mac_mc_packets;
1281 u64 rx_mac_bc_packets;
1282 u64 rx_mac_frames_ok;
1284 u64 tx_mac_uc_packets;
1285 u64 tx_mac_mc_packets;
1286 u64 tx_mac_bc_packets;
1287 u64 tx_mac_ctrl_frames;
1288 u64 link_change_count;
1291 struct qed_eth_stats_bb {
1292 u64 rx_1519_to_1522_byte_packets;
1293 u64 rx_1519_to_2047_byte_packets;
1294 u64 rx_2048_to_4095_byte_packets;
1295 u64 rx_4096_to_9216_byte_packets;
1296 u64 rx_9217_to_16383_byte_packets;
1297 u64 tx_1519_to_2047_byte_packets;
1298 u64 tx_2048_to_4095_byte_packets;
1299 u64 tx_4096_to_9216_byte_packets;
1300 u64 tx_9217_to_16383_byte_packets;
1301 u64 tx_lpi_entry_count;
1302 u64 tx_total_collisions;
1305 struct qed_eth_stats_ah {
1306 u64 rx_1519_to_max_byte_packets;
1307 u64 tx_1519_to_max_byte_packets;
1310 struct qed_eth_stats {
1311 struct qed_eth_stats_common common;
1314 struct qed_eth_stats_bb bb;
1315 struct qed_eth_stats_ah ah;
1319 #define QED_SB_IDX 0x0002
1322 #define TX_PI(tc) (RX_PI + 1 + tc)
1324 struct qed_sb_cnt_info {
1325 /* Original, current, and free SBs for PF */
1330 /* Original, current and free SBS for child VFs */
1336 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1341 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
1342 STATUS_BLOCK_E4_PROD_INDEX_MASK;
1343 if (sb_info->sb_ack != prod) {
1344 sb_info->sb_ack = prod;
1354 * @brief This function creates an update command for interrupts that is
1355 * written to the IGU.
1357 * @param sb_info - This is the structure allocated and
1358 * initialized per status block. Assumption is
1359 * that it was initialized using qed_sb_init
1360 * @param int_cmd - Enable/Disable/Nop
1361 * @param upd_flg - whether igu consumer should be
1364 * @return inline void
1366 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1367 enum igu_int_cmd int_cmd,
1370 struct igu_prod_cons_update igu_ack = { 0 };
1372 igu_ack.sb_id_and_flags =
1373 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1374 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1375 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1376 (IGU_SEG_ACCESS_REG <<
1377 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1379 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
1381 /* Both segments (interrupts & acks) are written to same place address;
1382 * Need to guarantee all commands will be received (in-order) by HW.
1387 static inline void __internal_ram_wr(void *p_hwfn,
1395 for (i = 0; i < size / sizeof(*data); i++)
1396 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1399 static inline void internal_ram_wr(void __iomem *addr,
1403 __internal_ram_wr(NULL, addr, size, data);
1409 QED_RSS_IPV4_TCP = 0x4,
1410 QED_RSS_IPV6_TCP = 0x8,
1411 QED_RSS_IPV4_UDP = 0x10,
1412 QED_RSS_IPV6_UDP = 0x20,
1415 #define QED_RSS_IND_TABLE_SIZE 128
1416 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */