1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <linux/interrupt.h>
38 #include <linux/netdevice.h>
39 #include <linux/pci.h>
40 #include <linux/skbuff.h>
41 #include <asm/byteorder.h>
43 #include <linux/compiler.h>
44 #include <linux/kernel.h>
45 #include <linux/list.h>
46 #include <linux/slab.h>
47 #include <linux/qed/common_hsi.h>
48 #include <linux/qed/qed_chain.h>
49 #include <linux/io-64-nonatomic-lo-hi.h>
51 enum dcbx_protocol_type {
55 DCBX_PROTOCOL_ROCE_V2,
57 DCBX_MAX_PROTOCOL_TYPE
60 #define QED_ROCE_PROTOCOL_INDEX (3)
62 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
63 #define QED_LLDP_PORT_ID_STAT_LEN 4
64 #define QED_DCBX_MAX_APP_PROTOCOL 32
65 #define QED_MAX_PFC_PRIORITIES 8
66 #define QED_DCBX_DSCP_SIZE 64
68 struct qed_dcbx_lldp_remote {
69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
77 struct qed_dcbx_lldp_local {
78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
82 struct qed_dcbx_app_prio {
90 struct qed_dbcx_pfc_params {
93 u8 prio[QED_MAX_PFC_PRIORITIES];
97 enum qed_dcbx_sf_ieee_type {
98 QED_DCBX_SF_IEEE_ETHTYPE,
99 QED_DCBX_SF_IEEE_TCP_PORT,
100 QED_DCBX_SF_IEEE_UDP_PORT,
101 QED_DCBX_SF_IEEE_TCP_UDP_PORT
104 struct qed_app_entry {
106 enum qed_dcbx_sf_ieee_type sf_ieee;
110 enum dcbx_protocol_type proto_type;
113 struct qed_dcbx_params {
114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
126 struct qed_dbcx_pfc_params pfc;
130 struct qed_dcbx_admin_params {
131 struct qed_dcbx_params params;
135 struct qed_dcbx_remote_params {
136 struct qed_dcbx_params params;
140 struct qed_dcbx_operational_params {
141 struct qed_dcbx_app_prio app_prio;
142 struct qed_dcbx_params params;
151 struct qed_dcbx_get {
152 struct qed_dcbx_operational_params operational;
153 struct qed_dcbx_lldp_remote lldp_remote;
154 struct qed_dcbx_lldp_local lldp_local;
155 struct qed_dcbx_remote_params remote;
156 struct qed_dcbx_admin_params local;
159 enum qed_nvm_images {
160 QED_NVM_IMAGE_ISCSI_CFG,
161 QED_NVM_IMAGE_FCOE_CFG,
163 QED_NVM_IMAGE_NVM_CFG1,
164 QED_NVM_IMAGE_DEFAULT_CFG,
165 QED_NVM_IMAGE_NVM_META,
168 struct qed_link_eee_params {
170 #define QED_EEE_1G_ADV BIT(0)
171 #define QED_EEE_10G_ADV BIT(1)
173 /* Capabilities are represented using QED_EEE_*_ADV values */
186 struct qed_mfw_tlv_eth {
188 bool lso_maxoff_size_set;
190 bool lso_minseg_size_set;
194 bool tx_descr_size_set;
196 bool rx_descr_size_set;
200 bool tcp4_offloads_set;
202 bool tcp6_offloads_set;
204 bool tx_descr_qdepth_set;
206 bool rx_descr_qdepth_set;
208 #define QED_MFW_TLV_IOV_OFFLOAD_NONE (0)
209 #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1)
210 #define QED_MFW_TLV_IOV_OFFLOAD_VEB (2)
211 #define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3)
212 bool iov_offload_set;
218 bool num_txqs_full_set;
220 bool num_rxqs_full_set;
223 #define QED_MFW_TLV_TIME_SIZE 14
224 struct qed_mfw_tlv_time {
234 struct qed_mfw_tlv_fcoe {
236 bool scsi_timeout_set;
250 bool num_npiv_ids_set;
252 bool switch_name_set;
254 bool switch_portnum_set;
256 bool switch_portid_set;
258 bool vendor_name_set;
260 bool switch_model_set;
261 u8 switch_fw_version[8];
262 bool switch_fw_version_set;
268 #define QED_MFW_TLV_PORT_STATE_OFFLINE (0)
269 #define QED_MFW_TLV_PORT_STATE_LOOP (1)
270 #define QED_MFW_TLV_PORT_STATE_P2P (2)
271 #define QED_MFW_TLV_PORT_STATE_FABRIC (3)
273 u16 fip_tx_descr_size;
274 bool fip_tx_descr_size_set;
275 u16 fip_rx_descr_size;
276 bool fip_rx_descr_size_set;
278 bool link_failures_set;
279 u8 fcoe_boot_progress;
280 bool fcoe_boot_progress_set;
286 bool fcoe_txq_depth_set;
288 bool fcoe_rxq_depth_set;
290 bool fcoe_rx_frames_set;
292 bool fcoe_rx_bytes_set;
294 bool fcoe_tx_frames_set;
296 bool fcoe_tx_bytes_set;
299 u32 crc_err_src_fcid[5];
300 bool crc_err_src_fcid_set[5];
301 struct qed_mfw_tlv_time crc_err[5];
307 bool primtive_err_set;
309 bool disparity_err_set;
310 u16 code_violation_err;
311 bool code_violation_err_set;
313 bool flogi_param_set[4];
314 struct qed_mfw_tlv_time flogi_tstamp;
315 u32 flogi_acc_param[4];
316 bool flogi_acc_param_set[4];
317 struct qed_mfw_tlv_time flogi_acc_tstamp;
320 struct qed_mfw_tlv_time flogi_rjt_tstamp;
333 u32 plogi_dst_fcid[5];
334 bool plogi_dst_fcid_set[5];
335 struct qed_mfw_tlv_time plogi_tstamp[5];
336 u32 plogi_acc_src_fcid[5];
337 bool plogi_acc_src_fcid_set[5];
338 struct qed_mfw_tlv_time plogi_acc_tstamp[5];
345 u32 plogo_src_fcid[5];
346 bool plogo_src_fcid_set[5];
347 struct qed_mfw_tlv_time plogo_tstamp[5];
359 bool rx_abts_acc_set;
361 bool rx_abts_rjt_set;
362 u32 abts_dst_fcid[5];
363 bool abts_dst_fcid_set[5];
364 struct qed_mfw_tlv_time abts_tstamp[5];
367 u32 rx_rscn_nport[4];
368 bool rx_rscn_nport_set[4];
372 bool abort_task_sets_set;
396 bool scsi_cond_met_set;
401 u8 scsi_inter_cond_met;
402 bool scsi_inter_cond_met_set;
403 u8 scsi_rsv_conflicts;
404 bool scsi_rsv_conflicts_set;
406 bool scsi_tsk_full_set;
408 bool scsi_aca_active_set;
410 bool scsi_tsk_abort_set;
412 bool scsi_rx_chk_set[5];
413 struct qed_mfw_tlv_time scsi_chk_tstamp[5];
416 struct qed_mfw_tlv_iscsi {
418 bool target_llmnr_set;
420 bool header_digest_set;
422 bool data_digest_set;
424 #define QED_MFW_TLV_AUTH_METHOD_NONE (1)
425 #define QED_MFW_TLV_AUTH_METHOD_CHAP (2)
426 #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3)
427 bool auth_method_set;
428 u16 boot_taget_portal;
429 bool boot_taget_portal_set;
433 bool tx_desc_size_set;
435 bool rx_desc_size_set;
437 bool boot_progress_set;
439 bool tx_desc_qdepth_set;
441 bool rx_desc_qdepth_set;
452 enum qed_db_rec_width {
457 enum qed_db_rec_space {
462 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
463 (void __iomem *)(reg_addr))
465 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
467 #define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val, \
468 (void __iomem *)(reg_addr))
470 #define QED_COALESCE_MAX 0x1FF
471 #define QED_DEFAULT_RX_USECS 12
472 #define QED_DEFAULT_TX_USECS 48
477 struct qed_eth_pf_params {
478 /* The following parameters are used during HW-init
479 * and these parameters need to be passed as arguments
480 * to update_pf_params routine invoked before slowpath start
484 /* per-VF number of CIDs */
486 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32)
488 /* To enable arfs, previous to HW-init a positive number needs to be
489 * set [as filters require allocated searcher ILT memory].
490 * This will set the maximal number of configured steering-filters.
492 u32 num_arfs_filters;
495 struct qed_fcoe_pf_params {
496 /* The following parameters are used during protocol-init */
497 u64 glbl_q_params_addr;
498 u64 bdq_pbl_base_addr[2];
500 /* The following parameters are used during HW-init
501 * and these parameters need to be passed as arguments
502 * to update_pf_params routine invoked before slowpath start
507 /* The following parameters are used during protocol-init */
508 u16 sq_num_pbl_pages;
511 u16 cmdq_num_entries;
512 u16 rq_buffer_log_size;
515 u16 bdq_xoff_threshold[2];
516 u16 bdq_xon_threshold[2];
518 u8 num_cqs; /* num of global CQs */
524 u8 bdq_pbl_num_entries[2];
527 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
528 struct qed_iscsi_pf_params {
529 u64 glbl_q_params_addr;
530 u64 bdq_pbl_base_addr[3];
532 u16 cmdq_num_entries;
536 /* The following parameters are used during HW-init
537 * and these parameters need to be passed as arguments
538 * to update_pf_params routine invoked before slowpath start
543 /* The following parameters are used during protocol-init */
544 u16 half_way_close_timeout;
545 u16 bdq_xoff_threshold[3];
546 u16 bdq_xon_threshold[3];
547 u16 cmdq_xoff_threshold;
548 u16 cmdq_xon_threshold;
551 u8 num_sq_pages_in_ring;
552 u8 num_r2tq_pages_in_ring;
553 u8 num_uhq_pages_in_ring;
565 u8 soc_num_of_blocks_log;
566 u8 bdq_pbl_num_entries[3];
569 struct qed_rdma_pf_params {
570 /* Supplied to QED during resource allocation (may affect the ILT and
573 u32 min_dpis; /* number of requested DPIs */
574 u32 num_qps; /* number of requested Queue Pairs */
575 u32 num_srqs; /* number of requested SRQ */
576 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
577 u8 gl_pi; /* protocol index */
579 /* Will allocate rate limiters to be used with QPs */
583 struct qed_pf_params {
584 struct qed_eth_pf_params eth_pf_params;
585 struct qed_fcoe_pf_params fcoe_pf_params;
586 struct qed_iscsi_pf_params iscsi_pf_params;
587 struct qed_rdma_pf_params rdma_pf_params;
598 struct status_block_e4 *sb_virt;
600 u32 sb_ack; /* Last given ack */
602 void __iomem *igu_addr;
604 #define QED_SB_INFO_INIT 0x1
605 #define QED_SB_INFO_SETUP 0x2
607 struct qed_dev *cdev;
615 struct qed_dev_info {
616 unsigned long pci_mem_start;
617 unsigned long pci_mem_end;
618 unsigned int pci_irq;
631 #define QED_MFW_VERSION_0_MASK 0x000000FF
632 #define QED_MFW_VERSION_0_OFFSET 0
633 #define QED_MFW_VERSION_1_MASK 0x0000FF00
634 #define QED_MFW_VERSION_1_OFFSET 8
635 #define QED_MFW_VERSION_2_MASK 0x00FF0000
636 #define QED_MFW_VERSION_2_OFFSET 16
637 #define QED_MFW_VERSION_3_MASK 0xFF000000
638 #define QED_MFW_VERSION_3_OFFSET 24
641 bool b_inter_pf_switch;
651 #define QED_MBI_VERSION_0_MASK 0x000000FF
652 #define QED_MBI_VERSION_0_OFFSET 0
653 #define QED_MBI_VERSION_1_MASK 0x0000FF00
654 #define QED_MBI_VERSION_1_OFFSET 8
655 #define QED_MBI_VERSION_2_MASK 0x00FF0000
656 #define QED_MBI_VERSION_2_OFFSET 16
658 enum qed_dev_type dev_type;
660 /* Output parameters for qede */
669 QED_SB_TYPE_L2_QUEUE,
680 enum qed_link_mode_bits {
681 QED_LM_FIBRE_BIT = BIT(0),
682 QED_LM_Autoneg_BIT = BIT(1),
683 QED_LM_Asym_Pause_BIT = BIT(2),
684 QED_LM_Pause_BIT = BIT(3),
685 QED_LM_1000baseT_Full_BIT = BIT(4),
686 QED_LM_10000baseT_Full_BIT = BIT(5),
687 QED_LM_10000baseKR_Full_BIT = BIT(6),
688 QED_LM_20000baseKR2_Full_BIT = BIT(7),
689 QED_LM_25000baseKR_Full_BIT = BIT(8),
690 QED_LM_40000baseLR4_Full_BIT = BIT(9),
691 QED_LM_50000baseKR2_Full_BIT = BIT(10),
692 QED_LM_100000baseKR4_Full_BIT = BIT(11),
693 QED_LM_TP_BIT = BIT(12),
694 QED_LM_Backplane_BIT = BIT(13),
695 QED_LM_1000baseKX_Full_BIT = BIT(14),
696 QED_LM_10000baseKX4_Full_BIT = BIT(15),
697 QED_LM_10000baseR_FEC_BIT = BIT(16),
698 QED_LM_40000baseKR4_Full_BIT = BIT(17),
699 QED_LM_40000baseCR4_Full_BIT = BIT(18),
700 QED_LM_40000baseSR4_Full_BIT = BIT(19),
701 QED_LM_25000baseCR_Full_BIT = BIT(20),
702 QED_LM_25000baseSR_Full_BIT = BIT(21),
703 QED_LM_50000baseCR2_Full_BIT = BIT(22),
704 QED_LM_100000baseSR4_Full_BIT = BIT(23),
705 QED_LM_100000baseCR4_Full_BIT = BIT(24),
706 QED_LM_100000baseLR4_ER4_Full_BIT = BIT(25),
707 QED_LM_50000baseSR2_Full_BIT = BIT(26),
708 QED_LM_1000baseX_Full_BIT = BIT(27),
709 QED_LM_10000baseCR_Full_BIT = BIT(28),
710 QED_LM_10000baseSR_Full_BIT = BIT(29),
711 QED_LM_10000baseLR_Full_BIT = BIT(30),
712 QED_LM_10000baseLRM_Full_BIT = BIT(31),
716 struct qed_link_params {
719 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
720 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
721 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
722 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
723 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
724 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
729 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
730 #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
731 #define QED_LINK_PAUSE_TX_ENABLE BIT(2)
733 #define QED_LINK_LOOPBACK_NONE BIT(0)
734 #define QED_LINK_LOOPBACK_INT_PHY BIT(1)
735 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
736 #define QED_LINK_LOOPBACK_EXT BIT(3)
737 #define QED_LINK_LOOPBACK_MAC BIT(4)
739 struct qed_link_eee_params eee;
742 struct qed_link_output {
745 /* In QED_LM_* defs */
750 u32 speed; /* In Mb/s */
751 u8 duplex; /* In DUPLEX defs */
752 u8 port; /* In PORT defs */
756 /* EEE - capability & param */
760 struct qed_link_eee_params eee;
763 struct qed_probe_params {
764 enum qed_protocol protocol;
771 #define QED_DRV_VER_STR_SIZE 12
772 struct qed_slowpath_params {
778 u8 name[QED_DRV_VER_STR_SIZE];
781 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
783 struct qed_int_info {
784 struct msix_entry *msix;
787 /* This should be updated by the protocol driver */
791 struct qed_generic_tlvs {
792 #define QED_TLV_IP_CSUM BIT(0)
793 #define QED_TLV_LSO BIT(1)
795 #define QED_TLV_MAC_COUNT 3
796 u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
799 #define QED_I2C_DEV_ADDR_A0 0xA0
800 #define QED_I2C_DEV_ADDR_A2 0xA2
802 #define QED_NVM_SIGNATURE 0x12435687
804 enum qed_nvm_flash_cmd {
805 QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
806 QED_NVM_FLASH_CMD_FILE_START = 0x3,
807 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
808 QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
809 QED_NVM_FLASH_CMD_NVM_MAX,
812 struct qed_common_cb_ops {
813 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
814 void (*link_update)(void *dev,
815 struct qed_link_output *link);
816 void (*schedule_recovery_handler)(void *dev);
817 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
818 void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
819 void (*get_protocol_tlv_data)(void *dev, void *data);
822 struct qed_selftest_ops {
824 * @brief selftest_interrupt - Perform interrupt test
828 * @return 0 on success, error otherwise.
830 int (*selftest_interrupt)(struct qed_dev *cdev);
833 * @brief selftest_memory - Perform memory test
837 * @return 0 on success, error otherwise.
839 int (*selftest_memory)(struct qed_dev *cdev);
842 * @brief selftest_register - Perform register test
846 * @return 0 on success, error otherwise.
848 int (*selftest_register)(struct qed_dev *cdev);
851 * @brief selftest_clock - Perform clock test
855 * @return 0 on success, error otherwise.
857 int (*selftest_clock)(struct qed_dev *cdev);
860 * @brief selftest_nvram - Perform nvram test
864 * @return 0 on success, error otherwise.
866 int (*selftest_nvram) (struct qed_dev *cdev);
869 struct qed_common_ops {
870 struct qed_selftest_ops *selftest;
872 struct qed_dev* (*probe)(struct pci_dev *dev,
873 struct qed_probe_params *params);
875 void (*remove)(struct qed_dev *cdev);
877 int (*set_power_state)(struct qed_dev *cdev,
880 void (*set_name) (struct qed_dev *cdev, char name[]);
882 /* Client drivers need to make this call before slowpath_start.
883 * PF params required for the call before slowpath_start is
884 * documented within the qed_pf_params structure definition.
886 void (*update_pf_params)(struct qed_dev *cdev,
887 struct qed_pf_params *params);
888 int (*slowpath_start)(struct qed_dev *cdev,
889 struct qed_slowpath_params *params);
891 int (*slowpath_stop)(struct qed_dev *cdev);
893 /* Requests to use `cnt' interrupts for fastpath.
894 * upon success, returns number of interrupts allocated for fastpath.
896 int (*set_fp_int)(struct qed_dev *cdev,
899 /* Fills `info' with pointers required for utilizing interrupts */
900 int (*get_fp_int)(struct qed_dev *cdev,
901 struct qed_int_info *info);
903 u32 (*sb_init)(struct qed_dev *cdev,
904 struct qed_sb_info *sb_info,
906 dma_addr_t sb_phy_addr,
908 enum qed_sb_type type);
910 u32 (*sb_release)(struct qed_dev *cdev,
911 struct qed_sb_info *sb_info,
913 enum qed_sb_type type);
915 void (*simd_handler_config)(struct qed_dev *cdev,
918 void (*handler)(void *));
920 void (*simd_handler_clean)(struct qed_dev *cdev,
922 int (*dbg_grc)(struct qed_dev *cdev,
923 void *buffer, u32 *num_dumped_bytes);
925 int (*dbg_grc_size)(struct qed_dev *cdev);
927 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
929 int (*dbg_all_data_size) (struct qed_dev *cdev);
932 * @brief can_link_change - can the instance change the link or not
936 * @return true if link-change is allowed, false otherwise.
938 bool (*can_link_change)(struct qed_dev *cdev);
941 * @brief set_link - set links according to params
944 * @param params - values used to override the default link configuration
946 * @return 0 on success, error otherwise.
948 int (*set_link)(struct qed_dev *cdev,
949 struct qed_link_params *params);
952 * @brief get_link - returns the current link state.
955 * @param if_link - structure to be filled with current link configuration.
957 void (*get_link)(struct qed_dev *cdev,
958 struct qed_link_output *if_link);
961 * @brief - drains chip in case Tx completions fail to arrive due to pause.
965 int (*drain)(struct qed_dev *cdev);
968 * @brief update_msglvl - update module debug level
974 void (*update_msglvl)(struct qed_dev *cdev,
978 int (*chain_alloc)(struct qed_dev *cdev,
979 enum qed_chain_use_mode intended_use,
980 enum qed_chain_mode mode,
981 enum qed_chain_cnt_type cnt_type,
984 struct qed_chain *p_chain,
985 struct qed_chain_ext_pbl *ext_pbl);
987 void (*chain_free)(struct qed_dev *cdev,
988 struct qed_chain *p_chain);
991 * @brief nvm_flash - Flash nvm data.
994 * @param name - file containing the data
996 * @return 0 on success, error otherwise.
998 int (*nvm_flash)(struct qed_dev *cdev, const char *name);
1001 * @brief nvm_get_image - reads an entire image from nvram
1004 * @param type - type of the request nvram image
1005 * @param buf - preallocated buffer to fill with the image
1006 * @param len - length of the allocated buffer
1008 * @return 0 on success, error otherwise
1010 int (*nvm_get_image)(struct qed_dev *cdev,
1011 enum qed_nvm_images type, u8 *buf, u16 len);
1014 * @brief set_coalesce - Configure Rx coalesce value in usec
1017 * @param rx_coal - Rx coalesce value in usec
1018 * @param tx_coal - Tx coalesce value in usec
1019 * @param qid - Queue index
1020 * @param sb_id - Status Block Id
1022 * @return 0 on success, error otherwise.
1024 int (*set_coalesce)(struct qed_dev *cdev,
1025 u16 rx_coal, u16 tx_coal, void *handle);
1028 * @brief set_led - Configure LED mode
1031 * @param mode - LED mode
1033 * @return 0 on success, error otherwise.
1035 int (*set_led)(struct qed_dev *cdev,
1036 enum qed_led_mode mode);
1038 * @brief db_recovery_add - add doorbell information to the doorbell
1039 * recovery mechanism.
1042 * @param db_addr - doorbell address
1043 * @param db_data - address of where db_data is stored
1044 * @param db_is_32b - doorbell is 32b pr 64b
1045 * @param db_is_user - doorbell recovery addresses are user or kernel space
1047 int (*db_recovery_add)(struct qed_dev *cdev,
1048 void __iomem *db_addr,
1050 enum qed_db_rec_width db_width,
1051 enum qed_db_rec_space db_space);
1054 * @brief db_recovery_del - remove doorbell information from the doorbell
1055 * recovery mechanism. db_data serves as key (db_addr is not unique).
1058 * @param db_addr - doorbell address
1059 * @param db_data - address where db_data is stored. Serves as key for the
1062 int (*db_recovery_del)(struct qed_dev *cdev,
1063 void __iomem *db_addr, void *db_data);
1066 * @brief recovery_process - Trigger a recovery process
1070 * @return 0 on success, error otherwise.
1072 int (*recovery_process)(struct qed_dev *cdev);
1075 * @brief recovery_prolog - Execute the prolog operations of a recovery process
1079 * @return 0 on success, error otherwise.
1081 int (*recovery_prolog)(struct qed_dev *cdev);
1084 * @brief update_drv_state - API to inform the change in the driver state.
1090 int (*update_drv_state)(struct qed_dev *cdev, bool active);
1093 * @brief update_mac - API to inform the change in the mac address
1099 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
1102 * @brief update_mtu - API to inform the change in the mtu
1108 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
1111 * @brief update_wol - update of changes in the WoL configuration
1114 * @param enabled - true iff WoL should be enabled.
1116 int (*update_wol) (struct qed_dev *cdev, bool enabled);
1119 * @brief read_module_eeprom
1122 * @param buf - buffer
1123 * @param dev_addr - PHY device memory region
1124 * @param offset - offset into eeprom contents to be read
1125 * @param len - buffer length, i.e., max bytes to be read
1127 int (*read_module_eeprom)(struct qed_dev *cdev,
1128 char *buf, u8 dev_addr, u32 offset, u32 len);
1131 * @brief get_affin_hwfn_idx
1135 u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
1138 * @brief read_nvm_cfg - Read NVM config attribute value.
1140 * @param buf - buffer
1141 * @param cmd - NVM CFG command id
1142 * @param entity_id - Entity id
1145 int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
1148 * @brief read_nvm_cfg - Read NVM config attribute value.
1150 * @param cmd - NVM CFG command id
1152 * @return config id length, 0 on error.
1154 int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
1157 * @brief set_grc_config - Configure value for grc config id.
1159 * @param cfg_id - grc config id
1160 * @param val - grc config value
1163 int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
1166 #define MASK_FIELD(_name, _value) \
1167 ((_value) &= (_name ## _MASK))
1169 #define FIELD_VALUE(_name, _value) \
1170 ((_value & _name ## _MASK) << _name ## _SHIFT)
1172 #define SET_FIELD(value, name, flag) \
1174 (value) &= ~(name ## _MASK << name ## _SHIFT); \
1175 (value) |= (((u64)flag) << (name ## _SHIFT)); \
1178 #define GET_FIELD(value, name) \
1179 (((value) >> (name ## _SHIFT)) & name ## _MASK)
1181 #define GET_MFW_FIELD(name, field) \
1182 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
1184 #define SET_MFW_FIELD(name, field, value) \
1186 (name) &= ~(field ## _MASK); \
1187 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\
1190 #define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
1192 /* Debug print definitions */
1193 #define DP_ERR(cdev, fmt, ...) \
1195 pr_err("[%s:%d(%s)]" fmt, \
1196 __func__, __LINE__, \
1197 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1201 #define DP_NOTICE(cdev, fmt, ...) \
1203 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1204 pr_notice("[%s:%d(%s)]" fmt, \
1205 __func__, __LINE__, \
1206 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1212 #define DP_INFO(cdev, fmt, ...) \
1214 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
1215 pr_notice("[%s:%d(%s)]" fmt, \
1216 __func__, __LINE__, \
1217 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1222 #define DP_VERBOSE(cdev, module, fmt, ...) \
1224 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
1225 ((cdev)->dp_module & module))) { \
1226 pr_notice("[%s:%d(%s)]" fmt, \
1227 __func__, __LINE__, \
1228 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1234 QED_LEVEL_VERBOSE = 0x0,
1235 QED_LEVEL_INFO = 0x1,
1236 QED_LEVEL_NOTICE = 0x2,
1237 QED_LEVEL_ERR = 0x3,
1240 #define QED_LOG_LEVEL_SHIFT (30)
1241 #define QED_LOG_VERBOSE_MASK (0x3fffffff)
1242 #define QED_LOG_INFO_MASK (0x40000000)
1243 #define QED_LOG_NOTICE_MASK (0x80000000)
1246 QED_MSG_SPQ = 0x10000,
1247 QED_MSG_STATS = 0x20000,
1248 QED_MSG_DCB = 0x40000,
1249 QED_MSG_IOV = 0x80000,
1250 QED_MSG_SP = 0x100000,
1251 QED_MSG_STORAGE = 0x200000,
1252 QED_MSG_CXT = 0x800000,
1253 QED_MSG_LL2 = 0x1000000,
1254 QED_MSG_ILT = 0x2000000,
1255 QED_MSG_RDMA = 0x4000000,
1256 QED_MSG_DEBUG = 0x8000000,
1257 /* to be added...up to 0x8000000 */
1266 struct qed_eth_stats_common {
1267 u64 no_buff_discards;
1268 u64 packet_too_big_discard;
1276 u64 mftag_filter_discards;
1277 u64 mac_filter_discards;
1278 u64 gft_filter_drop;
1285 u64 tx_err_drop_pkts;
1286 u64 tpa_coalesced_pkts;
1287 u64 tpa_coalesced_events;
1289 u64 tpa_not_coalesced_pkts;
1290 u64 tpa_coalesced_bytes;
1293 u64 rx_64_byte_packets;
1294 u64 rx_65_to_127_byte_packets;
1295 u64 rx_128_to_255_byte_packets;
1296 u64 rx_256_to_511_byte_packets;
1297 u64 rx_512_to_1023_byte_packets;
1298 u64 rx_1024_to_1518_byte_packets;
1300 u64 rx_mac_crtl_frames;
1301 u64 rx_pause_frames;
1303 u64 rx_align_errors;
1304 u64 rx_carrier_errors;
1305 u64 rx_oversize_packets;
1307 u64 rx_undersize_packets;
1309 u64 tx_64_byte_packets;
1310 u64 tx_65_to_127_byte_packets;
1311 u64 tx_128_to_255_byte_packets;
1312 u64 tx_256_to_511_byte_packets;
1313 u64 tx_512_to_1023_byte_packets;
1314 u64 tx_1024_to_1518_byte_packets;
1315 u64 tx_pause_frames;
1320 u64 rx_mac_uc_packets;
1321 u64 rx_mac_mc_packets;
1322 u64 rx_mac_bc_packets;
1323 u64 rx_mac_frames_ok;
1325 u64 tx_mac_uc_packets;
1326 u64 tx_mac_mc_packets;
1327 u64 tx_mac_bc_packets;
1328 u64 tx_mac_ctrl_frames;
1329 u64 link_change_count;
1332 struct qed_eth_stats_bb {
1333 u64 rx_1519_to_1522_byte_packets;
1334 u64 rx_1519_to_2047_byte_packets;
1335 u64 rx_2048_to_4095_byte_packets;
1336 u64 rx_4096_to_9216_byte_packets;
1337 u64 rx_9217_to_16383_byte_packets;
1338 u64 tx_1519_to_2047_byte_packets;
1339 u64 tx_2048_to_4095_byte_packets;
1340 u64 tx_4096_to_9216_byte_packets;
1341 u64 tx_9217_to_16383_byte_packets;
1342 u64 tx_lpi_entry_count;
1343 u64 tx_total_collisions;
1346 struct qed_eth_stats_ah {
1347 u64 rx_1519_to_max_byte_packets;
1348 u64 tx_1519_to_max_byte_packets;
1351 struct qed_eth_stats {
1352 struct qed_eth_stats_common common;
1355 struct qed_eth_stats_bb bb;
1356 struct qed_eth_stats_ah ah;
1360 #define QED_SB_IDX 0x0002
1363 #define TX_PI(tc) (RX_PI + 1 + tc)
1365 struct qed_sb_cnt_info {
1366 /* Original, current, and free SBs for PF */
1371 /* Original, current and free SBS for child VFs */
1377 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1382 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
1383 STATUS_BLOCK_E4_PROD_INDEX_MASK;
1384 if (sb_info->sb_ack != prod) {
1385 sb_info->sb_ack = prod;
1395 * @brief This function creates an update command for interrupts that is
1396 * written to the IGU.
1398 * @param sb_info - This is the structure allocated and
1399 * initialized per status block. Assumption is
1400 * that it was initialized using qed_sb_init
1401 * @param int_cmd - Enable/Disable/Nop
1402 * @param upd_flg - whether igu consumer should be
1405 * @return inline void
1407 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1408 enum igu_int_cmd int_cmd,
1411 struct igu_prod_cons_update igu_ack = { 0 };
1413 igu_ack.sb_id_and_flags =
1414 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1415 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1416 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1417 (IGU_SEG_ACCESS_REG <<
1418 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1420 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
1422 /* Both segments (interrupts & acks) are written to same place address;
1423 * Need to guarantee all commands will be received (in-order) by HW.
1428 static inline void __internal_ram_wr(void *p_hwfn,
1436 for (i = 0; i < size / sizeof(*data); i++)
1437 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1440 static inline void internal_ram_wr(void __iomem *addr,
1444 __internal_ram_wr(NULL, addr, size, data);
1450 QED_RSS_IPV4_TCP = 0x4,
1451 QED_RSS_IPV6_TCP = 0x8,
1452 QED_RSS_IPV4_UDP = 0x10,
1453 QED_RSS_IPV6_UDP = 0x20,
1456 #define QED_RSS_IND_TABLE_SIZE 128
1457 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */