1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __ETH_COMMON__
34 #define __ETH_COMMON__
36 /********************/
37 /* ETH FW CONSTANTS */
38 /********************/
40 #define ETH_HSI_VER_MAJOR 3
41 #define ETH_HSI_VER_MINOR 11
43 #define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
44 /* Maximum number of pinned L2 connections (CIDs) */
45 #define ETH_PINNED_CONN_MAX_NUM 32
47 #define ETH_CACHE_LINE_SIZE 64
48 #define ETH_RX_CQE_GAP 32
49 #define ETH_MAX_RAMROD_PER_CON 8
50 #define ETH_TX_BD_PAGE_SIZE_BYTES 4096
51 #define ETH_RX_BD_PAGE_SIZE_BYTES 4096
52 #define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
53 #define ETH_RX_NUM_NEXT_PAGE_BDS 2
55 #define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
56 #define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
58 #define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
59 #define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
60 #define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
61 #define ETH_TX_MAX_LSO_HDR_NBD 4
62 #define ETH_TX_MIN_BDS_PER_LSO_PKT 3
63 #define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
64 #define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
65 #define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
66 #define ETH_TX_MIN_BDS_PER_PKT_W_VPORT_FORWARDING 4
67 #define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
68 #define ETH_TX_MAX_LSO_HDR_BYTES 510
69 #define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
70 #define ETH_TX_LSO_WINDOW_MIN_LEN 9700
71 #define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
72 #define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
73 #define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
75 #define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
76 #define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
77 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
78 #define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
79 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
81 #define ETH_RX_MAX_BUFF_PER_PKT 5
82 #define ETH_RX_BD_THRESHOLD 16
84 /* Num of MAC/VLAN filters */
85 #define ETH_NUM_MAC_FILTERS 512
86 #define ETH_NUM_VLAN_FILTERS 512
88 /* Approx. multicast constants */
89 #define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
90 #define ETH_MULTICAST_MAC_BINS 256
91 #define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
93 /* Ethernet vport update constants */
94 #define ETH_FILTER_RULES_COUNT 10
95 #define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
96 #define ETH_RSS_KEY_SIZE_REGS 10
97 #define ETH_RSS_ENGINE_NUM_K2 207
98 #define ETH_RSS_ENGINE_NUM_BB 127
101 #define ETH_TPA_MAX_AGGS_NUM 64
102 #define ETH_TPA_CQE_START_BW_LEN_LIST_SIZE 2
103 #define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
104 #define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
106 /* Control frame check constants */
107 #define ETH_CTL_FRAME_ETH_TYPE_NUM 4
110 #define ETH_GFT_TRASHCAN_VPORT 0x1FF /* GFT drop flow vport number */
112 /* Destination port mode */
116 DST_PORT_PHY_LOOPBACK,
121 /* Ethernet address type */
130 struct eth_tx_1st_bd_flags {
132 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
133 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
134 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
135 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
136 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
137 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
138 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
139 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
140 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
141 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
142 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
143 #define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
144 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
145 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
146 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
147 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
150 /* The parsing information data fo rthe first tx bd of a given packet */
151 struct eth_tx_data_1st_bd {
154 struct eth_tx_1st_bd_flags bd_flags;
156 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
157 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
158 #define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
159 #define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
160 #define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
161 #define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
164 /* The parsing information data for the second tx bd of a given packet */
165 struct eth_tx_data_2nd_bd {
168 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
169 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
170 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
171 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
172 #define ETH_TX_DATA_2ND_BD_DST_PORT_MODE_MASK 0x3
173 #define ETH_TX_DATA_2ND_BD_DST_PORT_MODE_SHIFT 6
174 #define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
175 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
176 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
177 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
178 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
179 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
180 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
181 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
182 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
183 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
184 #define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
185 #define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
186 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
187 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
189 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
190 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
191 #define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
192 #define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
195 /* Firmware data for L2-EDPM packet */
196 struct eth_edpm_fw_data {
197 struct eth_tx_data_1st_bd data_1st_bd;
198 struct eth_tx_data_2nd_bd data_2nd_bd;
202 /* Tunneling parsing flags */
203 struct eth_tunnel_parsing_flags {
205 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
206 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
207 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
208 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
209 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
210 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
211 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
212 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
213 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
214 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
215 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
216 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
219 /* PMD flow control bits */
220 struct eth_pmd_flow_flags {
222 #define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
223 #define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
224 #define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
225 #define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
226 #define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
227 #define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
230 /* Regular ETH Rx FP CQE */
231 struct eth_fast_path_rx_reg_cqe {
234 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
235 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
236 #define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
237 #define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
238 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
239 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
241 struct parsing_and_err_flags pars_flags;
244 __le16 len_on_first_bd;
246 struct eth_tunnel_parsing_flags tunnel_pars_flags;
250 __le32 flow_id_or_resource_id;
252 struct eth_pmd_flow_flags pmd_flags;
255 /* TPA-continue ETH Rx FP CQE */
256 struct eth_fast_path_rx_tpa_cont_cqe {
259 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
262 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
264 struct eth_pmd_flow_flags pmd_flags;
267 /* TPA-end ETH Rx FP CQE */
268 struct eth_fast_path_rx_tpa_end_cqe {
271 __le16 total_packet_len;
274 __le16 num_of_coalesced_segs;
276 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
277 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
280 struct eth_pmd_flow_flags pmd_flags;
283 /* TPA-start ETH Rx FP CQE */
284 struct eth_fast_path_rx_tpa_start_cqe {
287 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
288 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
289 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
290 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
291 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
292 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
294 struct parsing_and_err_flags pars_flags;
297 __le16 len_on_first_bd;
299 struct eth_tunnel_parsing_flags tunnel_pars_flags;
302 __le16 bw_ext_bd_len_list[ETH_TPA_CQE_START_BW_LEN_LIST_SIZE];
304 __le32 flow_id_or_resource_id;
306 struct eth_pmd_flow_flags pmd_flags;
309 /* The L4 pseudo checksum mode for Ethernet */
310 enum eth_l4_pseudo_checksum_mode {
311 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
312 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
313 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
320 /* Regular ETH Rx SP CQE */
321 struct eth_slow_path_rx_cqe {
328 struct eth_pmd_flow_flags pmd_flags;
331 /* Union for all ETH Rx CQE types */
333 struct eth_fast_path_rx_reg_cqe fast_path_regular;
334 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
335 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
336 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
337 struct eth_slow_path_rx_cqe slow_path;
340 /* ETH Rx CQE type */
341 enum eth_rx_cqe_type {
342 ETH_RX_CQE_TYPE_UNUSED,
343 ETH_RX_CQE_TYPE_REGULAR,
344 ETH_RX_CQE_TYPE_SLOW_PATH,
345 ETH_RX_CQE_TYPE_TPA_START,
346 ETH_RX_CQE_TYPE_TPA_CONT,
347 ETH_RX_CQE_TYPE_TPA_END,
351 struct eth_rx_pmd_cqe {
352 union eth_rx_cqe cqe;
353 u8 reserved[ETH_RX_CQE_GAP];
356 enum eth_rx_tunn_type {
364 /* Aggregation end reason. */
365 enum eth_tpa_end_reason {
367 ETH_AGG_END_SP_UPDATE,
369 ETH_AGG_END_LAST_SEG,
371 ETH_AGG_END_NOT_CONSISTENT,
372 ETH_AGG_END_OUT_OF_ORDER,
373 ETH_AGG_END_NON_TPA_SEG,
374 MAX_ETH_TPA_END_REASON
377 /* The first tx bd of a given packet */
378 struct eth_tx_1st_bd {
381 struct eth_tx_data_1st_bd data;
384 /* The second tx bd of a given packet */
385 struct eth_tx_2nd_bd {
388 struct eth_tx_data_2nd_bd data;
391 /* The parsing information data for the third tx bd of a given packet */
392 struct eth_tx_data_3rd_bd {
395 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
396 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
397 #define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
398 #define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
399 #define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
400 #define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
401 #define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
402 #define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
403 u8 tunn_l4_hdr_start_offset_w;
407 /* The third tx bd of a given packet */
408 struct eth_tx_3rd_bd {
411 struct eth_tx_data_3rd_bd data;
414 /* The parsing information data for the forth tx bd of a given packet. */
415 struct eth_tx_data_4th_bd {
419 #define ETH_TX_DATA_4TH_BD_DST_VPORT_ID_VALID_MASK 0x1
420 #define ETH_TX_DATA_4TH_BD_DST_VPORT_ID_VALID_SHIFT 0
421 #define ETH_TX_DATA_4TH_BD_RESERVED1_MASK 0x7F
422 #define ETH_TX_DATA_4TH_BD_RESERVED1_SHIFT 1
423 #define ETH_TX_DATA_4TH_BD_START_BD_MASK 0x1
424 #define ETH_TX_DATA_4TH_BD_START_BD_SHIFT 8
425 #define ETH_TX_DATA_4TH_BD_RESERVED2_MASK 0x7F
426 #define ETH_TX_DATA_4TH_BD_RESERVED2_SHIFT 9
430 /* The forth tx bd of a given packet */
431 struct eth_tx_4th_bd {
432 struct regpair addr; /* Single continuous buffer */
433 __le16 nbytes; /* Number of bytes in this BD */
434 struct eth_tx_data_4th_bd data; /* Parsing information data */
437 /* Complementary information for the regular tx bd of a given packet */
438 struct eth_tx_data_bd {
441 #define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
442 #define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
443 #define ETH_TX_DATA_BD_START_BD_MASK 0x1
444 #define ETH_TX_DATA_BD_START_BD_SHIFT 8
445 #define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
446 #define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
450 /* The common non-special TX BD ring element */
454 struct eth_tx_data_bd data;
457 union eth_tx_bd_types {
458 struct eth_tx_1st_bd first_bd;
459 struct eth_tx_2nd_bd second_bd;
460 struct eth_tx_3rd_bd third_bd;
461 struct eth_tx_4th_bd fourth_bd;
462 struct eth_tx_bd reg_bd;
465 /* Mstorm Queue Zone */
466 enum eth_tx_tunn_type {
474 /* Mstorm Queue Zone */
475 struct mstorm_eth_queue_zone {
476 struct eth_rx_prod_data rx_producers;
480 /* Ystorm Queue Zone */
481 struct xstorm_eth_queue_zone {
482 struct coalescing_timeset int_coalescing_timeset;
486 /* ETH doorbell data */
489 #define ETH_DB_DATA_DEST_MASK 0x3
490 #define ETH_DB_DATA_DEST_SHIFT 0
491 #define ETH_DB_DATA_AGG_CMD_MASK 0x3
492 #define ETH_DB_DATA_AGG_CMD_SHIFT 2
493 #define ETH_DB_DATA_BYPASS_EN_MASK 0x1
494 #define ETH_DB_DATA_BYPASS_EN_SHIFT 4
495 #define ETH_DB_DATA_RESERVED_MASK 0x1
496 #define ETH_DB_DATA_RESERVED_SHIFT 5
497 #define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
498 #define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
505 RSS_HASH_TYPE_DEFAULT = 0,
506 RSS_HASH_TYPE_IPV4 = 1,
507 RSS_HASH_TYPE_TCP_IPV4 = 2,
508 RSS_HASH_TYPE_IPV6 = 3,
509 RSS_HASH_TYPE_TCP_IPV6 = 4,
510 RSS_HASH_TYPE_UDP_IPV4 = 5,
511 RSS_HASH_TYPE_UDP_IPV6 = 6,
515 #endif /* __ETH_COMMON__ */