1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __ETH_COMMON__
34 #define __ETH_COMMON__
36 /********************/
37 /* ETH FW CONSTANTS */
38 /********************/
40 #define ETH_HSI_VER_MAJOR 3
41 #define ETH_HSI_VER_MINOR 10
43 #define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
45 #define ETH_CACHE_LINE_SIZE 64
46 #define ETH_RX_CQE_GAP 32
47 #define ETH_MAX_RAMROD_PER_CON 8
48 #define ETH_TX_BD_PAGE_SIZE_BYTES 4096
49 #define ETH_RX_BD_PAGE_SIZE_BYTES 4096
50 #define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
51 #define ETH_RX_NUM_NEXT_PAGE_BDS 2
53 #define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
54 #define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
56 #define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
57 #define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
58 #define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
59 #define ETH_TX_MAX_LSO_HDR_NBD 4
60 #define ETH_TX_MIN_BDS_PER_LSO_PKT 3
61 #define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
62 #define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
63 #define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
64 #define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
65 #define ETH_TX_MAX_LSO_HDR_BYTES 510
66 #define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
67 #define ETH_TX_LSO_WINDOW_MIN_LEN 9700
68 #define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
69 #define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
70 #define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
72 #define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
73 #define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
74 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
75 #define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
76 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
78 /* Maximum number of buffers, used for RX packet placement */
79 #define ETH_RX_MAX_BUFF_PER_PKT 5
80 #define ETH_RX_BD_THRESHOLD 12
82 /* Num of MAC/VLAN filters */
83 #define ETH_NUM_MAC_FILTERS 512
84 #define ETH_NUM_VLAN_FILTERS 512
86 /* Approx. multicast constants */
87 #define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
88 #define ETH_MULTICAST_MAC_BINS 256
89 #define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
91 /* Ethernet vport update constants */
92 #define ETH_FILTER_RULES_COUNT 10
93 #define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
94 #define ETH_RSS_KEY_SIZE_REGS 10
95 #define ETH_RSS_ENGINE_NUM_K2 207
96 #define ETH_RSS_ENGINE_NUM_BB 127
99 #define ETH_TPA_MAX_AGGS_NUM 64
100 #define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
101 #define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
102 #define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
104 /* Control frame check constants */
105 #define ETH_CTL_FRAME_ETH_TYPE_NUM 4
107 struct eth_tx_1st_bd_flags {
109 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
110 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
111 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
112 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
113 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
114 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
115 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
116 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
117 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
118 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
119 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
120 #define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
121 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
122 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
123 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
124 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
127 /* The parsing information data fo rthe first tx bd of a given packet */
128 struct eth_tx_data_1st_bd {
131 struct eth_tx_1st_bd_flags bd_flags;
133 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
134 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
135 #define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
136 #define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
137 #define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
138 #define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
141 /* The parsing information data for the second tx bd of a given packet */
142 struct eth_tx_data_2nd_bd {
145 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
146 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
147 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
148 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
149 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
150 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
151 #define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
152 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
153 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
154 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
155 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
156 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
157 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
158 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
159 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
160 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
161 #define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
162 #define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
163 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
164 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
166 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
167 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
168 #define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
169 #define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
172 /* Firmware data for L2-EDPM packet */
173 struct eth_edpm_fw_data {
174 struct eth_tx_data_1st_bd data_1st_bd;
175 struct eth_tx_data_2nd_bd data_2nd_bd;
179 struct eth_fast_path_cqe_fw_debug {
183 /* Tunneling parsing flags */
184 struct eth_tunnel_parsing_flags {
186 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
187 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
188 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
189 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
190 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
191 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
192 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
193 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
194 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
195 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
196 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
197 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
200 /* PMD flow control bits */
201 struct eth_pmd_flow_flags {
203 #define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
204 #define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
205 #define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
206 #define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
207 #define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
208 #define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
211 /* Regular ETH Rx FP CQE */
212 struct eth_fast_path_rx_reg_cqe {
215 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
216 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
217 #define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
218 #define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
219 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
220 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
222 struct parsing_and_err_flags pars_flags;
225 __le16 len_on_first_bd;
227 struct eth_tunnel_parsing_flags tunnel_pars_flags;
230 struct eth_fast_path_cqe_fw_debug fw_debug;
232 struct eth_pmd_flow_flags pmd_flags;
235 /* TPA-continue ETH Rx FP CQE */
236 struct eth_fast_path_rx_tpa_cont_cqe {
239 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
242 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
244 struct eth_pmd_flow_flags pmd_flags;
247 /* TPA-end ETH Rx FP CQE */
248 struct eth_fast_path_rx_tpa_end_cqe {
251 __le16 total_packet_len;
254 __le16 num_of_coalesced_segs;
256 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
257 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
260 struct eth_pmd_flow_flags pmd_flags;
263 /* TPA-start ETH Rx FP CQE */
264 struct eth_fast_path_rx_tpa_start_cqe {
267 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
268 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
269 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
270 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
271 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
272 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
274 struct parsing_and_err_flags pars_flags;
277 __le16 len_on_first_bd;
279 struct eth_tunnel_parsing_flags tunnel_pars_flags;
282 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
283 struct eth_fast_path_cqe_fw_debug fw_debug;
285 struct eth_pmd_flow_flags pmd_flags;
288 /* The L4 pseudo checksum mode for Ethernet */
289 enum eth_l4_pseudo_checksum_mode {
290 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
291 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
292 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
299 /* Regular ETH Rx SP CQE */
300 struct eth_slow_path_rx_cqe {
307 struct eth_pmd_flow_flags pmd_flags;
310 /* Union for all ETH Rx CQE types */
312 struct eth_fast_path_rx_reg_cqe fast_path_regular;
313 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
314 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
315 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
316 struct eth_slow_path_rx_cqe slow_path;
319 /* ETH Rx CQE type */
320 enum eth_rx_cqe_type {
321 ETH_RX_CQE_TYPE_UNUSED,
322 ETH_RX_CQE_TYPE_REGULAR,
323 ETH_RX_CQE_TYPE_SLOW_PATH,
324 ETH_RX_CQE_TYPE_TPA_START,
325 ETH_RX_CQE_TYPE_TPA_CONT,
326 ETH_RX_CQE_TYPE_TPA_END,
330 struct eth_rx_pmd_cqe {
331 union eth_rx_cqe cqe;
332 u8 reserved[ETH_RX_CQE_GAP];
335 enum eth_rx_tunn_type {
343 /* Aggregation end reason. */
344 enum eth_tpa_end_reason {
346 ETH_AGG_END_SP_UPDATE,
348 ETH_AGG_END_LAST_SEG,
350 ETH_AGG_END_NOT_CONSISTENT,
351 ETH_AGG_END_OUT_OF_ORDER,
352 ETH_AGG_END_NON_TPA_SEG,
353 MAX_ETH_TPA_END_REASON
356 /* The first tx bd of a given packet */
357 struct eth_tx_1st_bd {
360 struct eth_tx_data_1st_bd data;
363 /* The second tx bd of a given packet */
364 struct eth_tx_2nd_bd {
367 struct eth_tx_data_2nd_bd data;
370 /* The parsing information data for the third tx bd of a given packet */
371 struct eth_tx_data_3rd_bd {
374 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
375 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
376 #define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
377 #define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
378 #define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
379 #define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
380 #define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
381 #define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
382 u8 tunn_l4_hdr_start_offset_w;
386 /* The third tx bd of a given packet */
387 struct eth_tx_3rd_bd {
390 struct eth_tx_data_3rd_bd data;
393 /* Complementary information for the regular tx bd of a given packet */
394 struct eth_tx_data_bd {
397 #define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
398 #define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
399 #define ETH_TX_DATA_BD_START_BD_MASK 0x1
400 #define ETH_TX_DATA_BD_START_BD_SHIFT 8
401 #define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
402 #define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
406 /* The common non-special TX BD ring element */
410 struct eth_tx_data_bd data;
413 union eth_tx_bd_types {
414 struct eth_tx_1st_bd first_bd;
415 struct eth_tx_2nd_bd second_bd;
416 struct eth_tx_3rd_bd third_bd;
417 struct eth_tx_bd reg_bd;
420 /* Mstorm Queue Zone */
421 enum eth_tx_tunn_type {
429 /* Ystorm Queue Zone */
430 struct xstorm_eth_queue_zone {
431 struct coalescing_timeset int_coalescing_timeset;
435 /* ETH doorbell data */
438 #define ETH_DB_DATA_DEST_MASK 0x3
439 #define ETH_DB_DATA_DEST_SHIFT 0
440 #define ETH_DB_DATA_AGG_CMD_MASK 0x3
441 #define ETH_DB_DATA_AGG_CMD_SHIFT 2
442 #define ETH_DB_DATA_BYPASS_EN_MASK 0x1
443 #define ETH_DB_DATA_BYPASS_EN_SHIFT 4
444 #define ETH_DB_DATA_RESERVED_MASK 0x1
445 #define ETH_DB_DATA_RESERVED_SHIFT 5
446 #define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
447 #define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
454 RSS_HASH_TYPE_DEFAULT = 0,
455 RSS_HASH_TYPE_IPV4 = 1,
456 RSS_HASH_TYPE_TCP_IPV4 = 2,
457 RSS_HASH_TYPE_IPV6 = 3,
458 RSS_HASH_TYPE_TCP_IPV6 = 4,
459 RSS_HASH_TYPE_UDP_IPV4 = 5,
460 RSS_HASH_TYPE_UDP_IPV6 = 6,
464 #endif /* __ETH_COMMON__ */