1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2015 Linaro Ltd.
9 #include <linux/types.h>
10 #include <linux/cpumask.h>
12 #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
13 #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
14 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
15 #define QCOM_SCM_HDCP_MAX_REQ_CNT 5
17 struct qcom_scm_hdcp_req {
22 struct qcom_scm_vmperm {
27 enum qcom_scm_ocmem_client {
28 QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
29 QCOM_SCM_OCMEM_GRAPHICS_ID,
30 QCOM_SCM_OCMEM_VIDEO_ID,
31 QCOM_SCM_OCMEM_LP_AUDIO_ID,
32 QCOM_SCM_OCMEM_SENSORS_ID,
33 QCOM_SCM_OCMEM_OTHER_OS_ID,
34 QCOM_SCM_OCMEM_DEBUG_ID,
37 enum qcom_scm_sec_dev_id {
38 QCOM_SCM_MDSS_DEV_ID = 1,
39 QCOM_SCM_OCMEM_DEV_ID = 5,
40 QCOM_SCM_PCIE0_DEV_ID = 11,
41 QCOM_SCM_PCIE1_DEV_ID = 12,
42 QCOM_SCM_GFX_DEV_ID = 18,
43 QCOM_SCM_UFS_DEV_ID = 19,
44 QCOM_SCM_ICE_DEV_ID = 20,
47 enum qcom_scm_ice_cipher {
48 QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
49 QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
50 QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
51 QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
54 #define QCOM_SCM_VMID_HLOS 0x3
55 #define QCOM_SCM_VMID_MSS_MSA 0xF
56 #define QCOM_SCM_VMID_WLAN 0x18
57 #define QCOM_SCM_VMID_WLAN_CE 0x19
58 #define QCOM_SCM_PERM_READ 0x4
59 #define QCOM_SCM_PERM_WRITE 0x2
60 #define QCOM_SCM_PERM_EXEC 0x1
61 #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
62 #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
64 extern bool qcom_scm_is_available(void);
66 extern int qcom_scm_set_cold_boot_addr(void *entry);
67 extern int qcom_scm_set_warm_boot_addr(void *entry);
68 extern void qcom_scm_cpu_power_down(u32 flags);
69 extern int qcom_scm_set_remote_state(u32 state, u32 id);
71 struct qcom_scm_pas_metadata {
77 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
79 struct qcom_scm_pas_metadata *ctx);
80 void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
81 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
83 extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
84 extern int qcom_scm_pas_shutdown(u32 peripheral);
85 extern bool qcom_scm_pas_supported(u32 peripheral);
87 extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
88 extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
90 extern bool qcom_scm_restore_sec_cfg_available(void);
91 extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
92 extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
93 extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
94 extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
95 extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
96 u32 cp_nonpixel_start,
97 u32 cp_nonpixel_size);
98 extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
100 const struct qcom_scm_vmperm *newvm,
101 unsigned int dest_cnt);
103 extern bool qcom_scm_ocmem_lock_available(void);
104 extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
106 extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
109 extern bool qcom_scm_ice_available(void);
110 extern int qcom_scm_ice_invalidate_key(u32 index);
111 extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
112 enum qcom_scm_ice_cipher cipher,
115 extern bool qcom_scm_hdcp_available(void);
116 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
119 extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
120 extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
122 extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
123 u64 limit_node, u32 node_id, u64 version);
124 extern int qcom_scm_lmh_profile_change(u32 profile_id);
125 extern bool qcom_scm_lmh_dcvsh_available(void);