1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_PGTABLE_H
3 #define _LINUX_PGTABLE_H
6 #include <asm/pgtable.h>
8 #define PMD_ORDER (PMD_SHIFT - PAGE_SHIFT)
9 #define PUD_ORDER (PUD_SHIFT - PAGE_SHIFT)
14 #include <linux/mm_types.h>
15 #include <linux/bug.h>
16 #include <linux/errno.h>
17 #include <asm-generic/pgtable_uffd.h>
18 #include <linux/page_table_check.h>
20 #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \
21 defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS
22 #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED
26 * On almost all architectures and configurations, 0 can be used as the
27 * upper ceiling to free_pgtables(): on many architectures it has the same
28 * effect as using TASK_SIZE. However, there is one configuration which
29 * must impose a more careful limit, to avoid freeing kernel pgtables.
31 #ifndef USER_PGTABLES_CEILING
32 #define USER_PGTABLES_CEILING 0UL
36 * This defines the first usable user address. Platforms
37 * can override its value with custom FIRST_USER_ADDRESS
38 * defined in their respective <asm/pgtable.h>.
40 #ifndef FIRST_USER_ADDRESS
41 #define FIRST_USER_ADDRESS 0UL
45 * This defines the generic helper for accessing PMD page
46 * table page. Although platforms can still override this
47 * via their respective <asm/pgtable.h>.
50 #define pmd_pgtable(pmd) pmd_page(pmd)
54 * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD]
56 * The pXx_index() functions return the index of the entry in the page
57 * table page which would control the given virtual address
59 * As these functions may be used by the same code for different levels of
60 * the page table folding, they are always available, regardless of
61 * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0
62 * because in such cases PTRS_PER_PxD equals 1.
65 static inline unsigned long pte_index(unsigned long address)
67 return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
71 static inline unsigned long pmd_index(unsigned long address)
73 return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
75 #define pmd_index pmd_index
79 static inline unsigned long pud_index(unsigned long address)
81 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
83 #define pud_index pud_index
87 /* Must be a compile-time constant, so implement it as a macro */
88 #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
91 #ifndef pte_offset_kernel
92 static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address)
94 return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address);
96 #define pte_offset_kernel pte_offset_kernel
100 #define __pte_map(pmd, address) \
101 ((pte_t *)kmap_local_page(pmd_page(*(pmd))) + pte_index((address)))
102 #define pte_unmap(pte) do { \
103 kunmap_local((pte)); \
107 static inline pte_t *__pte_map(pmd_t *pmd, unsigned long address)
109 return pte_offset_kernel(pmd, address);
111 static inline void pte_unmap(pte_t *pte)
117 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable);
119 /* Find an entry in the second-level page table.. */
121 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
123 return pud_pgtable(*pud) + pmd_index(address);
125 #define pmd_offset pmd_offset
129 static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address)
131 return p4d_pgtable(*p4d) + pud_index(address);
133 #define pud_offset pud_offset
136 static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address)
138 return (pgd + pgd_index(address));
142 * a shortcut to get a pgd_t in a given mm
145 #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address))
149 * a shortcut which implies the use of the kernel's pgd, instead
153 #define pgd_offset_k(address) pgd_offset(&init_mm, (address))
157 * In many cases it is known that a virtual address is mapped at PMD or PTE
158 * level, so instead of traversing all the page table levels, we can get a
159 * pointer to the PMD entry in user or kernel page table or translate a virtual
160 * address to the pointer in the PTE in the kernel page tables with simple
163 static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va)
165 return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va);
168 static inline pmd_t *pmd_off_k(unsigned long va)
170 return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va);
173 static inline pte_t *virt_to_kpte(unsigned long vaddr)
175 pmd_t *pmd = pmd_off_k(vaddr);
177 return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr);
181 static inline int pmd_young(pmd_t pmd)
188 * A facility to provide lazy MMU batching. This allows PTE updates and
189 * page invalidations to be delayed until a call to leave lazy MMU mode
190 * is issued. Some architectures may benefit from doing this, and it is
191 * beneficial for both shadow and direct mode hypervisors, which may batch
192 * the PTE updates which happen during this window. Note that using this
193 * interface requires that read hazards be removed from the code. A read
194 * hazard could result in the direct mode hypervisor case, since the actual
195 * write to the page tables may not yet have taken place, so reads though
196 * a raw PTE pointer after it has been modified are not guaranteed to be
197 * up to date. This mode can only be entered and left under the protection of
198 * the page table locks for all page tables which may be modified. In the UP
199 * case, this is required so that preemption is disabled, and in the SMP case,
200 * it must synchronize the delayed page table writes properly on other CPUs.
202 #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE
203 #define arch_enter_lazy_mmu_mode() do {} while (0)
204 #define arch_leave_lazy_mmu_mode() do {} while (0)
205 #define arch_flush_lazy_mmu_mode() do {} while (0)
211 static inline pte_t pte_next_pfn(pte_t pte)
213 return __pte(pte_val(pte) + (1UL << PFN_PTE_SHIFT));
218 * set_ptes - Map consecutive pages to a contiguous range of addresses.
219 * @mm: Address space to map the pages into.
220 * @addr: Address to map the first page at.
221 * @ptep: Page table pointer for the first entry.
222 * @pte: Page table entry for the first page.
223 * @nr: Number of pages to map.
225 * May be overridden by the architecture, or the architecture can define
226 * set_pte() and PFN_PTE_SHIFT.
228 * Context: The caller holds the page table lock. The pages all belong
229 * to the same folio. The PTEs are all in the same PMD.
231 static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
232 pte_t *ptep, pte_t pte, unsigned int nr)
234 page_table_check_ptes_set(mm, ptep, pte, nr);
236 arch_enter_lazy_mmu_mode();
242 pte = pte_next_pfn(pte);
244 arch_leave_lazy_mmu_mode();
247 #define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1)
249 #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
250 extern int ptep_set_access_flags(struct vm_area_struct *vma,
251 unsigned long address, pte_t *ptep,
252 pte_t entry, int dirty);
255 #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
256 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
257 extern int pmdp_set_access_flags(struct vm_area_struct *vma,
258 unsigned long address, pmd_t *pmdp,
259 pmd_t entry, int dirty);
260 extern int pudp_set_access_flags(struct vm_area_struct *vma,
261 unsigned long address, pud_t *pudp,
262 pud_t entry, int dirty);
264 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
265 unsigned long address, pmd_t *pmdp,
266 pmd_t entry, int dirty)
271 static inline int pudp_set_access_flags(struct vm_area_struct *vma,
272 unsigned long address, pud_t *pudp,
273 pud_t entry, int dirty)
278 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
282 static inline pte_t ptep_get(pte_t *ptep)
284 return READ_ONCE(*ptep);
289 static inline pmd_t pmdp_get(pmd_t *pmdp)
291 return READ_ONCE(*pmdp);
296 static inline pud_t pudp_get(pud_t *pudp)
298 return READ_ONCE(*pudp);
303 static inline p4d_t p4dp_get(p4d_t *p4dp)
305 return READ_ONCE(*p4dp);
310 static inline pgd_t pgdp_get(pgd_t *pgdp)
312 return READ_ONCE(*pgdp);
316 #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
317 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
318 unsigned long address,
321 pte_t pte = ptep_get(ptep);
326 set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte));
331 #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
332 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG)
333 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
334 unsigned long address,
342 set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd));
346 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
347 unsigned long address,
353 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */
356 #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
357 int ptep_clear_flush_young(struct vm_area_struct *vma,
358 unsigned long address, pte_t *ptep);
361 #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
362 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
363 extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
364 unsigned long address, pmd_t *pmdp);
367 * Despite relevant to THP only, this API is called from generic rmap code
368 * under PageTransHuge(), hence needs a dummy implementation for !THP
370 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma,
371 unsigned long address, pmd_t *pmdp)
376 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
379 #ifndef arch_has_hw_nonleaf_pmd_young
381 * Return whether the accessed bit in non-leaf PMD entries is supported on the
384 static inline bool arch_has_hw_nonleaf_pmd_young(void)
386 return IS_ENABLED(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG);
390 #ifndef arch_has_hw_pte_young
392 * Return whether the accessed bit is supported on the local CPU.
394 * This stub assumes accessing through an old PTE triggers a page fault.
395 * Architectures that automatically set the access bit should overwrite it.
397 static inline bool arch_has_hw_pte_young(void)
403 #ifndef arch_check_zapped_pte
404 static inline void arch_check_zapped_pte(struct vm_area_struct *vma,
410 #ifndef arch_check_zapped_pmd
411 static inline void arch_check_zapped_pmd(struct vm_area_struct *vma,
417 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR
418 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
419 unsigned long address,
422 pte_t pte = ptep_get(ptep);
423 pte_clear(mm, address, ptep);
424 page_table_check_pte_clear(mm, pte);
429 static inline void ptep_clear(struct mm_struct *mm, unsigned long addr,
432 ptep_get_and_clear(mm, addr, ptep);
435 #ifdef CONFIG_GUP_GET_PXX_LOW_HIGH
437 * For walking the pagetables without holding any locks. Some architectures
438 * (eg x86-32 PAE) cannot load the entries atomically without using expensive
439 * instructions. We are guaranteed that a PTE will only either go from not
440 * present to present, or present to not present -- it will not switch to a
441 * completely different present page without a TLB flush inbetween; which we
442 * are blocking by holding interrupts off.
444 * Setting ptes from not present to present goes:
446 * ptep->pte_high = h;
450 * And present to not present goes:
454 * ptep->pte_high = 0;
456 * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'.
457 * We load pte_high *after* loading pte_low, which ensures we don't see an older
458 * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't
459 * picked up a changed pte high. We might have gotten rubbish values from
460 * pte_low and pte_high, but we are guaranteed that pte_low will not have the
461 * present bit set *unless* it is 'l'. Because get_user_pages_fast() only
462 * operates on present ptes we're safe.
464 static inline pte_t ptep_get_lockless(pte_t *ptep)
469 pte.pte_low = ptep->pte_low;
471 pte.pte_high = ptep->pte_high;
473 } while (unlikely(pte.pte_low != ptep->pte_low));
477 #define ptep_get_lockless ptep_get_lockless
479 #if CONFIG_PGTABLE_LEVELS > 2
480 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp)
485 pmd.pmd_low = pmdp->pmd_low;
487 pmd.pmd_high = pmdp->pmd_high;
489 } while (unlikely(pmd.pmd_low != pmdp->pmd_low));
493 #define pmdp_get_lockless pmdp_get_lockless
494 #define pmdp_get_lockless_sync() tlb_remove_table_sync_one()
495 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
496 #endif /* CONFIG_GUP_GET_PXX_LOW_HIGH */
499 * We require that the PTE can be read atomically.
501 #ifndef ptep_get_lockless
502 static inline pte_t ptep_get_lockless(pte_t *ptep)
504 return ptep_get(ptep);
508 #ifndef pmdp_get_lockless
509 static inline pmd_t pmdp_get_lockless(pmd_t *pmdp)
511 return pmdp_get(pmdp);
513 static inline void pmdp_get_lockless_sync(void)
518 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
519 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
520 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
521 unsigned long address,
527 page_table_check_pmd_clear(mm, pmd);
531 #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */
532 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
533 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
534 unsigned long address,
540 page_table_check_pud_clear(mm, pud);
544 #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */
545 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
547 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
548 #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
549 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
550 unsigned long address, pmd_t *pmdp,
553 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
557 #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL
558 static inline pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma,
559 unsigned long address, pud_t *pudp,
562 return pudp_huge_get_and_clear(vma->vm_mm, address, pudp);
565 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
567 #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
568 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
569 unsigned long address, pte_t *ptep,
572 return ptep_get_and_clear(mm, address, ptep);
578 * If two threads concurrently fault at the same page, the thread that
579 * won the race updates the PTE and its local TLB/Cache. The other thread
580 * gives up, simply does nothing, and continues; on architectures where
581 * software can update TLB, local TLB can be updated here to avoid next page
582 * fault. This function updates TLB only, do nothing with cache or others.
583 * It is the difference with function update_mmu_cache.
585 #ifndef __HAVE_ARCH_UPDATE_MMU_TLB
586 static inline void update_mmu_tlb(struct vm_area_struct *vma,
587 unsigned long address, pte_t *ptep)
590 #define __HAVE_ARCH_UPDATE_MMU_TLB
594 * Some architectures may be able to avoid expensive synchronization
595 * primitives when modifications are made to PTE's which are already
596 * not present, or in the process of an address space destruction.
598 #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
599 static inline void pte_clear_not_present_full(struct mm_struct *mm,
600 unsigned long address,
604 pte_clear(mm, address, ptep);
608 #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
609 extern pte_t ptep_clear_flush(struct vm_area_struct *vma,
610 unsigned long address,
614 #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
615 extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
616 unsigned long address,
618 extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma,
619 unsigned long address,
624 static inline pte_t pte_mkwrite(pte_t pte, struct vm_area_struct *vma)
626 return pte_mkwrite_novma(pte);
630 #if defined(CONFIG_ARCH_WANT_PMD_MKWRITE) && !defined(pmd_mkwrite)
631 static inline pmd_t pmd_mkwrite(pmd_t pmd, struct vm_area_struct *vma)
633 return pmd_mkwrite_novma(pmd);
637 #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT
639 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
641 pte_t old_pte = ptep_get(ptep);
642 set_pte_at(mm, address, ptep, pte_wrprotect(old_pte));
647 * On some architectures hardware does not set page access bit when accessing
648 * memory page, it is responsibility of software setting this bit. It brings
649 * out extra page fault penalty to track page access bit. For optimization page
650 * access bit can be set during all page fault flow on these arches.
651 * To be differentiate with macro pte_mkyoung, this macro is used on platforms
652 * where software maintains page access bit.
654 #ifndef pte_sw_mkyoung
655 static inline pte_t pte_sw_mkyoung(pte_t pte)
659 #define pte_sw_mkyoung pte_sw_mkyoung
662 #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT
663 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
664 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
665 unsigned long address, pmd_t *pmdp)
667 pmd_t old_pmd = *pmdp;
668 set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd));
671 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
672 unsigned long address, pmd_t *pmdp)
676 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
678 #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT
679 #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
680 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
681 static inline void pudp_set_wrprotect(struct mm_struct *mm,
682 unsigned long address, pud_t *pudp)
684 pud_t old_pud = *pudp;
686 set_pud_at(mm, address, pudp, pud_wrprotect(old_pud));
689 static inline void pudp_set_wrprotect(struct mm_struct *mm,
690 unsigned long address, pud_t *pudp)
694 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
695 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */
698 #ifndef pmdp_collapse_flush
699 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
700 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
701 unsigned long address, pmd_t *pmdp);
703 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
704 unsigned long address,
710 #define pmdp_collapse_flush pmdp_collapse_flush
711 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
714 #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT
715 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
719 #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW
720 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
723 #ifndef arch_needs_pgtable_deposit
724 #define arch_needs_pgtable_deposit() (false)
727 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
729 * This is an implementation of pmdp_establish() that is only suitable for an
730 * architecture that doesn't have hardware dirty/accessed bits. In this case we
731 * can't race with CPU which sets these bits and non-atomic approach is fine.
733 static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma,
734 unsigned long address, pmd_t *pmdp, pmd_t pmd)
736 pmd_t old_pmd = *pmdp;
737 set_pmd_at(vma->vm_mm, address, pmdp, pmd);
742 #ifndef __HAVE_ARCH_PMDP_INVALIDATE
743 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
747 #ifndef __HAVE_ARCH_PMDP_INVALIDATE_AD
750 * pmdp_invalidate_ad() invalidates the PMD while changing a transparent
751 * hugepage mapping in the page tables. This function is similar to
752 * pmdp_invalidate(), but should only be used if the access and dirty bits would
753 * not be cleared by the software in the new PMD value. The function ensures
754 * that hardware changes of the access and dirty bits updates would not be lost.
756 * Doing so can allow in certain architectures to avoid a TLB flush in most
757 * cases. Yet, another TLB flush might be necessary later if the PMD update
758 * itself requires such flush (e.g., if protection was set to be stricter). Yet,
759 * even when a TLB flush is needed because of the update, the caller may be able
760 * to batch these TLB flushing operations, so fewer TLB flush operations are
763 extern pmd_t pmdp_invalidate_ad(struct vm_area_struct *vma,
764 unsigned long address, pmd_t *pmdp);
767 #ifndef __HAVE_ARCH_PTE_SAME
768 static inline int pte_same(pte_t pte_a, pte_t pte_b)
770 return pte_val(pte_a) == pte_val(pte_b);
774 #ifndef __HAVE_ARCH_PTE_UNUSED
776 * Some architectures provide facilities to virtualization guests
777 * so that they can flag allocated pages as unused. This allows the
778 * host to transparently reclaim unused pages. This function returns
779 * whether the pte's page is unused.
781 static inline int pte_unused(pte_t pte)
787 #ifndef pte_access_permitted
788 #define pte_access_permitted(pte, write) \
789 (pte_present(pte) && (!(write) || pte_write(pte)))
792 #ifndef pmd_access_permitted
793 #define pmd_access_permitted(pmd, write) \
794 (pmd_present(pmd) && (!(write) || pmd_write(pmd)))
797 #ifndef pud_access_permitted
798 #define pud_access_permitted(pud, write) \
799 (pud_present(pud) && (!(write) || pud_write(pud)))
802 #ifndef p4d_access_permitted
803 #define p4d_access_permitted(p4d, write) \
804 (p4d_present(p4d) && (!(write) || p4d_write(p4d)))
807 #ifndef pgd_access_permitted
808 #define pgd_access_permitted(pgd, write) \
809 (pgd_present(pgd) && (!(write) || pgd_write(pgd)))
812 #ifndef __HAVE_ARCH_PMD_SAME
813 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
815 return pmd_val(pmd_a) == pmd_val(pmd_b);
820 static inline int pud_same(pud_t pud_a, pud_t pud_b)
822 return pud_val(pud_a) == pud_val(pud_b);
824 #define pud_same pud_same
827 #ifndef __HAVE_ARCH_P4D_SAME
828 static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b)
830 return p4d_val(p4d_a) == p4d_val(p4d_b);
834 #ifndef __HAVE_ARCH_PGD_SAME
835 static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b)
837 return pgd_val(pgd_a) == pgd_val(pgd_b);
842 * Use set_p*_safe(), and elide TLB flushing, when confident that *no*
843 * TLB flush will be required as a result of the "set". For example, use
844 * in scenarios where it is known ahead of time that the routine is
845 * setting non-present entries, or re-setting an existing entry to the
846 * same value. Otherwise, use the typical "set" helpers and flush the
849 #define set_pte_safe(ptep, pte) \
851 WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \
852 set_pte(ptep, pte); \
855 #define set_pmd_safe(pmdp, pmd) \
857 WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \
858 set_pmd(pmdp, pmd); \
861 #define set_pud_safe(pudp, pud) \
863 WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \
864 set_pud(pudp, pud); \
867 #define set_p4d_safe(p4dp, p4d) \
869 WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \
870 set_p4d(p4dp, p4d); \
873 #define set_pgd_safe(pgdp, pgd) \
875 WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \
876 set_pgd(pgdp, pgd); \
879 #ifndef __HAVE_ARCH_DO_SWAP_PAGE
881 * Some architectures support metadata associated with a page. When a
882 * page is being swapped out, this metadata must be saved so it can be
883 * restored when the page is swapped back in. SPARC M7 and newer
884 * processors support an ADI (Application Data Integrity) tag for the
885 * page as metadata for the page. arch_do_swap_page() can restore this
886 * metadata when a page is swapped back in.
888 static inline void arch_do_swap_page(struct mm_struct *mm,
889 struct vm_area_struct *vma,
891 pte_t pte, pte_t oldpte)
897 #ifndef __HAVE_ARCH_UNMAP_ONE
899 * Some architectures support metadata associated with a page. When a
900 * page is being swapped out, this metadata must be saved so it can be
901 * restored when the page is swapped back in. SPARC M7 and newer
902 * processors support an ADI (Application Data Integrity) tag for the
903 * page as metadata for the page. arch_unmap_one() can save this
904 * metadata on a swap-out of a page.
906 static inline int arch_unmap_one(struct mm_struct *mm,
907 struct vm_area_struct *vma,
916 * Allow architectures to preserve additional metadata associated with
917 * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function
918 * prototypes must be defined in the arch-specific asm/pgtable.h file.
920 #ifndef __HAVE_ARCH_PREPARE_TO_SWAP
921 static inline int arch_prepare_to_swap(struct page *page)
927 #ifndef __HAVE_ARCH_SWAP_INVALIDATE
928 static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
932 static inline void arch_swap_invalidate_area(int type)
937 #ifndef __HAVE_ARCH_SWAP_RESTORE
938 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio)
943 #ifndef __HAVE_ARCH_PGD_OFFSET_GATE
944 #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr)
947 #ifndef __HAVE_ARCH_MOVE_PTE
948 #define move_pte(pte, prot, old_addr, new_addr) (pte)
951 #ifndef pte_accessible
952 # define pte_accessible(mm, pte) ((void)(pte), 1)
955 #ifndef flush_tlb_fix_spurious_fault
956 #define flush_tlb_fix_spurious_fault(vma, address, ptep) flush_tlb_page(vma, address)
960 * When walking page tables, get the address of the next boundary,
961 * or the end address of the range if that comes earlier. Although no
962 * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout.
965 #define pgd_addr_end(addr, end) \
966 ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
967 (__boundary - 1 < (end) - 1)? __boundary: (end); \
971 #define p4d_addr_end(addr, end) \
972 ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \
973 (__boundary - 1 < (end) - 1)? __boundary: (end); \
978 #define pud_addr_end(addr, end) \
979 ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \
980 (__boundary - 1 < (end) - 1)? __boundary: (end); \
985 #define pmd_addr_end(addr, end) \
986 ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
987 (__boundary - 1 < (end) - 1)? __boundary: (end); \
992 * When walking page tables, we usually want to skip any p?d_none entries;
993 * and any p?d_bad entries - reporting the error before resetting to none.
994 * Do the tests inline, but report and clear the bad entry in mm/memory.c.
996 void pgd_clear_bad(pgd_t *);
998 #ifndef __PAGETABLE_P4D_FOLDED
999 void p4d_clear_bad(p4d_t *);
1001 #define p4d_clear_bad(p4d) do { } while (0)
1004 #ifndef __PAGETABLE_PUD_FOLDED
1005 void pud_clear_bad(pud_t *);
1007 #define pud_clear_bad(p4d) do { } while (0)
1010 void pmd_clear_bad(pmd_t *);
1012 static inline int pgd_none_or_clear_bad(pgd_t *pgd)
1016 if (unlikely(pgd_bad(*pgd))) {
1023 static inline int p4d_none_or_clear_bad(p4d_t *p4d)
1027 if (unlikely(p4d_bad(*p4d))) {
1034 static inline int pud_none_or_clear_bad(pud_t *pud)
1038 if (unlikely(pud_bad(*pud))) {
1045 static inline int pmd_none_or_clear_bad(pmd_t *pmd)
1049 if (unlikely(pmd_bad(*pmd))) {
1056 static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma,
1061 * Get the current pte state, but zero it out to make it
1062 * non-present, preventing the hardware from asynchronously
1065 return ptep_get_and_clear(vma->vm_mm, addr, ptep);
1068 static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma,
1070 pte_t *ptep, pte_t pte)
1073 * The pte is non-present, so there's no hardware state to
1076 set_pte_at(vma->vm_mm, addr, ptep, pte);
1079 #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1081 * Start a pte protection read-modify-write transaction, which
1082 * protects against asynchronous hardware modifications to the pte.
1083 * The intention is not to prevent the hardware from making pte
1084 * updates, but to prevent any updates it may make from being lost.
1086 * This does not protect against other software modifications of the
1087 * pte; the appropriate pte lock must be held over the transaction.
1089 * Note that this interface is intended to be batchable, meaning that
1090 * ptep_modify_prot_commit may not actually update the pte, but merely
1091 * queue the update to be done at some later time. The update must be
1092 * actually committed before the pte lock is released, however.
1094 static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma,
1098 return __ptep_modify_prot_start(vma, addr, ptep);
1102 * Commit an update to a pte, leaving any hardware-controlled bits in
1103 * the PTE unmodified.
1105 static inline void ptep_modify_prot_commit(struct vm_area_struct *vma,
1107 pte_t *ptep, pte_t old_pte, pte_t pte)
1109 __ptep_modify_prot_commit(vma, addr, ptep, pte);
1111 #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */
1112 #endif /* CONFIG_MMU */
1115 * No-op macros that just return the current protection value. Defined here
1116 * because these macros can be used even if CONFIG_MMU is not defined.
1120 #define pgprot_nx(prot) (prot)
1123 #ifndef pgprot_noncached
1124 #define pgprot_noncached(prot) (prot)
1127 #ifndef pgprot_writecombine
1128 #define pgprot_writecombine pgprot_noncached
1131 #ifndef pgprot_writethrough
1132 #define pgprot_writethrough pgprot_noncached
1135 #ifndef pgprot_device
1136 #define pgprot_device pgprot_noncached
1140 #define pgprot_mhp(prot) (prot)
1144 #ifndef pgprot_modify
1145 #define pgprot_modify pgprot_modify
1146 static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
1148 if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot)))
1149 newprot = pgprot_noncached(newprot);
1150 if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot)))
1151 newprot = pgprot_writecombine(newprot);
1152 if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot)))
1153 newprot = pgprot_device(newprot);
1157 #endif /* CONFIG_MMU */
1159 #ifndef pgprot_encrypted
1160 #define pgprot_encrypted(prot) (prot)
1163 #ifndef pgprot_decrypted
1164 #define pgprot_decrypted(prot) (prot)
1168 * A facility to provide batching of the reload of page tables and
1169 * other process state with the actual context switch code for
1170 * paravirtualized guests. By convention, only one of the batched
1171 * update (lazy) modes (CPU, MMU) should be active at any given time,
1172 * entry should never be nested, and entry and exits should always be
1173 * paired. This is for sanity of maintaining and reasoning about the
1174 * kernel code. In this case, the exit (end of the context switch) is
1175 * in architecture-specific code, and so doesn't need a generic
1178 #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH
1179 #define arch_start_context_switch(prev) do {} while (0)
1182 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1183 #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION
1184 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
1189 static inline int pmd_swp_soft_dirty(pmd_t pmd)
1194 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
1199 #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */
1200 static inline int pte_soft_dirty(pte_t pte)
1205 static inline int pmd_soft_dirty(pmd_t pmd)
1210 static inline pte_t pte_mksoft_dirty(pte_t pte)
1215 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
1220 static inline pte_t pte_clear_soft_dirty(pte_t pte)
1225 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
1230 static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
1235 static inline int pte_swp_soft_dirty(pte_t pte)
1240 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
1245 static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd)
1250 static inline int pmd_swp_soft_dirty(pmd_t pmd)
1255 static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd)
1261 #ifndef __HAVE_PFNMAP_TRACKING
1263 * Interfaces that can be used by architecture code to keep track of
1264 * memory type of pfn mappings specified by the remap_pfn_range,
1269 * track_pfn_remap is called when a _new_ pfn mapping is being established
1270 * by remap_pfn_range() for physical range indicated by pfn and size.
1272 static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
1273 unsigned long pfn, unsigned long addr,
1280 * track_pfn_insert is called when a _new_ single pfn is established
1281 * by vmf_insert_pfn().
1283 static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
1289 * track_pfn_copy is called when vma that is covering the pfnmap gets
1290 * copied through copy_page_range().
1292 static inline int track_pfn_copy(struct vm_area_struct *vma)
1298 * untrack_pfn is called while unmapping a pfnmap for a region.
1299 * untrack can be called for a specific region indicated by pfn and size or
1300 * can be for the entire vma (in which case pfn, size are zero).
1302 static inline void untrack_pfn(struct vm_area_struct *vma,
1303 unsigned long pfn, unsigned long size,
1309 * untrack_pfn_clear is called while mremapping a pfnmap for a new region
1310 * or fails to copy pgtable during duplicate vm area.
1312 static inline void untrack_pfn_clear(struct vm_area_struct *vma)
1316 extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot,
1317 unsigned long pfn, unsigned long addr,
1318 unsigned long size);
1319 extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot,
1321 extern int track_pfn_copy(struct vm_area_struct *vma);
1322 extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn,
1323 unsigned long size, bool mm_wr_locked);
1324 extern void untrack_pfn_clear(struct vm_area_struct *vma);
1328 #ifdef __HAVE_COLOR_ZERO_PAGE
1329 static inline int is_zero_pfn(unsigned long pfn)
1331 extern unsigned long zero_pfn;
1332 unsigned long offset_from_zero_pfn = pfn - zero_pfn;
1333 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
1336 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
1339 static inline int is_zero_pfn(unsigned long pfn)
1341 extern unsigned long zero_pfn;
1342 return pfn == zero_pfn;
1345 static inline unsigned long my_zero_pfn(unsigned long addr)
1347 extern unsigned long zero_pfn;
1352 static inline int is_zero_pfn(unsigned long pfn)
1357 static inline unsigned long my_zero_pfn(unsigned long addr)
1361 #endif /* CONFIG_MMU */
1365 #ifndef CONFIG_TRANSPARENT_HUGEPAGE
1366 static inline int pmd_trans_huge(pmd_t pmd)
1371 static inline int pmd_write(pmd_t pmd)
1376 #endif /* pmd_write */
1377 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1380 static inline int pud_write(pud_t pud)
1385 #endif /* pud_write */
1387 #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE)
1388 static inline int pmd_devmap(pmd_t pmd)
1392 static inline int pud_devmap(pud_t pud)
1396 static inline int pgd_devmap(pgd_t pgd)
1402 #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \
1403 !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
1404 static inline int pud_trans_huge(pud_t pud)
1410 static inline int pud_trans_unstable(pud_t *pud)
1412 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
1413 defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
1414 pud_t pudval = READ_ONCE(*pud);
1416 if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval))
1418 if (unlikely(pud_bad(pudval))) {
1426 #ifndef CONFIG_NUMA_BALANCING
1428 * In an inaccessible (PROT_NONE) VMA, pte_protnone() may indicate "yes". It is
1429 * perfectly valid to indicate "no" in that case, which is why our default
1430 * implementation defaults to "always no".
1432 * In an accessible VMA, however, pte_protnone() reliably indicates PROT_NONE
1433 * page protection due to NUMA hinting. NUMA hinting faults only apply in
1436 * So, to reliably identify PROT_NONE PTEs that require a NUMA hinting fault,
1437 * looking at the VMA accessibility is sufficient.
1439 static inline int pte_protnone(pte_t pte)
1444 static inline int pmd_protnone(pmd_t pmd)
1448 #endif /* CONFIG_NUMA_BALANCING */
1450 #endif /* CONFIG_MMU */
1452 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
1454 #ifndef __PAGETABLE_P4D_FOLDED
1455 int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot);
1456 void p4d_clear_huge(p4d_t *p4d);
1458 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
1462 static inline void p4d_clear_huge(p4d_t *p4d) { }
1463 #endif /* !__PAGETABLE_P4D_FOLDED */
1465 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);
1466 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
1467 int pud_clear_huge(pud_t *pud);
1468 int pmd_clear_huge(pmd_t *pmd);
1469 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr);
1470 int pud_free_pmd_page(pud_t *pud, unsigned long addr);
1471 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr);
1472 #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */
1473 static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
1477 static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
1481 static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
1485 static inline void p4d_clear_huge(p4d_t *p4d) { }
1486 static inline int pud_clear_huge(pud_t *pud)
1490 static inline int pmd_clear_huge(pmd_t *pmd)
1494 static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr)
1498 static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr)
1502 static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
1506 #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
1508 #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
1509 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1511 * ARCHes with special requirements for evicting THP backing TLB entries can
1512 * implement this. Otherwise also, it can help optimize normal TLB flush in
1513 * THP regime. Stock flush_tlb_range() typically has optimization to nuke the
1514 * entire TLB if flush span is greater than a threshold, which will
1515 * likely be true for a single huge page. Thus a single THP flush will
1516 * invalidate the entire TLB which is not desirable.
1517 * e.g. see arch/arc: flush_pmd_tlb_range
1519 #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
1520 #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end)
1522 #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG()
1523 #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG()
1528 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
1529 unsigned long size, pgprot_t *vma_prot);
1531 #ifndef CONFIG_X86_ESPFIX64
1532 static inline void init_espfix_bsp(void) { }
1535 extern void __init pgtable_cache_init(void);
1537 #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED
1538 static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot)
1543 static inline bool arch_has_pfn_modify_check(void)
1547 #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */
1550 * Architecture PAGE_KERNEL_* fallbacks
1552 * Some architectures don't define certain PAGE_KERNEL_* flags. This is either
1553 * because they really don't support them, or the port needs to be updated to
1554 * reflect the required functionality. Below are a set of relatively safe
1555 * fallbacks, as best effort, which we can count on in lieu of the architectures
1556 * not defining them on their own yet.
1559 #ifndef PAGE_KERNEL_RO
1560 # define PAGE_KERNEL_RO PAGE_KERNEL
1563 #ifndef PAGE_KERNEL_EXEC
1564 # define PAGE_KERNEL_EXEC PAGE_KERNEL
1568 * Page Table Modification bits for pgtbl_mod_mask.
1570 * These are used by the p?d_alloc_track*() set of functions an in the generic
1571 * vmalloc/ioremap code to track at which page-table levels entries have been
1572 * modified. Based on that the code can better decide when vmalloc and ioremap
1573 * mapping changes need to be synchronized to other page-tables in the system.
1575 #define __PGTBL_PGD_MODIFIED 0
1576 #define __PGTBL_P4D_MODIFIED 1
1577 #define __PGTBL_PUD_MODIFIED 2
1578 #define __PGTBL_PMD_MODIFIED 3
1579 #define __PGTBL_PTE_MODIFIED 4
1581 #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED)
1582 #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED)
1583 #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED)
1584 #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED)
1585 #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED)
1587 /* Page-Table Modification Mask */
1588 typedef unsigned int pgtbl_mod_mask;
1590 #endif /* !__ASSEMBLY__ */
1592 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT)
1593 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1595 * ZSMALLOC needs to know the highest PFN on 32-bit architectures
1596 * with physical address space extension, but falls back to
1597 * BITS_PER_LONG otherwise.
1599 #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition
1601 #define MAX_POSSIBLE_PHYSMEM_BITS 32
1605 #ifndef has_transparent_hugepage
1606 #define has_transparent_hugepage() IS_BUILTIN(CONFIG_TRANSPARENT_HUGEPAGE)
1609 #ifndef has_transparent_pud_hugepage
1610 #define has_transparent_pud_hugepage() IS_BUILTIN(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
1613 * On some architectures it depends on the mm if the p4d/pud or pmd
1614 * layer of the page table hierarchy is folded or not.
1616 #ifndef mm_p4d_folded
1617 #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED)
1620 #ifndef mm_pud_folded
1621 #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED)
1624 #ifndef mm_pmd_folded
1625 #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED)
1628 #ifndef p4d_offset_lockless
1629 #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address)
1631 #ifndef pud_offset_lockless
1632 #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address)
1634 #ifndef pmd_offset_lockless
1635 #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address)
1639 * p?d_leaf() - true if this entry is a final mapping to a physical address.
1640 * This differs from p?d_huge() by the fact that they are always available (if
1641 * the architecture supports large pages at the appropriate level) even
1642 * if CONFIG_HUGETLB_PAGE is not defined.
1643 * Only meaningful when called on a valid entry.
1646 #define pgd_leaf(x) 0
1649 #define p4d_leaf(x) 0
1652 #define pud_leaf(x) 0
1655 #define pmd_leaf(x) 0
1658 #ifndef pgd_leaf_size
1659 #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT)
1661 #ifndef p4d_leaf_size
1662 #define p4d_leaf_size(x) P4D_SIZE
1664 #ifndef pud_leaf_size
1665 #define pud_leaf_size(x) PUD_SIZE
1667 #ifndef pmd_leaf_size
1668 #define pmd_leaf_size(x) PMD_SIZE
1670 #ifndef pte_leaf_size
1671 #define pte_leaf_size(x) PAGE_SIZE
1675 * Some architectures have MMUs that are configurable or selectable at boot
1676 * time. These lead to variable PTRS_PER_x. For statically allocated arrays it
1677 * helps to have a static maximum value.
1680 #ifndef MAX_PTRS_PER_PTE
1681 #define MAX_PTRS_PER_PTE PTRS_PER_PTE
1684 #ifndef MAX_PTRS_PER_PMD
1685 #define MAX_PTRS_PER_PMD PTRS_PER_PMD
1688 #ifndef MAX_PTRS_PER_PUD
1689 #define MAX_PTRS_PER_PUD PTRS_PER_PUD
1692 #ifndef MAX_PTRS_PER_P4D
1693 #define MAX_PTRS_PER_P4D PTRS_PER_P4D
1696 /* description of effects of mapping type and prot in current implementation.
1697 * this is due to the limited x86 page protection hardware. The expected
1698 * behavior is in parens:
1701 * PROT_NONE PROT_READ PROT_WRITE PROT_EXEC
1702 * MAP_SHARED r: (no) no r: (yes) yes r: (no) yes r: (no) yes
1703 * w: (no) no w: (no) no w: (yes) yes w: (no) no
1704 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes
1706 * MAP_PRIVATE r: (no) no r: (yes) yes r: (no) yes r: (no) yes
1707 * w: (no) no w: (no) no w: (copy) copy w: (no) no
1708 * x: (no) no x: (no) yes x: (no) yes x: (yes) yes
1710 * On arm64, PROT_EXEC has the following behaviour for both MAP_SHARED and
1711 * MAP_PRIVATE (with Enhanced PAN supported):
1716 #define DECLARE_VM_GET_PAGE_PROT \
1717 pgprot_t vm_get_page_prot(unsigned long vm_flags) \
1719 return protection_map[vm_flags & \
1720 (VM_READ | VM_WRITE | VM_EXEC | VM_SHARED)]; \
1722 EXPORT_SYMBOL(vm_get_page_prot);
1724 #endif /* _LINUX_PGTABLE_H */