1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
43 #include <linux/pci_ids.h>
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
53 * The PCI interface treats multi-function devices as independent
54 * devices. The slot/function address of each device is encoded
55 * in a single byte as follows:
60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
61 * In the interest of not exposing interfaces to user-space unnecessarily,
62 * the following kernel-only defines are being added here.
64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
68 /* pci_slot represents a physical slot */
70 struct pci_bus *bus; /* Bus this slot is on */
71 struct list_head list; /* Node in list of slots */
72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
77 static inline const char *pci_slot_name(const struct pci_slot *slot)
79 return kobject_name(&slot->kobj);
82 /* File state for mmap()s on /proc/bus/pci/X/Y */
88 /* For PCI devices, the region numbers are assigned this way: */
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
94 /* #6: expansion ROM resource */
97 /* Device-specific resources */
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
103 /* Resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
110 /* Total resources associated with a PCI device */
113 /* Preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
118 * enum pci_interrupt_pin - PCI INTx interrupt values
119 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
120 * @PCI_INTERRUPT_INTA: PCI INTA pin
121 * @PCI_INTERRUPT_INTB: PCI INTB pin
122 * @PCI_INTERRUPT_INTC: PCI INTC pin
123 * @PCI_INTERRUPT_INTD: PCI INTD pin
125 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
126 * PCI_INTERRUPT_PIN register.
128 enum pci_interrupt_pin {
129 PCI_INTERRUPT_UNKNOWN,
136 /* The number of legacy PCI INTx interrupts */
137 #define PCI_NUM_INTX 4
140 * pci_power_t values must match the bits in the Capabilities PME_Support
141 * and Control/Status PowerState fields in the Power Management capability.
143 typedef int __bitwise pci_power_t;
145 #define PCI_D0 ((pci_power_t __force) 0)
146 #define PCI_D1 ((pci_power_t __force) 1)
147 #define PCI_D2 ((pci_power_t __force) 2)
148 #define PCI_D3hot ((pci_power_t __force) 3)
149 #define PCI_D3cold ((pci_power_t __force) 4)
150 #define PCI_UNKNOWN ((pci_power_t __force) 5)
151 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
153 /* Remember to update this when the list above changes! */
154 extern const char *pci_power_names[];
156 static inline const char *pci_power_name(pci_power_t state)
158 return pci_power_names[1 + (__force int) state];
162 * typedef pci_channel_state_t
164 * The pci_channel state describes connectivity between the CPU and
165 * the PCI device. If some PCI bus between here and the PCI device
166 * has crashed or locked up, this info is reflected here.
168 typedef unsigned int __bitwise pci_channel_state_t;
170 enum pci_channel_state {
171 /* I/O channel is in normal state */
172 pci_channel_io_normal = (__force pci_channel_state_t) 1,
174 /* I/O to channel is blocked */
175 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
177 /* PCI card is dead */
178 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
181 typedef unsigned int __bitwise pcie_reset_state_t;
183 enum pcie_reset_state {
184 /* Reset is NOT asserted (Use to deassert reset) */
185 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
187 /* Use #PERST to reset PCIe device */
188 pcie_warm_reset = (__force pcie_reset_state_t) 2,
190 /* Use PCIe Hot Reset to reset device */
191 pcie_hot_reset = (__force pcie_reset_state_t) 3
194 typedef unsigned short __bitwise pci_dev_flags_t;
196 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
197 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
198 /* Device configuration is irrevocably lost if disabled into D3 */
199 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
200 /* Provide indication device is assigned by a Virtual Machine Manager */
201 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
202 /* Flag for quirk use to store if quirk-specific ACS is enabled */
203 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
204 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
205 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
206 /* Do not use bus resets for device */
207 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
208 /* Do not use PM reset even if device advertises NoSoftRst- */
209 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
210 /* Get VPD from function 0 VPD */
211 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
212 /* A non-root bridge where translation occurs, stop alias search here */
213 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
214 /* Do not use FLR even if device advertises PCI_AF_CAP */
215 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
216 /* Don't use Relaxed Ordering for TLPs directed at this device */
217 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
220 enum pci_irq_reroute_variant {
221 INTEL_IRQ_REROUTE_VARIANT = 1,
222 MAX_IRQ_REROUTE_VARIANTS = 3
225 typedef unsigned short __bitwise pci_bus_flags_t;
227 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
228 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
229 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
230 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
233 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
234 enum pcie_link_width {
235 PCIE_LNK_WIDTH_RESRV = 0x00,
243 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
246 /* See matching string table in pci_speed_string() */
248 PCI_SPEED_33MHz = 0x00,
249 PCI_SPEED_66MHz = 0x01,
250 PCI_SPEED_66MHz_PCIX = 0x02,
251 PCI_SPEED_100MHz_PCIX = 0x03,
252 PCI_SPEED_133MHz_PCIX = 0x04,
253 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
254 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
255 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
256 PCI_SPEED_66MHz_PCIX_266 = 0x09,
257 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
258 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
264 PCI_SPEED_66MHz_PCIX_533 = 0x11,
265 PCI_SPEED_100MHz_PCIX_533 = 0x12,
266 PCI_SPEED_133MHz_PCIX_533 = 0x13,
267 PCIE_SPEED_2_5GT = 0x14,
268 PCIE_SPEED_5_0GT = 0x15,
269 PCIE_SPEED_8_0GT = 0x16,
270 PCIE_SPEED_16_0GT = 0x17,
271 PCIE_SPEED_32_0GT = 0x18,
272 PCI_SPEED_UNKNOWN = 0xff,
275 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
276 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
278 struct pci_cap_saved_data {
285 struct pci_cap_saved_state {
286 struct hlist_node next;
287 struct pci_cap_saved_data cap;
291 struct pcie_link_state;
296 /* The pci_dev structure describes PCI devices */
298 struct list_head bus_list; /* Node in per-bus list */
299 struct pci_bus *bus; /* Bus this device is on */
300 struct pci_bus *subordinate; /* Bus this device bridges to */
302 void *sysdata; /* Hook for sys-specific extension */
303 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
304 struct pci_slot *slot; /* Physical slot this device is in */
306 unsigned int devfn; /* Encoded device & function index */
307 unsigned short vendor;
308 unsigned short device;
309 unsigned short subsystem_vendor;
310 unsigned short subsystem_device;
311 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
312 u8 revision; /* PCI revision, low byte of class word */
313 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
314 #ifdef CONFIG_PCIEAER
315 u16 aer_cap; /* AER capability offset */
316 struct aer_stats *aer_stats; /* AER stats for this device */
318 u8 pcie_cap; /* PCIe capability offset */
319 u8 msi_cap; /* MSI capability offset */
320 u8 msix_cap; /* MSI-X capability offset */
321 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
322 u8 rom_base_reg; /* Config register controlling ROM */
323 u8 pin; /* Interrupt pin this device uses */
324 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
325 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
327 struct pci_driver *driver; /* Driver bound to this device */
328 u64 dma_mask; /* Mask of the bits of bus address this
329 device implements. Normally this is
330 0xffffffff. You only need to change
331 this if your device has broken DMA
332 or supports 64-bit transfers. */
334 struct device_dma_parameters dma_parms;
336 pci_power_t current_state; /* Current operating state. In ACPI,
337 this is D0-D3, D0 being fully
338 functional, and D3 being off. */
339 unsigned int imm_ready:1; /* Supports Immediate Readiness */
340 u8 pm_cap; /* PM capability offset */
341 unsigned int pme_support:5; /* Bitmask of states from which PME#
343 unsigned int pme_poll:1; /* Poll device's PME status bit */
344 unsigned int d1_support:1; /* Low power state D1 is supported */
345 unsigned int d2_support:1; /* Low power state D2 is supported */
346 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
347 unsigned int no_d3cold:1; /* D3cold is forbidden */
348 unsigned int bridge_d3:1; /* Allow D3 for bridge */
349 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
350 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
351 decoding during BAR sizing */
352 unsigned int wakeup_prepared:1;
353 unsigned int runtime_d3cold:1; /* Whether go through runtime
354 D3cold, not set for devices
355 powered on/off by the
356 corresponding bridge */
357 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
358 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
359 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
360 controlled exclusively by
362 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
364 unsigned int d3_delay; /* D3->D0 transition time in ms */
365 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
367 #ifdef CONFIG_PCIEASPM
368 struct pcie_link_state *link_state; /* ASPM link state */
369 unsigned int ltr_path:1; /* Latency Tolerance Reporting
370 supported from root to here */
372 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
374 pci_channel_state_t error_state; /* Current connectivity state */
375 struct device dev; /* Generic device interface */
377 int cfg_size; /* Size of config space */
380 * Instead of touching interrupt line and base address registers
381 * directly, use the values stored here. They might be different!
384 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
386 bool match_driver; /* Skip attaching driver */
388 unsigned int transparent:1; /* Subtractive decode bridge */
389 unsigned int io_window:1; /* Bridge has I/O window */
390 unsigned int pref_window:1; /* Bridge has pref mem window */
391 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
392 unsigned int multifunction:1; /* Multi-function device */
394 unsigned int is_busmaster:1; /* Is busmaster */
395 unsigned int no_msi:1; /* May not use MSI */
396 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
397 unsigned int block_cfg_access:1; /* Config space access blocked */
398 unsigned int broken_parity_status:1; /* Generates false positive parity */
399 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
400 unsigned int msi_enabled:1;
401 unsigned int msix_enabled:1;
402 unsigned int ari_enabled:1; /* ARI forwarding */
403 unsigned int ats_enabled:1; /* Address Translation Svc */
404 unsigned int pasid_enabled:1; /* Process Address Space ID */
405 unsigned int pri_enabled:1; /* Page Request Interface */
406 unsigned int is_managed:1;
407 unsigned int needs_freset:1; /* Requires fundamental reset */
408 unsigned int state_saved:1;
409 unsigned int is_physfn:1;
410 unsigned int is_virtfn:1;
411 unsigned int reset_fn:1;
412 unsigned int is_hotplug_bridge:1;
413 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
414 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
416 * Devices marked being untrusted are the ones that can potentially
417 * execute DMA attacks and similar. They are typically connected
418 * through external ports such as Thunderbolt but not limited to
419 * that. When an IOMMU is enabled they should be getting full
420 * mappings to make sure they cannot access arbitrary memory.
422 unsigned int untrusted:1;
423 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
424 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
425 unsigned int irq_managed:1;
426 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
427 unsigned int is_probed:1; /* Device probing in progress */
428 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
429 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
430 pci_dev_flags_t dev_flags;
431 atomic_t enable_cnt; /* pci_enable_device has been called */
433 u32 saved_config_space[16]; /* Config space saved at suspend time */
434 struct hlist_head saved_cap_space;
435 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
436 int rom_attr_enabled; /* Display of ROM attribute enabled? */
437 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
438 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
440 #ifdef CONFIG_HOTPLUG_PCI_PCIE
441 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
443 #ifdef CONFIG_PCIE_PTM
444 unsigned int ptm_root:1;
445 unsigned int ptm_enabled:1;
448 #ifdef CONFIG_PCI_MSI
449 const struct attribute_group **msi_irq_groups;
452 #ifdef CONFIG_PCIE_DPC
454 unsigned int dpc_rp_extensions:1;
457 #ifdef CONFIG_PCI_ATS
459 struct pci_sriov *sriov; /* PF: SR-IOV info */
460 struct pci_dev *physfn; /* VF: related PF */
462 u16 ats_cap; /* ATS Capability offset */
463 u8 ats_stu; /* ATS Smallest Translation Unit */
465 #ifdef CONFIG_PCI_PRI
466 u16 pri_cap; /* PRI Capability offset */
467 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
468 unsigned int pasid_required:1; /* PRG Response PASID Required */
470 #ifdef CONFIG_PCI_PASID
471 u16 pasid_cap; /* PASID Capability offset */
474 #ifdef CONFIG_PCI_P2PDMA
475 struct pci_p2pdma *p2pdma;
477 phys_addr_t rom; /* Physical address if not from BAR */
478 size_t romlen; /* Length if not from BAR */
479 char *driver_override; /* Driver name to force a match */
481 unsigned long priv_flags; /* Private flags for the PCI driver */
484 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
486 #ifdef CONFIG_PCI_IOV
493 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
495 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
496 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
498 static inline int pci_channel_offline(struct pci_dev *pdev)
500 return (pdev->error_state != pci_channel_io_normal);
503 struct pci_host_bridge {
505 struct pci_bus *bus; /* Root bus */
509 struct list_head windows; /* resource_entry */
510 struct list_head dma_ranges; /* dma ranges resource list */
511 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
512 int (*map_irq)(const struct pci_dev *, u8, u8);
513 void (*release_fn)(struct pci_host_bridge *);
515 struct msi_controller *msi;
516 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
517 unsigned int no_ext_tags:1; /* No Extended Tags */
518 unsigned int native_aer:1; /* OS may use PCIe AER */
519 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
520 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
521 unsigned int native_pme:1; /* OS may use PCIe PME */
522 unsigned int native_ltr:1; /* OS may use PCIe LTR */
523 unsigned int native_dpc:1; /* OS may use PCIe DPC */
524 unsigned int preserve_config:1; /* Preserve FW resource setup */
525 unsigned int size_windows:1; /* Enable root bus sizing */
527 /* Resource alignment requirements */
528 resource_size_t (*align_resource)(struct pci_dev *dev,
529 const struct resource *res,
530 resource_size_t start,
531 resource_size_t size,
532 resource_size_t align);
533 unsigned long private[0] ____cacheline_aligned;
536 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
538 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
540 return (void *)bridge->private;
543 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
545 return container_of(priv, struct pci_host_bridge, private);
548 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
549 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
551 void pci_free_host_bridge(struct pci_host_bridge *bridge);
552 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
554 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
555 void (*release_fn)(struct pci_host_bridge *),
558 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
561 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
562 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
563 * buses below host bridges or subtractive decode bridges) go in the list.
564 * Use pci_bus_for_each_resource() to iterate through all the resources.
568 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
569 * and there's no way to program the bridge with the details of the window.
570 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
571 * decode bit set, because they are explicit and can be programmed with _SRS.
573 #define PCI_SUBTRACTIVE_DECODE 0x1
575 struct pci_bus_resource {
576 struct list_head list;
577 struct resource *res;
581 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
584 struct list_head node; /* Node in list of buses */
585 struct pci_bus *parent; /* Parent bus this bridge is on */
586 struct list_head children; /* List of child buses */
587 struct list_head devices; /* List of devices on this bus */
588 struct pci_dev *self; /* Bridge device as seen by parent */
589 struct list_head slots; /* List of slots on this bus;
590 protected by pci_slot_mutex */
591 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
592 struct list_head resources; /* Address space routed to this bus */
593 struct resource busn_res; /* Bus numbers routed to this bus */
595 struct pci_ops *ops; /* Configuration access functions */
596 struct msi_controller *msi; /* MSI controller */
597 void *sysdata; /* Hook for sys-specific extension */
598 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
600 unsigned char number; /* Bus number */
601 unsigned char primary; /* Number of primary bridge */
602 unsigned char max_bus_speed; /* enum pci_bus_speed */
603 unsigned char cur_bus_speed; /* enum pci_bus_speed */
604 #ifdef CONFIG_PCI_DOMAINS_GENERIC
610 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
611 pci_bus_flags_t bus_flags; /* Inherited by child buses */
612 struct device *bridge;
614 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
615 struct bin_attribute *legacy_mem; /* Legacy mem */
616 unsigned int is_added:1;
619 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
621 static inline u16 pci_dev_id(struct pci_dev *dev)
623 return PCI_DEVID(dev->bus->number, dev->devfn);
627 * Returns true if the PCI bus is root (behind host-PCI bridge),
630 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
631 * This is incorrect because "virtual" buses added for SR-IOV (via
632 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
634 static inline bool pci_is_root_bus(struct pci_bus *pbus)
636 return !(pbus->parent);
640 * pci_is_bridge - check if the PCI device is a bridge
643 * Return true if the PCI device is bridge whether it has subordinate
646 static inline bool pci_is_bridge(struct pci_dev *dev)
648 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
649 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
652 #define for_each_pci_bridge(dev, bus) \
653 list_for_each_entry(dev, &bus->devices, bus_list) \
654 if (!pci_is_bridge(dev)) {} else
656 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
658 dev = pci_physfn(dev);
659 if (pci_is_root_bus(dev->bus))
662 return dev->bus->self;
665 #ifdef CONFIG_PCI_MSI
666 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
668 return pci_dev->msi_enabled || pci_dev->msix_enabled;
671 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
674 /* Error values that may be returned by PCI functions */
675 #define PCIBIOS_SUCCESSFUL 0x00
676 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
677 #define PCIBIOS_BAD_VENDOR_ID 0x83
678 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
679 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
680 #define PCIBIOS_SET_FAILED 0x88
681 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
683 /* Translate above to generic errno for passing back through non-PCI code */
684 static inline int pcibios_err_to_errno(int err)
686 if (err <= PCIBIOS_SUCCESSFUL)
687 return err; /* Assume already errno */
690 case PCIBIOS_FUNC_NOT_SUPPORTED:
692 case PCIBIOS_BAD_VENDOR_ID:
694 case PCIBIOS_DEVICE_NOT_FOUND:
696 case PCIBIOS_BAD_REGISTER_NUMBER:
698 case PCIBIOS_SET_FAILED:
700 case PCIBIOS_BUFFER_TOO_SMALL:
707 /* Low-level architecture-dependent routines */
710 int (*add_bus)(struct pci_bus *bus);
711 void (*remove_bus)(struct pci_bus *bus);
712 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
713 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
714 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
718 * ACPI needs to be able to access PCI config space before we've done a
719 * PCI bus scan and created pci_bus structures.
721 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
722 int reg, int len, u32 *val);
723 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
724 int reg, int len, u32 val);
726 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
727 typedef u64 pci_bus_addr_t;
729 typedef u32 pci_bus_addr_t;
732 struct pci_bus_region {
733 pci_bus_addr_t start;
738 spinlock_t lock; /* Protects list, index */
739 struct list_head list; /* For IDs added at runtime */
744 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
745 * a set of callbacks in struct pci_error_handlers, that device driver
746 * will be notified of PCI bus errors, and will be driven to recovery
747 * when an error occurs.
750 typedef unsigned int __bitwise pci_ers_result_t;
752 enum pci_ers_result {
753 /* No result/none/not supported in device driver */
754 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
756 /* Device driver can recover without slot reset */
757 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
759 /* Device driver wants slot to be reset */
760 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
762 /* Device has completely failed, is unrecoverable */
763 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
765 /* Device driver is fully recovered and operational */
766 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
768 /* No AER capabilities registered for the driver */
769 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
772 /* PCI bus error event callbacks */
773 struct pci_error_handlers {
774 /* PCI bus error detected on this device */
775 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
776 enum pci_channel_state error);
778 /* MMIO has been re-enabled, but not DMA */
779 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
781 /* PCI slot has been reset */
782 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
784 /* PCI function reset prepare or completed */
785 void (*reset_prepare)(struct pci_dev *dev);
786 void (*reset_done)(struct pci_dev *dev);
788 /* Device driver may resume normal operations */
789 void (*resume)(struct pci_dev *dev);
796 * struct pci_driver - PCI driver structure
797 * @node: List of driver structures.
798 * @name: Driver name.
799 * @id_table: Pointer to table of device IDs the driver is
800 * interested in. Most drivers should export this
801 * table using MODULE_DEVICE_TABLE(pci,...).
802 * @probe: This probing function gets called (during execution
803 * of pci_register_driver() for already existing
804 * devices or later if a new device gets inserted) for
805 * all PCI devices which match the ID table and are not
806 * "owned" by the other drivers yet. This function gets
807 * passed a "struct pci_dev \*" for each device whose
808 * entry in the ID table matches the device. The probe
809 * function returns zero when the driver chooses to
810 * take "ownership" of the device or an error code
811 * (negative number) otherwise.
812 * The probe function always gets called from process
813 * context, so it can sleep.
814 * @remove: The remove() function gets called whenever a device
815 * being handled by this driver is removed (either during
816 * deregistration of the driver or when it's manually
817 * pulled out of a hot-pluggable slot).
818 * The remove function always gets called from process
819 * context, so it can sleep.
820 * @suspend: Put device into low power state.
821 * @resume: Wake device from low power state.
822 * (Please see Documentation/power/pci.rst for descriptions
823 * of PCI Power Management and the related functions.)
824 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
825 * Intended to stop any idling DMA operations.
826 * Useful for enabling wake-on-lan (NIC) or changing
827 * the power state of a device before reboot.
828 * e.g. drivers/net/e100.c.
829 * @sriov_configure: Optional driver callback to allow configuration of
830 * number of VFs to enable via sysfs "sriov_numvfs" file.
831 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
832 * @groups: Sysfs attribute groups.
833 * @driver: Driver model structure.
834 * @dynids: List of dynamically added device IDs.
837 struct list_head node;
839 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
840 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
841 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
842 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
843 int (*resume)(struct pci_dev *dev); /* Device woken up */
844 void (*shutdown)(struct pci_dev *dev);
845 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
846 const struct pci_error_handlers *err_handler;
847 const struct attribute_group **groups;
848 struct device_driver driver;
849 struct pci_dynids dynids;
852 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
855 * PCI_DEVICE - macro used to describe a specific PCI device
856 * @vend: the 16 bit PCI Vendor ID
857 * @dev: the 16 bit PCI Device ID
859 * This macro is used to create a struct pci_device_id that matches a
860 * specific device. The subvendor and subdevice fields will be set to
863 #define PCI_DEVICE(vend,dev) \
864 .vendor = (vend), .device = (dev), \
865 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
868 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
869 * @vend: the 16 bit PCI Vendor ID
870 * @dev: the 16 bit PCI Device ID
871 * @subvend: the 16 bit PCI Subvendor ID
872 * @subdev: the 16 bit PCI Subdevice ID
874 * This macro is used to create a struct pci_device_id that matches a
875 * specific device with subsystem information.
877 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
878 .vendor = (vend), .device = (dev), \
879 .subvendor = (subvend), .subdevice = (subdev)
882 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
883 * @dev_class: the class, subclass, prog-if triple for this device
884 * @dev_class_mask: the class mask for this device
886 * This macro is used to create a struct pci_device_id that matches a
887 * specific PCI class. The vendor, device, subvendor, and subdevice
888 * fields will be set to PCI_ANY_ID.
890 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
891 .class = (dev_class), .class_mask = (dev_class_mask), \
892 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
893 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
896 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
897 * @vend: the vendor name
898 * @dev: the 16 bit PCI Device ID
900 * This macro is used to create a struct pci_device_id that matches a
901 * specific PCI device. The subvendor, and subdevice fields will be set
902 * to PCI_ANY_ID. The macro allows the next field to follow as the device
905 #define PCI_VDEVICE(vend, dev) \
906 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
907 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
910 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
911 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
912 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
913 * @data: the driver data to be filled
915 * This macro is used to create a struct pci_device_id that matches a
916 * specific PCI device. The subvendor, and subdevice fields will be set
919 #define PCI_DEVICE_DATA(vend, dev, data) \
920 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
921 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
922 .driver_data = (kernel_ulong_t)(data)
925 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
926 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
927 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
928 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
929 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
930 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
931 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
934 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
935 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
936 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
937 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
939 /* These external functions are only available when PCI support is enabled */
942 extern unsigned int pci_flags;
944 static inline void pci_set_flags(int flags) { pci_flags = flags; }
945 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
946 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
947 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
949 void pcie_bus_configure_settings(struct pci_bus *bus);
951 enum pcie_bus_config_types {
952 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
953 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
954 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
955 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
956 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
959 extern enum pcie_bus_config_types pcie_bus_config;
961 extern struct bus_type pci_bus_type;
963 /* Do NOT directly access these two variables, unless you are arch-specific PCI
964 * code, or PCI core code. */
965 extern struct list_head pci_root_buses; /* List of all known PCI buses */
966 /* Some device drivers need know if PCI is initiated */
967 int no_pci_devices(void);
969 void pcibios_resource_survey_bus(struct pci_bus *bus);
970 void pcibios_bus_add_device(struct pci_dev *pdev);
971 void pcibios_add_bus(struct pci_bus *bus);
972 void pcibios_remove_bus(struct pci_bus *bus);
973 void pcibios_fixup_bus(struct pci_bus *);
974 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
975 /* Architecture-specific versions may override this (weak) */
976 char *pcibios_setup(char *str);
978 /* Used only when drivers/pci/setup.c is used */
979 resource_size_t pcibios_align_resource(void *, const struct resource *,
983 /* Weak but can be overridden by arch */
984 void pci_fixup_cardbus(struct pci_bus *);
986 /* Generic PCI functions used internally */
988 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
989 struct resource *res);
990 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
991 struct pci_bus_region *region);
992 void pcibios_scan_specific_bus(int busn);
993 struct pci_bus *pci_find_bus(int domain, int busnr);
994 void pci_bus_add_devices(const struct pci_bus *bus);
995 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
996 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
997 struct pci_ops *ops, void *sysdata,
998 struct list_head *resources);
999 int pci_host_probe(struct pci_host_bridge *bridge);
1000 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1001 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1002 void pci_bus_release_busn_res(struct pci_bus *b);
1003 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1004 struct pci_ops *ops, void *sysdata,
1005 struct list_head *resources);
1006 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1007 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1009 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1011 struct hotplug_slot *hotplug);
1012 void pci_destroy_slot(struct pci_slot *slot);
1014 void pci_dev_assign_slot(struct pci_dev *dev);
1016 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1018 int pci_scan_slot(struct pci_bus *bus, int devfn);
1019 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1020 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1021 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1022 void pci_bus_add_device(struct pci_dev *dev);
1023 void pci_read_bridge_bases(struct pci_bus *child);
1024 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1025 struct resource *res);
1026 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
1027 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1028 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1029 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1030 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1031 void pci_dev_put(struct pci_dev *dev);
1032 void pci_remove_bus(struct pci_bus *b);
1033 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1034 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1035 void pci_stop_root_bus(struct pci_bus *bus);
1036 void pci_remove_root_bus(struct pci_bus *bus);
1037 void pci_setup_cardbus(struct pci_bus *bus);
1038 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1039 void pci_sort_breadthfirst(void);
1040 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1041 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1043 /* Generic PCI functions exported to card drivers */
1045 enum pci_lost_interrupt_reason {
1046 PCI_LOST_IRQ_NO_INFORMATION = 0,
1047 PCI_LOST_IRQ_DISABLE_MSI,
1048 PCI_LOST_IRQ_DISABLE_MSIX,
1049 PCI_LOST_IRQ_DISABLE_ACPI,
1051 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
1052 int pci_find_capability(struct pci_dev *dev, int cap);
1053 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1054 int pci_find_ext_capability(struct pci_dev *dev, int cap);
1055 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1056 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1057 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1058 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1060 u64 pci_get_dsn(struct pci_dev *dev);
1062 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1063 struct pci_dev *from);
1064 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1065 unsigned int ss_vendor, unsigned int ss_device,
1066 struct pci_dev *from);
1067 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1068 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1069 unsigned int devfn);
1070 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1071 int pci_dev_present(const struct pci_device_id *ids);
1073 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1074 int where, u8 *val);
1075 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1076 int where, u16 *val);
1077 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1078 int where, u32 *val);
1079 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1081 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1082 int where, u16 val);
1083 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1084 int where, u32 val);
1086 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1087 int where, int size, u32 *val);
1088 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1089 int where, int size, u32 val);
1090 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1091 int where, int size, u32 *val);
1092 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1093 int where, int size, u32 val);
1095 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1097 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1098 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1099 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1100 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1101 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1102 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1104 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1105 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1106 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1107 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1108 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1109 u16 clear, u16 set);
1110 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1111 u32 clear, u32 set);
1113 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1116 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1119 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1122 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1125 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1128 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1131 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1134 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1137 /* User-space driven config access */
1138 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1139 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1140 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1141 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1142 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1143 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1145 int __must_check pci_enable_device(struct pci_dev *dev);
1146 int __must_check pci_enable_device_io(struct pci_dev *dev);
1147 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1148 int __must_check pci_reenable_device(struct pci_dev *);
1149 int __must_check pcim_enable_device(struct pci_dev *pdev);
1150 void pcim_pin_device(struct pci_dev *pdev);
1152 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1155 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1156 * writable and no quirk has marked the feature broken.
1158 return !pdev->broken_intx_masking;
1161 static inline int pci_is_enabled(struct pci_dev *pdev)
1163 return (atomic_read(&pdev->enable_cnt) > 0);
1166 static inline int pci_is_managed(struct pci_dev *pdev)
1168 return pdev->is_managed;
1171 void pci_disable_device(struct pci_dev *dev);
1173 extern unsigned int pcibios_max_latency;
1174 void pci_set_master(struct pci_dev *dev);
1175 void pci_clear_master(struct pci_dev *dev);
1177 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1178 int pci_set_cacheline_size(struct pci_dev *dev);
1179 #define HAVE_PCI_SET_MWI
1180 int __must_check pci_set_mwi(struct pci_dev *dev);
1181 int __must_check pcim_set_mwi(struct pci_dev *dev);
1182 int pci_try_set_mwi(struct pci_dev *dev);
1183 void pci_clear_mwi(struct pci_dev *dev);
1184 void pci_intx(struct pci_dev *dev, int enable);
1185 bool pci_check_and_mask_intx(struct pci_dev *dev);
1186 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1187 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1188 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1189 int pcix_get_max_mmrbc(struct pci_dev *dev);
1190 int pcix_get_mmrbc(struct pci_dev *dev);
1191 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1192 int pcie_get_readrq(struct pci_dev *dev);
1193 int pcie_set_readrq(struct pci_dev *dev, int rq);
1194 int pcie_get_mps(struct pci_dev *dev);
1195 int pcie_set_mps(struct pci_dev *dev, int mps);
1196 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1197 enum pci_bus_speed *speed,
1198 enum pcie_link_width *width);
1199 void pcie_print_link_status(struct pci_dev *dev);
1200 bool pcie_has_flr(struct pci_dev *dev);
1201 int pcie_flr(struct pci_dev *dev);
1202 int __pci_reset_function_locked(struct pci_dev *dev);
1203 int pci_reset_function(struct pci_dev *dev);
1204 int pci_reset_function_locked(struct pci_dev *dev);
1205 int pci_try_reset_function(struct pci_dev *dev);
1206 int pci_probe_reset_slot(struct pci_slot *slot);
1207 int pci_probe_reset_bus(struct pci_bus *bus);
1208 int pci_reset_bus(struct pci_dev *dev);
1209 void pci_reset_secondary_bus(struct pci_dev *dev);
1210 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1211 void pci_update_resource(struct pci_dev *dev, int resno);
1212 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1213 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1214 void pci_release_resource(struct pci_dev *dev, int resno);
1215 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1216 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1217 bool pci_device_is_present(struct pci_dev *pdev);
1218 void pci_ignore_hotplug(struct pci_dev *dev);
1219 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1220 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1222 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1223 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1224 const char *fmt, ...);
1225 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1227 /* ROM control related routines */
1228 int pci_enable_rom(struct pci_dev *pdev);
1229 void pci_disable_rom(struct pci_dev *pdev);
1230 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1231 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1233 /* Power management related routines */
1234 int pci_save_state(struct pci_dev *dev);
1235 void pci_restore_state(struct pci_dev *dev);
1236 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1237 int pci_load_saved_state(struct pci_dev *dev,
1238 struct pci_saved_state *state);
1239 int pci_load_and_free_saved_state(struct pci_dev *dev,
1240 struct pci_saved_state **state);
1241 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1242 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1244 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1245 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1246 u16 cap, unsigned int size);
1247 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1248 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1249 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1250 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1251 void pci_pme_active(struct pci_dev *dev, bool enable);
1252 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1253 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1254 int pci_prepare_to_sleep(struct pci_dev *dev);
1255 int pci_back_from_sleep(struct pci_dev *dev);
1256 bool pci_dev_run_wake(struct pci_dev *dev);
1257 void pci_d3cold_enable(struct pci_dev *dev);
1258 void pci_d3cold_disable(struct pci_dev *dev);
1259 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1260 void pci_wakeup_bus(struct pci_bus *bus);
1261 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1263 /* For use by arch with custom probe code */
1264 void set_pcie_port_type(struct pci_dev *pdev);
1265 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1267 /* Functions for PCI Hotplug drivers to use */
1268 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1269 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1270 unsigned int pci_rescan_bus(struct pci_bus *bus);
1271 void pci_lock_rescan_remove(void);
1272 void pci_unlock_rescan_remove(void);
1274 /* Vital Product Data routines */
1275 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1276 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1277 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1279 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1280 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1281 void pci_bus_assign_resources(const struct pci_bus *bus);
1282 void pci_bus_claim_resources(struct pci_bus *bus);
1283 void pci_bus_size_bridges(struct pci_bus *bus);
1284 int pci_claim_resource(struct pci_dev *, int);
1285 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1286 void pci_assign_unassigned_resources(void);
1287 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1288 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1289 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1290 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1291 void pdev_enable_device(struct pci_dev *);
1292 int pci_enable_resources(struct pci_dev *, int mask);
1293 void pci_assign_irq(struct pci_dev *dev);
1294 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1295 #define HAVE_PCI_REQ_REGIONS 2
1296 int __must_check pci_request_regions(struct pci_dev *, const char *);
1297 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1298 void pci_release_regions(struct pci_dev *);
1299 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1300 void pci_release_region(struct pci_dev *, int);
1301 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1302 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1303 void pci_release_selected_regions(struct pci_dev *, int);
1305 /* drivers/pci/bus.c */
1306 void pci_add_resource(struct list_head *resources, struct resource *res);
1307 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1308 resource_size_t offset);
1309 void pci_free_resource_list(struct list_head *resources);
1310 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1311 unsigned int flags);
1312 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1313 void pci_bus_remove_resources(struct pci_bus *bus);
1314 int devm_request_pci_bus_resources(struct device *dev,
1315 struct list_head *resources);
1317 /* Temporary until new and working PCI SBR API in place */
1318 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1320 #define pci_bus_for_each_resource(bus, res, i) \
1322 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1325 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1326 struct resource *res, resource_size_t size,
1327 resource_size_t align, resource_size_t min,
1328 unsigned long type_mask,
1329 resource_size_t (*alignf)(void *,
1330 const struct resource *,
1336 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1337 resource_size_t size);
1338 unsigned long pci_address_to_pio(phys_addr_t addr);
1339 phys_addr_t pci_pio_to_address(unsigned long pio);
1340 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1341 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1342 phys_addr_t phys_addr);
1343 void pci_unmap_iospace(struct resource *res);
1344 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1345 resource_size_t offset,
1346 resource_size_t size);
1347 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1348 struct resource *res);
1350 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1352 struct pci_bus_region region;
1354 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1355 return region.start;
1358 /* Proper probing supporting hot-pluggable devices */
1359 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1360 const char *mod_name);
1362 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1363 #define pci_register_driver(driver) \
1364 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1366 void pci_unregister_driver(struct pci_driver *dev);
1369 * module_pci_driver() - Helper macro for registering a PCI driver
1370 * @__pci_driver: pci_driver struct
1372 * Helper macro for PCI drivers which do not do anything special in module
1373 * init/exit. This eliminates a lot of boilerplate. Each module may only
1374 * use this macro once, and calling it replaces module_init() and module_exit()
1376 #define module_pci_driver(__pci_driver) \
1377 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1380 * builtin_pci_driver() - Helper macro for registering a PCI driver
1381 * @__pci_driver: pci_driver struct
1383 * Helper macro for PCI drivers which do not do anything special in their
1384 * init code. This eliminates a lot of boilerplate. Each driver may only
1385 * use this macro once, and calling it replaces device_initcall(...)
1387 #define builtin_pci_driver(__pci_driver) \
1388 builtin_driver(__pci_driver, pci_register_driver)
1390 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1391 int pci_add_dynid(struct pci_driver *drv,
1392 unsigned int vendor, unsigned int device,
1393 unsigned int subvendor, unsigned int subdevice,
1394 unsigned int class, unsigned int class_mask,
1395 unsigned long driver_data);
1396 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1397 struct pci_dev *dev);
1398 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1401 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1403 int pci_cfg_space_size(struct pci_dev *dev);
1404 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1405 void pci_setup_bridge(struct pci_bus *bus);
1406 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1407 unsigned long type);
1409 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1410 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1412 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1413 unsigned int command_bits, u32 flags);
1416 * Virtual interrupts allow for more interrupts to be allocated
1417 * than the device has interrupts for. These are not programmed
1418 * into the device's MSI-X table and must be handled by some
1419 * other driver means.
1421 #define PCI_IRQ_VIRTUAL (1 << 4)
1423 #define PCI_IRQ_ALL_TYPES \
1424 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1426 /* kmem_cache style wrapper around pci_alloc_consistent() */
1428 #include <linux/dmapool.h>
1430 #define pci_pool dma_pool
1431 #define pci_pool_create(name, pdev, size, align, allocation) \
1432 dma_pool_create(name, &pdev->dev, size, align, allocation)
1433 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1434 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1435 #define pci_pool_zalloc(pool, flags, handle) \
1436 dma_pool_zalloc(pool, flags, handle)
1437 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1440 u32 vector; /* Kernel uses to write allocated vector */
1441 u16 entry; /* Driver uses to specify entry, OS writes */
1444 #ifdef CONFIG_PCI_MSI
1445 int pci_msi_vec_count(struct pci_dev *dev);
1446 void pci_disable_msi(struct pci_dev *dev);
1447 int pci_msix_vec_count(struct pci_dev *dev);
1448 void pci_disable_msix(struct pci_dev *dev);
1449 void pci_restore_msi_state(struct pci_dev *dev);
1450 int pci_msi_enabled(void);
1451 int pci_enable_msi(struct pci_dev *dev);
1452 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1453 int minvec, int maxvec);
1454 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1455 struct msix_entry *entries, int nvec)
1457 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1462 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1463 unsigned int max_vecs, unsigned int flags,
1464 struct irq_affinity *affd);
1466 void pci_free_irq_vectors(struct pci_dev *dev);
1467 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1468 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1471 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1472 static inline void pci_disable_msi(struct pci_dev *dev) { }
1473 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1474 static inline void pci_disable_msix(struct pci_dev *dev) { }
1475 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1476 static inline int pci_msi_enabled(void) { return 0; }
1477 static inline int pci_enable_msi(struct pci_dev *dev)
1479 static inline int pci_enable_msix_range(struct pci_dev *dev,
1480 struct msix_entry *entries, int minvec, int maxvec)
1482 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1483 struct msix_entry *entries, int nvec)
1487 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1488 unsigned int max_vecs, unsigned int flags,
1489 struct irq_affinity *aff_desc)
1491 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1496 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1500 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1502 if (WARN_ON_ONCE(nr > 0))
1506 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1509 return cpu_possible_mask;
1514 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1515 * @d: the INTx IRQ domain
1516 * @node: the DT node for the device whose interrupt we're translating
1517 * @intspec: the interrupt specifier data from the DT
1518 * @intsize: the number of entries in @intspec
1519 * @out_hwirq: pointer at which to write the hwirq number
1520 * @out_type: pointer at which to write the interrupt type
1522 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1523 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1524 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1525 * INTx value to obtain the hwirq number.
1527 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1529 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1530 struct device_node *node,
1532 unsigned int intsize,
1533 unsigned long *out_hwirq,
1534 unsigned int *out_type)
1536 const u32 intx = intspec[0];
1538 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1541 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1545 #ifdef CONFIG_PCIEPORTBUS
1546 extern bool pcie_ports_disabled;
1547 extern bool pcie_ports_native;
1549 #define pcie_ports_disabled true
1550 #define pcie_ports_native false
1553 #define PCIE_LINK_STATE_L0S BIT(0)
1554 #define PCIE_LINK_STATE_L1 BIT(1)
1555 #define PCIE_LINK_STATE_CLKPM BIT(2)
1556 #define PCIE_LINK_STATE_L1_1 BIT(3)
1557 #define PCIE_LINK_STATE_L1_2 BIT(4)
1558 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1559 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1561 #ifdef CONFIG_PCIEASPM
1562 int pci_disable_link_state(struct pci_dev *pdev, int state);
1563 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1564 void pcie_no_aspm(void);
1565 bool pcie_aspm_support_enabled(void);
1566 bool pcie_aspm_enabled(struct pci_dev *pdev);
1568 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1570 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1572 static inline void pcie_no_aspm(void) { }
1573 static inline bool pcie_aspm_support_enabled(void) { return false; }
1574 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1577 #ifdef CONFIG_PCIEAER
1578 bool pci_aer_available(void);
1580 static inline bool pci_aer_available(void) { return false; }
1583 bool pci_ats_disabled(void);
1585 void pci_cfg_access_lock(struct pci_dev *dev);
1586 bool pci_cfg_access_trylock(struct pci_dev *dev);
1587 void pci_cfg_access_unlock(struct pci_dev *dev);
1590 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1591 * a PCI domain is defined to be a set of PCI buses which share
1592 * configuration space.
1594 #ifdef CONFIG_PCI_DOMAINS
1595 extern int pci_domains_supported;
1597 enum { pci_domains_supported = 0 };
1598 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1599 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1600 #endif /* CONFIG_PCI_DOMAINS */
1603 * Generic implementation for PCI domain support. If your
1604 * architecture does not need custom management of PCI
1605 * domains then this implementation will be used
1607 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1608 static inline int pci_domain_nr(struct pci_bus *bus)
1610 return bus->domain_nr;
1613 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1615 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1618 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1621 /* Some architectures require additional setup to direct VGA traffic */
1622 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1623 unsigned int command_bits, u32 flags);
1624 void pci_register_set_vga_state(arch_set_vga_state_t func);
1627 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1629 return pci_request_selected_regions(pdev,
1630 pci_select_bars(pdev, IORESOURCE_IO), name);
1634 pci_release_io_regions(struct pci_dev *pdev)
1636 return pci_release_selected_regions(pdev,
1637 pci_select_bars(pdev, IORESOURCE_IO));
1641 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1643 return pci_request_selected_regions(pdev,
1644 pci_select_bars(pdev, IORESOURCE_MEM), name);
1648 pci_release_mem_regions(struct pci_dev *pdev)
1650 return pci_release_selected_regions(pdev,
1651 pci_select_bars(pdev, IORESOURCE_MEM));
1654 #else /* CONFIG_PCI is not enabled */
1656 static inline void pci_set_flags(int flags) { }
1657 static inline void pci_add_flags(int flags) { }
1658 static inline void pci_clear_flags(int flags) { }
1659 static inline int pci_has_flag(int flag) { return 0; }
1662 * If the system does not have PCI, clearly these return errors. Define
1663 * these as simple inline functions to avoid hair in drivers.
1665 #define _PCI_NOP(o, s, t) \
1666 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1668 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1670 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1671 _PCI_NOP(o, word, u16 x) \
1672 _PCI_NOP(o, dword, u32 x)
1673 _PCI_NOP_ALL(read, *)
1674 _PCI_NOP_ALL(write,)
1676 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1677 unsigned int device,
1678 struct pci_dev *from)
1681 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1682 unsigned int device,
1683 unsigned int ss_vendor,
1684 unsigned int ss_device,
1685 struct pci_dev *from)
1688 static inline struct pci_dev *pci_get_class(unsigned int class,
1689 struct pci_dev *from)
1692 #define pci_dev_present(ids) (0)
1693 #define no_pci_devices() (1)
1694 #define pci_dev_put(dev) do { } while (0)
1696 static inline void pci_set_master(struct pci_dev *dev) { }
1697 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1698 static inline void pci_disable_device(struct pci_dev *dev) { }
1699 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1700 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1702 static inline int __pci_register_driver(struct pci_driver *drv,
1703 struct module *owner)
1705 static inline int pci_register_driver(struct pci_driver *drv)
1707 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1708 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1710 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1713 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1716 static inline u64 pci_get_dsn(struct pci_dev *dev)
1719 /* Power management related routines */
1720 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1721 static inline void pci_restore_state(struct pci_dev *dev) { }
1722 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1724 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1726 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1729 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1733 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1734 struct resource *res)
1736 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1738 static inline void pci_release_regions(struct pci_dev *dev) { }
1740 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1742 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1744 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1747 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1748 unsigned int bus, unsigned int devfn)
1751 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1752 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1754 #define dev_is_pci(d) (false)
1755 #define dev_is_pf(d) (false)
1756 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1758 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1759 struct device_node *node,
1761 unsigned int intsize,
1762 unsigned long *out_hwirq,
1763 unsigned int *out_type)
1766 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1767 struct pci_dev *dev)
1769 static inline bool pci_ats_disabled(void) { return true; }
1771 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1777 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1778 unsigned int max_vecs, unsigned int flags,
1779 struct irq_affinity *aff_desc)
1783 #endif /* CONFIG_PCI */
1786 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1787 unsigned int max_vecs, unsigned int flags)
1789 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1793 /* Include architecture-dependent settings and functions */
1795 #include <asm/pci.h>
1797 /* These two functions provide almost identical functionality. Depending
1798 * on the architecture, one will be implemented as a wrapper around the
1799 * other (in drivers/pci/mmap.c).
1801 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1802 * is expected to be an offset within that region.
1804 * pci_mmap_page_range() is the legacy architecture-specific interface,
1805 * which accepts a "user visible" resource address converted by
1806 * pci_resource_to_user(), as used in the legacy mmap() interface in
1809 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1810 struct vm_area_struct *vma,
1811 enum pci_mmap_state mmap_state, int write_combine);
1812 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1813 struct vm_area_struct *vma,
1814 enum pci_mmap_state mmap_state, int write_combine);
1816 #ifndef arch_can_pci_mmap_wc
1817 #define arch_can_pci_mmap_wc() 0
1820 #ifndef arch_can_pci_mmap_io
1821 #define arch_can_pci_mmap_io() 0
1822 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1824 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1827 #ifndef pci_root_bus_fwnode
1828 #define pci_root_bus_fwnode(bus) NULL
1832 * These helpers provide future and backwards compatibility
1833 * for accessing popular PCI BAR info
1835 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1836 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1837 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1838 #define pci_resource_len(dev,bar) \
1839 ((pci_resource_start((dev), (bar)) == 0 && \
1840 pci_resource_end((dev), (bar)) == \
1841 pci_resource_start((dev), (bar))) ? 0 : \
1843 (pci_resource_end((dev), (bar)) - \
1844 pci_resource_start((dev), (bar)) + 1))
1847 * Similar to the helpers above, these manipulate per-pci_dev
1848 * driver-specific data. They are really just a wrapper around
1849 * the generic device structure functions of these calls.
1851 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1853 return dev_get_drvdata(&pdev->dev);
1856 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1858 dev_set_drvdata(&pdev->dev, data);
1861 static inline const char *pci_name(const struct pci_dev *pdev)
1863 return dev_name(&pdev->dev);
1866 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1867 const struct resource *rsrc,
1868 resource_size_t *start, resource_size_t *end);
1871 * The world is not perfect and supplies us with broken PCI devices.
1872 * For at least a part of these bugs we need a work-around, so both
1873 * generic (drivers/pci/quirks.c) and per-architecture code can define
1874 * fixup hooks to be called for particular buggy devices.
1878 u16 vendor; /* Or PCI_ANY_ID */
1879 u16 device; /* Or PCI_ANY_ID */
1880 u32 class; /* Or PCI_ANY_ID */
1881 unsigned int class_shift; /* should be 0, 8, 16 */
1882 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1885 void (*hook)(struct pci_dev *dev);
1889 enum pci_fixup_pass {
1890 pci_fixup_early, /* Before probing BARs */
1891 pci_fixup_header, /* After reading configuration header */
1892 pci_fixup_final, /* Final phase of device fixups */
1893 pci_fixup_enable, /* pci_enable_device() time */
1894 pci_fixup_resume, /* pci_device_resume() */
1895 pci_fixup_suspend, /* pci_device_suspend() */
1896 pci_fixup_resume_early, /* pci_device_resume_early() */
1897 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1900 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1901 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1902 class_shift, hook) \
1903 __ADDRESSABLE(hook) \
1904 asm(".section " #sec ", \"a\" \n" \
1906 ".short " #vendor ", " #device " \n" \
1907 ".long " #class ", " #class_shift " \n" \
1908 ".long " #hook " - . \n" \
1910 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1911 class_shift, hook) \
1912 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1915 /* Anonymous variables would be nice... */
1916 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1917 class_shift, hook) \
1918 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1919 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1920 = { vendor, device, class, class_shift, hook };
1923 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1924 class_shift, hook) \
1925 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1926 hook, vendor, device, class, class_shift, hook)
1927 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1928 class_shift, hook) \
1929 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1930 hook, vendor, device, class, class_shift, hook)
1931 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1932 class_shift, hook) \
1933 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1934 hook, vendor, device, class, class_shift, hook)
1935 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1936 class_shift, hook) \
1937 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1938 hook, vendor, device, class, class_shift, hook)
1939 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1940 class_shift, hook) \
1941 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1942 resume##hook, vendor, device, class, class_shift, hook)
1943 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1944 class_shift, hook) \
1945 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1946 resume_early##hook, vendor, device, class, class_shift, hook)
1947 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1948 class_shift, hook) \
1949 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1950 suspend##hook, vendor, device, class, class_shift, hook)
1951 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1952 class_shift, hook) \
1953 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1954 suspend_late##hook, vendor, device, class, class_shift, hook)
1956 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1957 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1958 hook, vendor, device, PCI_ANY_ID, 0, hook)
1959 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1960 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1961 hook, vendor, device, PCI_ANY_ID, 0, hook)
1962 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1963 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1964 hook, vendor, device, PCI_ANY_ID, 0, hook)
1965 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1966 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1967 hook, vendor, device, PCI_ANY_ID, 0, hook)
1968 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1969 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1970 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1971 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1972 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1973 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1974 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1975 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1976 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1977 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1978 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1979 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1981 #ifdef CONFIG_PCI_QUIRKS
1982 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1984 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1985 struct pci_dev *dev) { }
1988 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1989 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1990 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1991 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1992 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1994 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1996 extern int pci_pci_problems;
1997 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1998 #define PCIPCI_TRITON 2
1999 #define PCIPCI_NATOMA 4
2000 #define PCIPCI_VIAETBF 8
2001 #define PCIPCI_VSFX 16
2002 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2003 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2005 extern unsigned long pci_cardbus_io_size;
2006 extern unsigned long pci_cardbus_mem_size;
2007 extern u8 pci_dfl_cache_line_size;
2008 extern u8 pci_cache_line_size;
2010 /* Architecture-specific versions may override these (weak) */
2011 void pcibios_disable_device(struct pci_dev *dev);
2012 void pcibios_set_master(struct pci_dev *dev);
2013 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2014 enum pcie_reset_state state);
2015 int pcibios_add_device(struct pci_dev *dev);
2016 void pcibios_release_device(struct pci_dev *dev);
2018 void pcibios_penalize_isa_irq(int irq, int active);
2020 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2022 int pcibios_alloc_irq(struct pci_dev *dev);
2023 void pcibios_free_irq(struct pci_dev *dev);
2024 resource_size_t pcibios_default_alignment(void);
2026 #ifdef CONFIG_HIBERNATE_CALLBACKS
2027 extern struct dev_pm_ops pcibios_pm_ops;
2030 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2031 void __init pci_mmcfg_early_init(void);
2032 void __init pci_mmcfg_late_init(void);
2034 static inline void pci_mmcfg_early_init(void) { }
2035 static inline void pci_mmcfg_late_init(void) { }
2038 int pci_ext_cfg_avail(void);
2040 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2041 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2043 #ifdef CONFIG_PCI_IOV
2044 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2045 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2047 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2048 void pci_disable_sriov(struct pci_dev *dev);
2049 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2050 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2051 int pci_num_vf(struct pci_dev *dev);
2052 int pci_vfs_assigned(struct pci_dev *dev);
2053 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2054 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2055 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2056 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2057 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2059 /* Arch may override these (weak) */
2060 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2061 int pcibios_sriov_disable(struct pci_dev *pdev);
2062 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2064 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2068 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2072 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2074 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2078 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2080 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2081 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2082 static inline int pci_vfs_assigned(struct pci_dev *dev)
2084 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2086 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2088 #define pci_sriov_configure_simple NULL
2089 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2091 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2094 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2095 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2096 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2100 * pci_pcie_cap - get the saved PCIe capability offset
2103 * PCIe capability offset is calculated at PCI device initialization
2104 * time and saved in the data structure. This function returns saved
2105 * PCIe capability offset. Using this instead of pci_find_capability()
2106 * reduces unnecessary search in the PCI configuration space. If you
2107 * need to calculate PCIe capability offset from raw device for some
2108 * reasons, please use pci_find_capability() instead.
2110 static inline int pci_pcie_cap(struct pci_dev *dev)
2112 return dev->pcie_cap;
2116 * pci_is_pcie - check if the PCI device is PCI Express capable
2119 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2121 static inline bool pci_is_pcie(struct pci_dev *dev)
2123 return pci_pcie_cap(dev);
2127 * pcie_caps_reg - get the PCIe Capabilities Register
2130 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2132 return dev->pcie_flags_reg;
2136 * pci_pcie_type - get the PCIe device/port type
2139 static inline int pci_pcie_type(const struct pci_dev *dev)
2141 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2144 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2147 if (!pci_is_pcie(dev))
2149 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2151 if (!dev->bus->self)
2153 dev = dev->bus->self;
2158 void pci_request_acs(void);
2159 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2160 bool pci_acs_path_enabled(struct pci_dev *start,
2161 struct pci_dev *end, u16 acs_flags);
2162 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2164 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2165 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2167 /* Large Resource Data Type Tag Item Names */
2168 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2169 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2170 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2172 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2173 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2174 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2176 /* Small Resource Data Type Tag Item Names */
2177 #define PCI_VPD_STIN_END 0x0f /* End */
2179 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2181 #define PCI_VPD_SRDT_TIN_MASK 0x78
2182 #define PCI_VPD_SRDT_LEN_MASK 0x07
2183 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2185 #define PCI_VPD_LRDT_TAG_SIZE 3
2186 #define PCI_VPD_SRDT_TAG_SIZE 1
2188 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2190 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2191 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2192 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2193 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2194 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2197 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2198 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2200 * Returns the extracted Large Resource Data Type length.
2202 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2204 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2208 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2209 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2211 * Returns the extracted Large Resource Data Type Tag item.
2213 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2215 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2219 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2220 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2222 * Returns the extracted Small Resource Data Type length.
2224 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2226 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2230 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2231 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2233 * Returns the extracted Small Resource Data Type Tag Item.
2235 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2237 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2241 * pci_vpd_info_field_size - Extracts the information field length
2242 * @info_field: Pointer to the beginning of an information field header
2244 * Returns the extracted information field length.
2246 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2248 return info_field[2];
2252 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2253 * @buf: Pointer to buffered vpd data
2254 * @off: The offset into the buffer at which to begin the search
2255 * @len: The length of the vpd buffer
2256 * @rdt: The Resource Data Type to search for
2258 * Returns the index where the Resource Data Type was found or
2259 * -ENOENT otherwise.
2261 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2264 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2265 * @buf: Pointer to buffered vpd data
2266 * @off: The offset into the buffer at which to begin the search
2267 * @len: The length of the buffer area, relative to off, in which to search
2268 * @kw: The keyword to search for
2270 * Returns the index where the information field keyword was found or
2271 * -ENOENT otherwise.
2273 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2274 unsigned int len, const char *kw);
2276 /* PCI <-> OF binding helpers */
2280 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2281 int pci_parse_request_of_pci_ranges(struct device *dev,
2282 struct list_head *resources,
2283 struct list_head *ib_resources,
2284 struct resource **bus_range);
2286 /* Arch may override this (weak) */
2287 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2289 #else /* CONFIG_OF */
2290 static inline struct irq_domain *
2291 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2293 pci_parse_request_of_pci_ranges(struct device *dev,
2294 struct list_head *resources,
2295 struct list_head *ib_resources,
2296 struct resource **bus_range)
2300 #endif /* CONFIG_OF */
2302 static inline struct device_node *
2303 pci_device_to_OF_node(const struct pci_dev *pdev)
2305 return pdev ? pdev->dev.of_node : NULL;
2308 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2310 return bus ? bus->dev.of_node : NULL;
2314 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2317 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2318 bool pci_pr3_present(struct pci_dev *pdev);
2320 static inline struct irq_domain *
2321 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2322 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2326 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2328 return pdev->dev.archdata.edev;
2332 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2333 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2334 int pci_for_each_dma_alias(struct pci_dev *pdev,
2335 int (*fn)(struct pci_dev *pdev,
2336 u16 alias, void *data), void *data);
2338 /* Helper functions for operation of device flag */
2339 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2341 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2343 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2345 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2347 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2349 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2353 * pci_ari_enabled - query ARI forwarding status
2356 * Returns true if ARI forwarding is enabled.
2358 static inline bool pci_ari_enabled(struct pci_bus *bus)
2360 return bus->self && bus->self->ari_enabled;
2364 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2365 * @pdev: PCI device to check
2367 * Walk upwards from @pdev and check for each encountered bridge if it's part
2368 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2369 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2371 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2373 struct pci_dev *parent = pdev;
2375 if (pdev->is_thunderbolt)
2378 while ((parent = pci_upstream_bridge(parent)))
2379 if (parent->is_thunderbolt)
2385 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2386 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2389 /* Provide the legacy pci_dma_* API */
2390 #include <linux/pci-dma-compat.h>
2392 #define pci_printk(level, pdev, fmt, arg...) \
2393 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2395 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2396 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2397 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2398 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2399 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2400 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2401 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2402 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2404 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2405 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2407 #define pci_info_ratelimited(pdev, fmt, arg...) \
2408 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2410 #define pci_WARN(pdev, condition, fmt, arg...) \
2411 WARN(condition, "%s %s: " fmt, \
2412 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2414 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2415 WARN_ONCE(condition, "%s %s: " fmt, \
2416 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2418 #endif /* LINUX_PCI_H */