1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <linux/msi_api.h>
42 #include <uapi/linux/pci.h>
44 #include <linux/pci_ids.h>
46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
54 #define PCI_NUM_RESET_METHODS 7
56 #define PCI_RESET_PROBE true
57 #define PCI_RESET_DO_RESET false
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
75 /* pci_slot represents a physical slot */
77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
84 static inline const char *pci_slot_name(const struct pci_slot *slot)
86 return kobject_name(&slot->kobj);
89 /* File state for mmap()s on /proc/bus/pci/X/Y */
95 /* For PCI devices, the region numbers are assigned this way: */
97 /* #0-5: standard PCI resources */
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
101 /* #6: expansion ROM resource */
104 /* Device-specific resources */
105 #ifdef CONFIG_PCI_IOV
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
110 /* PCI-to-PCI (P2P) bridge windows */
111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
115 /* CardBus bridge windows */
116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
121 /* Total number of bridge resources for P2P and CardBus */
122 #define PCI_BRIDGE_RESOURCE_NUM 4
124 /* Resources assigned to buses behind the bridge */
125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
129 /* Total resources associated with a PCI device */
132 /* Preserve this for compatibility */
133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
147 enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
155 /* The number of legacy PCI INTx interrupts */
156 #define PCI_NUM_INTX 4
159 * Reading from a device that doesn't respond typically returns ~0. A
160 * successful read from a device may also return ~0, so you need additional
161 * information to reliably identify errors.
163 #define PCI_ERROR_RESPONSE (~0ULL)
164 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
165 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
168 * pci_power_t values must match the bits in the Capabilities PME_Support
169 * and Control/Status PowerState fields in the Power Management capability.
171 typedef int __bitwise pci_power_t;
173 #define PCI_D0 ((pci_power_t __force) 0)
174 #define PCI_D1 ((pci_power_t __force) 1)
175 #define PCI_D2 ((pci_power_t __force) 2)
176 #define PCI_D3hot ((pci_power_t __force) 3)
177 #define PCI_D3cold ((pci_power_t __force) 4)
178 #define PCI_UNKNOWN ((pci_power_t __force) 5)
179 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
181 /* Remember to update this when the list above changes! */
182 extern const char *pci_power_names[];
184 static inline const char *pci_power_name(pci_power_t state)
186 return pci_power_names[1 + (__force int) state];
190 * typedef pci_channel_state_t
192 * The pci_channel state describes connectivity between the CPU and
193 * the PCI device. If some PCI bus between here and the PCI device
194 * has crashed or locked up, this info is reflected here.
196 typedef unsigned int __bitwise pci_channel_state_t;
199 /* I/O channel is in normal state */
200 pci_channel_io_normal = (__force pci_channel_state_t) 1,
202 /* I/O to channel is blocked */
203 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
205 /* PCI card is dead */
206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
209 typedef unsigned int __bitwise pcie_reset_state_t;
211 enum pcie_reset_state {
212 /* Reset is NOT asserted (Use to deassert reset) */
213 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
215 /* Use #PERST to reset PCIe device */
216 pcie_warm_reset = (__force pcie_reset_state_t) 2,
218 /* Use PCIe Hot Reset to reset device */
219 pcie_hot_reset = (__force pcie_reset_state_t) 3
222 typedef unsigned short __bitwise pci_dev_flags_t;
224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
226 /* Device configuration is irrevocably lost if disabled into D3 */
227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
228 /* Provide indication device is assigned by a Virtual Machine Manager */
229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
230 /* Flag for quirk use to store if quirk-specific ACS is enabled */
231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
234 /* Do not use bus resets for device */
235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
236 /* Do not use PM reset even if device advertises NoSoftRst- */
237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
238 /* Get VPD from function 0 VPD */
239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
240 /* A non-root bridge where translation occurs, stop alias search here */
241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
242 /* Do not use FLR even if device advertises PCI_AF_CAP */
243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
244 /* Don't use Relaxed Ordering for TLPs directed at this device */
245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
246 /* Device does honor MSI masking despite saying otherwise */
247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
250 enum pci_irq_reroute_variant {
251 INTEL_IRQ_REROUTE_VARIANT = 1,
252 MAX_IRQ_REROUTE_VARIANTS = 3
255 typedef unsigned short __bitwise pci_bus_flags_t;
257 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
258 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
259 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
260 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
263 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
264 enum pcie_link_width {
265 PCIE_LNK_WIDTH_RESRV = 0x00,
273 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
276 /* See matching string table in pci_speed_string() */
278 PCI_SPEED_33MHz = 0x00,
279 PCI_SPEED_66MHz = 0x01,
280 PCI_SPEED_66MHz_PCIX = 0x02,
281 PCI_SPEED_100MHz_PCIX = 0x03,
282 PCI_SPEED_133MHz_PCIX = 0x04,
283 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
284 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
285 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
286 PCI_SPEED_66MHz_PCIX_266 = 0x09,
287 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
288 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
294 PCI_SPEED_66MHz_PCIX_533 = 0x11,
295 PCI_SPEED_100MHz_PCIX_533 = 0x12,
296 PCI_SPEED_133MHz_PCIX_533 = 0x13,
297 PCIE_SPEED_2_5GT = 0x14,
298 PCIE_SPEED_5_0GT = 0x15,
299 PCIE_SPEED_8_0GT = 0x16,
300 PCIE_SPEED_16_0GT = 0x17,
301 PCIE_SPEED_32_0GT = 0x18,
302 PCIE_SPEED_64_0GT = 0x19,
303 PCI_SPEED_UNKNOWN = 0xff,
306 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
307 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
316 struct pcie_link_state;
321 /* The pci_dev structure describes PCI devices */
323 struct list_head bus_list; /* Node in per-bus list */
324 struct pci_bus *bus; /* Bus this device is on */
325 struct pci_bus *subordinate; /* Bus this device bridges to */
327 void *sysdata; /* Hook for sys-specific extension */
328 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
329 struct pci_slot *slot; /* Physical slot this device is in */
331 unsigned int devfn; /* Encoded device & function index */
332 unsigned short vendor;
333 unsigned short device;
334 unsigned short subsystem_vendor;
335 unsigned short subsystem_device;
336 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
337 u8 revision; /* PCI revision, low byte of class word */
338 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
339 #ifdef CONFIG_PCIEAER
340 u16 aer_cap; /* AER capability offset */
341 struct aer_stats *aer_stats; /* AER stats for this device */
343 #ifdef CONFIG_PCIEPORTBUS
344 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
345 struct pci_dev *rcec; /* Associated RCEC device */
347 u32 devcap; /* PCIe Device Capabilities */
348 u8 pcie_cap; /* PCIe capability offset */
349 u8 msi_cap; /* MSI capability offset */
350 u8 msix_cap; /* MSI-X capability offset */
351 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
352 u8 rom_base_reg; /* Config register controlling ROM */
353 u8 pin; /* Interrupt pin this device uses */
354 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
355 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
357 struct pci_driver *driver; /* Driver bound to this device */
358 u64 dma_mask; /* Mask of the bits of bus address this
359 device implements. Normally this is
360 0xffffffff. You only need to change
361 this if your device has broken DMA
362 or supports 64-bit transfers. */
364 struct device_dma_parameters dma_parms;
366 pci_power_t current_state; /* Current operating state. In ACPI,
367 this is D0-D3, D0 being fully
368 functional, and D3 being off. */
369 unsigned int imm_ready:1; /* Supports Immediate Readiness */
370 u8 pm_cap; /* PM capability offset */
371 unsigned int pme_support:5; /* Bitmask of states from which PME#
373 unsigned int pme_poll:1; /* Poll device's PME status bit */
374 unsigned int d1_support:1; /* Low power state D1 is supported */
375 unsigned int d2_support:1; /* Low power state D2 is supported */
376 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
377 unsigned int no_d3cold:1; /* D3cold is forbidden */
378 unsigned int bridge_d3:1; /* Allow D3 for bridge */
379 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
380 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
381 decoding during BAR sizing */
382 unsigned int wakeup_prepared:1;
383 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
384 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
385 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
386 controlled exclusively by
388 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
390 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
391 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
393 #ifdef CONFIG_PCIEASPM
394 struct pcie_link_state *link_state; /* ASPM link state */
395 unsigned int ltr_path:1; /* Latency Tolerance Reporting
396 supported from root to here */
397 u16 l1ss; /* L1SS Capability pointer */
399 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
400 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
402 pci_channel_state_t error_state; /* Current connectivity state */
403 struct device dev; /* Generic device interface */
405 int cfg_size; /* Size of config space */
408 * Instead of touching interrupt line and base address registers
409 * directly, use the values stored here. They might be different!
412 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
414 bool match_driver; /* Skip attaching driver */
416 unsigned int transparent:1; /* Subtractive decode bridge */
417 unsigned int io_window:1; /* Bridge has I/O window */
418 unsigned int pref_window:1; /* Bridge has pref mem window */
419 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
420 unsigned int multifunction:1; /* Multi-function device */
422 unsigned int is_busmaster:1; /* Is busmaster */
423 unsigned int no_msi:1; /* May not use MSI */
424 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
425 unsigned int block_cfg_access:1; /* Config space access blocked */
426 unsigned int broken_parity_status:1; /* Generates false positive parity */
427 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
428 unsigned int msi_enabled:1;
429 unsigned int msix_enabled:1;
430 unsigned int ari_enabled:1; /* ARI forwarding */
431 unsigned int ats_enabled:1; /* Address Translation Svc */
432 unsigned int pasid_enabled:1; /* Process Address Space ID */
433 unsigned int pri_enabled:1; /* Page Request Interface */
434 unsigned int is_managed:1; /* Managed via devres */
435 unsigned int is_msi_managed:1; /* MSI release via devres installed */
436 unsigned int needs_freset:1; /* Requires fundamental reset */
437 unsigned int state_saved:1;
438 unsigned int is_physfn:1;
439 unsigned int is_virtfn:1;
440 unsigned int is_hotplug_bridge:1;
441 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
442 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
444 * Devices marked being untrusted are the ones that can potentially
445 * execute DMA attacks and similar. They are typically connected
446 * through external ports such as Thunderbolt but not limited to
447 * that. When an IOMMU is enabled they should be getting full
448 * mappings to make sure they cannot access arbitrary memory.
450 unsigned int untrusted:1;
452 * Info from the platform, e.g., ACPI or device tree, may mark a
453 * device as "external-facing". An external-facing device is
454 * itself internal but devices downstream from it are external.
456 unsigned int external_facing:1;
457 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
458 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
459 unsigned int irq_managed:1;
460 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
461 unsigned int is_probed:1; /* Device probing in progress */
462 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
463 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
464 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
465 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
466 pci_dev_flags_t dev_flags;
467 atomic_t enable_cnt; /* pci_enable_device has been called */
469 u32 saved_config_space[16]; /* Config space saved at suspend time */
470 struct hlist_head saved_cap_space;
471 int rom_attr_enabled; /* Display of ROM attribute enabled? */
472 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
473 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
475 #ifdef CONFIG_HOTPLUG_PCI_PCIE
476 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
478 #ifdef CONFIG_PCIE_PTM
479 u16 ptm_cap; /* PTM Capability */
480 unsigned int ptm_root:1;
481 unsigned int ptm_enabled:1;
484 #ifdef CONFIG_PCI_MSI
485 void __iomem *msix_base;
486 raw_spinlock_t msi_lock;
489 #ifdef CONFIG_PCIE_DPC
491 unsigned int dpc_rp_extensions:1;
494 #ifdef CONFIG_PCI_ATS
496 struct pci_sriov *sriov; /* PF: SR-IOV info */
497 struct pci_dev *physfn; /* VF: related PF */
499 u16 ats_cap; /* ATS Capability offset */
500 u8 ats_stu; /* ATS Smallest Translation Unit */
502 #ifdef CONFIG_PCI_PRI
503 u16 pri_cap; /* PRI Capability offset */
504 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
505 unsigned int pasid_required:1; /* PRG Response PASID Required */
507 #ifdef CONFIG_PCI_PASID
508 u16 pasid_cap; /* PASID Capability offset */
511 #ifdef CONFIG_PCI_P2PDMA
512 struct pci_p2pdma __rcu *p2pdma;
514 u16 acs_cap; /* ACS Capability offset */
515 phys_addr_t rom; /* Physical address if not from BAR */
516 size_t romlen; /* Length if not from BAR */
518 * Driver name to force a match. Do not set directly, because core
519 * frees it. Use driver_set_override() to set or clear it.
521 const char *driver_override;
523 unsigned long priv_flags; /* Private flags for the PCI driver */
525 /* These methods index pci_reset_fn_methods[] */
526 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
529 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
531 #ifdef CONFIG_PCI_IOV
538 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
540 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
541 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
543 static inline int pci_channel_offline(struct pci_dev *pdev)
545 return (pdev->error_state != pci_channel_io_normal);
549 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
550 * Group number is limited to a 16-bit value, therefore (int)-1 is
551 * not a valid PCI domain number, and can be used as a sentinel
552 * value indicating ->domain_nr is not set by the driver (and
553 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
554 * pci_bus_find_domain_nr()).
556 #define PCI_DOMAIN_NR_NOT_SET (-1)
558 struct pci_host_bridge {
560 struct pci_bus *bus; /* Root bus */
562 struct pci_ops *child_ops;
566 struct list_head windows; /* resource_entry */
567 struct list_head dma_ranges; /* dma ranges resource list */
568 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
569 int (*map_irq)(const struct pci_dev *, u8, u8);
570 void (*release_fn)(struct pci_host_bridge *);
572 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
573 unsigned int no_ext_tags:1; /* No Extended Tags */
574 unsigned int native_aer:1; /* OS may use PCIe AER */
575 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
576 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
577 unsigned int native_pme:1; /* OS may use PCIe PME */
578 unsigned int native_ltr:1; /* OS may use PCIe LTR */
579 unsigned int native_dpc:1; /* OS may use PCIe DPC */
580 unsigned int preserve_config:1; /* Preserve FW resource setup */
581 unsigned int size_windows:1; /* Enable root bus sizing */
582 unsigned int msi_domain:1; /* Bridge wants MSI domain */
584 /* Resource alignment requirements */
585 resource_size_t (*align_resource)(struct pci_dev *dev,
586 const struct resource *res,
587 resource_size_t start,
588 resource_size_t size,
589 resource_size_t align);
590 unsigned long private[] ____cacheline_aligned;
593 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
595 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
597 return (void *)bridge->private;
600 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
602 return container_of(priv, struct pci_host_bridge, private);
605 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
606 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
608 void pci_free_host_bridge(struct pci_host_bridge *bridge);
609 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
611 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
612 void (*release_fn)(struct pci_host_bridge *),
615 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
618 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
619 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
620 * buses below host bridges or subtractive decode bridges) go in the list.
621 * Use pci_bus_for_each_resource() to iterate through all the resources.
625 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
626 * and there's no way to program the bridge with the details of the window.
627 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
628 * decode bit set, because they are explicit and can be programmed with _SRS.
630 #define PCI_SUBTRACTIVE_DECODE 0x1
632 struct pci_bus_resource {
633 struct list_head list;
634 struct resource *res;
638 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
641 struct list_head node; /* Node in list of buses */
642 struct pci_bus *parent; /* Parent bus this bridge is on */
643 struct list_head children; /* List of child buses */
644 struct list_head devices; /* List of devices on this bus */
645 struct pci_dev *self; /* Bridge device as seen by parent */
646 struct list_head slots; /* List of slots on this bus;
647 protected by pci_slot_mutex */
648 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
649 struct list_head resources; /* Address space routed to this bus */
650 struct resource busn_res; /* Bus numbers routed to this bus */
652 struct pci_ops *ops; /* Configuration access functions */
653 void *sysdata; /* Hook for sys-specific extension */
654 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
656 unsigned char number; /* Bus number */
657 unsigned char primary; /* Number of primary bridge */
658 unsigned char max_bus_speed; /* enum pci_bus_speed */
659 unsigned char cur_bus_speed; /* enum pci_bus_speed */
660 #ifdef CONFIG_PCI_DOMAINS_GENERIC
666 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
667 pci_bus_flags_t bus_flags; /* Inherited by child buses */
668 struct device *bridge;
670 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
671 struct bin_attribute *legacy_mem; /* Legacy mem */
672 unsigned int is_added:1;
673 unsigned int unsafe_warn:1; /* warned about RW1C config write */
676 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
678 static inline u16 pci_dev_id(struct pci_dev *dev)
680 return PCI_DEVID(dev->bus->number, dev->devfn);
684 * Returns true if the PCI bus is root (behind host-PCI bridge),
687 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
688 * This is incorrect because "virtual" buses added for SR-IOV (via
689 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
691 static inline bool pci_is_root_bus(struct pci_bus *pbus)
693 return !(pbus->parent);
697 * pci_is_bridge - check if the PCI device is a bridge
700 * Return true if the PCI device is bridge whether it has subordinate
703 static inline bool pci_is_bridge(struct pci_dev *dev)
705 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
706 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
709 #define for_each_pci_bridge(dev, bus) \
710 list_for_each_entry(dev, &bus->devices, bus_list) \
711 if (!pci_is_bridge(dev)) {} else
713 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
715 dev = pci_physfn(dev);
716 if (pci_is_root_bus(dev->bus))
719 return dev->bus->self;
722 #ifdef CONFIG_PCI_MSI
723 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
725 return pci_dev->msi_enabled || pci_dev->msix_enabled;
728 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
731 /* Error values that may be returned by PCI functions */
732 #define PCIBIOS_SUCCESSFUL 0x00
733 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
734 #define PCIBIOS_BAD_VENDOR_ID 0x83
735 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
736 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
737 #define PCIBIOS_SET_FAILED 0x88
738 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
740 /* Translate above to generic errno for passing back through non-PCI code */
741 static inline int pcibios_err_to_errno(int err)
743 if (err <= PCIBIOS_SUCCESSFUL)
744 return err; /* Assume already errno */
747 case PCIBIOS_FUNC_NOT_SUPPORTED:
749 case PCIBIOS_BAD_VENDOR_ID:
751 case PCIBIOS_DEVICE_NOT_FOUND:
753 case PCIBIOS_BAD_REGISTER_NUMBER:
755 case PCIBIOS_SET_FAILED:
757 case PCIBIOS_BUFFER_TOO_SMALL:
764 /* Low-level architecture-dependent routines */
767 int (*add_bus)(struct pci_bus *bus);
768 void (*remove_bus)(struct pci_bus *bus);
769 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
770 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
771 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
775 * ACPI needs to be able to access PCI config space before we've done a
776 * PCI bus scan and created pci_bus structures.
778 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
779 int reg, int len, u32 *val);
780 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
781 int reg, int len, u32 val);
783 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
784 typedef u64 pci_bus_addr_t;
786 typedef u32 pci_bus_addr_t;
789 struct pci_bus_region {
790 pci_bus_addr_t start;
795 spinlock_t lock; /* Protects list, index */
796 struct list_head list; /* For IDs added at runtime */
801 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
802 * a set of callbacks in struct pci_error_handlers, that device driver
803 * will be notified of PCI bus errors, and will be driven to recovery
804 * when an error occurs.
807 typedef unsigned int __bitwise pci_ers_result_t;
809 enum pci_ers_result {
810 /* No result/none/not supported in device driver */
811 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
813 /* Device driver can recover without slot reset */
814 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
816 /* Device driver wants slot to be reset */
817 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
819 /* Device has completely failed, is unrecoverable */
820 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
822 /* Device driver is fully recovered and operational */
823 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
825 /* No AER capabilities registered for the driver */
826 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
829 /* PCI bus error event callbacks */
830 struct pci_error_handlers {
831 /* PCI bus error detected on this device */
832 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
833 pci_channel_state_t error);
835 /* MMIO has been re-enabled, but not DMA */
836 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
838 /* PCI slot has been reset */
839 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
841 /* PCI function reset prepare or completed */
842 void (*reset_prepare)(struct pci_dev *dev);
843 void (*reset_done)(struct pci_dev *dev);
845 /* Device driver may resume normal operations */
846 void (*resume)(struct pci_dev *dev);
853 * struct pci_driver - PCI driver structure
854 * @node: List of driver structures.
855 * @name: Driver name.
856 * @id_table: Pointer to table of device IDs the driver is
857 * interested in. Most drivers should export this
858 * table using MODULE_DEVICE_TABLE(pci,...).
859 * @probe: This probing function gets called (during execution
860 * of pci_register_driver() for already existing
861 * devices or later if a new device gets inserted) for
862 * all PCI devices which match the ID table and are not
863 * "owned" by the other drivers yet. This function gets
864 * passed a "struct pci_dev \*" for each device whose
865 * entry in the ID table matches the device. The probe
866 * function returns zero when the driver chooses to
867 * take "ownership" of the device or an error code
868 * (negative number) otherwise.
869 * The probe function always gets called from process
870 * context, so it can sleep.
871 * @remove: The remove() function gets called whenever a device
872 * being handled by this driver is removed (either during
873 * deregistration of the driver or when it's manually
874 * pulled out of a hot-pluggable slot).
875 * The remove function always gets called from process
876 * context, so it can sleep.
877 * @suspend: Put device into low power state.
878 * @resume: Wake device from low power state.
879 * (Please see Documentation/power/pci.rst for descriptions
880 * of PCI Power Management and the related functions.)
881 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
882 * Intended to stop any idling DMA operations.
883 * Useful for enabling wake-on-lan (NIC) or changing
884 * the power state of a device before reboot.
885 * e.g. drivers/net/e100.c.
886 * @sriov_configure: Optional driver callback to allow configuration of
887 * number of VFs to enable via sysfs "sriov_numvfs" file.
888 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
889 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
890 * This will change MSI-X Table Size in the VF Message Control
892 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
893 * MSI-X vectors available for distribution to the VFs.
894 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
895 * @groups: Sysfs attribute groups.
896 * @dev_groups: Attributes attached to the device that will be
897 * created once it is bound to the driver.
898 * @driver: Driver model structure.
899 * @dynids: List of dynamically added device IDs.
900 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
901 * For most device drivers, no need to care about this flag
902 * as long as all DMAs are handled through the kernel DMA API.
903 * For some special ones, for example VFIO drivers, they know
904 * how to manage the DMA themselves and set this flag so that
905 * the IOMMU layer will allow them to setup and manage their
906 * own I/O address space.
909 struct list_head node;
911 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
912 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
913 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
914 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
915 int (*resume)(struct pci_dev *dev); /* Device woken up */
916 void (*shutdown)(struct pci_dev *dev);
917 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
918 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
919 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
920 const struct pci_error_handlers *err_handler;
921 const struct attribute_group **groups;
922 const struct attribute_group **dev_groups;
923 struct device_driver driver;
924 struct pci_dynids dynids;
925 bool driver_managed_dma;
928 static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
930 return drv ? container_of(drv, struct pci_driver, driver) : NULL;
934 * PCI_DEVICE - macro used to describe a specific PCI device
935 * @vend: the 16 bit PCI Vendor ID
936 * @dev: the 16 bit PCI Device ID
938 * This macro is used to create a struct pci_device_id that matches a
939 * specific device. The subvendor and subdevice fields will be set to
942 #define PCI_DEVICE(vend,dev) \
943 .vendor = (vend), .device = (dev), \
944 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
947 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
948 * override_only flags.
949 * @vend: the 16 bit PCI Vendor ID
950 * @dev: the 16 bit PCI Device ID
951 * @driver_override: the 32 bit PCI Device override_only
953 * This macro is used to create a struct pci_device_id that matches only a
954 * driver_override device. The subvendor and subdevice fields will be set to
957 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
958 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
959 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
962 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
963 * "driver_override" PCI device.
964 * @vend: the 16 bit PCI Vendor ID
965 * @dev: the 16 bit PCI Device ID
967 * This macro is used to create a struct pci_device_id that matches a
968 * specific device. The subvendor and subdevice fields will be set to
969 * PCI_ANY_ID and the driver_override will be set to
970 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
972 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
973 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
976 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
977 * @vend: the 16 bit PCI Vendor ID
978 * @dev: the 16 bit PCI Device ID
979 * @subvend: the 16 bit PCI Subvendor ID
980 * @subdev: the 16 bit PCI Subdevice ID
982 * This macro is used to create a struct pci_device_id that matches a
983 * specific device with subsystem information.
985 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
986 .vendor = (vend), .device = (dev), \
987 .subvendor = (subvend), .subdevice = (subdev)
990 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
991 * @dev_class: the class, subclass, prog-if triple for this device
992 * @dev_class_mask: the class mask for this device
994 * This macro is used to create a struct pci_device_id that matches a
995 * specific PCI class. The vendor, device, subvendor, and subdevice
996 * fields will be set to PCI_ANY_ID.
998 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
999 .class = (dev_class), .class_mask = (dev_class_mask), \
1000 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1001 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1004 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1005 * @vend: the vendor name
1006 * @dev: the 16 bit PCI Device ID
1008 * This macro is used to create a struct pci_device_id that matches a
1009 * specific PCI device. The subvendor, and subdevice fields will be set
1010 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1013 #define PCI_VDEVICE(vend, dev) \
1014 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1015 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1018 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1019 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1020 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1021 * @data: the driver data to be filled
1023 * This macro is used to create a struct pci_device_id that matches a
1024 * specific PCI device. The subvendor, and subdevice fields will be set
1027 #define PCI_DEVICE_DATA(vend, dev, data) \
1028 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1029 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1030 .driver_data = (kernel_ulong_t)(data)
1033 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1034 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1035 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1036 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1037 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1038 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1039 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1042 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1043 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1044 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1045 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1047 /* These external functions are only available when PCI support is enabled */
1050 extern unsigned int pci_flags;
1052 static inline void pci_set_flags(int flags) { pci_flags = flags; }
1053 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1054 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1055 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1057 void pcie_bus_configure_settings(struct pci_bus *bus);
1059 enum pcie_bus_config_types {
1060 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1061 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1062 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1063 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1064 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1067 extern enum pcie_bus_config_types pcie_bus_config;
1069 extern struct bus_type pci_bus_type;
1071 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1072 * code, or PCI core code. */
1073 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1074 /* Some device drivers need know if PCI is initiated */
1075 int no_pci_devices(void);
1077 void pcibios_resource_survey_bus(struct pci_bus *bus);
1078 void pcibios_bus_add_device(struct pci_dev *pdev);
1079 void pcibios_add_bus(struct pci_bus *bus);
1080 void pcibios_remove_bus(struct pci_bus *bus);
1081 void pcibios_fixup_bus(struct pci_bus *);
1082 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1083 /* Architecture-specific versions may override this (weak) */
1084 char *pcibios_setup(char *str);
1086 /* Used only when drivers/pci/setup.c is used */
1087 resource_size_t pcibios_align_resource(void *, const struct resource *,
1091 /* Weak but can be overridden by arch */
1092 void pci_fixup_cardbus(struct pci_bus *);
1094 /* Generic PCI functions used internally */
1096 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1097 struct resource *res);
1098 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1099 struct pci_bus_region *region);
1100 void pcibios_scan_specific_bus(int busn);
1101 struct pci_bus *pci_find_bus(int domain, int busnr);
1102 void pci_bus_add_devices(const struct pci_bus *bus);
1103 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1104 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1105 struct pci_ops *ops, void *sysdata,
1106 struct list_head *resources);
1107 int pci_host_probe(struct pci_host_bridge *bridge);
1108 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1109 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1110 void pci_bus_release_busn_res(struct pci_bus *b);
1111 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1112 struct pci_ops *ops, void *sysdata,
1113 struct list_head *resources);
1114 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1115 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1117 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1119 struct hotplug_slot *hotplug);
1120 void pci_destroy_slot(struct pci_slot *slot);
1122 void pci_dev_assign_slot(struct pci_dev *dev);
1124 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1126 int pci_scan_slot(struct pci_bus *bus, int devfn);
1127 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1128 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1129 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1130 void pci_bus_add_device(struct pci_dev *dev);
1131 void pci_read_bridge_bases(struct pci_bus *child);
1132 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1133 struct resource *res);
1134 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1135 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1136 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1137 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1138 void pci_dev_put(struct pci_dev *dev);
1139 void pci_remove_bus(struct pci_bus *b);
1140 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1141 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1142 void pci_stop_root_bus(struct pci_bus *bus);
1143 void pci_remove_root_bus(struct pci_bus *bus);
1144 void pci_setup_cardbus(struct pci_bus *bus);
1145 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1146 void pci_sort_breadthfirst(void);
1147 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1148 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1150 /* Generic PCI functions exported to card drivers */
1152 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1153 u8 pci_find_capability(struct pci_dev *dev, int cap);
1154 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1155 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1156 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1157 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1158 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1159 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1160 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1161 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1163 u64 pci_get_dsn(struct pci_dev *dev);
1165 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1166 struct pci_dev *from);
1167 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1168 unsigned int ss_vendor, unsigned int ss_device,
1169 struct pci_dev *from);
1170 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1171 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1172 unsigned int devfn);
1173 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1174 int pci_dev_present(const struct pci_device_id *ids);
1176 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1177 int where, u8 *val);
1178 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1179 int where, u16 *val);
1180 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1181 int where, u32 *val);
1182 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1184 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1185 int where, u16 val);
1186 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1187 int where, u32 val);
1189 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1190 int where, int size, u32 *val);
1191 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1192 int where, int size, u32 val);
1193 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1194 int where, int size, u32 *val);
1195 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1196 int where, int size, u32 val);
1198 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1200 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1201 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1202 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1203 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1204 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1205 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1207 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1208 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1209 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1210 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1211 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1212 u16 clear, u16 set);
1213 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1214 u32 clear, u32 set);
1216 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1219 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1222 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1225 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1228 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1231 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1234 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1237 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1240 /* User-space driven config access */
1241 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1242 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1243 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1244 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1245 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1246 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1248 int __must_check pci_enable_device(struct pci_dev *dev);
1249 int __must_check pci_enable_device_io(struct pci_dev *dev);
1250 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1251 int __must_check pci_reenable_device(struct pci_dev *);
1252 int __must_check pcim_enable_device(struct pci_dev *pdev);
1253 void pcim_pin_device(struct pci_dev *pdev);
1255 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1258 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1259 * writable and no quirk has marked the feature broken.
1261 return !pdev->broken_intx_masking;
1264 static inline int pci_is_enabled(struct pci_dev *pdev)
1266 return (atomic_read(&pdev->enable_cnt) > 0);
1269 static inline int pci_is_managed(struct pci_dev *pdev)
1271 return pdev->is_managed;
1274 void pci_disable_device(struct pci_dev *dev);
1276 extern unsigned int pcibios_max_latency;
1277 void pci_set_master(struct pci_dev *dev);
1278 void pci_clear_master(struct pci_dev *dev);
1280 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1281 int pci_set_cacheline_size(struct pci_dev *dev);
1282 int __must_check pci_set_mwi(struct pci_dev *dev);
1283 int __must_check pcim_set_mwi(struct pci_dev *dev);
1284 int pci_try_set_mwi(struct pci_dev *dev);
1285 void pci_clear_mwi(struct pci_dev *dev);
1286 void pci_disable_parity(struct pci_dev *dev);
1287 void pci_intx(struct pci_dev *dev, int enable);
1288 bool pci_check_and_mask_intx(struct pci_dev *dev);
1289 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1290 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1291 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1292 int pcix_get_max_mmrbc(struct pci_dev *dev);
1293 int pcix_get_mmrbc(struct pci_dev *dev);
1294 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1295 int pcie_get_readrq(struct pci_dev *dev);
1296 int pcie_set_readrq(struct pci_dev *dev, int rq);
1297 int pcie_get_mps(struct pci_dev *dev);
1298 int pcie_set_mps(struct pci_dev *dev, int mps);
1299 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1300 enum pci_bus_speed *speed,
1301 enum pcie_link_width *width);
1302 void pcie_print_link_status(struct pci_dev *dev);
1303 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1304 int pcie_flr(struct pci_dev *dev);
1305 int __pci_reset_function_locked(struct pci_dev *dev);
1306 int pci_reset_function(struct pci_dev *dev);
1307 int pci_reset_function_locked(struct pci_dev *dev);
1308 int pci_try_reset_function(struct pci_dev *dev);
1309 int pci_probe_reset_slot(struct pci_slot *slot);
1310 int pci_probe_reset_bus(struct pci_bus *bus);
1311 int pci_reset_bus(struct pci_dev *dev);
1312 void pci_reset_secondary_bus(struct pci_dev *dev);
1313 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1314 void pci_update_resource(struct pci_dev *dev, int resno);
1315 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1316 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1317 void pci_release_resource(struct pci_dev *dev, int resno);
1318 static inline int pci_rebar_bytes_to_size(u64 bytes)
1320 bytes = roundup_pow_of_two(bytes);
1322 /* Return BAR size as defined in the resizable BAR specification */
1323 return max(ilog2(bytes), 20) - 20;
1326 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1327 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1328 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1329 bool pci_device_is_present(struct pci_dev *pdev);
1330 void pci_ignore_hotplug(struct pci_dev *dev);
1331 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1332 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1334 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1335 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1336 const char *fmt, ...);
1337 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1339 /* ROM control related routines */
1340 int pci_enable_rom(struct pci_dev *pdev);
1341 void pci_disable_rom(struct pci_dev *pdev);
1342 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1343 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1345 /* Power management related routines */
1346 int pci_save_state(struct pci_dev *dev);
1347 void pci_restore_state(struct pci_dev *dev);
1348 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1349 int pci_load_saved_state(struct pci_dev *dev,
1350 struct pci_saved_state *state);
1351 int pci_load_and_free_saved_state(struct pci_dev *dev,
1352 struct pci_saved_state **state);
1353 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1354 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1355 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1356 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1357 void pci_pme_active(struct pci_dev *dev, bool enable);
1358 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1359 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1360 int pci_prepare_to_sleep(struct pci_dev *dev);
1361 int pci_back_from_sleep(struct pci_dev *dev);
1362 bool pci_dev_run_wake(struct pci_dev *dev);
1363 void pci_d3cold_enable(struct pci_dev *dev);
1364 void pci_d3cold_disable(struct pci_dev *dev);
1365 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1366 void pci_resume_bus(struct pci_bus *bus);
1367 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1369 /* For use by arch with custom probe code */
1370 void set_pcie_port_type(struct pci_dev *pdev);
1371 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1373 /* Functions for PCI Hotplug drivers to use */
1374 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1375 unsigned int pci_rescan_bus(struct pci_bus *bus);
1376 void pci_lock_rescan_remove(void);
1377 void pci_unlock_rescan_remove(void);
1379 /* Vital Product Data routines */
1380 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1381 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1382 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1383 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1385 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1386 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1387 void pci_bus_assign_resources(const struct pci_bus *bus);
1388 void pci_bus_claim_resources(struct pci_bus *bus);
1389 void pci_bus_size_bridges(struct pci_bus *bus);
1390 int pci_claim_resource(struct pci_dev *, int);
1391 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1392 void pci_assign_unassigned_resources(void);
1393 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1394 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1395 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1396 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1397 void pdev_enable_device(struct pci_dev *);
1398 int pci_enable_resources(struct pci_dev *, int mask);
1399 void pci_assign_irq(struct pci_dev *dev);
1400 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1401 #define HAVE_PCI_REQ_REGIONS 2
1402 int __must_check pci_request_regions(struct pci_dev *, const char *);
1403 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1404 void pci_release_regions(struct pci_dev *);
1405 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1406 void pci_release_region(struct pci_dev *, int);
1407 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1408 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1409 void pci_release_selected_regions(struct pci_dev *, int);
1411 /* drivers/pci/bus.c */
1412 void pci_add_resource(struct list_head *resources, struct resource *res);
1413 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1414 resource_size_t offset);
1415 void pci_free_resource_list(struct list_head *resources);
1416 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1417 unsigned int flags);
1418 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1419 void pci_bus_remove_resources(struct pci_bus *bus);
1420 int devm_request_pci_bus_resources(struct device *dev,
1421 struct list_head *resources);
1423 /* Temporary until new and working PCI SBR API in place */
1424 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1426 #define pci_bus_for_each_resource(bus, res, i) \
1428 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1431 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1432 struct resource *res, resource_size_t size,
1433 resource_size_t align, resource_size_t min,
1434 unsigned long type_mask,
1435 resource_size_t (*alignf)(void *,
1436 const struct resource *,
1442 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1443 resource_size_t size);
1444 unsigned long pci_address_to_pio(phys_addr_t addr);
1445 phys_addr_t pci_pio_to_address(unsigned long pio);
1446 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1447 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1448 phys_addr_t phys_addr);
1449 void pci_unmap_iospace(struct resource *res);
1450 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1451 resource_size_t offset,
1452 resource_size_t size);
1453 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1454 struct resource *res);
1456 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1458 struct pci_bus_region region;
1460 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1461 return region.start;
1464 /* Proper probing supporting hot-pluggable devices */
1465 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1466 const char *mod_name);
1468 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1469 #define pci_register_driver(driver) \
1470 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1472 void pci_unregister_driver(struct pci_driver *dev);
1475 * module_pci_driver() - Helper macro for registering a PCI driver
1476 * @__pci_driver: pci_driver struct
1478 * Helper macro for PCI drivers which do not do anything special in module
1479 * init/exit. This eliminates a lot of boilerplate. Each module may only
1480 * use this macro once, and calling it replaces module_init() and module_exit()
1482 #define module_pci_driver(__pci_driver) \
1483 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1486 * builtin_pci_driver() - Helper macro for registering a PCI driver
1487 * @__pci_driver: pci_driver struct
1489 * Helper macro for PCI drivers which do not do anything special in their
1490 * init code. This eliminates a lot of boilerplate. Each driver may only
1491 * use this macro once, and calling it replaces device_initcall(...)
1493 #define builtin_pci_driver(__pci_driver) \
1494 builtin_driver(__pci_driver, pci_register_driver)
1496 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1497 int pci_add_dynid(struct pci_driver *drv,
1498 unsigned int vendor, unsigned int device,
1499 unsigned int subvendor, unsigned int subdevice,
1500 unsigned int class, unsigned int class_mask,
1501 unsigned long driver_data);
1502 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1503 struct pci_dev *dev);
1504 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1507 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1509 int pci_cfg_space_size(struct pci_dev *dev);
1510 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1511 void pci_setup_bridge(struct pci_bus *bus);
1512 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1513 unsigned long type);
1515 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1516 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1518 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1519 unsigned int command_bits, u32 flags);
1522 * Virtual interrupts allow for more interrupts to be allocated
1523 * than the device has interrupts for. These are not programmed
1524 * into the device's MSI-X table and must be handled by some
1525 * other driver means.
1527 #define PCI_IRQ_VIRTUAL (1 << 4)
1529 #define PCI_IRQ_ALL_TYPES \
1530 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1532 #include <linux/dmapool.h>
1535 u32 vector; /* Kernel uses to write allocated vector */
1536 u16 entry; /* Driver uses to specify entry, OS writes */
1539 #ifdef CONFIG_PCI_MSI
1540 int pci_msi_vec_count(struct pci_dev *dev);
1541 void pci_disable_msi(struct pci_dev *dev);
1542 int pci_msix_vec_count(struct pci_dev *dev);
1543 void pci_disable_msix(struct pci_dev *dev);
1544 void pci_restore_msi_state(struct pci_dev *dev);
1545 int pci_msi_enabled(void);
1546 int pci_enable_msi(struct pci_dev *dev);
1547 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1548 int minvec, int maxvec);
1549 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1550 struct msix_entry *entries, int nvec)
1552 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1557 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1558 unsigned int max_vecs, unsigned int flags);
1559 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1560 unsigned int max_vecs, unsigned int flags,
1561 struct irq_affinity *affd);
1563 bool pci_msix_can_alloc_dyn(struct pci_dev *dev);
1564 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1565 const struct irq_affinity_desc *affdesc);
1566 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
1568 void pci_free_irq_vectors(struct pci_dev *dev);
1569 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1570 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1573 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1574 static inline void pci_disable_msi(struct pci_dev *dev) { }
1575 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1576 static inline void pci_disable_msix(struct pci_dev *dev) { }
1577 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1578 static inline int pci_msi_enabled(void) { return 0; }
1579 static inline int pci_enable_msi(struct pci_dev *dev)
1581 static inline int pci_enable_msix_range(struct pci_dev *dev,
1582 struct msix_entry *entries, int minvec, int maxvec)
1584 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1585 struct msix_entry *entries, int nvec)
1589 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1590 unsigned int max_vecs, unsigned int flags,
1591 struct irq_affinity *aff_desc)
1593 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1598 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1599 unsigned int max_vecs, unsigned int flags)
1601 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,
1605 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1609 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1611 if (WARN_ON_ONCE(nr > 0))
1615 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1618 return cpu_possible_mask;
1623 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1624 * @d: the INTx IRQ domain
1625 * @node: the DT node for the device whose interrupt we're translating
1626 * @intspec: the interrupt specifier data from the DT
1627 * @intsize: the number of entries in @intspec
1628 * @out_hwirq: pointer at which to write the hwirq number
1629 * @out_type: pointer at which to write the interrupt type
1631 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1632 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1633 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1634 * INTx value to obtain the hwirq number.
1636 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1638 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1639 struct device_node *node,
1641 unsigned int intsize,
1642 unsigned long *out_hwirq,
1643 unsigned int *out_type)
1645 const u32 intx = intspec[0];
1647 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1650 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1654 #ifdef CONFIG_PCIEPORTBUS
1655 extern bool pcie_ports_disabled;
1656 extern bool pcie_ports_native;
1658 #define pcie_ports_disabled true
1659 #define pcie_ports_native false
1662 #define PCIE_LINK_STATE_L0S BIT(0)
1663 #define PCIE_LINK_STATE_L1 BIT(1)
1664 #define PCIE_LINK_STATE_CLKPM BIT(2)
1665 #define PCIE_LINK_STATE_L1_1 BIT(3)
1666 #define PCIE_LINK_STATE_L1_2 BIT(4)
1667 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1668 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1670 #ifdef CONFIG_PCIEASPM
1671 int pci_disable_link_state(struct pci_dev *pdev, int state);
1672 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1673 void pcie_no_aspm(void);
1674 bool pcie_aspm_support_enabled(void);
1675 bool pcie_aspm_enabled(struct pci_dev *pdev);
1677 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1679 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1681 static inline void pcie_no_aspm(void) { }
1682 static inline bool pcie_aspm_support_enabled(void) { return false; }
1683 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1686 #ifdef CONFIG_PCIEAER
1687 bool pci_aer_available(void);
1689 static inline bool pci_aer_available(void) { return false; }
1692 bool pci_ats_disabled(void);
1694 #ifdef CONFIG_PCIE_PTM
1695 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1696 void pci_disable_ptm(struct pci_dev *dev);
1697 bool pcie_ptm_enabled(struct pci_dev *dev);
1699 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1701 static inline void pci_disable_ptm(struct pci_dev *dev) { }
1702 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1706 void pci_cfg_access_lock(struct pci_dev *dev);
1707 bool pci_cfg_access_trylock(struct pci_dev *dev);
1708 void pci_cfg_access_unlock(struct pci_dev *dev);
1710 void pci_dev_lock(struct pci_dev *dev);
1711 int pci_dev_trylock(struct pci_dev *dev);
1712 void pci_dev_unlock(struct pci_dev *dev);
1715 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1716 * a PCI domain is defined to be a set of PCI buses which share
1717 * configuration space.
1719 #ifdef CONFIG_PCI_DOMAINS
1720 extern int pci_domains_supported;
1722 enum { pci_domains_supported = 0 };
1723 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1724 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1725 #endif /* CONFIG_PCI_DOMAINS */
1728 * Generic implementation for PCI domain support. If your
1729 * architecture does not need custom management of PCI
1730 * domains then this implementation will be used
1732 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1733 static inline int pci_domain_nr(struct pci_bus *bus)
1735 return bus->domain_nr;
1738 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1740 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1743 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1746 /* Some architectures require additional setup to direct VGA traffic */
1747 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1748 unsigned int command_bits, u32 flags);
1749 void pci_register_set_vga_state(arch_set_vga_state_t func);
1752 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1754 return pci_request_selected_regions(pdev,
1755 pci_select_bars(pdev, IORESOURCE_IO), name);
1759 pci_release_io_regions(struct pci_dev *pdev)
1761 return pci_release_selected_regions(pdev,
1762 pci_select_bars(pdev, IORESOURCE_IO));
1766 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1768 return pci_request_selected_regions(pdev,
1769 pci_select_bars(pdev, IORESOURCE_MEM), name);
1773 pci_release_mem_regions(struct pci_dev *pdev)
1775 return pci_release_selected_regions(pdev,
1776 pci_select_bars(pdev, IORESOURCE_MEM));
1779 #else /* CONFIG_PCI is not enabled */
1781 static inline void pci_set_flags(int flags) { }
1782 static inline void pci_add_flags(int flags) { }
1783 static inline void pci_clear_flags(int flags) { }
1784 static inline int pci_has_flag(int flag) { return 0; }
1787 * If the system does not have PCI, clearly these return errors. Define
1788 * these as simple inline functions to avoid hair in drivers.
1790 #define _PCI_NOP(o, s, t) \
1791 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1793 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1795 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1796 _PCI_NOP(o, word, u16 x) \
1797 _PCI_NOP(o, dword, u32 x)
1798 _PCI_NOP_ALL(read, *)
1799 _PCI_NOP_ALL(write,)
1801 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1802 unsigned int device,
1803 struct pci_dev *from)
1806 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1807 unsigned int device,
1808 unsigned int ss_vendor,
1809 unsigned int ss_device,
1810 struct pci_dev *from)
1813 static inline struct pci_dev *pci_get_class(unsigned int class,
1814 struct pci_dev *from)
1818 static inline int pci_dev_present(const struct pci_device_id *ids)
1821 #define no_pci_devices() (1)
1822 #define pci_dev_put(dev) do { } while (0)
1824 static inline void pci_set_master(struct pci_dev *dev) { }
1825 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1826 static inline void pci_disable_device(struct pci_dev *dev) { }
1827 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1828 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1830 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1831 struct module *owner,
1832 const char *mod_name)
1834 static inline int pci_register_driver(struct pci_driver *drv)
1836 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1837 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1839 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1842 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1845 static inline u64 pci_get_dsn(struct pci_dev *dev)
1848 /* Power management related routines */
1849 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1850 static inline void pci_restore_state(struct pci_dev *dev) { }
1851 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1853 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1855 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1858 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1862 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1863 struct resource *res)
1865 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1867 static inline void pci_release_regions(struct pci_dev *dev) { }
1869 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1870 phys_addr_t addr, resource_size_t size)
1873 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1875 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1877 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1880 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1881 unsigned int bus, unsigned int devfn)
1884 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1885 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1887 #define dev_is_pci(d) (false)
1888 #define dev_is_pf(d) (false)
1889 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1891 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1892 struct device_node *node,
1894 unsigned int intsize,
1895 unsigned long *out_hwirq,
1896 unsigned int *out_type)
1899 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1900 struct pci_dev *dev)
1902 static inline bool pci_ats_disabled(void) { return true; }
1904 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1910 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1911 unsigned int max_vecs, unsigned int flags,
1912 struct irq_affinity *aff_desc)
1917 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1918 unsigned int max_vecs, unsigned int flags)
1922 #endif /* CONFIG_PCI */
1924 /* Include architecture-dependent settings and functions */
1926 #include <asm/pci.h>
1929 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1930 * is expected to be an offset within that region.
1933 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1934 struct vm_area_struct *vma,
1935 enum pci_mmap_state mmap_state, int write_combine);
1937 #ifndef arch_can_pci_mmap_wc
1938 #define arch_can_pci_mmap_wc() 0
1941 #ifndef arch_can_pci_mmap_io
1942 #define arch_can_pci_mmap_io() 0
1943 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1945 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1948 #ifndef pci_root_bus_fwnode
1949 #define pci_root_bus_fwnode(bus) NULL
1953 * These helpers provide future and backwards compatibility
1954 * for accessing popular PCI BAR info
1956 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1957 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1958 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1959 #define pci_resource_len(dev,bar) \
1960 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1962 (pci_resource_end((dev), (bar)) - \
1963 pci_resource_start((dev), (bar)) + 1))
1966 * Similar to the helpers above, these manipulate per-pci_dev
1967 * driver-specific data. They are really just a wrapper around
1968 * the generic device structure functions of these calls.
1970 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1972 return dev_get_drvdata(&pdev->dev);
1975 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1977 dev_set_drvdata(&pdev->dev, data);
1980 static inline const char *pci_name(const struct pci_dev *pdev)
1982 return dev_name(&pdev->dev);
1985 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1986 const struct resource *rsrc,
1987 resource_size_t *start, resource_size_t *end);
1990 * The world is not perfect and supplies us with broken PCI devices.
1991 * For at least a part of these bugs we need a work-around, so both
1992 * generic (drivers/pci/quirks.c) and per-architecture code can define
1993 * fixup hooks to be called for particular buggy devices.
1997 u16 vendor; /* Or PCI_ANY_ID */
1998 u16 device; /* Or PCI_ANY_ID */
1999 u32 class; /* Or PCI_ANY_ID */
2000 unsigned int class_shift; /* should be 0, 8, 16 */
2001 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2004 void (*hook)(struct pci_dev *dev);
2008 enum pci_fixup_pass {
2009 pci_fixup_early, /* Before probing BARs */
2010 pci_fixup_header, /* After reading configuration header */
2011 pci_fixup_final, /* Final phase of device fixups */
2012 pci_fixup_enable, /* pci_enable_device() time */
2013 pci_fixup_resume, /* pci_device_resume() */
2014 pci_fixup_suspend, /* pci_device_suspend() */
2015 pci_fixup_resume_early, /* pci_device_resume_early() */
2016 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2019 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2020 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2021 class_shift, hook) \
2022 __ADDRESSABLE(hook) \
2023 asm(".section " #sec ", \"a\" \n" \
2025 ".short " #vendor ", " #device " \n" \
2026 ".long " #class ", " #class_shift " \n" \
2027 ".long " #hook " - . \n" \
2031 * Clang's LTO may rename static functions in C, but has no way to
2032 * handle such renamings when referenced from inline asm. To work
2033 * around this, create global C stubs for these cases.
2035 #ifdef CONFIG_LTO_CLANG
2036 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2037 class_shift, hook, stub) \
2038 void stub(struct pci_dev *dev); \
2039 void stub(struct pci_dev *dev) \
2043 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2046 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2047 class_shift, hook, stub) \
2048 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2052 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2053 class_shift, hook) \
2054 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2055 class_shift, hook, __UNIQUE_ID(hook))
2057 /* Anonymous variables would be nice... */
2058 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2059 class_shift, hook) \
2060 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2061 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2062 = { vendor, device, class, class_shift, hook };
2065 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2066 class_shift, hook) \
2067 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2068 hook, vendor, device, class, class_shift, hook)
2069 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2070 class_shift, hook) \
2071 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2072 hook, vendor, device, class, class_shift, hook)
2073 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2074 class_shift, hook) \
2075 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2076 hook, vendor, device, class, class_shift, hook)
2077 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2078 class_shift, hook) \
2079 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2080 hook, vendor, device, class, class_shift, hook)
2081 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2082 class_shift, hook) \
2083 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2084 resume##hook, vendor, device, class, class_shift, hook)
2085 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2086 class_shift, hook) \
2087 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2088 resume_early##hook, vendor, device, class, class_shift, hook)
2089 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2090 class_shift, hook) \
2091 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2092 suspend##hook, vendor, device, class, class_shift, hook)
2093 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2094 class_shift, hook) \
2095 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2096 suspend_late##hook, vendor, device, class, class_shift, hook)
2098 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2099 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2100 hook, vendor, device, PCI_ANY_ID, 0, hook)
2101 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2102 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2103 hook, vendor, device, PCI_ANY_ID, 0, hook)
2104 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2105 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2106 hook, vendor, device, PCI_ANY_ID, 0, hook)
2107 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2108 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2109 hook, vendor, device, PCI_ANY_ID, 0, hook)
2110 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2111 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2112 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2113 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2114 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2115 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2116 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2117 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2118 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2119 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2120 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2121 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2123 #ifdef CONFIG_PCI_QUIRKS
2124 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2126 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2127 struct pci_dev *dev) { }
2130 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2131 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2132 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2133 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2134 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2136 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2138 extern int pci_pci_problems;
2139 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2140 #define PCIPCI_TRITON 2
2141 #define PCIPCI_NATOMA 4
2142 #define PCIPCI_VIAETBF 8
2143 #define PCIPCI_VSFX 16
2144 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2145 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2147 extern unsigned long pci_cardbus_io_size;
2148 extern unsigned long pci_cardbus_mem_size;
2149 extern u8 pci_dfl_cache_line_size;
2150 extern u8 pci_cache_line_size;
2152 /* Architecture-specific versions may override these (weak) */
2153 void pcibios_disable_device(struct pci_dev *dev);
2154 void pcibios_set_master(struct pci_dev *dev);
2155 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2156 enum pcie_reset_state state);
2157 int pcibios_device_add(struct pci_dev *dev);
2158 void pcibios_release_device(struct pci_dev *dev);
2160 void pcibios_penalize_isa_irq(int irq, int active);
2162 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2164 int pcibios_alloc_irq(struct pci_dev *dev);
2165 void pcibios_free_irq(struct pci_dev *dev);
2166 resource_size_t pcibios_default_alignment(void);
2168 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2169 void __init pci_mmcfg_early_init(void);
2170 void __init pci_mmcfg_late_init(void);
2172 static inline void pci_mmcfg_early_init(void) { }
2173 static inline void pci_mmcfg_late_init(void) { }
2176 int pci_ext_cfg_avail(void);
2178 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2179 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2181 #ifdef CONFIG_PCI_IOV
2182 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2183 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2184 int pci_iov_vf_id(struct pci_dev *dev);
2185 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2186 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2187 void pci_disable_sriov(struct pci_dev *dev);
2189 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2190 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2191 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2192 int pci_num_vf(struct pci_dev *dev);
2193 int pci_vfs_assigned(struct pci_dev *dev);
2194 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2195 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2196 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2197 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2198 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2200 /* Arch may override these (weak) */
2201 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2202 int pcibios_sriov_disable(struct pci_dev *pdev);
2203 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2205 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2209 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2214 static inline int pci_iov_vf_id(struct pci_dev *dev)
2219 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2220 struct pci_driver *pf_driver)
2222 return ERR_PTR(-EINVAL);
2225 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2228 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2229 struct pci_dev *virtfn, int id)
2233 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2237 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2239 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2240 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2241 static inline int pci_vfs_assigned(struct pci_dev *dev)
2243 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2245 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2247 #define pci_sriov_configure_simple NULL
2248 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2250 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2253 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2254 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2255 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2259 * pci_pcie_cap - get the saved PCIe capability offset
2262 * PCIe capability offset is calculated at PCI device initialization
2263 * time and saved in the data structure. This function returns saved
2264 * PCIe capability offset. Using this instead of pci_find_capability()
2265 * reduces unnecessary search in the PCI configuration space. If you
2266 * need to calculate PCIe capability offset from raw device for some
2267 * reasons, please use pci_find_capability() instead.
2269 static inline int pci_pcie_cap(struct pci_dev *dev)
2271 return dev->pcie_cap;
2275 * pci_is_pcie - check if the PCI device is PCI Express capable
2278 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2280 static inline bool pci_is_pcie(struct pci_dev *dev)
2282 return pci_pcie_cap(dev);
2286 * pcie_caps_reg - get the PCIe Capabilities Register
2289 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2291 return dev->pcie_flags_reg;
2295 * pci_pcie_type - get the PCIe device/port type
2298 static inline int pci_pcie_type(const struct pci_dev *dev)
2300 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2304 * pcie_find_root_port - Get the PCIe root port device
2307 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2308 * for a given PCI/PCIe Device.
2310 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2313 if (pci_is_pcie(dev) &&
2314 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2316 dev = pci_upstream_bridge(dev);
2322 void pci_request_acs(void);
2323 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2324 bool pci_acs_path_enabled(struct pci_dev *start,
2325 struct pci_dev *end, u16 acs_flags);
2326 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2328 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2329 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2331 /* Large Resource Data Type Tag Item Names */
2332 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2333 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2334 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2336 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2337 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2338 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2340 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2341 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2342 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2343 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2344 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2347 * pci_vpd_alloc - Allocate buffer and read VPD into it
2349 * @size: pointer to field where VPD length is returned
2351 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2353 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2356 * pci_vpd_find_id_string - Locate id string in VPD
2357 * @buf: Pointer to buffered VPD data
2358 * @len: The length of the buffer area in which to search
2359 * @size: Pointer to field where length of id string is returned
2361 * Returns the index of the id string or -ENOENT if not found.
2363 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2366 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2367 * @buf: Pointer to buffered VPD data
2368 * @len: The length of the buffer area in which to search
2369 * @kw: The keyword to search for
2370 * @size: Pointer to field where length of found keyword data is returned
2372 * Returns the index of the information field keyword data or -ENOENT if
2375 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2376 const char *kw, unsigned int *size);
2379 * pci_vpd_check_csum - Check VPD checksum
2380 * @buf: Pointer to buffered VPD data
2383 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2385 int pci_vpd_check_csum(const void *buf, unsigned int len);
2387 /* PCI <-> OF binding helpers */
2391 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2392 bool pci_host_of_has_msi_map(struct device *dev);
2394 /* Arch may override this (weak) */
2395 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2397 #else /* CONFIG_OF */
2398 static inline struct irq_domain *
2399 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2400 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2401 #endif /* CONFIG_OF */
2403 static inline struct device_node *
2404 pci_device_to_OF_node(const struct pci_dev *pdev)
2406 return pdev ? pdev->dev.of_node : NULL;
2409 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2411 return bus ? bus->dev.of_node : NULL;
2415 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2418 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2419 bool pci_pr3_present(struct pci_dev *pdev);
2421 static inline struct irq_domain *
2422 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2423 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2427 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2429 return pdev->dev.archdata.edev;
2433 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2434 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2435 int pci_for_each_dma_alias(struct pci_dev *pdev,
2436 int (*fn)(struct pci_dev *pdev,
2437 u16 alias, void *data), void *data);
2439 /* Helper functions for operation of device flag */
2440 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2442 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2444 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2446 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2448 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2450 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2454 * pci_ari_enabled - query ARI forwarding status
2457 * Returns true if ARI forwarding is enabled.
2459 static inline bool pci_ari_enabled(struct pci_bus *bus)
2461 return bus->self && bus->self->ari_enabled;
2465 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2466 * @pdev: PCI device to check
2468 * Walk upwards from @pdev and check for each encountered bridge if it's part
2469 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2470 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2472 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2474 struct pci_dev *parent = pdev;
2476 if (pdev->is_thunderbolt)
2479 while ((parent = pci_upstream_bridge(parent)))
2480 if (parent->is_thunderbolt)
2486 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2487 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2490 struct msi_domain_template;
2492 bool pci_create_ims_domain(struct pci_dev *pdev, const struct msi_domain_template *template,
2493 unsigned int hwsize, void *data);
2494 struct msi_map pci_ims_alloc_irq(struct pci_dev *pdev, union msi_instance_cookie *icookie,
2495 const struct irq_affinity_desc *affdesc);
2496 void pci_ims_free_irq(struct pci_dev *pdev, struct msi_map map);
2498 #include <linux/dma-mapping.h>
2500 #define pci_printk(level, pdev, fmt, arg...) \
2501 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2503 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2504 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2505 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2506 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2507 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2508 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2509 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2510 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2512 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2513 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2515 #define pci_info_ratelimited(pdev, fmt, arg...) \
2516 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2518 #define pci_WARN(pdev, condition, fmt, arg...) \
2519 WARN(condition, "%s %s: " fmt, \
2520 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2522 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2523 WARN_ONCE(condition, "%s %s: " fmt, \
2524 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2526 #endif /* LINUX_PCI_H */