1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
43 #include <linux/pci_ids.h>
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
53 * The PCI interface treats multi-function devices as independent
54 * devices. The slot/function address of each device is encoded
55 * in a single byte as follows:
60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
61 * In the interest of not exposing interfaces to user-space unnecessarily,
62 * the following kernel-only defines are being added here.
64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
68 /* pci_slot represents a physical slot */
70 struct pci_bus *bus; /* Bus this slot is on */
71 struct list_head list; /* Node in list of slots */
72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
77 static inline const char *pci_slot_name(const struct pci_slot *slot)
79 return kobject_name(&slot->kobj);
82 /* File state for mmap()s on /proc/bus/pci/X/Y */
88 /* For PCI devices, the region numbers are assigned this way: */
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
94 /* #6: expansion ROM resource */
97 /* Device-specific resources */
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
103 /* PCI-to-PCI (P2P) bridge windows */
104 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
105 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
106 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
108 /* CardBus bridge windows */
109 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
110 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
111 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
112 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
114 /* Total number of bridge resources for P2P and CardBus */
115 #define PCI_BRIDGE_RESOURCE_NUM 4
117 /* Resources assigned to buses behind the bridge */
118 PCI_BRIDGE_RESOURCES,
119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
120 PCI_BRIDGE_RESOURCE_NUM - 1,
122 /* Total resources associated with a PCI device */
125 /* Preserve this for compatibility */
126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
130 * enum pci_interrupt_pin - PCI INTx interrupt values
131 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
132 * @PCI_INTERRUPT_INTA: PCI INTA pin
133 * @PCI_INTERRUPT_INTB: PCI INTB pin
134 * @PCI_INTERRUPT_INTC: PCI INTC pin
135 * @PCI_INTERRUPT_INTD: PCI INTD pin
137 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
138 * PCI_INTERRUPT_PIN register.
140 enum pci_interrupt_pin {
141 PCI_INTERRUPT_UNKNOWN,
148 /* The number of legacy PCI INTx interrupts */
149 #define PCI_NUM_INTX 4
152 * pci_power_t values must match the bits in the Capabilities PME_Support
153 * and Control/Status PowerState fields in the Power Management capability.
155 typedef int __bitwise pci_power_t;
157 #define PCI_D0 ((pci_power_t __force) 0)
158 #define PCI_D1 ((pci_power_t __force) 1)
159 #define PCI_D2 ((pci_power_t __force) 2)
160 #define PCI_D3hot ((pci_power_t __force) 3)
161 #define PCI_D3cold ((pci_power_t __force) 4)
162 #define PCI_UNKNOWN ((pci_power_t __force) 5)
163 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
165 /* Remember to update this when the list above changes! */
166 extern const char *pci_power_names[];
168 static inline const char *pci_power_name(pci_power_t state)
170 return pci_power_names[1 + (__force int) state];
174 * typedef pci_channel_state_t
176 * The pci_channel state describes connectivity between the CPU and
177 * the PCI device. If some PCI bus between here and the PCI device
178 * has crashed or locked up, this info is reflected here.
180 typedef unsigned int __bitwise pci_channel_state_t;
183 /* I/O channel is in normal state */
184 pci_channel_io_normal = (__force pci_channel_state_t) 1,
186 /* I/O to channel is blocked */
187 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
189 /* PCI card is dead */
190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
193 typedef unsigned int __bitwise pcie_reset_state_t;
195 enum pcie_reset_state {
196 /* Reset is NOT asserted (Use to deassert reset) */
197 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
199 /* Use #PERST to reset PCIe device */
200 pcie_warm_reset = (__force pcie_reset_state_t) 2,
202 /* Use PCIe Hot Reset to reset device */
203 pcie_hot_reset = (__force pcie_reset_state_t) 3
206 typedef unsigned short __bitwise pci_dev_flags_t;
208 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
210 /* Device configuration is irrevocably lost if disabled into D3 */
211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
212 /* Provide indication device is assigned by a Virtual Machine Manager */
213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
214 /* Flag for quirk use to store if quirk-specific ACS is enabled */
215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
216 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
218 /* Do not use bus resets for device */
219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
220 /* Do not use PM reset even if device advertises NoSoftRst- */
221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
222 /* Get VPD from function 0 VPD */
223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
224 /* A non-root bridge where translation occurs, stop alias search here */
225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
226 /* Do not use FLR even if device advertises PCI_AF_CAP */
227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
228 /* Don't use Relaxed Ordering for TLPs directed at this device */
229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
232 enum pci_irq_reroute_variant {
233 INTEL_IRQ_REROUTE_VARIANT = 1,
234 MAX_IRQ_REROUTE_VARIANTS = 3
237 typedef unsigned short __bitwise pci_bus_flags_t;
239 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
240 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
241 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
242 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
245 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
246 enum pcie_link_width {
247 PCIE_LNK_WIDTH_RESRV = 0x00,
255 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
258 /* See matching string table in pci_speed_string() */
260 PCI_SPEED_33MHz = 0x00,
261 PCI_SPEED_66MHz = 0x01,
262 PCI_SPEED_66MHz_PCIX = 0x02,
263 PCI_SPEED_100MHz_PCIX = 0x03,
264 PCI_SPEED_133MHz_PCIX = 0x04,
265 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
266 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
267 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
268 PCI_SPEED_66MHz_PCIX_266 = 0x09,
269 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
270 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
276 PCI_SPEED_66MHz_PCIX_533 = 0x11,
277 PCI_SPEED_100MHz_PCIX_533 = 0x12,
278 PCI_SPEED_133MHz_PCIX_533 = 0x13,
279 PCIE_SPEED_2_5GT = 0x14,
280 PCIE_SPEED_5_0GT = 0x15,
281 PCIE_SPEED_8_0GT = 0x16,
282 PCIE_SPEED_16_0GT = 0x17,
283 PCIE_SPEED_32_0GT = 0x18,
284 PCI_SPEED_UNKNOWN = 0xff,
287 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
288 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
290 struct pci_cap_saved_data {
297 struct pci_cap_saved_state {
298 struct hlist_node next;
299 struct pci_cap_saved_data cap;
303 struct pcie_link_state;
309 /* The pci_dev structure describes PCI devices */
311 struct list_head bus_list; /* Node in per-bus list */
312 struct pci_bus *bus; /* Bus this device is on */
313 struct pci_bus *subordinate; /* Bus this device bridges to */
315 void *sysdata; /* Hook for sys-specific extension */
316 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
317 struct pci_slot *slot; /* Physical slot this device is in */
319 unsigned int devfn; /* Encoded device & function index */
320 unsigned short vendor;
321 unsigned short device;
322 unsigned short subsystem_vendor;
323 unsigned short subsystem_device;
324 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
325 u8 revision; /* PCI revision, low byte of class word */
326 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
327 #ifdef CONFIG_PCIEAER
328 u16 aer_cap; /* AER capability offset */
329 struct aer_stats *aer_stats; /* AER stats for this device */
331 #ifdef CONFIG_PCIEPORTBUS
332 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
334 u8 pcie_cap; /* PCIe capability offset */
335 u8 msi_cap; /* MSI capability offset */
336 u8 msix_cap; /* MSI-X capability offset */
337 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
338 u8 rom_base_reg; /* Config register controlling ROM */
339 u8 pin; /* Interrupt pin this device uses */
340 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
341 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
343 struct pci_driver *driver; /* Driver bound to this device */
344 u64 dma_mask; /* Mask of the bits of bus address this
345 device implements. Normally this is
346 0xffffffff. You only need to change
347 this if your device has broken DMA
348 or supports 64-bit transfers. */
350 struct device_dma_parameters dma_parms;
352 pci_power_t current_state; /* Current operating state. In ACPI,
353 this is D0-D3, D0 being fully
354 functional, and D3 being off. */
355 unsigned int imm_ready:1; /* Supports Immediate Readiness */
356 u8 pm_cap; /* PM capability offset */
357 unsigned int pme_support:5; /* Bitmask of states from which PME#
359 unsigned int pme_poll:1; /* Poll device's PME status bit */
360 unsigned int d1_support:1; /* Low power state D1 is supported */
361 unsigned int d2_support:1; /* Low power state D2 is supported */
362 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
363 unsigned int no_d3cold:1; /* D3cold is forbidden */
364 unsigned int bridge_d3:1; /* Allow D3 for bridge */
365 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
366 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
367 decoding during BAR sizing */
368 unsigned int wakeup_prepared:1;
369 unsigned int runtime_d3cold:1; /* Whether go through runtime
370 D3cold, not set for devices
371 powered on/off by the
372 corresponding bridge */
373 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
374 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
375 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
376 controlled exclusively by
378 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
380 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
381 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
383 #ifdef CONFIG_PCIEASPM
384 struct pcie_link_state *link_state; /* ASPM link state */
385 unsigned int ltr_path:1; /* Latency Tolerance Reporting
386 supported from root to here */
387 int l1ss; /* L1SS Capability pointer */
389 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
391 pci_channel_state_t error_state; /* Current connectivity state */
392 struct device dev; /* Generic device interface */
394 int cfg_size; /* Size of config space */
397 * Instead of touching interrupt line and base address registers
398 * directly, use the values stored here. They might be different!
401 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
403 bool match_driver; /* Skip attaching driver */
405 unsigned int transparent:1; /* Subtractive decode bridge */
406 unsigned int io_window:1; /* Bridge has I/O window */
407 unsigned int pref_window:1; /* Bridge has pref mem window */
408 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
409 unsigned int multifunction:1; /* Multi-function device */
411 unsigned int is_busmaster:1; /* Is busmaster */
412 unsigned int no_msi:1; /* May not use MSI */
413 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
414 unsigned int block_cfg_access:1; /* Config space access blocked */
415 unsigned int broken_parity_status:1; /* Generates false positive parity */
416 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
417 unsigned int msi_enabled:1;
418 unsigned int msix_enabled:1;
419 unsigned int ari_enabled:1; /* ARI forwarding */
420 unsigned int ats_enabled:1; /* Address Translation Svc */
421 unsigned int pasid_enabled:1; /* Process Address Space ID */
422 unsigned int pri_enabled:1; /* Page Request Interface */
423 unsigned int is_managed:1;
424 unsigned int needs_freset:1; /* Requires fundamental reset */
425 unsigned int state_saved:1;
426 unsigned int is_physfn:1;
427 unsigned int is_virtfn:1;
428 unsigned int reset_fn:1;
429 unsigned int is_hotplug_bridge:1;
430 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
431 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
433 * Devices marked being untrusted are the ones that can potentially
434 * execute DMA attacks and similar. They are typically connected
435 * through external ports such as Thunderbolt but not limited to
436 * that. When an IOMMU is enabled they should be getting full
437 * mappings to make sure they cannot access arbitrary memory.
439 unsigned int untrusted:1;
441 * Info from the platform, e.g., ACPI or device tree, may mark a
442 * device as "external-facing". An external-facing device is
443 * itself internal but devices downstream from it are external.
445 unsigned int external_facing:1;
446 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
447 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
448 unsigned int irq_managed:1;
449 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
450 unsigned int is_probed:1; /* Device probing in progress */
451 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
452 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
453 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
454 pci_dev_flags_t dev_flags;
455 atomic_t enable_cnt; /* pci_enable_device has been called */
457 u32 saved_config_space[16]; /* Config space saved at suspend time */
458 struct hlist_head saved_cap_space;
459 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
460 int rom_attr_enabled; /* Display of ROM attribute enabled? */
461 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
462 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
464 #ifdef CONFIG_HOTPLUG_PCI_PCIE
465 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
467 #ifdef CONFIG_PCIE_PTM
468 unsigned int ptm_root:1;
469 unsigned int ptm_enabled:1;
472 #ifdef CONFIG_PCI_MSI
473 const struct attribute_group **msi_irq_groups;
476 #ifdef CONFIG_PCIE_DPC
478 unsigned int dpc_rp_extensions:1;
481 #ifdef CONFIG_PCI_ATS
483 struct pci_sriov *sriov; /* PF: SR-IOV info */
484 struct pci_dev *physfn; /* VF: related PF */
486 u16 ats_cap; /* ATS Capability offset */
487 u8 ats_stu; /* ATS Smallest Translation Unit */
489 #ifdef CONFIG_PCI_PRI
490 u16 pri_cap; /* PRI Capability offset */
491 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
492 unsigned int pasid_required:1; /* PRG Response PASID Required */
494 #ifdef CONFIG_PCI_PASID
495 u16 pasid_cap; /* PASID Capability offset */
498 #ifdef CONFIG_PCI_P2PDMA
499 struct pci_p2pdma *p2pdma;
501 u16 acs_cap; /* ACS Capability offset */
502 phys_addr_t rom; /* Physical address if not from BAR */
503 size_t romlen; /* Length if not from BAR */
504 char *driver_override; /* Driver name to force a match */
506 unsigned long priv_flags; /* Private flags for the PCI driver */
509 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
511 #ifdef CONFIG_PCI_IOV
518 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
520 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
521 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
523 static inline int pci_channel_offline(struct pci_dev *pdev)
525 return (pdev->error_state != pci_channel_io_normal);
528 struct pci_host_bridge {
530 struct pci_bus *bus; /* Root bus */
532 struct pci_ops *child_ops;
535 struct list_head windows; /* resource_entry */
536 struct list_head dma_ranges; /* dma ranges resource list */
537 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
538 int (*map_irq)(const struct pci_dev *, u8, u8);
539 void (*release_fn)(struct pci_host_bridge *);
541 struct msi_controller *msi;
542 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
543 unsigned int no_ext_tags:1; /* No Extended Tags */
544 unsigned int native_aer:1; /* OS may use PCIe AER */
545 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
546 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
547 unsigned int native_pme:1; /* OS may use PCIe PME */
548 unsigned int native_ltr:1; /* OS may use PCIe LTR */
549 unsigned int native_dpc:1; /* OS may use PCIe DPC */
550 unsigned int preserve_config:1; /* Preserve FW resource setup */
551 unsigned int size_windows:1; /* Enable root bus sizing */
553 /* Resource alignment requirements */
554 resource_size_t (*align_resource)(struct pci_dev *dev,
555 const struct resource *res,
556 resource_size_t start,
557 resource_size_t size,
558 resource_size_t align);
559 unsigned long private[] ____cacheline_aligned;
562 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
564 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
566 return (void *)bridge->private;
569 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
571 return container_of(priv, struct pci_host_bridge, private);
574 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
575 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
577 void pci_free_host_bridge(struct pci_host_bridge *bridge);
578 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
580 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
581 void (*release_fn)(struct pci_host_bridge *),
584 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
587 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
588 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
589 * buses below host bridges or subtractive decode bridges) go in the list.
590 * Use pci_bus_for_each_resource() to iterate through all the resources.
594 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
595 * and there's no way to program the bridge with the details of the window.
596 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
597 * decode bit set, because they are explicit and can be programmed with _SRS.
599 #define PCI_SUBTRACTIVE_DECODE 0x1
601 struct pci_bus_resource {
602 struct list_head list;
603 struct resource *res;
607 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
610 struct list_head node; /* Node in list of buses */
611 struct pci_bus *parent; /* Parent bus this bridge is on */
612 struct list_head children; /* List of child buses */
613 struct list_head devices; /* List of devices on this bus */
614 struct pci_dev *self; /* Bridge device as seen by parent */
615 struct list_head slots; /* List of slots on this bus;
616 protected by pci_slot_mutex */
617 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
618 struct list_head resources; /* Address space routed to this bus */
619 struct resource busn_res; /* Bus numbers routed to this bus */
621 struct pci_ops *ops; /* Configuration access functions */
622 struct msi_controller *msi; /* MSI controller */
623 void *sysdata; /* Hook for sys-specific extension */
624 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
626 unsigned char number; /* Bus number */
627 unsigned char primary; /* Number of primary bridge */
628 unsigned char max_bus_speed; /* enum pci_bus_speed */
629 unsigned char cur_bus_speed; /* enum pci_bus_speed */
630 #ifdef CONFIG_PCI_DOMAINS_GENERIC
636 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
637 pci_bus_flags_t bus_flags; /* Inherited by child buses */
638 struct device *bridge;
640 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
641 struct bin_attribute *legacy_mem; /* Legacy mem */
642 unsigned int is_added:1;
645 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
647 static inline u16 pci_dev_id(struct pci_dev *dev)
649 return PCI_DEVID(dev->bus->number, dev->devfn);
653 * Returns true if the PCI bus is root (behind host-PCI bridge),
656 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
657 * This is incorrect because "virtual" buses added for SR-IOV (via
658 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
660 static inline bool pci_is_root_bus(struct pci_bus *pbus)
662 return !(pbus->parent);
666 * pci_is_bridge - check if the PCI device is a bridge
669 * Return true if the PCI device is bridge whether it has subordinate
672 static inline bool pci_is_bridge(struct pci_dev *dev)
674 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
675 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
678 #define for_each_pci_bridge(dev, bus) \
679 list_for_each_entry(dev, &bus->devices, bus_list) \
680 if (!pci_is_bridge(dev)) {} else
682 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
684 dev = pci_physfn(dev);
685 if (pci_is_root_bus(dev->bus))
688 return dev->bus->self;
691 #ifdef CONFIG_PCI_MSI
692 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
694 return pci_dev->msi_enabled || pci_dev->msix_enabled;
697 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
700 /* Error values that may be returned by PCI functions */
701 #define PCIBIOS_SUCCESSFUL 0x00
702 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
703 #define PCIBIOS_BAD_VENDOR_ID 0x83
704 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
705 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
706 #define PCIBIOS_SET_FAILED 0x88
707 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
709 /* Translate above to generic errno for passing back through non-PCI code */
710 static inline int pcibios_err_to_errno(int err)
712 if (err <= PCIBIOS_SUCCESSFUL)
713 return err; /* Assume already errno */
716 case PCIBIOS_FUNC_NOT_SUPPORTED:
718 case PCIBIOS_BAD_VENDOR_ID:
720 case PCIBIOS_DEVICE_NOT_FOUND:
722 case PCIBIOS_BAD_REGISTER_NUMBER:
724 case PCIBIOS_SET_FAILED:
726 case PCIBIOS_BUFFER_TOO_SMALL:
733 /* Low-level architecture-dependent routines */
736 int (*add_bus)(struct pci_bus *bus);
737 void (*remove_bus)(struct pci_bus *bus);
738 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
739 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
740 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
744 * ACPI needs to be able to access PCI config space before we've done a
745 * PCI bus scan and created pci_bus structures.
747 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
748 int reg, int len, u32 *val);
749 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
750 int reg, int len, u32 val);
752 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
753 typedef u64 pci_bus_addr_t;
755 typedef u32 pci_bus_addr_t;
758 struct pci_bus_region {
759 pci_bus_addr_t start;
764 spinlock_t lock; /* Protects list, index */
765 struct list_head list; /* For IDs added at runtime */
770 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
771 * a set of callbacks in struct pci_error_handlers, that device driver
772 * will be notified of PCI bus errors, and will be driven to recovery
773 * when an error occurs.
776 typedef unsigned int __bitwise pci_ers_result_t;
778 enum pci_ers_result {
779 /* No result/none/not supported in device driver */
780 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
782 /* Device driver can recover without slot reset */
783 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
785 /* Device driver wants slot to be reset */
786 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
788 /* Device has completely failed, is unrecoverable */
789 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
791 /* Device driver is fully recovered and operational */
792 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
794 /* No AER capabilities registered for the driver */
795 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
798 /* PCI bus error event callbacks */
799 struct pci_error_handlers {
800 /* PCI bus error detected on this device */
801 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
802 pci_channel_state_t error);
804 /* MMIO has been re-enabled, but not DMA */
805 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
807 /* PCI slot has been reset */
808 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
810 /* PCI function reset prepare or completed */
811 void (*reset_prepare)(struct pci_dev *dev);
812 void (*reset_done)(struct pci_dev *dev);
814 /* Device driver may resume normal operations */
815 void (*resume)(struct pci_dev *dev);
822 * struct pci_driver - PCI driver structure
823 * @node: List of driver structures.
824 * @name: Driver name.
825 * @id_table: Pointer to table of device IDs the driver is
826 * interested in. Most drivers should export this
827 * table using MODULE_DEVICE_TABLE(pci,...).
828 * @probe: This probing function gets called (during execution
829 * of pci_register_driver() for already existing
830 * devices or later if a new device gets inserted) for
831 * all PCI devices which match the ID table and are not
832 * "owned" by the other drivers yet. This function gets
833 * passed a "struct pci_dev \*" for each device whose
834 * entry in the ID table matches the device. The probe
835 * function returns zero when the driver chooses to
836 * take "ownership" of the device or an error code
837 * (negative number) otherwise.
838 * The probe function always gets called from process
839 * context, so it can sleep.
840 * @remove: The remove() function gets called whenever a device
841 * being handled by this driver is removed (either during
842 * deregistration of the driver or when it's manually
843 * pulled out of a hot-pluggable slot).
844 * The remove function always gets called from process
845 * context, so it can sleep.
846 * @suspend: Put device into low power state.
847 * @resume: Wake device from low power state.
848 * (Please see Documentation/power/pci.rst for descriptions
849 * of PCI Power Management and the related functions.)
850 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
851 * Intended to stop any idling DMA operations.
852 * Useful for enabling wake-on-lan (NIC) or changing
853 * the power state of a device before reboot.
854 * e.g. drivers/net/e100.c.
855 * @sriov_configure: Optional driver callback to allow configuration of
856 * number of VFs to enable via sysfs "sriov_numvfs" file.
857 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
858 * @groups: Sysfs attribute groups.
859 * @driver: Driver model structure.
860 * @dynids: List of dynamically added device IDs.
863 struct list_head node;
865 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
866 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
867 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
868 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
869 int (*resume)(struct pci_dev *dev); /* Device woken up */
870 void (*shutdown)(struct pci_dev *dev);
871 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
872 const struct pci_error_handlers *err_handler;
873 const struct attribute_group **groups;
874 struct device_driver driver;
875 struct pci_dynids dynids;
878 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
881 * PCI_DEVICE - macro used to describe a specific PCI device
882 * @vend: the 16 bit PCI Vendor ID
883 * @dev: the 16 bit PCI Device ID
885 * This macro is used to create a struct pci_device_id that matches a
886 * specific device. The subvendor and subdevice fields will be set to
889 #define PCI_DEVICE(vend,dev) \
890 .vendor = (vend), .device = (dev), \
891 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
894 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
895 * @vend: the 16 bit PCI Vendor ID
896 * @dev: the 16 bit PCI Device ID
897 * @subvend: the 16 bit PCI Subvendor ID
898 * @subdev: the 16 bit PCI Subdevice ID
900 * This macro is used to create a struct pci_device_id that matches a
901 * specific device with subsystem information.
903 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
904 .vendor = (vend), .device = (dev), \
905 .subvendor = (subvend), .subdevice = (subdev)
908 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
909 * @dev_class: the class, subclass, prog-if triple for this device
910 * @dev_class_mask: the class mask for this device
912 * This macro is used to create a struct pci_device_id that matches a
913 * specific PCI class. The vendor, device, subvendor, and subdevice
914 * fields will be set to PCI_ANY_ID.
916 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
917 .class = (dev_class), .class_mask = (dev_class_mask), \
918 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
919 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
922 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
923 * @vend: the vendor name
924 * @dev: the 16 bit PCI Device ID
926 * This macro is used to create a struct pci_device_id that matches a
927 * specific PCI device. The subvendor, and subdevice fields will be set
928 * to PCI_ANY_ID. The macro allows the next field to follow as the device
931 #define PCI_VDEVICE(vend, dev) \
932 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
933 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
936 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
937 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
938 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
939 * @data: the driver data to be filled
941 * This macro is used to create a struct pci_device_id that matches a
942 * specific PCI device. The subvendor, and subdevice fields will be set
945 #define PCI_DEVICE_DATA(vend, dev, data) \
946 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
947 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
948 .driver_data = (kernel_ulong_t)(data)
951 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
952 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
953 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
954 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
955 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
956 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
957 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
960 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
961 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
962 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
963 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
965 /* These external functions are only available when PCI support is enabled */
968 extern unsigned int pci_flags;
970 static inline void pci_set_flags(int flags) { pci_flags = flags; }
971 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
972 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
973 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
975 void pcie_bus_configure_settings(struct pci_bus *bus);
977 enum pcie_bus_config_types {
978 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
979 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
980 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
981 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
982 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
985 extern enum pcie_bus_config_types pcie_bus_config;
987 extern struct bus_type pci_bus_type;
989 /* Do NOT directly access these two variables, unless you are arch-specific PCI
990 * code, or PCI core code. */
991 extern struct list_head pci_root_buses; /* List of all known PCI buses */
992 /* Some device drivers need know if PCI is initiated */
993 int no_pci_devices(void);
995 void pcibios_resource_survey_bus(struct pci_bus *bus);
996 void pcibios_bus_add_device(struct pci_dev *pdev);
997 void pcibios_add_bus(struct pci_bus *bus);
998 void pcibios_remove_bus(struct pci_bus *bus);
999 void pcibios_fixup_bus(struct pci_bus *);
1000 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1001 /* Architecture-specific versions may override this (weak) */
1002 char *pcibios_setup(char *str);
1004 /* Used only when drivers/pci/setup.c is used */
1005 resource_size_t pcibios_align_resource(void *, const struct resource *,
1009 /* Weak but can be overridden by arch */
1010 void pci_fixup_cardbus(struct pci_bus *);
1012 /* Generic PCI functions used internally */
1014 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1015 struct resource *res);
1016 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1017 struct pci_bus_region *region);
1018 void pcibios_scan_specific_bus(int busn);
1019 struct pci_bus *pci_find_bus(int domain, int busnr);
1020 void pci_bus_add_devices(const struct pci_bus *bus);
1021 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1022 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1023 struct pci_ops *ops, void *sysdata,
1024 struct list_head *resources);
1025 int pci_host_probe(struct pci_host_bridge *bridge);
1026 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1027 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1028 void pci_bus_release_busn_res(struct pci_bus *b);
1029 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1030 struct pci_ops *ops, void *sysdata,
1031 struct list_head *resources);
1032 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1033 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1035 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1037 struct hotplug_slot *hotplug);
1038 void pci_destroy_slot(struct pci_slot *slot);
1040 void pci_dev_assign_slot(struct pci_dev *dev);
1042 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1044 int pci_scan_slot(struct pci_bus *bus, int devfn);
1045 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1046 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1047 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1048 void pci_bus_add_device(struct pci_dev *dev);
1049 void pci_read_bridge_bases(struct pci_bus *child);
1050 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1051 struct resource *res);
1052 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1053 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1054 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1055 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1056 void pci_dev_put(struct pci_dev *dev);
1057 void pci_remove_bus(struct pci_bus *b);
1058 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1059 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1060 void pci_stop_root_bus(struct pci_bus *bus);
1061 void pci_remove_root_bus(struct pci_bus *bus);
1062 void pci_setup_cardbus(struct pci_bus *bus);
1063 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1064 void pci_sort_breadthfirst(void);
1065 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1066 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1068 /* Generic PCI functions exported to card drivers */
1070 int pci_find_capability(struct pci_dev *dev, int cap);
1071 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1072 int pci_find_ext_capability(struct pci_dev *dev, int cap);
1073 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1074 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1075 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1076 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1078 u64 pci_get_dsn(struct pci_dev *dev);
1080 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1081 struct pci_dev *from);
1082 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1083 unsigned int ss_vendor, unsigned int ss_device,
1084 struct pci_dev *from);
1085 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1086 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1087 unsigned int devfn);
1088 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1089 int pci_dev_present(const struct pci_device_id *ids);
1091 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1092 int where, u8 *val);
1093 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1094 int where, u16 *val);
1095 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1096 int where, u32 *val);
1097 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1099 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1100 int where, u16 val);
1101 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1102 int where, u32 val);
1104 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1105 int where, int size, u32 *val);
1106 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1107 int where, int size, u32 val);
1108 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1109 int where, int size, u32 *val);
1110 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1111 int where, int size, u32 val);
1113 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1115 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1116 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1117 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1118 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1119 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1120 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1122 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1123 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1124 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1125 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1126 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1127 u16 clear, u16 set);
1128 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1129 u32 clear, u32 set);
1131 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1134 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1137 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1140 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1143 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1146 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1149 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1152 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1155 /* User-space driven config access */
1156 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1157 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1158 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1159 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1160 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1161 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1163 int __must_check pci_enable_device(struct pci_dev *dev);
1164 int __must_check pci_enable_device_io(struct pci_dev *dev);
1165 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1166 int __must_check pci_reenable_device(struct pci_dev *);
1167 int __must_check pcim_enable_device(struct pci_dev *pdev);
1168 void pcim_pin_device(struct pci_dev *pdev);
1170 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1173 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1174 * writable and no quirk has marked the feature broken.
1176 return !pdev->broken_intx_masking;
1179 static inline int pci_is_enabled(struct pci_dev *pdev)
1181 return (atomic_read(&pdev->enable_cnt) > 0);
1184 static inline int pci_is_managed(struct pci_dev *pdev)
1186 return pdev->is_managed;
1189 void pci_disable_device(struct pci_dev *dev);
1191 extern unsigned int pcibios_max_latency;
1192 void pci_set_master(struct pci_dev *dev);
1193 void pci_clear_master(struct pci_dev *dev);
1195 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1196 int pci_set_cacheline_size(struct pci_dev *dev);
1197 #define HAVE_PCI_SET_MWI
1198 int __must_check pci_set_mwi(struct pci_dev *dev);
1199 int __must_check pcim_set_mwi(struct pci_dev *dev);
1200 int pci_try_set_mwi(struct pci_dev *dev);
1201 void pci_clear_mwi(struct pci_dev *dev);
1202 void pci_intx(struct pci_dev *dev, int enable);
1203 bool pci_check_and_mask_intx(struct pci_dev *dev);
1204 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1205 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1206 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1207 int pcix_get_max_mmrbc(struct pci_dev *dev);
1208 int pcix_get_mmrbc(struct pci_dev *dev);
1209 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1210 int pcie_get_readrq(struct pci_dev *dev);
1211 int pcie_set_readrq(struct pci_dev *dev, int rq);
1212 int pcie_get_mps(struct pci_dev *dev);
1213 int pcie_set_mps(struct pci_dev *dev, int mps);
1214 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1215 enum pci_bus_speed *speed,
1216 enum pcie_link_width *width);
1217 void pcie_print_link_status(struct pci_dev *dev);
1218 bool pcie_has_flr(struct pci_dev *dev);
1219 int pcie_flr(struct pci_dev *dev);
1220 int __pci_reset_function_locked(struct pci_dev *dev);
1221 int pci_reset_function(struct pci_dev *dev);
1222 int pci_reset_function_locked(struct pci_dev *dev);
1223 int pci_try_reset_function(struct pci_dev *dev);
1224 int pci_probe_reset_slot(struct pci_slot *slot);
1225 int pci_probe_reset_bus(struct pci_bus *bus);
1226 int pci_reset_bus(struct pci_dev *dev);
1227 void pci_reset_secondary_bus(struct pci_dev *dev);
1228 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1229 void pci_update_resource(struct pci_dev *dev, int resno);
1230 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1231 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1232 void pci_release_resource(struct pci_dev *dev, int resno);
1233 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1234 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1235 bool pci_device_is_present(struct pci_dev *pdev);
1236 void pci_ignore_hotplug(struct pci_dev *dev);
1237 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1238 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1240 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1241 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1242 const char *fmt, ...);
1243 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1245 /* ROM control related routines */
1246 int pci_enable_rom(struct pci_dev *pdev);
1247 void pci_disable_rom(struct pci_dev *pdev);
1248 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1249 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1251 /* Power management related routines */
1252 int pci_save_state(struct pci_dev *dev);
1253 void pci_restore_state(struct pci_dev *dev);
1254 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1255 int pci_load_saved_state(struct pci_dev *dev,
1256 struct pci_saved_state *state);
1257 int pci_load_and_free_saved_state(struct pci_dev *dev,
1258 struct pci_saved_state **state);
1259 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1260 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1262 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1263 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1264 u16 cap, unsigned int size);
1265 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1266 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1267 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1268 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1269 void pci_pme_active(struct pci_dev *dev, bool enable);
1270 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1271 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1272 int pci_prepare_to_sleep(struct pci_dev *dev);
1273 int pci_back_from_sleep(struct pci_dev *dev);
1274 bool pci_dev_run_wake(struct pci_dev *dev);
1275 void pci_d3cold_enable(struct pci_dev *dev);
1276 void pci_d3cold_disable(struct pci_dev *dev);
1277 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1278 void pci_wakeup_bus(struct pci_bus *bus);
1279 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1281 /* For use by arch with custom probe code */
1282 void set_pcie_port_type(struct pci_dev *pdev);
1283 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1285 /* Functions for PCI Hotplug drivers to use */
1286 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1287 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1288 unsigned int pci_rescan_bus(struct pci_bus *bus);
1289 void pci_lock_rescan_remove(void);
1290 void pci_unlock_rescan_remove(void);
1292 /* Vital Product Data routines */
1293 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1294 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1295 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1297 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1298 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1299 void pci_bus_assign_resources(const struct pci_bus *bus);
1300 void pci_bus_claim_resources(struct pci_bus *bus);
1301 void pci_bus_size_bridges(struct pci_bus *bus);
1302 int pci_claim_resource(struct pci_dev *, int);
1303 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1304 void pci_assign_unassigned_resources(void);
1305 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1306 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1307 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1308 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1309 void pdev_enable_device(struct pci_dev *);
1310 int pci_enable_resources(struct pci_dev *, int mask);
1311 void pci_assign_irq(struct pci_dev *dev);
1312 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1313 #define HAVE_PCI_REQ_REGIONS 2
1314 int __must_check pci_request_regions(struct pci_dev *, const char *);
1315 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1316 void pci_release_regions(struct pci_dev *);
1317 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1318 void pci_release_region(struct pci_dev *, int);
1319 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1320 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1321 void pci_release_selected_regions(struct pci_dev *, int);
1323 /* drivers/pci/bus.c */
1324 void pci_add_resource(struct list_head *resources, struct resource *res);
1325 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1326 resource_size_t offset);
1327 void pci_free_resource_list(struct list_head *resources);
1328 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1329 unsigned int flags);
1330 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1331 void pci_bus_remove_resources(struct pci_bus *bus);
1332 int devm_request_pci_bus_resources(struct device *dev,
1333 struct list_head *resources);
1335 /* Temporary until new and working PCI SBR API in place */
1336 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1338 #define pci_bus_for_each_resource(bus, res, i) \
1340 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1343 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1344 struct resource *res, resource_size_t size,
1345 resource_size_t align, resource_size_t min,
1346 unsigned long type_mask,
1347 resource_size_t (*alignf)(void *,
1348 const struct resource *,
1354 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1355 resource_size_t size);
1356 unsigned long pci_address_to_pio(phys_addr_t addr);
1357 phys_addr_t pci_pio_to_address(unsigned long pio);
1358 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1359 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1360 phys_addr_t phys_addr);
1361 void pci_unmap_iospace(struct resource *res);
1362 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1363 resource_size_t offset,
1364 resource_size_t size);
1365 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1366 struct resource *res);
1368 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1370 struct pci_bus_region region;
1372 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1373 return region.start;
1376 /* Proper probing supporting hot-pluggable devices */
1377 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1378 const char *mod_name);
1380 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1381 #define pci_register_driver(driver) \
1382 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1384 void pci_unregister_driver(struct pci_driver *dev);
1387 * module_pci_driver() - Helper macro for registering a PCI driver
1388 * @__pci_driver: pci_driver struct
1390 * Helper macro for PCI drivers which do not do anything special in module
1391 * init/exit. This eliminates a lot of boilerplate. Each module may only
1392 * use this macro once, and calling it replaces module_init() and module_exit()
1394 #define module_pci_driver(__pci_driver) \
1395 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1398 * builtin_pci_driver() - Helper macro for registering a PCI driver
1399 * @__pci_driver: pci_driver struct
1401 * Helper macro for PCI drivers which do not do anything special in their
1402 * init code. This eliminates a lot of boilerplate. Each driver may only
1403 * use this macro once, and calling it replaces device_initcall(...)
1405 #define builtin_pci_driver(__pci_driver) \
1406 builtin_driver(__pci_driver, pci_register_driver)
1408 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1409 int pci_add_dynid(struct pci_driver *drv,
1410 unsigned int vendor, unsigned int device,
1411 unsigned int subvendor, unsigned int subdevice,
1412 unsigned int class, unsigned int class_mask,
1413 unsigned long driver_data);
1414 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1415 struct pci_dev *dev);
1416 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1419 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1421 int pci_cfg_space_size(struct pci_dev *dev);
1422 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1423 void pci_setup_bridge(struct pci_bus *bus);
1424 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1425 unsigned long type);
1427 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1428 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1430 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1431 unsigned int command_bits, u32 flags);
1434 * Virtual interrupts allow for more interrupts to be allocated
1435 * than the device has interrupts for. These are not programmed
1436 * into the device's MSI-X table and must be handled by some
1437 * other driver means.
1439 #define PCI_IRQ_VIRTUAL (1 << 4)
1441 #define PCI_IRQ_ALL_TYPES \
1442 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1444 /* kmem_cache style wrapper around pci_alloc_consistent() */
1446 #include <linux/dmapool.h>
1448 #define pci_pool dma_pool
1449 #define pci_pool_create(name, pdev, size, align, allocation) \
1450 dma_pool_create(name, &pdev->dev, size, align, allocation)
1451 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1452 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1453 #define pci_pool_zalloc(pool, flags, handle) \
1454 dma_pool_zalloc(pool, flags, handle)
1455 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1458 u32 vector; /* Kernel uses to write allocated vector */
1459 u16 entry; /* Driver uses to specify entry, OS writes */
1462 #ifdef CONFIG_PCI_MSI
1463 int pci_msi_vec_count(struct pci_dev *dev);
1464 void pci_disable_msi(struct pci_dev *dev);
1465 int pci_msix_vec_count(struct pci_dev *dev);
1466 void pci_disable_msix(struct pci_dev *dev);
1467 void pci_restore_msi_state(struct pci_dev *dev);
1468 int pci_msi_enabled(void);
1469 int pci_enable_msi(struct pci_dev *dev);
1470 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1471 int minvec, int maxvec);
1472 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1473 struct msix_entry *entries, int nvec)
1475 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1480 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1481 unsigned int max_vecs, unsigned int flags,
1482 struct irq_affinity *affd);
1484 void pci_free_irq_vectors(struct pci_dev *dev);
1485 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1486 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1489 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1490 static inline void pci_disable_msi(struct pci_dev *dev) { }
1491 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1492 static inline void pci_disable_msix(struct pci_dev *dev) { }
1493 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1494 static inline int pci_msi_enabled(void) { return 0; }
1495 static inline int pci_enable_msi(struct pci_dev *dev)
1497 static inline int pci_enable_msix_range(struct pci_dev *dev,
1498 struct msix_entry *entries, int minvec, int maxvec)
1500 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1501 struct msix_entry *entries, int nvec)
1505 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1506 unsigned int max_vecs, unsigned int flags,
1507 struct irq_affinity *aff_desc)
1509 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1514 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1518 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1520 if (WARN_ON_ONCE(nr > 0))
1524 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1527 return cpu_possible_mask;
1532 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1533 * @d: the INTx IRQ domain
1534 * @node: the DT node for the device whose interrupt we're translating
1535 * @intspec: the interrupt specifier data from the DT
1536 * @intsize: the number of entries in @intspec
1537 * @out_hwirq: pointer at which to write the hwirq number
1538 * @out_type: pointer at which to write the interrupt type
1540 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1541 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1542 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1543 * INTx value to obtain the hwirq number.
1545 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1547 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1548 struct device_node *node,
1550 unsigned int intsize,
1551 unsigned long *out_hwirq,
1552 unsigned int *out_type)
1554 const u32 intx = intspec[0];
1556 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1559 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1563 #ifdef CONFIG_PCIEPORTBUS
1564 extern bool pcie_ports_disabled;
1565 extern bool pcie_ports_native;
1567 #define pcie_ports_disabled true
1568 #define pcie_ports_native false
1571 #define PCIE_LINK_STATE_L0S BIT(0)
1572 #define PCIE_LINK_STATE_L1 BIT(1)
1573 #define PCIE_LINK_STATE_CLKPM BIT(2)
1574 #define PCIE_LINK_STATE_L1_1 BIT(3)
1575 #define PCIE_LINK_STATE_L1_2 BIT(4)
1576 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1577 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1579 #ifdef CONFIG_PCIEASPM
1580 int pci_disable_link_state(struct pci_dev *pdev, int state);
1581 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1582 void pcie_no_aspm(void);
1583 bool pcie_aspm_support_enabled(void);
1584 bool pcie_aspm_enabled(struct pci_dev *pdev);
1586 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1588 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1590 static inline void pcie_no_aspm(void) { }
1591 static inline bool pcie_aspm_support_enabled(void) { return false; }
1592 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1595 #ifdef CONFIG_PCIEAER
1596 bool pci_aer_available(void);
1598 static inline bool pci_aer_available(void) { return false; }
1601 bool pci_ats_disabled(void);
1603 void pci_cfg_access_lock(struct pci_dev *dev);
1604 bool pci_cfg_access_trylock(struct pci_dev *dev);
1605 void pci_cfg_access_unlock(struct pci_dev *dev);
1608 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1609 * a PCI domain is defined to be a set of PCI buses which share
1610 * configuration space.
1612 #ifdef CONFIG_PCI_DOMAINS
1613 extern int pci_domains_supported;
1615 enum { pci_domains_supported = 0 };
1616 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1617 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1618 #endif /* CONFIG_PCI_DOMAINS */
1621 * Generic implementation for PCI domain support. If your
1622 * architecture does not need custom management of PCI
1623 * domains then this implementation will be used
1625 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1626 static inline int pci_domain_nr(struct pci_bus *bus)
1628 return bus->domain_nr;
1631 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1633 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1636 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1639 /* Some architectures require additional setup to direct VGA traffic */
1640 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1641 unsigned int command_bits, u32 flags);
1642 void pci_register_set_vga_state(arch_set_vga_state_t func);
1645 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1647 return pci_request_selected_regions(pdev,
1648 pci_select_bars(pdev, IORESOURCE_IO), name);
1652 pci_release_io_regions(struct pci_dev *pdev)
1654 return pci_release_selected_regions(pdev,
1655 pci_select_bars(pdev, IORESOURCE_IO));
1659 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1661 return pci_request_selected_regions(pdev,
1662 pci_select_bars(pdev, IORESOURCE_MEM), name);
1666 pci_release_mem_regions(struct pci_dev *pdev)
1668 return pci_release_selected_regions(pdev,
1669 pci_select_bars(pdev, IORESOURCE_MEM));
1672 #else /* CONFIG_PCI is not enabled */
1674 static inline void pci_set_flags(int flags) { }
1675 static inline void pci_add_flags(int flags) { }
1676 static inline void pci_clear_flags(int flags) { }
1677 static inline int pci_has_flag(int flag) { return 0; }
1680 * If the system does not have PCI, clearly these return errors. Define
1681 * these as simple inline functions to avoid hair in drivers.
1683 #define _PCI_NOP(o, s, t) \
1684 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1686 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1688 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1689 _PCI_NOP(o, word, u16 x) \
1690 _PCI_NOP(o, dword, u32 x)
1691 _PCI_NOP_ALL(read, *)
1692 _PCI_NOP_ALL(write,)
1694 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1695 unsigned int device,
1696 struct pci_dev *from)
1699 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1700 unsigned int device,
1701 unsigned int ss_vendor,
1702 unsigned int ss_device,
1703 struct pci_dev *from)
1706 static inline struct pci_dev *pci_get_class(unsigned int class,
1707 struct pci_dev *from)
1710 #define pci_dev_present(ids) (0)
1711 #define no_pci_devices() (1)
1712 #define pci_dev_put(dev) do { } while (0)
1714 static inline void pci_set_master(struct pci_dev *dev) { }
1715 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1716 static inline void pci_disable_device(struct pci_dev *dev) { }
1717 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1718 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1720 static inline int __pci_register_driver(struct pci_driver *drv,
1721 struct module *owner)
1723 static inline int pci_register_driver(struct pci_driver *drv)
1725 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1726 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1728 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1731 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1734 static inline u64 pci_get_dsn(struct pci_dev *dev)
1737 /* Power management related routines */
1738 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1739 static inline void pci_restore_state(struct pci_dev *dev) { }
1740 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1742 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1744 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1747 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1751 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1752 struct resource *res)
1754 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1756 static inline void pci_release_regions(struct pci_dev *dev) { }
1758 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1760 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1762 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1765 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1766 unsigned int bus, unsigned int devfn)
1769 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1770 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1772 #define dev_is_pci(d) (false)
1773 #define dev_is_pf(d) (false)
1774 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1776 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1777 struct device_node *node,
1779 unsigned int intsize,
1780 unsigned long *out_hwirq,
1781 unsigned int *out_type)
1784 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1785 struct pci_dev *dev)
1787 static inline bool pci_ats_disabled(void) { return true; }
1789 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1795 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1796 unsigned int max_vecs, unsigned int flags,
1797 struct irq_affinity *aff_desc)
1801 #endif /* CONFIG_PCI */
1804 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1805 unsigned int max_vecs, unsigned int flags)
1807 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1811 /* Include architecture-dependent settings and functions */
1813 #include <asm/pci.h>
1815 /* These two functions provide almost identical functionality. Depending
1816 * on the architecture, one will be implemented as a wrapper around the
1817 * other (in drivers/pci/mmap.c).
1819 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1820 * is expected to be an offset within that region.
1822 * pci_mmap_page_range() is the legacy architecture-specific interface,
1823 * which accepts a "user visible" resource address converted by
1824 * pci_resource_to_user(), as used in the legacy mmap() interface in
1827 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1828 struct vm_area_struct *vma,
1829 enum pci_mmap_state mmap_state, int write_combine);
1830 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1831 struct vm_area_struct *vma,
1832 enum pci_mmap_state mmap_state, int write_combine);
1834 #ifndef arch_can_pci_mmap_wc
1835 #define arch_can_pci_mmap_wc() 0
1838 #ifndef arch_can_pci_mmap_io
1839 #define arch_can_pci_mmap_io() 0
1840 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1842 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1845 #ifndef pci_root_bus_fwnode
1846 #define pci_root_bus_fwnode(bus) NULL
1850 * These helpers provide future and backwards compatibility
1851 * for accessing popular PCI BAR info
1853 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1854 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1855 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1856 #define pci_resource_len(dev,bar) \
1857 ((pci_resource_start((dev), (bar)) == 0 && \
1858 pci_resource_end((dev), (bar)) == \
1859 pci_resource_start((dev), (bar))) ? 0 : \
1861 (pci_resource_end((dev), (bar)) - \
1862 pci_resource_start((dev), (bar)) + 1))
1865 * Similar to the helpers above, these manipulate per-pci_dev
1866 * driver-specific data. They are really just a wrapper around
1867 * the generic device structure functions of these calls.
1869 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1871 return dev_get_drvdata(&pdev->dev);
1874 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1876 dev_set_drvdata(&pdev->dev, data);
1879 static inline const char *pci_name(const struct pci_dev *pdev)
1881 return dev_name(&pdev->dev);
1884 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1885 const struct resource *rsrc,
1886 resource_size_t *start, resource_size_t *end);
1889 * The world is not perfect and supplies us with broken PCI devices.
1890 * For at least a part of these bugs we need a work-around, so both
1891 * generic (drivers/pci/quirks.c) and per-architecture code can define
1892 * fixup hooks to be called for particular buggy devices.
1896 u16 vendor; /* Or PCI_ANY_ID */
1897 u16 device; /* Or PCI_ANY_ID */
1898 u32 class; /* Or PCI_ANY_ID */
1899 unsigned int class_shift; /* should be 0, 8, 16 */
1900 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1903 void (*hook)(struct pci_dev *dev);
1907 enum pci_fixup_pass {
1908 pci_fixup_early, /* Before probing BARs */
1909 pci_fixup_header, /* After reading configuration header */
1910 pci_fixup_final, /* Final phase of device fixups */
1911 pci_fixup_enable, /* pci_enable_device() time */
1912 pci_fixup_resume, /* pci_device_resume() */
1913 pci_fixup_suspend, /* pci_device_suspend() */
1914 pci_fixup_resume_early, /* pci_device_resume_early() */
1915 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1918 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1919 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1920 class_shift, hook) \
1921 __ADDRESSABLE(hook) \
1922 asm(".section " #sec ", \"a\" \n" \
1924 ".short " #vendor ", " #device " \n" \
1925 ".long " #class ", " #class_shift " \n" \
1926 ".long " #hook " - . \n" \
1928 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1929 class_shift, hook) \
1930 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1933 /* Anonymous variables would be nice... */
1934 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1935 class_shift, hook) \
1936 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1937 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1938 = { vendor, device, class, class_shift, hook };
1941 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1942 class_shift, hook) \
1943 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1944 hook, vendor, device, class, class_shift, hook)
1945 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1946 class_shift, hook) \
1947 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1948 hook, vendor, device, class, class_shift, hook)
1949 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1950 class_shift, hook) \
1951 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1952 hook, vendor, device, class, class_shift, hook)
1953 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1954 class_shift, hook) \
1955 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1956 hook, vendor, device, class, class_shift, hook)
1957 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1958 class_shift, hook) \
1959 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1960 resume##hook, vendor, device, class, class_shift, hook)
1961 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1962 class_shift, hook) \
1963 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1964 resume_early##hook, vendor, device, class, class_shift, hook)
1965 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1966 class_shift, hook) \
1967 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1968 suspend##hook, vendor, device, class, class_shift, hook)
1969 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1970 class_shift, hook) \
1971 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1972 suspend_late##hook, vendor, device, class, class_shift, hook)
1974 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1975 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1976 hook, vendor, device, PCI_ANY_ID, 0, hook)
1977 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1978 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1979 hook, vendor, device, PCI_ANY_ID, 0, hook)
1980 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1981 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1982 hook, vendor, device, PCI_ANY_ID, 0, hook)
1983 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1984 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1985 hook, vendor, device, PCI_ANY_ID, 0, hook)
1986 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1987 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1988 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1989 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1990 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1991 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1992 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1993 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1994 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1995 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1996 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1997 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1999 #ifdef CONFIG_PCI_QUIRKS
2000 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2002 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2003 struct pci_dev *dev) { }
2006 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2007 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2008 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2009 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2010 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2012 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2014 extern int pci_pci_problems;
2015 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2016 #define PCIPCI_TRITON 2
2017 #define PCIPCI_NATOMA 4
2018 #define PCIPCI_VIAETBF 8
2019 #define PCIPCI_VSFX 16
2020 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2021 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2023 extern unsigned long pci_cardbus_io_size;
2024 extern unsigned long pci_cardbus_mem_size;
2025 extern u8 pci_dfl_cache_line_size;
2026 extern u8 pci_cache_line_size;
2028 /* Architecture-specific versions may override these (weak) */
2029 void pcibios_disable_device(struct pci_dev *dev);
2030 void pcibios_set_master(struct pci_dev *dev);
2031 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2032 enum pcie_reset_state state);
2033 int pcibios_add_device(struct pci_dev *dev);
2034 void pcibios_release_device(struct pci_dev *dev);
2036 void pcibios_penalize_isa_irq(int irq, int active);
2038 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2040 int pcibios_alloc_irq(struct pci_dev *dev);
2041 void pcibios_free_irq(struct pci_dev *dev);
2042 resource_size_t pcibios_default_alignment(void);
2044 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2045 void __init pci_mmcfg_early_init(void);
2046 void __init pci_mmcfg_late_init(void);
2048 static inline void pci_mmcfg_early_init(void) { }
2049 static inline void pci_mmcfg_late_init(void) { }
2052 int pci_ext_cfg_avail(void);
2054 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2055 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2057 #ifdef CONFIG_PCI_IOV
2058 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2059 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2061 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2062 void pci_disable_sriov(struct pci_dev *dev);
2064 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2065 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2066 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2067 int pci_num_vf(struct pci_dev *dev);
2068 int pci_vfs_assigned(struct pci_dev *dev);
2069 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2070 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2071 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2072 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2073 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2075 /* Arch may override these (weak) */
2076 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2077 int pcibios_sriov_disable(struct pci_dev *pdev);
2078 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2080 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2084 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2088 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2091 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2092 struct pci_dev *virtfn, int id)
2096 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2100 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2102 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2103 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2104 static inline int pci_vfs_assigned(struct pci_dev *dev)
2106 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2108 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2110 #define pci_sriov_configure_simple NULL
2111 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2113 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2116 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2117 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2118 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2122 * pci_pcie_cap - get the saved PCIe capability offset
2125 * PCIe capability offset is calculated at PCI device initialization
2126 * time and saved in the data structure. This function returns saved
2127 * PCIe capability offset. Using this instead of pci_find_capability()
2128 * reduces unnecessary search in the PCI configuration space. If you
2129 * need to calculate PCIe capability offset from raw device for some
2130 * reasons, please use pci_find_capability() instead.
2132 static inline int pci_pcie_cap(struct pci_dev *dev)
2134 return dev->pcie_cap;
2138 * pci_is_pcie - check if the PCI device is PCI Express capable
2141 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2143 static inline bool pci_is_pcie(struct pci_dev *dev)
2145 return pci_pcie_cap(dev);
2149 * pcie_caps_reg - get the PCIe Capabilities Register
2152 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2154 return dev->pcie_flags_reg;
2158 * pci_pcie_type - get the PCIe device/port type
2161 static inline int pci_pcie_type(const struct pci_dev *dev)
2163 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2167 * pcie_find_root_port - Get the PCIe root port device
2170 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2171 * for a given PCI/PCIe Device.
2173 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2176 if (pci_is_pcie(dev) &&
2177 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2179 dev = pci_upstream_bridge(dev);
2185 void pci_request_acs(void);
2186 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2187 bool pci_acs_path_enabled(struct pci_dev *start,
2188 struct pci_dev *end, u16 acs_flags);
2189 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2191 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2192 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2194 /* Large Resource Data Type Tag Item Names */
2195 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2196 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2197 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2199 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2200 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2201 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2203 /* Small Resource Data Type Tag Item Names */
2204 #define PCI_VPD_STIN_END 0x0f /* End */
2206 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2208 #define PCI_VPD_SRDT_TIN_MASK 0x78
2209 #define PCI_VPD_SRDT_LEN_MASK 0x07
2210 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2212 #define PCI_VPD_LRDT_TAG_SIZE 3
2213 #define PCI_VPD_SRDT_TAG_SIZE 1
2215 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2217 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2218 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2219 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2220 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2221 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2224 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2225 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2227 * Returns the extracted Large Resource Data Type length.
2229 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2231 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2235 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2236 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2238 * Returns the extracted Large Resource Data Type Tag item.
2240 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2242 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2246 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2247 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2249 * Returns the extracted Small Resource Data Type length.
2251 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2253 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2257 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2258 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2260 * Returns the extracted Small Resource Data Type Tag Item.
2262 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2264 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2268 * pci_vpd_info_field_size - Extracts the information field length
2269 * @info_field: Pointer to the beginning of an information field header
2271 * Returns the extracted information field length.
2273 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2275 return info_field[2];
2279 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2280 * @buf: Pointer to buffered vpd data
2281 * @off: The offset into the buffer at which to begin the search
2282 * @len: The length of the vpd buffer
2283 * @rdt: The Resource Data Type to search for
2285 * Returns the index where the Resource Data Type was found or
2286 * -ENOENT otherwise.
2288 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2291 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2292 * @buf: Pointer to buffered vpd data
2293 * @off: The offset into the buffer at which to begin the search
2294 * @len: The length of the buffer area, relative to off, in which to search
2295 * @kw: The keyword to search for
2297 * Returns the index where the information field keyword was found or
2298 * -ENOENT otherwise.
2300 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2301 unsigned int len, const char *kw);
2303 /* PCI <-> OF binding helpers */
2307 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2309 /* Arch may override this (weak) */
2310 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2312 #else /* CONFIG_OF */
2313 static inline struct irq_domain *
2314 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2315 #endif /* CONFIG_OF */
2317 static inline struct device_node *
2318 pci_device_to_OF_node(const struct pci_dev *pdev)
2320 return pdev ? pdev->dev.of_node : NULL;
2323 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2325 return bus ? bus->dev.of_node : NULL;
2329 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2332 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2333 bool pci_pr3_present(struct pci_dev *pdev);
2335 static inline struct irq_domain *
2336 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2337 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2341 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2343 return pdev->dev.archdata.edev;
2347 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2348 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2349 int pci_for_each_dma_alias(struct pci_dev *pdev,
2350 int (*fn)(struct pci_dev *pdev,
2351 u16 alias, void *data), void *data);
2353 /* Helper functions for operation of device flag */
2354 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2356 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2358 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2360 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2362 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2364 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2368 * pci_ari_enabled - query ARI forwarding status
2371 * Returns true if ARI forwarding is enabled.
2373 static inline bool pci_ari_enabled(struct pci_bus *bus)
2375 return bus->self && bus->self->ari_enabled;
2379 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2380 * @pdev: PCI device to check
2382 * Walk upwards from @pdev and check for each encountered bridge if it's part
2383 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2384 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2386 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2388 struct pci_dev *parent = pdev;
2390 if (pdev->is_thunderbolt)
2393 while ((parent = pci_upstream_bridge(parent)))
2394 if (parent->is_thunderbolt)
2400 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2401 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2404 /* Provide the legacy pci_dma_* API */
2405 #include <linux/pci-dma-compat.h>
2407 #define pci_printk(level, pdev, fmt, arg...) \
2408 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2410 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2411 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2412 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2413 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2414 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2415 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2416 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2417 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2419 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2420 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2422 #define pci_info_ratelimited(pdev, fmt, arg...) \
2423 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2425 #define pci_WARN(pdev, condition, fmt, arg...) \
2426 WARN(condition, "%s %s: " fmt, \
2427 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2429 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2430 WARN_ONCE(condition, "%s %s: " fmt, \
2431 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2433 #endif /* LINUX_PCI_H */