4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
74 * For PCI devices, the region numbers are assigned this way:
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* device specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* total resources associated with a PCI device */
100 /* preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
105 * pci_power_t values must match the bits in the Capabilities PME_Support
106 * and Control/Status PowerState fields in the Power Management capability.
108 typedef int __bitwise pci_power_t;
110 #define PCI_D0 ((pci_power_t __force) 0)
111 #define PCI_D1 ((pci_power_t __force) 1)
112 #define PCI_D2 ((pci_power_t __force) 2)
113 #define PCI_D3hot ((pci_power_t __force) 3)
114 #define PCI_D3cold ((pci_power_t __force) 4)
115 #define PCI_UNKNOWN ((pci_power_t __force) 5)
116 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
118 /* Remember to update this when the list above changes! */
119 extern const char *pci_power_names[];
121 static inline const char *pci_power_name(pci_power_t state)
123 return pci_power_names[1 + (__force int) state];
126 #define PCI_PM_D2_DELAY 200
127 #define PCI_PM_D3_WAIT 10
128 #define PCI_PM_D3COLD_WAIT 100
129 #define PCI_PM_BUS_WAIT 50
131 /** The pci_channel state describes connectivity between the CPU and
132 * the pci device. If some PCI bus between here and the pci device
133 * has crashed or locked up, this info is reflected here.
135 typedef unsigned int __bitwise pci_channel_state_t;
137 enum pci_channel_state {
138 /* I/O channel is in normal state */
139 pci_channel_io_normal = (__force pci_channel_state_t) 1,
141 /* I/O to channel is blocked */
142 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
144 /* PCI card is dead */
145 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148 typedef unsigned int __bitwise pcie_reset_state_t;
150 enum pcie_reset_state {
151 /* Reset is NOT asserted (Use to deassert reset) */
152 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
154 /* Use #PERST to reset PCIe device */
155 pcie_warm_reset = (__force pcie_reset_state_t) 2,
157 /* Use PCIe Hot Reset to reset device */
158 pcie_hot_reset = (__force pcie_reset_state_t) 3
161 typedef unsigned short __bitwise pci_dev_flags_t;
163 /* INTX_DISABLE in PCI_COMMAND register disables MSI
166 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
167 /* Device configuration is irrevocably lost if disabled into D3 */
168 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
169 /* Provide indication device is assigned by a Virtual Machine Manager */
170 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
171 /* Flag for quirk use to store if quirk-specific ACS is enabled */
172 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
173 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
174 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
175 /* Do not use bus resets for device */
176 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
177 /* Do not use PM reset even if device advertises NoSoftRst- */
178 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
179 /* Get VPD from function 0 VPD */
180 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
183 enum pci_irq_reroute_variant {
184 INTEL_IRQ_REROUTE_VARIANT = 1,
185 MAX_IRQ_REROUTE_VARIANTS = 3
188 typedef unsigned short __bitwise pci_bus_flags_t;
190 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
191 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
192 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
195 /* These values come from the PCI Express Spec */
196 enum pcie_link_width {
197 PCIE_LNK_WIDTH_RESRV = 0x00,
205 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
208 /* Based on the PCI Hotplug Spec, but some values are made up by us */
210 PCI_SPEED_33MHz = 0x00,
211 PCI_SPEED_66MHz = 0x01,
212 PCI_SPEED_66MHz_PCIX = 0x02,
213 PCI_SPEED_100MHz_PCIX = 0x03,
214 PCI_SPEED_133MHz_PCIX = 0x04,
215 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
216 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
217 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
218 PCI_SPEED_66MHz_PCIX_266 = 0x09,
219 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
220 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
226 PCI_SPEED_66MHz_PCIX_533 = 0x11,
227 PCI_SPEED_100MHz_PCIX_533 = 0x12,
228 PCI_SPEED_133MHz_PCIX_533 = 0x13,
229 PCIE_SPEED_2_5GT = 0x14,
230 PCIE_SPEED_5_0GT = 0x15,
231 PCIE_SPEED_8_0GT = 0x16,
232 PCI_SPEED_UNKNOWN = 0xff,
235 struct pci_cap_saved_data {
242 struct pci_cap_saved_state {
243 struct hlist_node next;
244 struct pci_cap_saved_data cap;
248 struct pcie_link_state;
254 * The pci_dev structure is used to describe PCI devices.
257 struct list_head bus_list; /* node in per-bus list */
258 struct pci_bus *bus; /* bus this device is on */
259 struct pci_bus *subordinate; /* bus this device bridges to */
261 void *sysdata; /* hook for sys-specific extension */
262 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
263 struct pci_slot *slot; /* Physical slot this device is in */
265 unsigned int devfn; /* encoded device & function index */
266 unsigned short vendor;
267 unsigned short device;
268 unsigned short subsystem_vendor;
269 unsigned short subsystem_device;
270 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
271 u8 revision; /* PCI revision, low byte of class word */
272 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
273 #ifdef CONFIG_PCIEAER
274 u16 aer_cap; /* AER capability offset */
276 u8 pcie_cap; /* PCIe capability offset */
277 u8 msi_cap; /* MSI capability offset */
278 u8 msix_cap; /* MSI-X capability offset */
279 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
280 u8 rom_base_reg; /* which config register controls the ROM */
281 u8 pin; /* which interrupt pin this device uses */
282 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
283 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
285 struct pci_driver *driver; /* which driver has allocated this device */
286 u64 dma_mask; /* Mask of the bits of bus address this
287 device implements. Normally this is
288 0xffffffff. You only need to change
289 this if your device has broken DMA
290 or supports 64-bit transfers. */
292 struct device_dma_parameters dma_parms;
294 pci_power_t current_state; /* Current operating state. In ACPI-speak,
295 this is D0-D3, D0 being fully functional,
297 u8 pm_cap; /* PM capability offset */
298 unsigned int pme_support:5; /* Bitmask of states from which PME#
300 unsigned int pme_interrupt:1;
301 unsigned int pme_poll:1; /* Poll device's PME status bit */
302 unsigned int d1_support:1; /* Low power state D1 is supported */
303 unsigned int d2_support:1; /* Low power state D2 is supported */
304 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
305 unsigned int no_d3cold:1; /* D3cold is forbidden */
306 unsigned int bridge_d3:1; /* Allow D3 for bridge */
307 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
308 unsigned int mmio_always_on:1; /* disallow turning off io/mem
309 decoding during bar sizing */
310 unsigned int wakeup_prepared:1;
311 unsigned int runtime_d3cold:1; /* whether go through runtime
312 D3cold, not set for devices
313 powered on/off by the
314 corresponding bridge */
315 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
316 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
317 controlled exclusively by
319 unsigned int d3_delay; /* D3->D0 transition time in ms */
320 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
322 #ifdef CONFIG_PCIEASPM
323 struct pcie_link_state *link_state; /* ASPM link state */
326 pci_channel_state_t error_state; /* current connectivity state */
327 struct device dev; /* Generic device interface */
329 int cfg_size; /* Size of configuration space */
332 * Instead of touching interrupt line and base address registers
333 * directly, use the values stored here. They might be different!
336 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
338 bool match_driver; /* Skip attaching driver */
339 /* These fields are used by common fixups */
340 unsigned int transparent:1; /* Subtractive decode PCI bridge */
341 unsigned int multifunction:1;/* Part of multi-function device */
342 /* keep track of device state */
343 unsigned int is_added:1;
344 unsigned int is_busmaster:1; /* device is busmaster */
345 unsigned int no_msi:1; /* device may not use msi */
346 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
347 unsigned int block_cfg_access:1; /* config space access is blocked */
348 unsigned int broken_parity_status:1; /* Device generates false positive parity */
349 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
350 unsigned int msi_enabled:1;
351 unsigned int msix_enabled:1;
352 unsigned int ari_enabled:1; /* ARI forwarding */
353 unsigned int ats_enabled:1; /* Address Translation Service */
354 unsigned int is_managed:1;
355 unsigned int needs_freset:1; /* Dev requires fundamental reset */
356 unsigned int state_saved:1;
357 unsigned int is_physfn:1;
358 unsigned int is_virtfn:1;
359 unsigned int reset_fn:1;
360 unsigned int is_hotplug_bridge:1;
361 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
362 unsigned int __aer_firmware_first_valid:1;
363 unsigned int __aer_firmware_first:1;
364 unsigned int broken_intx_masking:1;
365 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
366 unsigned int irq_managed:1;
367 unsigned int has_secondary_link:1;
368 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
369 pci_dev_flags_t dev_flags;
370 atomic_t enable_cnt; /* pci_enable_device has been called */
372 u32 saved_config_space[16]; /* config space saved at suspend time */
373 struct hlist_head saved_cap_space;
374 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
375 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
376 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
377 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
379 #ifdef CONFIG_PCIE_PTM
380 unsigned int ptm_root:1;
381 unsigned int ptm_enabled:1;
384 #ifdef CONFIG_PCI_MSI
385 const struct attribute_group **msi_irq_groups;
388 #ifdef CONFIG_PCI_ATS
390 struct pci_sriov *sriov; /* SR-IOV capability related */
391 struct pci_dev *physfn; /* the PF this VF is associated with */
393 u16 ats_cap; /* ATS Capability offset */
394 u8 ats_stu; /* ATS Smallest Translation Unit */
395 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
397 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
398 size_t romlen; /* Length of ROM if it's not from the BAR */
399 char *driver_override; /* Driver name to force a match */
402 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
404 #ifdef CONFIG_PCI_IOV
411 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
413 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
414 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
416 static inline int pci_channel_offline(struct pci_dev *pdev)
418 return (pdev->error_state != pci_channel_io_normal);
421 struct pci_host_bridge {
423 struct pci_bus *bus; /* root bus */
427 struct list_head windows; /* resource_entry */
428 void (*release_fn)(struct pci_host_bridge *);
430 struct msi_controller *msi;
431 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
432 /* Resource alignment requirements */
433 resource_size_t (*align_resource)(struct pci_dev *dev,
434 const struct resource *res,
435 resource_size_t start,
436 resource_size_t size,
437 resource_size_t align);
438 unsigned long private[0] ____cacheline_aligned;
441 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
443 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
445 return (void *)bridge->private;
448 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
450 return container_of(priv, struct pci_host_bridge, private);
453 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
454 int pci_register_host_bridge(struct pci_host_bridge *bridge);
455 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
457 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
458 void (*release_fn)(struct pci_host_bridge *),
461 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
464 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
465 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
466 * buses below host bridges or subtractive decode bridges) go in the list.
467 * Use pci_bus_for_each_resource() to iterate through all the resources.
471 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
472 * and there's no way to program the bridge with the details of the window.
473 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
474 * decode bit set, because they are explicit and can be programmed with _SRS.
476 #define PCI_SUBTRACTIVE_DECODE 0x1
478 struct pci_bus_resource {
479 struct list_head list;
480 struct resource *res;
484 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
487 struct list_head node; /* node in list of buses */
488 struct pci_bus *parent; /* parent bus this bridge is on */
489 struct list_head children; /* list of child buses */
490 struct list_head devices; /* list of devices on this bus */
491 struct pci_dev *self; /* bridge device as seen by parent */
492 struct list_head slots; /* list of slots on this bus;
493 protected by pci_slot_mutex */
494 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
495 struct list_head resources; /* address space routed to this bus */
496 struct resource busn_res; /* bus numbers routed to this bus */
498 struct pci_ops *ops; /* configuration access functions */
499 struct msi_controller *msi; /* MSI controller */
500 void *sysdata; /* hook for sys-specific extension */
501 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
503 unsigned char number; /* bus number */
504 unsigned char primary; /* number of primary bridge */
505 unsigned char max_bus_speed; /* enum pci_bus_speed */
506 unsigned char cur_bus_speed; /* enum pci_bus_speed */
507 #ifdef CONFIG_PCI_DOMAINS_GENERIC
513 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
514 pci_bus_flags_t bus_flags; /* inherited by child buses */
515 struct device *bridge;
517 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
518 struct bin_attribute *legacy_mem; /* legacy mem */
519 unsigned int is_added:1;
522 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
525 * Returns true if the PCI bus is root (behind host-PCI bridge),
528 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
529 * This is incorrect because "virtual" buses added for SR-IOV (via
530 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
532 static inline bool pci_is_root_bus(struct pci_bus *pbus)
534 return !(pbus->parent);
538 * pci_is_bridge - check if the PCI device is a bridge
541 * Return true if the PCI device is bridge whether it has subordinate
544 static inline bool pci_is_bridge(struct pci_dev *dev)
546 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
547 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
550 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
552 dev = pci_physfn(dev);
553 if (pci_is_root_bus(dev->bus))
556 return dev->bus->self;
559 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
560 void pci_put_host_bridge_device(struct device *dev);
562 #ifdef CONFIG_PCI_MSI
563 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
565 return pci_dev->msi_enabled || pci_dev->msix_enabled;
568 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
572 * Error values that may be returned by PCI functions.
574 #define PCIBIOS_SUCCESSFUL 0x00
575 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
576 #define PCIBIOS_BAD_VENDOR_ID 0x83
577 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
578 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
579 #define PCIBIOS_SET_FAILED 0x88
580 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
583 * Translate above to generic errno for passing back through non-PCI code.
585 static inline int pcibios_err_to_errno(int err)
587 if (err <= PCIBIOS_SUCCESSFUL)
588 return err; /* Assume already errno */
591 case PCIBIOS_FUNC_NOT_SUPPORTED:
593 case PCIBIOS_BAD_VENDOR_ID:
595 case PCIBIOS_DEVICE_NOT_FOUND:
597 case PCIBIOS_BAD_REGISTER_NUMBER:
599 case PCIBIOS_SET_FAILED:
601 case PCIBIOS_BUFFER_TOO_SMALL:
608 /* Low-level architecture-dependent routines */
611 int (*add_bus)(struct pci_bus *bus);
612 void (*remove_bus)(struct pci_bus *bus);
613 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
614 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
615 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
619 * ACPI needs to be able to access PCI config space before we've done a
620 * PCI bus scan and created pci_bus structures.
622 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
623 int reg, int len, u32 *val);
624 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
625 int reg, int len, u32 val);
627 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
628 typedef u64 pci_bus_addr_t;
630 typedef u32 pci_bus_addr_t;
633 struct pci_bus_region {
634 pci_bus_addr_t start;
639 spinlock_t lock; /* protects list, index */
640 struct list_head list; /* for IDs added at runtime */
645 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
646 * a set of callbacks in struct pci_error_handlers, that device driver
647 * will be notified of PCI bus errors, and will be driven to recovery
648 * when an error occurs.
651 typedef unsigned int __bitwise pci_ers_result_t;
653 enum pci_ers_result {
654 /* no result/none/not supported in device driver */
655 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
657 /* Device driver can recover without slot reset */
658 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
660 /* Device driver wants slot to be reset. */
661 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
663 /* Device has completely failed, is unrecoverable */
664 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
666 /* Device driver is fully recovered and operational */
667 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
669 /* No AER capabilities registered for the driver */
670 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
673 /* PCI bus error event callbacks */
674 struct pci_error_handlers {
675 /* PCI bus error detected on this device */
676 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
677 enum pci_channel_state error);
679 /* MMIO has been re-enabled, but not DMA */
680 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
682 /* PCI slot has been reset */
683 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
685 /* PCI function reset prepare or completed */
686 void (*reset_notify)(struct pci_dev *dev, bool prepare);
688 /* Device driver may resume normal operations */
689 void (*resume)(struct pci_dev *dev);
695 struct list_head node;
697 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
698 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
699 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
700 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
701 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
702 int (*resume_early) (struct pci_dev *dev);
703 int (*resume) (struct pci_dev *dev); /* Device woken up */
704 void (*shutdown) (struct pci_dev *dev);
705 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
706 const struct pci_error_handlers *err_handler;
707 struct device_driver driver;
708 struct pci_dynids dynids;
711 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
714 * PCI_DEVICE - macro used to describe a specific pci device
715 * @vend: the 16 bit PCI Vendor ID
716 * @dev: the 16 bit PCI Device ID
718 * This macro is used to create a struct pci_device_id that matches a
719 * specific device. The subvendor and subdevice fields will be set to
722 #define PCI_DEVICE(vend,dev) \
723 .vendor = (vend), .device = (dev), \
724 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
727 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
728 * @vend: the 16 bit PCI Vendor ID
729 * @dev: the 16 bit PCI Device ID
730 * @subvend: the 16 bit PCI Subvendor ID
731 * @subdev: the 16 bit PCI Subdevice ID
733 * This macro is used to create a struct pci_device_id that matches a
734 * specific device with subsystem information.
736 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
737 .vendor = (vend), .device = (dev), \
738 .subvendor = (subvend), .subdevice = (subdev)
741 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
742 * @dev_class: the class, subclass, prog-if triple for this device
743 * @dev_class_mask: the class mask for this device
745 * This macro is used to create a struct pci_device_id that matches a
746 * specific PCI class. The vendor, device, subvendor, and subdevice
747 * fields will be set to PCI_ANY_ID.
749 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
750 .class = (dev_class), .class_mask = (dev_class_mask), \
751 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
752 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
755 * PCI_VDEVICE - macro used to describe a specific pci device in short form
756 * @vend: the vendor name
757 * @dev: the 16 bit PCI Device ID
759 * This macro is used to create a struct pci_device_id that matches a
760 * specific PCI device. The subvendor, and subdevice fields will be set
761 * to PCI_ANY_ID. The macro allows the next field to follow as the device
765 #define PCI_VDEVICE(vend, dev) \
766 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
767 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
770 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
771 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
772 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
773 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
774 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
775 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
776 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
779 /* these external functions are only available when PCI support is enabled */
782 extern unsigned int pci_flags;
784 static inline void pci_set_flags(int flags) { pci_flags = flags; }
785 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
786 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
787 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
789 void pcie_bus_configure_settings(struct pci_bus *bus);
791 enum pcie_bus_config_types {
792 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
793 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
794 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
795 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
796 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
799 extern enum pcie_bus_config_types pcie_bus_config;
801 extern struct bus_type pci_bus_type;
803 /* Do NOT directly access these two variables, unless you are arch-specific PCI
804 * code, or PCI core code. */
805 extern struct list_head pci_root_buses; /* list of all known PCI buses */
806 /* Some device drivers need know if PCI is initiated */
807 int no_pci_devices(void);
809 void pcibios_resource_survey_bus(struct pci_bus *bus);
810 void pcibios_bus_add_device(struct pci_dev *pdev);
811 void pcibios_add_bus(struct pci_bus *bus);
812 void pcibios_remove_bus(struct pci_bus *bus);
813 void pcibios_fixup_bus(struct pci_bus *);
814 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
815 /* Architecture-specific versions may override this (weak) */
816 char *pcibios_setup(char *str);
818 /* Used only when drivers/pci/setup.c is used */
819 resource_size_t pcibios_align_resource(void *, const struct resource *,
822 void pcibios_update_irq(struct pci_dev *, int irq);
824 /* Weak but can be overriden by arch */
825 void pci_fixup_cardbus(struct pci_bus *);
827 /* Generic PCI functions used internally */
829 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
830 struct resource *res);
831 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
832 struct pci_bus_region *region);
833 void pcibios_scan_specific_bus(int busn);
834 struct pci_bus *pci_find_bus(int domain, int busnr);
835 void pci_bus_add_devices(const struct pci_bus *bus);
836 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
837 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
838 struct pci_ops *ops, void *sysdata,
839 struct list_head *resources);
840 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
841 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
842 void pci_bus_release_busn_res(struct pci_bus *b);
843 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
844 struct pci_ops *ops, void *sysdata,
845 struct list_head *resources,
846 struct msi_controller *msi);
847 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
848 struct pci_ops *ops, void *sysdata,
849 struct list_head *resources);
850 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
852 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
853 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
855 struct hotplug_slot *hotplug);
856 void pci_destroy_slot(struct pci_slot *slot);
858 void pci_dev_assign_slot(struct pci_dev *dev);
860 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
862 int pci_scan_slot(struct pci_bus *bus, int devfn);
863 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
864 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
865 unsigned int pci_scan_child_bus(struct pci_bus *bus);
866 void pci_bus_add_device(struct pci_dev *dev);
867 void pci_read_bridge_bases(struct pci_bus *child);
868 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
869 struct resource *res);
870 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
871 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
872 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
873 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
874 struct pci_dev *pci_dev_get(struct pci_dev *dev);
875 void pci_dev_put(struct pci_dev *dev);
876 void pci_remove_bus(struct pci_bus *b);
877 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
878 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
879 void pci_stop_root_bus(struct pci_bus *bus);
880 void pci_remove_root_bus(struct pci_bus *bus);
881 void pci_setup_cardbus(struct pci_bus *bus);
882 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
883 void pci_sort_breadthfirst(void);
884 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
885 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
887 /* Generic PCI functions exported to card drivers */
889 enum pci_lost_interrupt_reason {
890 PCI_LOST_IRQ_NO_INFORMATION = 0,
891 PCI_LOST_IRQ_DISABLE_MSI,
892 PCI_LOST_IRQ_DISABLE_MSIX,
893 PCI_LOST_IRQ_DISABLE_ACPI,
895 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
896 int pci_find_capability(struct pci_dev *dev, int cap);
897 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
898 int pci_find_ext_capability(struct pci_dev *dev, int cap);
899 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
900 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
901 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
902 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
904 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
905 struct pci_dev *from);
906 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
907 unsigned int ss_vendor, unsigned int ss_device,
908 struct pci_dev *from);
909 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
910 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
912 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
915 return pci_get_domain_bus_and_slot(0, bus, devfn);
917 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
918 int pci_dev_present(const struct pci_device_id *ids);
920 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
922 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
923 int where, u16 *val);
924 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
925 int where, u32 *val);
926 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
928 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
930 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
933 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
934 int where, int size, u32 *val);
935 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
936 int where, int size, u32 val);
937 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
938 int where, int size, u32 *val);
939 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
940 int where, int size, u32 val);
942 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
944 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
946 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
948 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
950 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
952 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
955 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
957 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
959 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
961 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
963 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
965 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
968 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
971 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
972 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
973 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
974 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
975 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
977 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
980 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
983 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
986 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
989 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
992 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
995 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
998 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1001 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1004 /* user-space driven config access */
1005 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1006 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1007 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1008 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1009 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1010 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1012 int __must_check pci_enable_device(struct pci_dev *dev);
1013 int __must_check pci_enable_device_io(struct pci_dev *dev);
1014 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1015 int __must_check pci_reenable_device(struct pci_dev *);
1016 int __must_check pcim_enable_device(struct pci_dev *pdev);
1017 void pcim_pin_device(struct pci_dev *pdev);
1019 static inline int pci_is_enabled(struct pci_dev *pdev)
1021 return (atomic_read(&pdev->enable_cnt) > 0);
1024 static inline int pci_is_managed(struct pci_dev *pdev)
1026 return pdev->is_managed;
1029 void pci_disable_device(struct pci_dev *dev);
1031 extern unsigned int pcibios_max_latency;
1032 void pci_set_master(struct pci_dev *dev);
1033 void pci_clear_master(struct pci_dev *dev);
1035 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1036 int pci_set_cacheline_size(struct pci_dev *dev);
1037 #define HAVE_PCI_SET_MWI
1038 int __must_check pci_set_mwi(struct pci_dev *dev);
1039 int pci_try_set_mwi(struct pci_dev *dev);
1040 void pci_clear_mwi(struct pci_dev *dev);
1041 void pci_intx(struct pci_dev *dev, int enable);
1042 bool pci_intx_mask_supported(struct pci_dev *dev);
1043 bool pci_check_and_mask_intx(struct pci_dev *dev);
1044 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1045 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1046 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1047 int pcix_get_max_mmrbc(struct pci_dev *dev);
1048 int pcix_get_mmrbc(struct pci_dev *dev);
1049 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1050 int pcie_get_readrq(struct pci_dev *dev);
1051 int pcie_set_readrq(struct pci_dev *dev, int rq);
1052 int pcie_get_mps(struct pci_dev *dev);
1053 int pcie_set_mps(struct pci_dev *dev, int mps);
1054 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1055 enum pcie_link_width *width);
1056 int __pci_reset_function(struct pci_dev *dev);
1057 int __pci_reset_function_locked(struct pci_dev *dev);
1058 int pci_reset_function(struct pci_dev *dev);
1059 int pci_try_reset_function(struct pci_dev *dev);
1060 int pci_probe_reset_slot(struct pci_slot *slot);
1061 int pci_reset_slot(struct pci_slot *slot);
1062 int pci_try_reset_slot(struct pci_slot *slot);
1063 int pci_probe_reset_bus(struct pci_bus *bus);
1064 int pci_reset_bus(struct pci_bus *bus);
1065 int pci_try_reset_bus(struct pci_bus *bus);
1066 void pci_reset_secondary_bus(struct pci_dev *dev);
1067 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1068 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1069 void pci_update_resource(struct pci_dev *dev, int resno);
1070 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1071 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1072 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1073 bool pci_device_is_present(struct pci_dev *pdev);
1074 void pci_ignore_hotplug(struct pci_dev *dev);
1076 /* ROM control related routines */
1077 int pci_enable_rom(struct pci_dev *pdev);
1078 void pci_disable_rom(struct pci_dev *pdev);
1079 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1080 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1081 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1082 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1084 /* Power management related routines */
1085 int pci_save_state(struct pci_dev *dev);
1086 void pci_restore_state(struct pci_dev *dev);
1087 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1088 int pci_load_saved_state(struct pci_dev *dev,
1089 struct pci_saved_state *state);
1090 int pci_load_and_free_saved_state(struct pci_dev *dev,
1091 struct pci_saved_state **state);
1092 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1093 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1095 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1096 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1097 u16 cap, unsigned int size);
1098 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1099 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1100 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1101 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1102 void pci_pme_active(struct pci_dev *dev, bool enable);
1103 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1104 bool runtime, bool enable);
1105 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1106 int pci_prepare_to_sleep(struct pci_dev *dev);
1107 int pci_back_from_sleep(struct pci_dev *dev);
1108 bool pci_dev_run_wake(struct pci_dev *dev);
1109 bool pci_check_pme_status(struct pci_dev *dev);
1110 void pci_pme_wakeup_bus(struct pci_bus *bus);
1111 void pci_d3cold_enable(struct pci_dev *dev);
1112 void pci_d3cold_disable(struct pci_dev *dev);
1114 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1117 return __pci_enable_wake(dev, state, false, enable);
1120 /* PCI Virtual Channel */
1121 int pci_save_vc_state(struct pci_dev *dev);
1122 void pci_restore_vc_state(struct pci_dev *dev);
1123 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1125 /* For use by arch with custom probe code */
1126 void set_pcie_port_type(struct pci_dev *pdev);
1127 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1129 /* Functions for PCI Hotplug drivers to use */
1130 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1131 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1132 unsigned int pci_rescan_bus(struct pci_bus *bus);
1133 void pci_lock_rescan_remove(void);
1134 void pci_unlock_rescan_remove(void);
1136 /* Vital product data routines */
1137 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1138 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1139 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1141 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1142 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1143 void pci_bus_assign_resources(const struct pci_bus *bus);
1144 void pci_bus_claim_resources(struct pci_bus *bus);
1145 void pci_bus_size_bridges(struct pci_bus *bus);
1146 int pci_claim_resource(struct pci_dev *, int);
1147 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1148 void pci_assign_unassigned_resources(void);
1149 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1150 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1151 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1152 void pdev_enable_device(struct pci_dev *);
1153 int pci_enable_resources(struct pci_dev *, int mask);
1154 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1155 int (*)(const struct pci_dev *, u8, u8));
1156 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1157 #define HAVE_PCI_REQ_REGIONS 2
1158 int __must_check pci_request_regions(struct pci_dev *, const char *);
1159 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1160 void pci_release_regions(struct pci_dev *);
1161 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1162 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1163 void pci_release_region(struct pci_dev *, int);
1164 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1165 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1166 void pci_release_selected_regions(struct pci_dev *, int);
1168 /* drivers/pci/bus.c */
1169 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1170 void pci_bus_put(struct pci_bus *bus);
1171 void pci_add_resource(struct list_head *resources, struct resource *res);
1172 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1173 resource_size_t offset);
1174 void pci_free_resource_list(struct list_head *resources);
1175 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1176 unsigned int flags);
1177 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1178 void pci_bus_remove_resources(struct pci_bus *bus);
1179 int devm_request_pci_bus_resources(struct device *dev,
1180 struct list_head *resources);
1182 #define pci_bus_for_each_resource(bus, res, i) \
1184 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1187 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1188 struct resource *res, resource_size_t size,
1189 resource_size_t align, resource_size_t min,
1190 unsigned long type_mask,
1191 resource_size_t (*alignf)(void *,
1192 const struct resource *,
1198 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1199 unsigned long pci_address_to_pio(phys_addr_t addr);
1200 phys_addr_t pci_pio_to_address(unsigned long pio);
1201 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1202 void pci_unmap_iospace(struct resource *res);
1204 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1206 struct pci_bus_region region;
1208 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1209 return region.start;
1212 /* Proper probing supporting hot-pluggable devices */
1213 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1214 const char *mod_name);
1217 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1219 #define pci_register_driver(driver) \
1220 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1222 void pci_unregister_driver(struct pci_driver *dev);
1225 * module_pci_driver() - Helper macro for registering a PCI driver
1226 * @__pci_driver: pci_driver struct
1228 * Helper macro for PCI drivers which do not do anything special in module
1229 * init/exit. This eliminates a lot of boilerplate. Each module may only
1230 * use this macro once, and calling it replaces module_init() and module_exit()
1232 #define module_pci_driver(__pci_driver) \
1233 module_driver(__pci_driver, pci_register_driver, \
1234 pci_unregister_driver)
1237 * builtin_pci_driver() - Helper macro for registering a PCI driver
1238 * @__pci_driver: pci_driver struct
1240 * Helper macro for PCI drivers which do not do anything special in their
1241 * init code. This eliminates a lot of boilerplate. Each driver may only
1242 * use this macro once, and calling it replaces device_initcall(...)
1244 #define builtin_pci_driver(__pci_driver) \
1245 builtin_driver(__pci_driver, pci_register_driver)
1247 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1248 int pci_add_dynid(struct pci_driver *drv,
1249 unsigned int vendor, unsigned int device,
1250 unsigned int subvendor, unsigned int subdevice,
1251 unsigned int class, unsigned int class_mask,
1252 unsigned long driver_data);
1253 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1254 struct pci_dev *dev);
1255 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1258 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1260 int pci_cfg_space_size(struct pci_dev *dev);
1261 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1262 void pci_setup_bridge(struct pci_bus *bus);
1263 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1264 unsigned long type);
1265 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1267 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1268 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1270 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1271 unsigned int command_bits, u32 flags);
1273 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1274 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1275 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1276 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1277 #define PCI_IRQ_ALL_TYPES \
1278 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1280 /* kmem_cache style wrapper around pci_alloc_consistent() */
1282 #include <linux/pci-dma.h>
1283 #include <linux/dmapool.h>
1285 #define pci_pool dma_pool
1286 #define pci_pool_create(name, pdev, size, align, allocation) \
1287 dma_pool_create(name, &pdev->dev, size, align, allocation)
1288 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1289 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1290 #define pci_pool_zalloc(pool, flags, handle) \
1291 dma_pool_zalloc(pool, flags, handle)
1292 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1295 u32 vector; /* kernel uses to write allocated vector */
1296 u16 entry; /* driver uses to specify entry, OS writes */
1299 #ifdef CONFIG_PCI_MSI
1300 int pci_msi_vec_count(struct pci_dev *dev);
1301 void pci_msi_shutdown(struct pci_dev *dev);
1302 void pci_disable_msi(struct pci_dev *dev);
1303 int pci_msix_vec_count(struct pci_dev *dev);
1304 void pci_msix_shutdown(struct pci_dev *dev);
1305 void pci_disable_msix(struct pci_dev *dev);
1306 void pci_restore_msi_state(struct pci_dev *dev);
1307 int pci_msi_enabled(void);
1308 int pci_enable_msi(struct pci_dev *dev);
1309 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1310 int minvec, int maxvec);
1311 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1312 struct msix_entry *entries, int nvec)
1314 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1319 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1320 unsigned int max_vecs, unsigned int flags,
1321 const struct irq_affinity *affd);
1323 void pci_free_irq_vectors(struct pci_dev *dev);
1324 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1325 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1326 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1329 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1330 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1331 static inline void pci_disable_msi(struct pci_dev *dev) { }
1332 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1333 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1334 static inline void pci_disable_msix(struct pci_dev *dev) { }
1335 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1336 static inline int pci_msi_enabled(void) { return 0; }
1337 static inline int pci_enable_msi(struct pci_dev *dev)
1339 static inline int pci_enable_msix_range(struct pci_dev *dev,
1340 struct msix_entry *entries, int minvec, int maxvec)
1342 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1343 struct msix_entry *entries, int nvec)
1347 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1348 unsigned int max_vecs, unsigned int flags,
1349 const struct irq_affinity *aff_desc)
1356 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1360 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1362 if (WARN_ON_ONCE(nr > 0))
1366 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1369 return cpu_possible_mask;
1372 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1374 return first_online_node;
1379 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1380 unsigned int max_vecs, unsigned int flags)
1382 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1386 #ifdef CONFIG_PCIEPORTBUS
1387 extern bool pcie_ports_disabled;
1388 extern bool pcie_ports_auto;
1390 #define pcie_ports_disabled true
1391 #define pcie_ports_auto false
1394 #ifdef CONFIG_PCIEASPM
1395 bool pcie_aspm_support_enabled(void);
1397 static inline bool pcie_aspm_support_enabled(void) { return false; }
1400 #ifdef CONFIG_PCIEAER
1401 void pci_no_aer(void);
1402 bool pci_aer_available(void);
1403 int pci_aer_init(struct pci_dev *dev);
1405 static inline void pci_no_aer(void) { }
1406 static inline bool pci_aer_available(void) { return false; }
1407 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1410 #ifdef CONFIG_PCIE_ECRC
1411 void pcie_set_ecrc_checking(struct pci_dev *dev);
1412 void pcie_ecrc_get_policy(char *str);
1414 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1415 static inline void pcie_ecrc_get_policy(char *str) { }
1418 #ifdef CONFIG_HT_IRQ
1419 /* The functions a driver should call */
1420 int ht_create_irq(struct pci_dev *dev, int idx);
1421 void ht_destroy_irq(unsigned int irq);
1422 #endif /* CONFIG_HT_IRQ */
1424 #ifdef CONFIG_PCI_ATS
1425 /* Address Translation Service */
1426 void pci_ats_init(struct pci_dev *dev);
1427 int pci_enable_ats(struct pci_dev *dev, int ps);
1428 void pci_disable_ats(struct pci_dev *dev);
1429 int pci_ats_queue_depth(struct pci_dev *dev);
1431 static inline void pci_ats_init(struct pci_dev *d) { }
1432 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1433 static inline void pci_disable_ats(struct pci_dev *d) { }
1434 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1437 #ifdef CONFIG_PCIE_PTM
1438 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1440 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1444 void pci_cfg_access_lock(struct pci_dev *dev);
1445 bool pci_cfg_access_trylock(struct pci_dev *dev);
1446 void pci_cfg_access_unlock(struct pci_dev *dev);
1449 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1450 * a PCI domain is defined to be a set of PCI buses which share
1451 * configuration space.
1453 #ifdef CONFIG_PCI_DOMAINS
1454 extern int pci_domains_supported;
1455 int pci_get_new_domain_nr(void);
1457 enum { pci_domains_supported = 0 };
1458 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1459 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1460 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1461 #endif /* CONFIG_PCI_DOMAINS */
1464 * Generic implementation for PCI domain support. If your
1465 * architecture does not need custom management of PCI
1466 * domains then this implementation will be used
1468 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1469 static inline int pci_domain_nr(struct pci_bus *bus)
1471 return bus->domain_nr;
1474 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1476 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1479 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1482 /* some architectures require additional setup to direct VGA traffic */
1483 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1484 unsigned int command_bits, u32 flags);
1485 void pci_register_set_vga_state(arch_set_vga_state_t func);
1488 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1490 return pci_request_selected_regions(pdev,
1491 pci_select_bars(pdev, IORESOURCE_IO), name);
1495 pci_release_io_regions(struct pci_dev *pdev)
1497 return pci_release_selected_regions(pdev,
1498 pci_select_bars(pdev, IORESOURCE_IO));
1502 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1504 return pci_request_selected_regions(pdev,
1505 pci_select_bars(pdev, IORESOURCE_MEM), name);
1509 pci_release_mem_regions(struct pci_dev *pdev)
1511 return pci_release_selected_regions(pdev,
1512 pci_select_bars(pdev, IORESOURCE_MEM));
1515 #else /* CONFIG_PCI is not enabled */
1517 static inline void pci_set_flags(int flags) { }
1518 static inline void pci_add_flags(int flags) { }
1519 static inline void pci_clear_flags(int flags) { }
1520 static inline int pci_has_flag(int flag) { return 0; }
1523 * If the system does not have PCI, clearly these return errors. Define
1524 * these as simple inline functions to avoid hair in drivers.
1527 #define _PCI_NOP(o, s, t) \
1528 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1530 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1532 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1533 _PCI_NOP(o, word, u16 x) \
1534 _PCI_NOP(o, dword, u32 x)
1535 _PCI_NOP_ALL(read, *)
1536 _PCI_NOP_ALL(write,)
1538 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1539 unsigned int device,
1540 struct pci_dev *from)
1543 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1544 unsigned int device,
1545 unsigned int ss_vendor,
1546 unsigned int ss_device,
1547 struct pci_dev *from)
1550 static inline struct pci_dev *pci_get_class(unsigned int class,
1551 struct pci_dev *from)
1554 #define pci_dev_present(ids) (0)
1555 #define no_pci_devices() (1)
1556 #define pci_dev_put(dev) do { } while (0)
1558 static inline void pci_set_master(struct pci_dev *dev) { }
1559 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1560 static inline void pci_disable_device(struct pci_dev *dev) { }
1561 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1563 static inline int __pci_register_driver(struct pci_driver *drv,
1564 struct module *owner)
1566 static inline int pci_register_driver(struct pci_driver *drv)
1568 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1569 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1571 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1574 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1577 /* Power management related routines */
1578 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1579 static inline void pci_restore_state(struct pci_dev *dev) { }
1580 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1582 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1584 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1587 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1591 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1592 struct resource *res)
1594 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1596 static inline void pci_release_regions(struct pci_dev *dev) { }
1598 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1600 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1601 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1603 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1605 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1607 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1610 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1614 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1615 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1616 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1618 #define dev_is_pci(d) (false)
1619 #define dev_is_pf(d) (false)
1620 #endif /* CONFIG_PCI */
1622 /* Include architecture-dependent settings and functions */
1624 #include <asm/pci.h>
1626 #ifndef pci_root_bus_fwnode
1627 #define pci_root_bus_fwnode(bus) NULL
1630 /* these helpers provide future and backwards compatibility
1631 * for accessing popular PCI BAR info */
1632 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1633 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1634 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1635 #define pci_resource_len(dev,bar) \
1636 ((pci_resource_start((dev), (bar)) == 0 && \
1637 pci_resource_end((dev), (bar)) == \
1638 pci_resource_start((dev), (bar))) ? 0 : \
1640 (pci_resource_end((dev), (bar)) - \
1641 pci_resource_start((dev), (bar)) + 1))
1643 /* Similar to the helpers above, these manipulate per-pci_dev
1644 * driver-specific data. They are really just a wrapper around
1645 * the generic device structure functions of these calls.
1647 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1649 return dev_get_drvdata(&pdev->dev);
1652 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1654 dev_set_drvdata(&pdev->dev, data);
1657 /* If you want to know what to call your pci_dev, ask this function.
1658 * Again, it's a wrapper around the generic device.
1660 static inline const char *pci_name(const struct pci_dev *pdev)
1662 return dev_name(&pdev->dev);
1666 /* Some archs don't want to expose struct resource to userland as-is
1667 * in sysfs and /proc
1669 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1670 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1671 const struct resource *rsrc,
1672 resource_size_t *start, resource_size_t *end);
1674 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1675 const struct resource *rsrc, resource_size_t *start,
1676 resource_size_t *end)
1678 *start = rsrc->start;
1681 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1685 * The world is not perfect and supplies us with broken PCI devices.
1686 * For at least a part of these bugs we need a work-around, so both
1687 * generic (drivers/pci/quirks.c) and per-architecture code can define
1688 * fixup hooks to be called for particular buggy devices.
1692 u16 vendor; /* You can use PCI_ANY_ID here of course */
1693 u16 device; /* You can use PCI_ANY_ID here of course */
1694 u32 class; /* You can use PCI_ANY_ID here too */
1695 unsigned int class_shift; /* should be 0, 8, 16 */
1696 void (*hook)(struct pci_dev *dev);
1699 enum pci_fixup_pass {
1700 pci_fixup_early, /* Before probing BARs */
1701 pci_fixup_header, /* After reading configuration header */
1702 pci_fixup_final, /* Final phase of device fixups */
1703 pci_fixup_enable, /* pci_enable_device() time */
1704 pci_fixup_resume, /* pci_device_resume() */
1705 pci_fixup_suspend, /* pci_device_suspend() */
1706 pci_fixup_resume_early, /* pci_device_resume_early() */
1707 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1710 /* Anonymous variables would be nice... */
1711 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1712 class_shift, hook) \
1713 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1714 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1715 = { vendor, device, class, class_shift, hook };
1717 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1718 class_shift, hook) \
1719 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1720 hook, vendor, device, class, class_shift, hook)
1721 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1722 class_shift, hook) \
1723 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1724 hook, vendor, device, class, class_shift, hook)
1725 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1726 class_shift, hook) \
1727 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1728 hook, vendor, device, class, class_shift, hook)
1729 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1730 class_shift, hook) \
1731 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1732 hook, vendor, device, class, class_shift, hook)
1733 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1734 class_shift, hook) \
1735 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1736 resume##hook, vendor, device, class, \
1738 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1739 class_shift, hook) \
1740 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1741 resume_early##hook, vendor, device, \
1742 class, class_shift, hook)
1743 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1744 class_shift, hook) \
1745 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1746 suspend##hook, vendor, device, class, \
1748 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1749 class_shift, hook) \
1750 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1751 suspend_late##hook, vendor, device, \
1752 class, class_shift, hook)
1754 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1755 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1756 hook, vendor, device, PCI_ANY_ID, 0, hook)
1757 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1758 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1759 hook, vendor, device, PCI_ANY_ID, 0, hook)
1760 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1761 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1762 hook, vendor, device, PCI_ANY_ID, 0, hook)
1763 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1764 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1765 hook, vendor, device, PCI_ANY_ID, 0, hook)
1766 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1767 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1768 resume##hook, vendor, device, \
1769 PCI_ANY_ID, 0, hook)
1770 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1771 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1772 resume_early##hook, vendor, device, \
1773 PCI_ANY_ID, 0, hook)
1774 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1775 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1776 suspend##hook, vendor, device, \
1777 PCI_ANY_ID, 0, hook)
1778 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1779 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1780 suspend_late##hook, vendor, device, \
1781 PCI_ANY_ID, 0, hook)
1783 #ifdef CONFIG_PCI_QUIRKS
1784 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1785 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1786 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1788 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1789 struct pci_dev *dev) { }
1790 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1795 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1801 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1802 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1803 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1804 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1805 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1807 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1809 extern int pci_pci_problems;
1810 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1811 #define PCIPCI_TRITON 2
1812 #define PCIPCI_NATOMA 4
1813 #define PCIPCI_VIAETBF 8
1814 #define PCIPCI_VSFX 16
1815 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1816 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1818 extern unsigned long pci_cardbus_io_size;
1819 extern unsigned long pci_cardbus_mem_size;
1820 extern u8 pci_dfl_cache_line_size;
1821 extern u8 pci_cache_line_size;
1823 extern unsigned long pci_hotplug_io_size;
1824 extern unsigned long pci_hotplug_mem_size;
1825 extern unsigned long pci_hotplug_bus_size;
1827 /* Architecture-specific versions may override these (weak) */
1828 void pcibios_disable_device(struct pci_dev *dev);
1829 void pcibios_set_master(struct pci_dev *dev);
1830 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1831 enum pcie_reset_state state);
1832 int pcibios_add_device(struct pci_dev *dev);
1833 void pcibios_release_device(struct pci_dev *dev);
1834 void pcibios_penalize_isa_irq(int irq, int active);
1835 int pcibios_alloc_irq(struct pci_dev *dev);
1836 void pcibios_free_irq(struct pci_dev *dev);
1838 #ifdef CONFIG_HIBERNATE_CALLBACKS
1839 extern struct dev_pm_ops pcibios_pm_ops;
1842 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1843 void __init pci_mmcfg_early_init(void);
1844 void __init pci_mmcfg_late_init(void);
1846 static inline void pci_mmcfg_early_init(void) { }
1847 static inline void pci_mmcfg_late_init(void) { }
1850 int pci_ext_cfg_avail(void);
1852 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1853 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1855 #ifdef CONFIG_PCI_IOV
1856 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1857 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1859 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1860 void pci_disable_sriov(struct pci_dev *dev);
1861 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1862 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1863 int pci_num_vf(struct pci_dev *dev);
1864 int pci_vfs_assigned(struct pci_dev *dev);
1865 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1866 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1867 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1869 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1873 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1877 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1879 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1883 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1884 int id, int reset) { }
1885 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1886 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1887 static inline int pci_vfs_assigned(struct pci_dev *dev)
1889 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1891 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1893 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1897 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1898 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1899 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1903 * pci_pcie_cap - get the saved PCIe capability offset
1906 * PCIe capability offset is calculated at PCI device initialization
1907 * time and saved in the data structure. This function returns saved
1908 * PCIe capability offset. Using this instead of pci_find_capability()
1909 * reduces unnecessary search in the PCI configuration space. If you
1910 * need to calculate PCIe capability offset from raw device for some
1911 * reasons, please use pci_find_capability() instead.
1913 static inline int pci_pcie_cap(struct pci_dev *dev)
1915 return dev->pcie_cap;
1919 * pci_is_pcie - check if the PCI device is PCI Express capable
1922 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1924 static inline bool pci_is_pcie(struct pci_dev *dev)
1926 return pci_pcie_cap(dev);
1930 * pcie_caps_reg - get the PCIe Capabilities Register
1933 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1935 return dev->pcie_flags_reg;
1939 * pci_pcie_type - get the PCIe device/port type
1942 static inline int pci_pcie_type(const struct pci_dev *dev)
1944 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1947 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
1950 if (!pci_is_pcie(dev))
1952 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1954 if (!dev->bus->self)
1956 dev = dev->bus->self;
1961 void pci_request_acs(void);
1962 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1963 bool pci_acs_path_enabled(struct pci_dev *start,
1964 struct pci_dev *end, u16 acs_flags);
1966 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1967 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1969 /* Large Resource Data Type Tag Item Names */
1970 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1971 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1972 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1974 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1975 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1976 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1978 /* Small Resource Data Type Tag Item Names */
1979 #define PCI_VPD_STIN_END 0x0f /* End */
1981 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
1983 #define PCI_VPD_SRDT_TIN_MASK 0x78
1984 #define PCI_VPD_SRDT_LEN_MASK 0x07
1985 #define PCI_VPD_LRDT_TIN_MASK 0x7f
1987 #define PCI_VPD_LRDT_TAG_SIZE 3
1988 #define PCI_VPD_SRDT_TAG_SIZE 1
1990 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1992 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1993 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1994 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1995 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1998 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1999 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2001 * Returns the extracted Large Resource Data Type length.
2003 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2005 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2009 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2010 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2012 * Returns the extracted Large Resource Data Type Tag item.
2014 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2016 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2020 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2021 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2023 * Returns the extracted Small Resource Data Type length.
2025 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2027 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2031 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2032 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2034 * Returns the extracted Small Resource Data Type Tag Item.
2036 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2038 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2042 * pci_vpd_info_field_size - Extracts the information field length
2043 * @lrdt: Pointer to the beginning of an information field header
2045 * Returns the extracted information field length.
2047 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2049 return info_field[2];
2053 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2054 * @buf: Pointer to buffered vpd data
2055 * @off: The offset into the buffer at which to begin the search
2056 * @len: The length of the vpd buffer
2057 * @rdt: The Resource Data Type to search for
2059 * Returns the index where the Resource Data Type was found or
2060 * -ENOENT otherwise.
2062 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2065 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2066 * @buf: Pointer to buffered vpd data
2067 * @off: The offset into the buffer at which to begin the search
2068 * @len: The length of the buffer area, relative to off, in which to search
2069 * @kw: The keyword to search for
2071 * Returns the index where the information field keyword was found or
2072 * -ENOENT otherwise.
2074 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2075 unsigned int len, const char *kw);
2077 /* PCI <-> OF binding helpers */
2081 void pci_set_of_node(struct pci_dev *dev);
2082 void pci_release_of_node(struct pci_dev *dev);
2083 void pci_set_bus_of_node(struct pci_bus *bus);
2084 void pci_release_bus_of_node(struct pci_bus *bus);
2085 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2087 /* Arch may override this (weak) */
2088 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2090 static inline struct device_node *
2091 pci_device_to_OF_node(const struct pci_dev *pdev)
2093 return pdev ? pdev->dev.of_node : NULL;
2096 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2098 return bus ? bus->dev.of_node : NULL;
2101 #else /* CONFIG_OF */
2102 static inline void pci_set_of_node(struct pci_dev *dev) { }
2103 static inline void pci_release_of_node(struct pci_dev *dev) { }
2104 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2105 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2106 static inline struct device_node *
2107 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2108 static inline struct irq_domain *
2109 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2110 #endif /* CONFIG_OF */
2113 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2116 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2118 static inline struct irq_domain *
2119 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2123 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2125 return pdev->dev.archdata.edev;
2129 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2130 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2131 int pci_for_each_dma_alias(struct pci_dev *pdev,
2132 int (*fn)(struct pci_dev *pdev,
2133 u16 alias, void *data), void *data);
2135 /* helper functions for operation of device flag */
2136 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2138 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2140 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2142 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2144 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2146 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2150 * pci_ari_enabled - query ARI forwarding status
2153 * Returns true if ARI forwarding is enabled.
2155 static inline bool pci_ari_enabled(struct pci_bus *bus)
2157 return bus->self && bus->self->ari_enabled;
2161 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2162 * @pdev: PCI device to check
2164 * Walk upwards from @pdev and check for each encountered bridge if it's part
2165 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2166 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2168 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2170 struct pci_dev *parent = pdev;
2172 if (pdev->is_thunderbolt)
2175 while ((parent = pci_upstream_bridge(parent)))
2176 if (parent->is_thunderbolt)
2182 /* provide the legacy pci_dma_* API */
2183 #include <linux/pci-dma-compat.h>
2185 #endif /* LINUX_PCI_H */