1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
43 #include <linux/pci_ids.h>
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
53 * The PCI interface treats multi-function devices as independent
54 * devices. The slot/function address of each device is encoded
55 * in a single byte as follows:
60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
61 * In the interest of not exposing interfaces to user-space unnecessarily,
62 * the following kernel-only defines are being added here.
64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
68 /* pci_slot represents a physical slot */
70 struct pci_bus *bus; /* Bus this slot is on */
71 struct list_head list; /* Node in list of slots */
72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
77 static inline const char *pci_slot_name(const struct pci_slot *slot)
79 return kobject_name(&slot->kobj);
82 /* File state for mmap()s on /proc/bus/pci/X/Y */
88 /* For PCI devices, the region numbers are assigned this way: */
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
94 /* #6: expansion ROM resource */
97 /* Device-specific resources */
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
103 /* PCI-to-PCI (P2P) bridge windows */
104 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
105 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
106 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
108 /* CardBus bridge windows */
109 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
110 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
111 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
112 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
114 /* Total number of bridge resources for P2P and CardBus */
115 #define PCI_BRIDGE_RESOURCE_NUM 4
117 /* Resources assigned to buses behind the bridge */
118 PCI_BRIDGE_RESOURCES,
119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
120 PCI_BRIDGE_RESOURCE_NUM - 1,
122 /* Total resources associated with a PCI device */
125 /* Preserve this for compatibility */
126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
130 * enum pci_interrupt_pin - PCI INTx interrupt values
131 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
132 * @PCI_INTERRUPT_INTA: PCI INTA pin
133 * @PCI_INTERRUPT_INTB: PCI INTB pin
134 * @PCI_INTERRUPT_INTC: PCI INTC pin
135 * @PCI_INTERRUPT_INTD: PCI INTD pin
137 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
138 * PCI_INTERRUPT_PIN register.
140 enum pci_interrupt_pin {
141 PCI_INTERRUPT_UNKNOWN,
148 /* The number of legacy PCI INTx interrupts */
149 #define PCI_NUM_INTX 4
152 * pci_power_t values must match the bits in the Capabilities PME_Support
153 * and Control/Status PowerState fields in the Power Management capability.
155 typedef int __bitwise pci_power_t;
157 #define PCI_D0 ((pci_power_t __force) 0)
158 #define PCI_D1 ((pci_power_t __force) 1)
159 #define PCI_D2 ((pci_power_t __force) 2)
160 #define PCI_D3hot ((pci_power_t __force) 3)
161 #define PCI_D3cold ((pci_power_t __force) 4)
162 #define PCI_UNKNOWN ((pci_power_t __force) 5)
163 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
165 /* Remember to update this when the list above changes! */
166 extern const char *pci_power_names[];
168 static inline const char *pci_power_name(pci_power_t state)
170 return pci_power_names[1 + (__force int) state];
174 * typedef pci_channel_state_t
176 * The pci_channel state describes connectivity between the CPU and
177 * the PCI device. If some PCI bus between here and the PCI device
178 * has crashed or locked up, this info is reflected here.
180 typedef unsigned int __bitwise pci_channel_state_t;
183 /* I/O channel is in normal state */
184 pci_channel_io_normal = (__force pci_channel_state_t) 1,
186 /* I/O to channel is blocked */
187 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
189 /* PCI card is dead */
190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
193 typedef unsigned int __bitwise pcie_reset_state_t;
195 enum pcie_reset_state {
196 /* Reset is NOT asserted (Use to deassert reset) */
197 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
199 /* Use #PERST to reset PCIe device */
200 pcie_warm_reset = (__force pcie_reset_state_t) 2,
202 /* Use PCIe Hot Reset to reset device */
203 pcie_hot_reset = (__force pcie_reset_state_t) 3
206 typedef unsigned short __bitwise pci_dev_flags_t;
208 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
210 /* Device configuration is irrevocably lost if disabled into D3 */
211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
212 /* Provide indication device is assigned by a Virtual Machine Manager */
213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
214 /* Flag for quirk use to store if quirk-specific ACS is enabled */
215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
216 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
218 /* Do not use bus resets for device */
219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
220 /* Do not use PM reset even if device advertises NoSoftRst- */
221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
222 /* Get VPD from function 0 VPD */
223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
224 /* A non-root bridge where translation occurs, stop alias search here */
225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
226 /* Do not use FLR even if device advertises PCI_AF_CAP */
227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
228 /* Don't use Relaxed Ordering for TLPs directed at this device */
229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
232 enum pci_irq_reroute_variant {
233 INTEL_IRQ_REROUTE_VARIANT = 1,
234 MAX_IRQ_REROUTE_VARIANTS = 3
237 typedef unsigned short __bitwise pci_bus_flags_t;
239 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
240 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
241 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
242 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
245 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
246 enum pcie_link_width {
247 PCIE_LNK_WIDTH_RESRV = 0x00,
255 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
258 /* See matching string table in pci_speed_string() */
260 PCI_SPEED_33MHz = 0x00,
261 PCI_SPEED_66MHz = 0x01,
262 PCI_SPEED_66MHz_PCIX = 0x02,
263 PCI_SPEED_100MHz_PCIX = 0x03,
264 PCI_SPEED_133MHz_PCIX = 0x04,
265 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
266 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
267 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
268 PCI_SPEED_66MHz_PCIX_266 = 0x09,
269 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
270 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
276 PCI_SPEED_66MHz_PCIX_533 = 0x11,
277 PCI_SPEED_100MHz_PCIX_533 = 0x12,
278 PCI_SPEED_133MHz_PCIX_533 = 0x13,
279 PCIE_SPEED_2_5GT = 0x14,
280 PCIE_SPEED_5_0GT = 0x15,
281 PCIE_SPEED_8_0GT = 0x16,
282 PCIE_SPEED_16_0GT = 0x17,
283 PCIE_SPEED_32_0GT = 0x18,
284 PCI_SPEED_UNKNOWN = 0xff,
287 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
288 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
290 struct pci_cap_saved_data {
297 struct pci_cap_saved_state {
298 struct hlist_node next;
299 struct pci_cap_saved_data cap;
303 struct pcie_link_state;
308 /* The pci_dev structure describes PCI devices */
310 struct list_head bus_list; /* Node in per-bus list */
311 struct pci_bus *bus; /* Bus this device is on */
312 struct pci_bus *subordinate; /* Bus this device bridges to */
314 void *sysdata; /* Hook for sys-specific extension */
315 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
316 struct pci_slot *slot; /* Physical slot this device is in */
318 unsigned int devfn; /* Encoded device & function index */
319 unsigned short vendor;
320 unsigned short device;
321 unsigned short subsystem_vendor;
322 unsigned short subsystem_device;
323 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
324 u8 revision; /* PCI revision, low byte of class word */
325 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
326 #ifdef CONFIG_PCIEAER
327 u16 aer_cap; /* AER capability offset */
328 struct aer_stats *aer_stats; /* AER stats for this device */
330 u8 pcie_cap; /* PCIe capability offset */
331 u8 msi_cap; /* MSI capability offset */
332 u8 msix_cap; /* MSI-X capability offset */
333 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
334 u8 rom_base_reg; /* Config register controlling ROM */
335 u8 pin; /* Interrupt pin this device uses */
336 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
337 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
339 struct pci_driver *driver; /* Driver bound to this device */
340 u64 dma_mask; /* Mask of the bits of bus address this
341 device implements. Normally this is
342 0xffffffff. You only need to change
343 this if your device has broken DMA
344 or supports 64-bit transfers. */
346 struct device_dma_parameters dma_parms;
348 pci_power_t current_state; /* Current operating state. In ACPI,
349 this is D0-D3, D0 being fully
350 functional, and D3 being off. */
351 unsigned int imm_ready:1; /* Supports Immediate Readiness */
352 u8 pm_cap; /* PM capability offset */
353 unsigned int pme_support:5; /* Bitmask of states from which PME#
355 unsigned int pme_poll:1; /* Poll device's PME status bit */
356 unsigned int d1_support:1; /* Low power state D1 is supported */
357 unsigned int d2_support:1; /* Low power state D2 is supported */
358 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
359 unsigned int no_d3cold:1; /* D3cold is forbidden */
360 unsigned int bridge_d3:1; /* Allow D3 for bridge */
361 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
362 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
363 decoding during BAR sizing */
364 unsigned int wakeup_prepared:1;
365 unsigned int runtime_d3cold:1; /* Whether go through runtime
366 D3cold, not set for devices
367 powered on/off by the
368 corresponding bridge */
369 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
370 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
371 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
372 controlled exclusively by
374 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
376 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
377 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
379 #ifdef CONFIG_PCIEASPM
380 struct pcie_link_state *link_state; /* ASPM link state */
381 unsigned int ltr_path:1; /* Latency Tolerance Reporting
382 supported from root to here */
383 int l1ss; /* L1SS Capability pointer */
385 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
387 pci_channel_state_t error_state; /* Current connectivity state */
388 struct device dev; /* Generic device interface */
390 int cfg_size; /* Size of config space */
393 * Instead of touching interrupt line and base address registers
394 * directly, use the values stored here. They might be different!
397 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
399 bool match_driver; /* Skip attaching driver */
401 unsigned int transparent:1; /* Subtractive decode bridge */
402 unsigned int io_window:1; /* Bridge has I/O window */
403 unsigned int pref_window:1; /* Bridge has pref mem window */
404 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
405 unsigned int multifunction:1; /* Multi-function device */
407 unsigned int is_busmaster:1; /* Is busmaster */
408 unsigned int no_msi:1; /* May not use MSI */
409 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
410 unsigned int block_cfg_access:1; /* Config space access blocked */
411 unsigned int broken_parity_status:1; /* Generates false positive parity */
412 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
413 unsigned int msi_enabled:1;
414 unsigned int msix_enabled:1;
415 unsigned int ari_enabled:1; /* ARI forwarding */
416 unsigned int ats_enabled:1; /* Address Translation Svc */
417 unsigned int pasid_enabled:1; /* Process Address Space ID */
418 unsigned int pri_enabled:1; /* Page Request Interface */
419 unsigned int is_managed:1;
420 unsigned int needs_freset:1; /* Requires fundamental reset */
421 unsigned int state_saved:1;
422 unsigned int is_physfn:1;
423 unsigned int is_virtfn:1;
424 unsigned int reset_fn:1;
425 unsigned int is_hotplug_bridge:1;
426 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
427 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
429 * Devices marked being untrusted are the ones that can potentially
430 * execute DMA attacks and similar. They are typically connected
431 * through external ports such as Thunderbolt but not limited to
432 * that. When an IOMMU is enabled they should be getting full
433 * mappings to make sure they cannot access arbitrary memory.
435 unsigned int untrusted:1;
437 * Info from the platform, e.g., ACPI or device tree, may mark a
438 * device as "external-facing". An external-facing device is
439 * itself internal but devices downstream from it are external.
441 unsigned int external_facing:1;
442 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
443 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
444 unsigned int irq_managed:1;
445 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
446 unsigned int is_probed:1; /* Device probing in progress */
447 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
448 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
449 pci_dev_flags_t dev_flags;
450 atomic_t enable_cnt; /* pci_enable_device has been called */
452 u32 saved_config_space[16]; /* Config space saved at suspend time */
453 struct hlist_head saved_cap_space;
454 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
455 int rom_attr_enabled; /* Display of ROM attribute enabled? */
456 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
457 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
459 #ifdef CONFIG_HOTPLUG_PCI_PCIE
460 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
462 #ifdef CONFIG_PCIE_PTM
463 unsigned int ptm_root:1;
464 unsigned int ptm_enabled:1;
467 #ifdef CONFIG_PCI_MSI
468 const struct attribute_group **msi_irq_groups;
471 #ifdef CONFIG_PCIE_DPC
473 unsigned int dpc_rp_extensions:1;
476 #ifdef CONFIG_PCI_ATS
478 struct pci_sriov *sriov; /* PF: SR-IOV info */
479 struct pci_dev *physfn; /* VF: related PF */
481 u16 ats_cap; /* ATS Capability offset */
482 u8 ats_stu; /* ATS Smallest Translation Unit */
484 #ifdef CONFIG_PCI_PRI
485 u16 pri_cap; /* PRI Capability offset */
486 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
487 unsigned int pasid_required:1; /* PRG Response PASID Required */
489 #ifdef CONFIG_PCI_PASID
490 u16 pasid_cap; /* PASID Capability offset */
493 #ifdef CONFIG_PCI_P2PDMA
494 struct pci_p2pdma *p2pdma;
496 u16 acs_cap; /* ACS Capability offset */
497 phys_addr_t rom; /* Physical address if not from BAR */
498 size_t romlen; /* Length if not from BAR */
499 char *driver_override; /* Driver name to force a match */
501 unsigned long priv_flags; /* Private flags for the PCI driver */
504 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
506 #ifdef CONFIG_PCI_IOV
513 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
515 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
516 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
518 static inline int pci_channel_offline(struct pci_dev *pdev)
520 return (pdev->error_state != pci_channel_io_normal);
523 struct pci_host_bridge {
525 struct pci_bus *bus; /* Root bus */
529 struct list_head windows; /* resource_entry */
530 struct list_head dma_ranges; /* dma ranges resource list */
531 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
532 int (*map_irq)(const struct pci_dev *, u8, u8);
533 void (*release_fn)(struct pci_host_bridge *);
535 struct msi_controller *msi;
536 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
537 unsigned int no_ext_tags:1; /* No Extended Tags */
538 unsigned int native_aer:1; /* OS may use PCIe AER */
539 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
540 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
541 unsigned int native_pme:1; /* OS may use PCIe PME */
542 unsigned int native_ltr:1; /* OS may use PCIe LTR */
543 unsigned int native_dpc:1; /* OS may use PCIe DPC */
544 unsigned int preserve_config:1; /* Preserve FW resource setup */
545 unsigned int size_windows:1; /* Enable root bus sizing */
547 /* Resource alignment requirements */
548 resource_size_t (*align_resource)(struct pci_dev *dev,
549 const struct resource *res,
550 resource_size_t start,
551 resource_size_t size,
552 resource_size_t align);
553 unsigned long private[] ____cacheline_aligned;
556 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
558 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
560 return (void *)bridge->private;
563 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
565 return container_of(priv, struct pci_host_bridge, private);
568 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
569 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
571 void pci_free_host_bridge(struct pci_host_bridge *bridge);
572 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
574 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
575 void (*release_fn)(struct pci_host_bridge *),
578 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
581 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
582 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
583 * buses below host bridges or subtractive decode bridges) go in the list.
584 * Use pci_bus_for_each_resource() to iterate through all the resources.
588 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
589 * and there's no way to program the bridge with the details of the window.
590 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
591 * decode bit set, because they are explicit and can be programmed with _SRS.
593 #define PCI_SUBTRACTIVE_DECODE 0x1
595 struct pci_bus_resource {
596 struct list_head list;
597 struct resource *res;
601 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
604 struct list_head node; /* Node in list of buses */
605 struct pci_bus *parent; /* Parent bus this bridge is on */
606 struct list_head children; /* List of child buses */
607 struct list_head devices; /* List of devices on this bus */
608 struct pci_dev *self; /* Bridge device as seen by parent */
609 struct list_head slots; /* List of slots on this bus;
610 protected by pci_slot_mutex */
611 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
612 struct list_head resources; /* Address space routed to this bus */
613 struct resource busn_res; /* Bus numbers routed to this bus */
615 struct pci_ops *ops; /* Configuration access functions */
616 struct msi_controller *msi; /* MSI controller */
617 void *sysdata; /* Hook for sys-specific extension */
618 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
620 unsigned char number; /* Bus number */
621 unsigned char primary; /* Number of primary bridge */
622 unsigned char max_bus_speed; /* enum pci_bus_speed */
623 unsigned char cur_bus_speed; /* enum pci_bus_speed */
624 #ifdef CONFIG_PCI_DOMAINS_GENERIC
630 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
631 pci_bus_flags_t bus_flags; /* Inherited by child buses */
632 struct device *bridge;
634 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
635 struct bin_attribute *legacy_mem; /* Legacy mem */
636 unsigned int is_added:1;
639 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
641 static inline u16 pci_dev_id(struct pci_dev *dev)
643 return PCI_DEVID(dev->bus->number, dev->devfn);
647 * Returns true if the PCI bus is root (behind host-PCI bridge),
650 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
651 * This is incorrect because "virtual" buses added for SR-IOV (via
652 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
654 static inline bool pci_is_root_bus(struct pci_bus *pbus)
656 return !(pbus->parent);
660 * pci_is_bridge - check if the PCI device is a bridge
663 * Return true if the PCI device is bridge whether it has subordinate
666 static inline bool pci_is_bridge(struct pci_dev *dev)
668 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
669 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
672 #define for_each_pci_bridge(dev, bus) \
673 list_for_each_entry(dev, &bus->devices, bus_list) \
674 if (!pci_is_bridge(dev)) {} else
676 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
678 dev = pci_physfn(dev);
679 if (pci_is_root_bus(dev->bus))
682 return dev->bus->self;
685 #ifdef CONFIG_PCI_MSI
686 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
688 return pci_dev->msi_enabled || pci_dev->msix_enabled;
691 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
694 /* Error values that may be returned by PCI functions */
695 #define PCIBIOS_SUCCESSFUL 0x00
696 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
697 #define PCIBIOS_BAD_VENDOR_ID 0x83
698 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
699 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
700 #define PCIBIOS_SET_FAILED 0x88
701 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
703 /* Translate above to generic errno for passing back through non-PCI code */
704 static inline int pcibios_err_to_errno(int err)
706 if (err <= PCIBIOS_SUCCESSFUL)
707 return err; /* Assume already errno */
710 case PCIBIOS_FUNC_NOT_SUPPORTED:
712 case PCIBIOS_BAD_VENDOR_ID:
714 case PCIBIOS_DEVICE_NOT_FOUND:
716 case PCIBIOS_BAD_REGISTER_NUMBER:
718 case PCIBIOS_SET_FAILED:
720 case PCIBIOS_BUFFER_TOO_SMALL:
727 /* Low-level architecture-dependent routines */
730 int (*add_bus)(struct pci_bus *bus);
731 void (*remove_bus)(struct pci_bus *bus);
732 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
733 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
734 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
738 * ACPI needs to be able to access PCI config space before we've done a
739 * PCI bus scan and created pci_bus structures.
741 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
742 int reg, int len, u32 *val);
743 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
744 int reg, int len, u32 val);
746 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
747 typedef u64 pci_bus_addr_t;
749 typedef u32 pci_bus_addr_t;
752 struct pci_bus_region {
753 pci_bus_addr_t start;
758 spinlock_t lock; /* Protects list, index */
759 struct list_head list; /* For IDs added at runtime */
764 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
765 * a set of callbacks in struct pci_error_handlers, that device driver
766 * will be notified of PCI bus errors, and will be driven to recovery
767 * when an error occurs.
770 typedef unsigned int __bitwise pci_ers_result_t;
772 enum pci_ers_result {
773 /* No result/none/not supported in device driver */
774 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
776 /* Device driver can recover without slot reset */
777 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
779 /* Device driver wants slot to be reset */
780 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
782 /* Device has completely failed, is unrecoverable */
783 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
785 /* Device driver is fully recovered and operational */
786 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
788 /* No AER capabilities registered for the driver */
789 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
792 /* PCI bus error event callbacks */
793 struct pci_error_handlers {
794 /* PCI bus error detected on this device */
795 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
796 pci_channel_state_t error);
798 /* MMIO has been re-enabled, but not DMA */
799 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
801 /* PCI slot has been reset */
802 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
804 /* PCI function reset prepare or completed */
805 void (*reset_prepare)(struct pci_dev *dev);
806 void (*reset_done)(struct pci_dev *dev);
808 /* Device driver may resume normal operations */
809 void (*resume)(struct pci_dev *dev);
816 * struct pci_driver - PCI driver structure
817 * @node: List of driver structures.
818 * @name: Driver name.
819 * @id_table: Pointer to table of device IDs the driver is
820 * interested in. Most drivers should export this
821 * table using MODULE_DEVICE_TABLE(pci,...).
822 * @probe: This probing function gets called (during execution
823 * of pci_register_driver() for already existing
824 * devices or later if a new device gets inserted) for
825 * all PCI devices which match the ID table and are not
826 * "owned" by the other drivers yet. This function gets
827 * passed a "struct pci_dev \*" for each device whose
828 * entry in the ID table matches the device. The probe
829 * function returns zero when the driver chooses to
830 * take "ownership" of the device or an error code
831 * (negative number) otherwise.
832 * The probe function always gets called from process
833 * context, so it can sleep.
834 * @remove: The remove() function gets called whenever a device
835 * being handled by this driver is removed (either during
836 * deregistration of the driver or when it's manually
837 * pulled out of a hot-pluggable slot).
838 * The remove function always gets called from process
839 * context, so it can sleep.
840 * @suspend: Put device into low power state.
841 * @resume: Wake device from low power state.
842 * (Please see Documentation/power/pci.rst for descriptions
843 * of PCI Power Management and the related functions.)
844 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
845 * Intended to stop any idling DMA operations.
846 * Useful for enabling wake-on-lan (NIC) or changing
847 * the power state of a device before reboot.
848 * e.g. drivers/net/e100.c.
849 * @sriov_configure: Optional driver callback to allow configuration of
850 * number of VFs to enable via sysfs "sriov_numvfs" file.
851 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
852 * @groups: Sysfs attribute groups.
853 * @driver: Driver model structure.
854 * @dynids: List of dynamically added device IDs.
857 struct list_head node;
859 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
860 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
861 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
862 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
863 int (*resume)(struct pci_dev *dev); /* Device woken up */
864 void (*shutdown)(struct pci_dev *dev);
865 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
866 const struct pci_error_handlers *err_handler;
867 const struct attribute_group **groups;
868 struct device_driver driver;
869 struct pci_dynids dynids;
872 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
875 * PCI_DEVICE - macro used to describe a specific PCI device
876 * @vend: the 16 bit PCI Vendor ID
877 * @dev: the 16 bit PCI Device ID
879 * This macro is used to create a struct pci_device_id that matches a
880 * specific device. The subvendor and subdevice fields will be set to
883 #define PCI_DEVICE(vend,dev) \
884 .vendor = (vend), .device = (dev), \
885 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
888 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
889 * @vend: the 16 bit PCI Vendor ID
890 * @dev: the 16 bit PCI Device ID
891 * @subvend: the 16 bit PCI Subvendor ID
892 * @subdev: the 16 bit PCI Subdevice ID
894 * This macro is used to create a struct pci_device_id that matches a
895 * specific device with subsystem information.
897 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
898 .vendor = (vend), .device = (dev), \
899 .subvendor = (subvend), .subdevice = (subdev)
902 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
903 * @dev_class: the class, subclass, prog-if triple for this device
904 * @dev_class_mask: the class mask for this device
906 * This macro is used to create a struct pci_device_id that matches a
907 * specific PCI class. The vendor, device, subvendor, and subdevice
908 * fields will be set to PCI_ANY_ID.
910 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
911 .class = (dev_class), .class_mask = (dev_class_mask), \
912 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
913 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
916 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
917 * @vend: the vendor name
918 * @dev: the 16 bit PCI Device ID
920 * This macro is used to create a struct pci_device_id that matches a
921 * specific PCI device. The subvendor, and subdevice fields will be set
922 * to PCI_ANY_ID. The macro allows the next field to follow as the device
925 #define PCI_VDEVICE(vend, dev) \
926 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
927 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
930 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
931 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
932 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
933 * @data: the driver data to be filled
935 * This macro is used to create a struct pci_device_id that matches a
936 * specific PCI device. The subvendor, and subdevice fields will be set
939 #define PCI_DEVICE_DATA(vend, dev, data) \
940 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
941 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
942 .driver_data = (kernel_ulong_t)(data)
945 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
946 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
947 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
948 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
949 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
950 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
951 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
954 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
955 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
956 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
957 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
959 /* These external functions are only available when PCI support is enabled */
962 extern unsigned int pci_flags;
964 static inline void pci_set_flags(int flags) { pci_flags = flags; }
965 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
966 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
967 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
969 void pcie_bus_configure_settings(struct pci_bus *bus);
971 enum pcie_bus_config_types {
972 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
973 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
974 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
975 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
976 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
979 extern enum pcie_bus_config_types pcie_bus_config;
981 extern struct bus_type pci_bus_type;
983 /* Do NOT directly access these two variables, unless you are arch-specific PCI
984 * code, or PCI core code. */
985 extern struct list_head pci_root_buses; /* List of all known PCI buses */
986 /* Some device drivers need know if PCI is initiated */
987 int no_pci_devices(void);
989 void pcibios_resource_survey_bus(struct pci_bus *bus);
990 void pcibios_bus_add_device(struct pci_dev *pdev);
991 void pcibios_add_bus(struct pci_bus *bus);
992 void pcibios_remove_bus(struct pci_bus *bus);
993 void pcibios_fixup_bus(struct pci_bus *);
994 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
995 /* Architecture-specific versions may override this (weak) */
996 char *pcibios_setup(char *str);
998 /* Used only when drivers/pci/setup.c is used */
999 resource_size_t pcibios_align_resource(void *, const struct resource *,
1003 /* Weak but can be overridden by arch */
1004 void pci_fixup_cardbus(struct pci_bus *);
1006 /* Generic PCI functions used internally */
1008 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1009 struct resource *res);
1010 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1011 struct pci_bus_region *region);
1012 void pcibios_scan_specific_bus(int busn);
1013 struct pci_bus *pci_find_bus(int domain, int busnr);
1014 void pci_bus_add_devices(const struct pci_bus *bus);
1015 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1016 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1017 struct pci_ops *ops, void *sysdata,
1018 struct list_head *resources);
1019 int pci_host_probe(struct pci_host_bridge *bridge);
1020 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1021 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1022 void pci_bus_release_busn_res(struct pci_bus *b);
1023 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1024 struct pci_ops *ops, void *sysdata,
1025 struct list_head *resources);
1026 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1027 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1029 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1031 struct hotplug_slot *hotplug);
1032 void pci_destroy_slot(struct pci_slot *slot);
1034 void pci_dev_assign_slot(struct pci_dev *dev);
1036 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1038 int pci_scan_slot(struct pci_bus *bus, int devfn);
1039 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1040 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1041 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1042 void pci_bus_add_device(struct pci_dev *dev);
1043 void pci_read_bridge_bases(struct pci_bus *child);
1044 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1045 struct resource *res);
1046 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1047 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1048 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1049 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1050 void pci_dev_put(struct pci_dev *dev);
1051 void pci_remove_bus(struct pci_bus *b);
1052 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1053 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1054 void pci_stop_root_bus(struct pci_bus *bus);
1055 void pci_remove_root_bus(struct pci_bus *bus);
1056 void pci_setup_cardbus(struct pci_bus *bus);
1057 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1058 void pci_sort_breadthfirst(void);
1059 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1060 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1062 /* Generic PCI functions exported to card drivers */
1064 int pci_find_capability(struct pci_dev *dev, int cap);
1065 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1066 int pci_find_ext_capability(struct pci_dev *dev, int cap);
1067 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1068 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1069 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1070 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1072 u64 pci_get_dsn(struct pci_dev *dev);
1074 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1075 struct pci_dev *from);
1076 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1077 unsigned int ss_vendor, unsigned int ss_device,
1078 struct pci_dev *from);
1079 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1080 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1081 unsigned int devfn);
1082 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1083 int pci_dev_present(const struct pci_device_id *ids);
1085 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1086 int where, u8 *val);
1087 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1088 int where, u16 *val);
1089 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1090 int where, u32 *val);
1091 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1093 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1094 int where, u16 val);
1095 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1096 int where, u32 val);
1098 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1099 int where, int size, u32 *val);
1100 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1101 int where, int size, u32 val);
1102 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1103 int where, int size, u32 *val);
1104 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1105 int where, int size, u32 val);
1107 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1109 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1110 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1111 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1112 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1113 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1114 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1116 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1117 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1118 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1119 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1120 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1121 u16 clear, u16 set);
1122 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1123 u32 clear, u32 set);
1125 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1128 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1131 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1134 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1137 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1140 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1143 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1146 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1149 /* User-space driven config access */
1150 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1151 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1152 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1153 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1154 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1155 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1157 int __must_check pci_enable_device(struct pci_dev *dev);
1158 int __must_check pci_enable_device_io(struct pci_dev *dev);
1159 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1160 int __must_check pci_reenable_device(struct pci_dev *);
1161 int __must_check pcim_enable_device(struct pci_dev *pdev);
1162 void pcim_pin_device(struct pci_dev *pdev);
1164 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1167 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1168 * writable and no quirk has marked the feature broken.
1170 return !pdev->broken_intx_masking;
1173 static inline int pci_is_enabled(struct pci_dev *pdev)
1175 return (atomic_read(&pdev->enable_cnt) > 0);
1178 static inline int pci_is_managed(struct pci_dev *pdev)
1180 return pdev->is_managed;
1183 void pci_disable_device(struct pci_dev *dev);
1185 extern unsigned int pcibios_max_latency;
1186 void pci_set_master(struct pci_dev *dev);
1187 void pci_clear_master(struct pci_dev *dev);
1189 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1190 int pci_set_cacheline_size(struct pci_dev *dev);
1191 #define HAVE_PCI_SET_MWI
1192 int __must_check pci_set_mwi(struct pci_dev *dev);
1193 int __must_check pcim_set_mwi(struct pci_dev *dev);
1194 int pci_try_set_mwi(struct pci_dev *dev);
1195 void pci_clear_mwi(struct pci_dev *dev);
1196 void pci_intx(struct pci_dev *dev, int enable);
1197 bool pci_check_and_mask_intx(struct pci_dev *dev);
1198 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1199 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1200 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1201 int pcix_get_max_mmrbc(struct pci_dev *dev);
1202 int pcix_get_mmrbc(struct pci_dev *dev);
1203 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1204 int pcie_get_readrq(struct pci_dev *dev);
1205 int pcie_set_readrq(struct pci_dev *dev, int rq);
1206 int pcie_get_mps(struct pci_dev *dev);
1207 int pcie_set_mps(struct pci_dev *dev, int mps);
1208 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1209 enum pci_bus_speed *speed,
1210 enum pcie_link_width *width);
1211 void pcie_print_link_status(struct pci_dev *dev);
1212 bool pcie_has_flr(struct pci_dev *dev);
1213 int pcie_flr(struct pci_dev *dev);
1214 int __pci_reset_function_locked(struct pci_dev *dev);
1215 int pci_reset_function(struct pci_dev *dev);
1216 int pci_reset_function_locked(struct pci_dev *dev);
1217 int pci_try_reset_function(struct pci_dev *dev);
1218 int pci_probe_reset_slot(struct pci_slot *slot);
1219 int pci_probe_reset_bus(struct pci_bus *bus);
1220 int pci_reset_bus(struct pci_dev *dev);
1221 void pci_reset_secondary_bus(struct pci_dev *dev);
1222 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1223 void pci_update_resource(struct pci_dev *dev, int resno);
1224 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1225 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1226 void pci_release_resource(struct pci_dev *dev, int resno);
1227 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1228 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1229 bool pci_device_is_present(struct pci_dev *pdev);
1230 void pci_ignore_hotplug(struct pci_dev *dev);
1231 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1232 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1234 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1235 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1236 const char *fmt, ...);
1237 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1239 /* ROM control related routines */
1240 int pci_enable_rom(struct pci_dev *pdev);
1241 void pci_disable_rom(struct pci_dev *pdev);
1242 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1243 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1245 /* Power management related routines */
1246 int pci_save_state(struct pci_dev *dev);
1247 void pci_restore_state(struct pci_dev *dev);
1248 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1249 int pci_load_saved_state(struct pci_dev *dev,
1250 struct pci_saved_state *state);
1251 int pci_load_and_free_saved_state(struct pci_dev *dev,
1252 struct pci_saved_state **state);
1253 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1254 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1256 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1257 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1258 u16 cap, unsigned int size);
1259 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1260 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1261 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1262 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1263 void pci_pme_active(struct pci_dev *dev, bool enable);
1264 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1265 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1266 int pci_prepare_to_sleep(struct pci_dev *dev);
1267 int pci_back_from_sleep(struct pci_dev *dev);
1268 bool pci_dev_run_wake(struct pci_dev *dev);
1269 void pci_d3cold_enable(struct pci_dev *dev);
1270 void pci_d3cold_disable(struct pci_dev *dev);
1271 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1272 void pci_wakeup_bus(struct pci_bus *bus);
1273 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1275 /* For use by arch with custom probe code */
1276 void set_pcie_port_type(struct pci_dev *pdev);
1277 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1279 /* Functions for PCI Hotplug drivers to use */
1280 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1281 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1282 unsigned int pci_rescan_bus(struct pci_bus *bus);
1283 void pci_lock_rescan_remove(void);
1284 void pci_unlock_rescan_remove(void);
1286 /* Vital Product Data routines */
1287 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1288 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1289 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1291 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1292 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1293 void pci_bus_assign_resources(const struct pci_bus *bus);
1294 void pci_bus_claim_resources(struct pci_bus *bus);
1295 void pci_bus_size_bridges(struct pci_bus *bus);
1296 int pci_claim_resource(struct pci_dev *, int);
1297 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1298 void pci_assign_unassigned_resources(void);
1299 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1300 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1301 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1302 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1303 void pdev_enable_device(struct pci_dev *);
1304 int pci_enable_resources(struct pci_dev *, int mask);
1305 void pci_assign_irq(struct pci_dev *dev);
1306 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1307 #define HAVE_PCI_REQ_REGIONS 2
1308 int __must_check pci_request_regions(struct pci_dev *, const char *);
1309 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1310 void pci_release_regions(struct pci_dev *);
1311 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1312 void pci_release_region(struct pci_dev *, int);
1313 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1314 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1315 void pci_release_selected_regions(struct pci_dev *, int);
1317 /* drivers/pci/bus.c */
1318 void pci_add_resource(struct list_head *resources, struct resource *res);
1319 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1320 resource_size_t offset);
1321 void pci_free_resource_list(struct list_head *resources);
1322 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1323 unsigned int flags);
1324 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1325 void pci_bus_remove_resources(struct pci_bus *bus);
1326 int devm_request_pci_bus_resources(struct device *dev,
1327 struct list_head *resources);
1329 /* Temporary until new and working PCI SBR API in place */
1330 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1332 #define pci_bus_for_each_resource(bus, res, i) \
1334 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1337 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1338 struct resource *res, resource_size_t size,
1339 resource_size_t align, resource_size_t min,
1340 unsigned long type_mask,
1341 resource_size_t (*alignf)(void *,
1342 const struct resource *,
1348 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1349 resource_size_t size);
1350 unsigned long pci_address_to_pio(phys_addr_t addr);
1351 phys_addr_t pci_pio_to_address(unsigned long pio);
1352 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1353 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1354 phys_addr_t phys_addr);
1355 void pci_unmap_iospace(struct resource *res);
1356 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1357 resource_size_t offset,
1358 resource_size_t size);
1359 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1360 struct resource *res);
1362 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1364 struct pci_bus_region region;
1366 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1367 return region.start;
1370 /* Proper probing supporting hot-pluggable devices */
1371 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1372 const char *mod_name);
1374 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1375 #define pci_register_driver(driver) \
1376 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1378 void pci_unregister_driver(struct pci_driver *dev);
1381 * module_pci_driver() - Helper macro for registering a PCI driver
1382 * @__pci_driver: pci_driver struct
1384 * Helper macro for PCI drivers which do not do anything special in module
1385 * init/exit. This eliminates a lot of boilerplate. Each module may only
1386 * use this macro once, and calling it replaces module_init() and module_exit()
1388 #define module_pci_driver(__pci_driver) \
1389 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1392 * builtin_pci_driver() - Helper macro for registering a PCI driver
1393 * @__pci_driver: pci_driver struct
1395 * Helper macro for PCI drivers which do not do anything special in their
1396 * init code. This eliminates a lot of boilerplate. Each driver may only
1397 * use this macro once, and calling it replaces device_initcall(...)
1399 #define builtin_pci_driver(__pci_driver) \
1400 builtin_driver(__pci_driver, pci_register_driver)
1402 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1403 int pci_add_dynid(struct pci_driver *drv,
1404 unsigned int vendor, unsigned int device,
1405 unsigned int subvendor, unsigned int subdevice,
1406 unsigned int class, unsigned int class_mask,
1407 unsigned long driver_data);
1408 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1409 struct pci_dev *dev);
1410 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1413 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1415 int pci_cfg_space_size(struct pci_dev *dev);
1416 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1417 void pci_setup_bridge(struct pci_bus *bus);
1418 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1419 unsigned long type);
1421 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1422 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1424 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1425 unsigned int command_bits, u32 flags);
1428 * Virtual interrupts allow for more interrupts to be allocated
1429 * than the device has interrupts for. These are not programmed
1430 * into the device's MSI-X table and must be handled by some
1431 * other driver means.
1433 #define PCI_IRQ_VIRTUAL (1 << 4)
1435 #define PCI_IRQ_ALL_TYPES \
1436 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1438 /* kmem_cache style wrapper around pci_alloc_consistent() */
1440 #include <linux/dmapool.h>
1442 #define pci_pool dma_pool
1443 #define pci_pool_create(name, pdev, size, align, allocation) \
1444 dma_pool_create(name, &pdev->dev, size, align, allocation)
1445 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1446 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1447 #define pci_pool_zalloc(pool, flags, handle) \
1448 dma_pool_zalloc(pool, flags, handle)
1449 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1452 u32 vector; /* Kernel uses to write allocated vector */
1453 u16 entry; /* Driver uses to specify entry, OS writes */
1456 #ifdef CONFIG_PCI_MSI
1457 int pci_msi_vec_count(struct pci_dev *dev);
1458 void pci_disable_msi(struct pci_dev *dev);
1459 int pci_msix_vec_count(struct pci_dev *dev);
1460 void pci_disable_msix(struct pci_dev *dev);
1461 void pci_restore_msi_state(struct pci_dev *dev);
1462 int pci_msi_enabled(void);
1463 int pci_enable_msi(struct pci_dev *dev);
1464 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1465 int minvec, int maxvec);
1466 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1467 struct msix_entry *entries, int nvec)
1469 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1474 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1475 unsigned int max_vecs, unsigned int flags,
1476 struct irq_affinity *affd);
1478 void pci_free_irq_vectors(struct pci_dev *dev);
1479 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1480 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1483 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1484 static inline void pci_disable_msi(struct pci_dev *dev) { }
1485 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1486 static inline void pci_disable_msix(struct pci_dev *dev) { }
1487 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1488 static inline int pci_msi_enabled(void) { return 0; }
1489 static inline int pci_enable_msi(struct pci_dev *dev)
1491 static inline int pci_enable_msix_range(struct pci_dev *dev,
1492 struct msix_entry *entries, int minvec, int maxvec)
1494 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1495 struct msix_entry *entries, int nvec)
1499 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1500 unsigned int max_vecs, unsigned int flags,
1501 struct irq_affinity *aff_desc)
1503 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1508 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1512 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1514 if (WARN_ON_ONCE(nr > 0))
1518 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1521 return cpu_possible_mask;
1526 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1527 * @d: the INTx IRQ domain
1528 * @node: the DT node for the device whose interrupt we're translating
1529 * @intspec: the interrupt specifier data from the DT
1530 * @intsize: the number of entries in @intspec
1531 * @out_hwirq: pointer at which to write the hwirq number
1532 * @out_type: pointer at which to write the interrupt type
1534 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1535 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1536 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1537 * INTx value to obtain the hwirq number.
1539 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1541 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1542 struct device_node *node,
1544 unsigned int intsize,
1545 unsigned long *out_hwirq,
1546 unsigned int *out_type)
1548 const u32 intx = intspec[0];
1550 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1553 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1557 #ifdef CONFIG_PCIEPORTBUS
1558 extern bool pcie_ports_disabled;
1559 extern bool pcie_ports_native;
1561 #define pcie_ports_disabled true
1562 #define pcie_ports_native false
1565 #define PCIE_LINK_STATE_L0S BIT(0)
1566 #define PCIE_LINK_STATE_L1 BIT(1)
1567 #define PCIE_LINK_STATE_CLKPM BIT(2)
1568 #define PCIE_LINK_STATE_L1_1 BIT(3)
1569 #define PCIE_LINK_STATE_L1_2 BIT(4)
1570 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1571 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1573 #ifdef CONFIG_PCIEASPM
1574 int pci_disable_link_state(struct pci_dev *pdev, int state);
1575 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1576 void pcie_no_aspm(void);
1577 bool pcie_aspm_support_enabled(void);
1578 bool pcie_aspm_enabled(struct pci_dev *pdev);
1580 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1582 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1584 static inline void pcie_no_aspm(void) { }
1585 static inline bool pcie_aspm_support_enabled(void) { return false; }
1586 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1589 #ifdef CONFIG_PCIEAER
1590 bool pci_aer_available(void);
1592 static inline bool pci_aer_available(void) { return false; }
1595 bool pci_ats_disabled(void);
1597 void pci_cfg_access_lock(struct pci_dev *dev);
1598 bool pci_cfg_access_trylock(struct pci_dev *dev);
1599 void pci_cfg_access_unlock(struct pci_dev *dev);
1602 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1603 * a PCI domain is defined to be a set of PCI buses which share
1604 * configuration space.
1606 #ifdef CONFIG_PCI_DOMAINS
1607 extern int pci_domains_supported;
1609 enum { pci_domains_supported = 0 };
1610 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1611 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1612 #endif /* CONFIG_PCI_DOMAINS */
1615 * Generic implementation for PCI domain support. If your
1616 * architecture does not need custom management of PCI
1617 * domains then this implementation will be used
1619 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1620 static inline int pci_domain_nr(struct pci_bus *bus)
1622 return bus->domain_nr;
1625 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1627 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1630 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1633 /* Some architectures require additional setup to direct VGA traffic */
1634 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1635 unsigned int command_bits, u32 flags);
1636 void pci_register_set_vga_state(arch_set_vga_state_t func);
1639 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1641 return pci_request_selected_regions(pdev,
1642 pci_select_bars(pdev, IORESOURCE_IO), name);
1646 pci_release_io_regions(struct pci_dev *pdev)
1648 return pci_release_selected_regions(pdev,
1649 pci_select_bars(pdev, IORESOURCE_IO));
1653 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1655 return pci_request_selected_regions(pdev,
1656 pci_select_bars(pdev, IORESOURCE_MEM), name);
1660 pci_release_mem_regions(struct pci_dev *pdev)
1662 return pci_release_selected_regions(pdev,
1663 pci_select_bars(pdev, IORESOURCE_MEM));
1666 #else /* CONFIG_PCI is not enabled */
1668 static inline void pci_set_flags(int flags) { }
1669 static inline void pci_add_flags(int flags) { }
1670 static inline void pci_clear_flags(int flags) { }
1671 static inline int pci_has_flag(int flag) { return 0; }
1674 * If the system does not have PCI, clearly these return errors. Define
1675 * these as simple inline functions to avoid hair in drivers.
1677 #define _PCI_NOP(o, s, t) \
1678 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1680 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1682 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1683 _PCI_NOP(o, word, u16 x) \
1684 _PCI_NOP(o, dword, u32 x)
1685 _PCI_NOP_ALL(read, *)
1686 _PCI_NOP_ALL(write,)
1688 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1689 unsigned int device,
1690 struct pci_dev *from)
1693 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1694 unsigned int device,
1695 unsigned int ss_vendor,
1696 unsigned int ss_device,
1697 struct pci_dev *from)
1700 static inline struct pci_dev *pci_get_class(unsigned int class,
1701 struct pci_dev *from)
1704 #define pci_dev_present(ids) (0)
1705 #define no_pci_devices() (1)
1706 #define pci_dev_put(dev) do { } while (0)
1708 static inline void pci_set_master(struct pci_dev *dev) { }
1709 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1710 static inline void pci_disable_device(struct pci_dev *dev) { }
1711 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1712 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1714 static inline int __pci_register_driver(struct pci_driver *drv,
1715 struct module *owner)
1717 static inline int pci_register_driver(struct pci_driver *drv)
1719 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1720 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1722 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1725 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1728 static inline u64 pci_get_dsn(struct pci_dev *dev)
1731 /* Power management related routines */
1732 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1733 static inline void pci_restore_state(struct pci_dev *dev) { }
1734 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1736 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1738 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1741 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1745 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1746 struct resource *res)
1748 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1750 static inline void pci_release_regions(struct pci_dev *dev) { }
1752 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1754 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1756 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1759 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1760 unsigned int bus, unsigned int devfn)
1763 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1764 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1766 #define dev_is_pci(d) (false)
1767 #define dev_is_pf(d) (false)
1768 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1770 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1771 struct device_node *node,
1773 unsigned int intsize,
1774 unsigned long *out_hwirq,
1775 unsigned int *out_type)
1778 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1779 struct pci_dev *dev)
1781 static inline bool pci_ats_disabled(void) { return true; }
1783 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1789 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1790 unsigned int max_vecs, unsigned int flags,
1791 struct irq_affinity *aff_desc)
1795 #endif /* CONFIG_PCI */
1798 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1799 unsigned int max_vecs, unsigned int flags)
1801 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1805 /* Include architecture-dependent settings and functions */
1807 #include <asm/pci.h>
1809 /* These two functions provide almost identical functionality. Depending
1810 * on the architecture, one will be implemented as a wrapper around the
1811 * other (in drivers/pci/mmap.c).
1813 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1814 * is expected to be an offset within that region.
1816 * pci_mmap_page_range() is the legacy architecture-specific interface,
1817 * which accepts a "user visible" resource address converted by
1818 * pci_resource_to_user(), as used in the legacy mmap() interface in
1821 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1822 struct vm_area_struct *vma,
1823 enum pci_mmap_state mmap_state, int write_combine);
1824 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1825 struct vm_area_struct *vma,
1826 enum pci_mmap_state mmap_state, int write_combine);
1828 #ifndef arch_can_pci_mmap_wc
1829 #define arch_can_pci_mmap_wc() 0
1832 #ifndef arch_can_pci_mmap_io
1833 #define arch_can_pci_mmap_io() 0
1834 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1836 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1839 #ifndef pci_root_bus_fwnode
1840 #define pci_root_bus_fwnode(bus) NULL
1844 * These helpers provide future and backwards compatibility
1845 * for accessing popular PCI BAR info
1847 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1848 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1849 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1850 #define pci_resource_len(dev,bar) \
1851 ((pci_resource_start((dev), (bar)) == 0 && \
1852 pci_resource_end((dev), (bar)) == \
1853 pci_resource_start((dev), (bar))) ? 0 : \
1855 (pci_resource_end((dev), (bar)) - \
1856 pci_resource_start((dev), (bar)) + 1))
1859 * Similar to the helpers above, these manipulate per-pci_dev
1860 * driver-specific data. They are really just a wrapper around
1861 * the generic device structure functions of these calls.
1863 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1865 return dev_get_drvdata(&pdev->dev);
1868 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1870 dev_set_drvdata(&pdev->dev, data);
1873 static inline const char *pci_name(const struct pci_dev *pdev)
1875 return dev_name(&pdev->dev);
1878 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1879 const struct resource *rsrc,
1880 resource_size_t *start, resource_size_t *end);
1883 * The world is not perfect and supplies us with broken PCI devices.
1884 * For at least a part of these bugs we need a work-around, so both
1885 * generic (drivers/pci/quirks.c) and per-architecture code can define
1886 * fixup hooks to be called for particular buggy devices.
1890 u16 vendor; /* Or PCI_ANY_ID */
1891 u16 device; /* Or PCI_ANY_ID */
1892 u32 class; /* Or PCI_ANY_ID */
1893 unsigned int class_shift; /* should be 0, 8, 16 */
1894 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1897 void (*hook)(struct pci_dev *dev);
1901 enum pci_fixup_pass {
1902 pci_fixup_early, /* Before probing BARs */
1903 pci_fixup_header, /* After reading configuration header */
1904 pci_fixup_final, /* Final phase of device fixups */
1905 pci_fixup_enable, /* pci_enable_device() time */
1906 pci_fixup_resume, /* pci_device_resume() */
1907 pci_fixup_suspend, /* pci_device_suspend() */
1908 pci_fixup_resume_early, /* pci_device_resume_early() */
1909 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1912 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1913 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1914 class_shift, hook) \
1915 __ADDRESSABLE(hook) \
1916 asm(".section " #sec ", \"a\" \n" \
1918 ".short " #vendor ", " #device " \n" \
1919 ".long " #class ", " #class_shift " \n" \
1920 ".long " #hook " - . \n" \
1922 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1923 class_shift, hook) \
1924 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1927 /* Anonymous variables would be nice... */
1928 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1929 class_shift, hook) \
1930 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1931 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1932 = { vendor, device, class, class_shift, hook };
1935 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1936 class_shift, hook) \
1937 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1938 hook, vendor, device, class, class_shift, hook)
1939 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1940 class_shift, hook) \
1941 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1942 hook, vendor, device, class, class_shift, hook)
1943 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1944 class_shift, hook) \
1945 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1946 hook, vendor, device, class, class_shift, hook)
1947 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1948 class_shift, hook) \
1949 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1950 hook, vendor, device, class, class_shift, hook)
1951 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1952 class_shift, hook) \
1953 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1954 resume##hook, vendor, device, class, class_shift, hook)
1955 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1956 class_shift, hook) \
1957 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1958 resume_early##hook, vendor, device, class, class_shift, hook)
1959 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1960 class_shift, hook) \
1961 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1962 suspend##hook, vendor, device, class, class_shift, hook)
1963 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1964 class_shift, hook) \
1965 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1966 suspend_late##hook, vendor, device, class, class_shift, hook)
1968 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1969 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1970 hook, vendor, device, PCI_ANY_ID, 0, hook)
1971 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1972 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1973 hook, vendor, device, PCI_ANY_ID, 0, hook)
1974 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1975 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1976 hook, vendor, device, PCI_ANY_ID, 0, hook)
1977 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1978 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1979 hook, vendor, device, PCI_ANY_ID, 0, hook)
1980 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1981 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1982 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1983 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1984 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1985 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1986 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1987 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1988 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1989 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1990 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1991 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1993 #ifdef CONFIG_PCI_QUIRKS
1994 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1996 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1997 struct pci_dev *dev) { }
2000 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2001 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2002 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2003 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2004 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2006 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2008 extern int pci_pci_problems;
2009 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2010 #define PCIPCI_TRITON 2
2011 #define PCIPCI_NATOMA 4
2012 #define PCIPCI_VIAETBF 8
2013 #define PCIPCI_VSFX 16
2014 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2015 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2017 extern unsigned long pci_cardbus_io_size;
2018 extern unsigned long pci_cardbus_mem_size;
2019 extern u8 pci_dfl_cache_line_size;
2020 extern u8 pci_cache_line_size;
2022 /* Architecture-specific versions may override these (weak) */
2023 void pcibios_disable_device(struct pci_dev *dev);
2024 void pcibios_set_master(struct pci_dev *dev);
2025 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2026 enum pcie_reset_state state);
2027 int pcibios_add_device(struct pci_dev *dev);
2028 void pcibios_release_device(struct pci_dev *dev);
2030 void pcibios_penalize_isa_irq(int irq, int active);
2032 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2034 int pcibios_alloc_irq(struct pci_dev *dev);
2035 void pcibios_free_irq(struct pci_dev *dev);
2036 resource_size_t pcibios_default_alignment(void);
2038 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2039 void __init pci_mmcfg_early_init(void);
2040 void __init pci_mmcfg_late_init(void);
2042 static inline void pci_mmcfg_early_init(void) { }
2043 static inline void pci_mmcfg_late_init(void) { }
2046 int pci_ext_cfg_avail(void);
2048 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2049 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2051 #ifdef CONFIG_PCI_IOV
2052 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2053 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2055 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2056 void pci_disable_sriov(struct pci_dev *dev);
2058 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2059 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2060 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2061 int pci_num_vf(struct pci_dev *dev);
2062 int pci_vfs_assigned(struct pci_dev *dev);
2063 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2064 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2065 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2066 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2067 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2069 /* Arch may override these (weak) */
2070 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2071 int pcibios_sriov_disable(struct pci_dev *pdev);
2072 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2074 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2078 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2082 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2085 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2086 struct pci_dev *virtfn, int id)
2090 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2094 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2096 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2097 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2098 static inline int pci_vfs_assigned(struct pci_dev *dev)
2100 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2102 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2104 #define pci_sriov_configure_simple NULL
2105 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2107 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2110 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2111 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2112 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2116 * pci_pcie_cap - get the saved PCIe capability offset
2119 * PCIe capability offset is calculated at PCI device initialization
2120 * time and saved in the data structure. This function returns saved
2121 * PCIe capability offset. Using this instead of pci_find_capability()
2122 * reduces unnecessary search in the PCI configuration space. If you
2123 * need to calculate PCIe capability offset from raw device for some
2124 * reasons, please use pci_find_capability() instead.
2126 static inline int pci_pcie_cap(struct pci_dev *dev)
2128 return dev->pcie_cap;
2132 * pci_is_pcie - check if the PCI device is PCI Express capable
2135 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2137 static inline bool pci_is_pcie(struct pci_dev *dev)
2139 return pci_pcie_cap(dev);
2143 * pcie_caps_reg - get the PCIe Capabilities Register
2146 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2148 return dev->pcie_flags_reg;
2152 * pci_pcie_type - get the PCIe device/port type
2155 static inline int pci_pcie_type(const struct pci_dev *dev)
2157 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2161 * pcie_find_root_port - Get the PCIe root port device
2164 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2165 * for a given PCI/PCIe Device.
2167 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2170 if (pci_is_pcie(dev) &&
2171 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2173 dev = pci_upstream_bridge(dev);
2179 void pci_request_acs(void);
2180 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2181 bool pci_acs_path_enabled(struct pci_dev *start,
2182 struct pci_dev *end, u16 acs_flags);
2183 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2185 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2186 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2188 /* Large Resource Data Type Tag Item Names */
2189 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2190 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2191 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2193 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2194 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2195 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2197 /* Small Resource Data Type Tag Item Names */
2198 #define PCI_VPD_STIN_END 0x0f /* End */
2200 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2202 #define PCI_VPD_SRDT_TIN_MASK 0x78
2203 #define PCI_VPD_SRDT_LEN_MASK 0x07
2204 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2206 #define PCI_VPD_LRDT_TAG_SIZE 3
2207 #define PCI_VPD_SRDT_TAG_SIZE 1
2209 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2211 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2212 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2213 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2214 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2215 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2218 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2219 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2221 * Returns the extracted Large Resource Data Type length.
2223 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2225 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2229 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2230 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2232 * Returns the extracted Large Resource Data Type Tag item.
2234 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2236 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2240 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2241 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2243 * Returns the extracted Small Resource Data Type length.
2245 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2247 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2251 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2252 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2254 * Returns the extracted Small Resource Data Type Tag Item.
2256 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2258 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2262 * pci_vpd_info_field_size - Extracts the information field length
2263 * @info_field: Pointer to the beginning of an information field header
2265 * Returns the extracted information field length.
2267 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2269 return info_field[2];
2273 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2274 * @buf: Pointer to buffered vpd data
2275 * @off: The offset into the buffer at which to begin the search
2276 * @len: The length of the vpd buffer
2277 * @rdt: The Resource Data Type to search for
2279 * Returns the index where the Resource Data Type was found or
2280 * -ENOENT otherwise.
2282 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2285 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2286 * @buf: Pointer to buffered vpd data
2287 * @off: The offset into the buffer at which to begin the search
2288 * @len: The length of the buffer area, relative to off, in which to search
2289 * @kw: The keyword to search for
2291 * Returns the index where the information field keyword was found or
2292 * -ENOENT otherwise.
2294 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2295 unsigned int len, const char *kw);
2297 /* PCI <-> OF binding helpers */
2301 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2303 /* Arch may override this (weak) */
2304 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2306 #else /* CONFIG_OF */
2307 static inline struct irq_domain *
2308 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2309 #endif /* CONFIG_OF */
2311 static inline struct device_node *
2312 pci_device_to_OF_node(const struct pci_dev *pdev)
2314 return pdev ? pdev->dev.of_node : NULL;
2317 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2319 return bus ? bus->dev.of_node : NULL;
2323 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2326 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2327 bool pci_pr3_present(struct pci_dev *pdev);
2329 static inline struct irq_domain *
2330 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2331 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2335 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2337 return pdev->dev.archdata.edev;
2341 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2342 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2343 int pci_for_each_dma_alias(struct pci_dev *pdev,
2344 int (*fn)(struct pci_dev *pdev,
2345 u16 alias, void *data), void *data);
2347 /* Helper functions for operation of device flag */
2348 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2350 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2352 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2354 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2356 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2358 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2362 * pci_ari_enabled - query ARI forwarding status
2365 * Returns true if ARI forwarding is enabled.
2367 static inline bool pci_ari_enabled(struct pci_bus *bus)
2369 return bus->self && bus->self->ari_enabled;
2373 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2374 * @pdev: PCI device to check
2376 * Walk upwards from @pdev and check for each encountered bridge if it's part
2377 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2378 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2380 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2382 struct pci_dev *parent = pdev;
2384 if (pdev->is_thunderbolt)
2387 while ((parent = pci_upstream_bridge(parent)))
2388 if (parent->is_thunderbolt)
2394 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2395 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2398 /* Provide the legacy pci_dma_* API */
2399 #include <linux/pci-dma-compat.h>
2401 #define pci_printk(level, pdev, fmt, arg...) \
2402 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2404 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2405 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2406 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2407 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2408 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2409 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2410 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2411 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2413 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2414 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2416 #define pci_info_ratelimited(pdev, fmt, arg...) \
2417 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2419 #define pci_WARN(pdev, condition, fmt, arg...) \
2420 WARN(condition, "%s %s: " fmt, \
2421 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2423 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2424 WARN_ONCE(condition, "%s %s: " fmt, \
2425 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2427 #endif /* LINUX_PCI_H */