1 /* SPDX-License-Identifier: GPL-2.0 */
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
27 #include <linux/mod_devicetable.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
43 #include <linux/pci_ids.h>
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
53 * The PCI interface treats multi-function devices as independent
54 * devices. The slot/function address of each device is encoded
55 * in a single byte as follows:
60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
61 * In the interest of not exposing interfaces to user-space unnecessarily,
62 * the following kernel-only defines are being added here.
64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
68 /* pci_slot represents a physical slot */
70 struct pci_bus *bus; /* Bus this slot is on */
71 struct list_head list; /* Node in list of slots */
72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
77 static inline const char *pci_slot_name(const struct pci_slot *slot)
79 return kobject_name(&slot->kobj);
82 /* File state for mmap()s on /proc/bus/pci/X/Y */
88 /* For PCI devices, the region numbers are assigned this way: */
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
94 /* #6: expansion ROM resource */
97 /* Device-specific resources */
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
103 /* PCI-to-PCI (P2P) bridge windows */
104 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
105 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
106 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
108 /* CardBus bridge windows */
109 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
110 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
111 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
112 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
114 /* Total number of bridge resources for P2P and CardBus */
115 #define PCI_BRIDGE_RESOURCE_NUM 4
117 /* Resources assigned to buses behind the bridge */
118 PCI_BRIDGE_RESOURCES,
119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
120 PCI_BRIDGE_RESOURCE_NUM - 1,
122 /* Total resources associated with a PCI device */
125 /* Preserve this for compatibility */
126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
130 * enum pci_interrupt_pin - PCI INTx interrupt values
131 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
132 * @PCI_INTERRUPT_INTA: PCI INTA pin
133 * @PCI_INTERRUPT_INTB: PCI INTB pin
134 * @PCI_INTERRUPT_INTC: PCI INTC pin
135 * @PCI_INTERRUPT_INTD: PCI INTD pin
137 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
138 * PCI_INTERRUPT_PIN register.
140 enum pci_interrupt_pin {
141 PCI_INTERRUPT_UNKNOWN,
148 /* The number of legacy PCI INTx interrupts */
149 #define PCI_NUM_INTX 4
152 * pci_power_t values must match the bits in the Capabilities PME_Support
153 * and Control/Status PowerState fields in the Power Management capability.
155 typedef int __bitwise pci_power_t;
157 #define PCI_D0 ((pci_power_t __force) 0)
158 #define PCI_D1 ((pci_power_t __force) 1)
159 #define PCI_D2 ((pci_power_t __force) 2)
160 #define PCI_D3hot ((pci_power_t __force) 3)
161 #define PCI_D3cold ((pci_power_t __force) 4)
162 #define PCI_UNKNOWN ((pci_power_t __force) 5)
163 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
165 /* Remember to update this when the list above changes! */
166 extern const char *pci_power_names[];
168 static inline const char *pci_power_name(pci_power_t state)
170 return pci_power_names[1 + (__force int) state];
174 * typedef pci_channel_state_t
176 * The pci_channel state describes connectivity between the CPU and
177 * the PCI device. If some PCI bus between here and the PCI device
178 * has crashed or locked up, this info is reflected here.
180 typedef unsigned int __bitwise pci_channel_state_t;
183 /* I/O channel is in normal state */
184 pci_channel_io_normal = (__force pci_channel_state_t) 1,
186 /* I/O to channel is blocked */
187 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
189 /* PCI card is dead */
190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
193 typedef unsigned int __bitwise pcie_reset_state_t;
195 enum pcie_reset_state {
196 /* Reset is NOT asserted (Use to deassert reset) */
197 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
199 /* Use #PERST to reset PCIe device */
200 pcie_warm_reset = (__force pcie_reset_state_t) 2,
202 /* Use PCIe Hot Reset to reset device */
203 pcie_hot_reset = (__force pcie_reset_state_t) 3
206 typedef unsigned short __bitwise pci_dev_flags_t;
208 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
210 /* Device configuration is irrevocably lost if disabled into D3 */
211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
212 /* Provide indication device is assigned by a Virtual Machine Manager */
213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
214 /* Flag for quirk use to store if quirk-specific ACS is enabled */
215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
216 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
218 /* Do not use bus resets for device */
219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
220 /* Do not use PM reset even if device advertises NoSoftRst- */
221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
222 /* Get VPD from function 0 VPD */
223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
224 /* A non-root bridge where translation occurs, stop alias search here */
225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
226 /* Do not use FLR even if device advertises PCI_AF_CAP */
227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
228 /* Don't use Relaxed Ordering for TLPs directed at this device */
229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
232 enum pci_irq_reroute_variant {
233 INTEL_IRQ_REROUTE_VARIANT = 1,
234 MAX_IRQ_REROUTE_VARIANTS = 3
237 typedef unsigned short __bitwise pci_bus_flags_t;
239 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
240 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
241 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
242 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
245 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
246 enum pcie_link_width {
247 PCIE_LNK_WIDTH_RESRV = 0x00,
255 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
258 /* See matching string table in pci_speed_string() */
260 PCI_SPEED_33MHz = 0x00,
261 PCI_SPEED_66MHz = 0x01,
262 PCI_SPEED_66MHz_PCIX = 0x02,
263 PCI_SPEED_100MHz_PCIX = 0x03,
264 PCI_SPEED_133MHz_PCIX = 0x04,
265 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
266 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
267 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
268 PCI_SPEED_66MHz_PCIX_266 = 0x09,
269 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
270 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
276 PCI_SPEED_66MHz_PCIX_533 = 0x11,
277 PCI_SPEED_100MHz_PCIX_533 = 0x12,
278 PCI_SPEED_133MHz_PCIX_533 = 0x13,
279 PCIE_SPEED_2_5GT = 0x14,
280 PCIE_SPEED_5_0GT = 0x15,
281 PCIE_SPEED_8_0GT = 0x16,
282 PCIE_SPEED_16_0GT = 0x17,
283 PCIE_SPEED_32_0GT = 0x18,
284 PCI_SPEED_UNKNOWN = 0xff,
287 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
288 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
290 struct pci_cap_saved_data {
297 struct pci_cap_saved_state {
298 struct hlist_node next;
299 struct pci_cap_saved_data cap;
303 struct pcie_link_state;
308 /* The pci_dev structure describes PCI devices */
310 struct list_head bus_list; /* Node in per-bus list */
311 struct pci_bus *bus; /* Bus this device is on */
312 struct pci_bus *subordinate; /* Bus this device bridges to */
314 void *sysdata; /* Hook for sys-specific extension */
315 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
316 struct pci_slot *slot; /* Physical slot this device is in */
318 unsigned int devfn; /* Encoded device & function index */
319 unsigned short vendor;
320 unsigned short device;
321 unsigned short subsystem_vendor;
322 unsigned short subsystem_device;
323 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
324 u8 revision; /* PCI revision, low byte of class word */
325 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
326 #ifdef CONFIG_PCIEAER
327 u16 aer_cap; /* AER capability offset */
328 struct aer_stats *aer_stats; /* AER stats for this device */
330 u8 pcie_cap; /* PCIe capability offset */
331 u8 msi_cap; /* MSI capability offset */
332 u8 msix_cap; /* MSI-X capability offset */
333 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
334 u8 rom_base_reg; /* Config register controlling ROM */
335 u8 pin; /* Interrupt pin this device uses */
336 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
337 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
339 struct pci_driver *driver; /* Driver bound to this device */
340 u64 dma_mask; /* Mask of the bits of bus address this
341 device implements. Normally this is
342 0xffffffff. You only need to change
343 this if your device has broken DMA
344 or supports 64-bit transfers. */
346 struct device_dma_parameters dma_parms;
348 pci_power_t current_state; /* Current operating state. In ACPI,
349 this is D0-D3, D0 being fully
350 functional, and D3 being off. */
351 unsigned int imm_ready:1; /* Supports Immediate Readiness */
352 u8 pm_cap; /* PM capability offset */
353 unsigned int pme_support:5; /* Bitmask of states from which PME#
355 unsigned int pme_poll:1; /* Poll device's PME status bit */
356 unsigned int d1_support:1; /* Low power state D1 is supported */
357 unsigned int d2_support:1; /* Low power state D2 is supported */
358 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
359 unsigned int no_d3cold:1; /* D3cold is forbidden */
360 unsigned int bridge_d3:1; /* Allow D3 for bridge */
361 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
362 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
363 decoding during BAR sizing */
364 unsigned int wakeup_prepared:1;
365 unsigned int runtime_d3cold:1; /* Whether go through runtime
366 D3cold, not set for devices
367 powered on/off by the
368 corresponding bridge */
369 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
370 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
371 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
372 controlled exclusively by
374 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
376 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
377 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
379 #ifdef CONFIG_PCIEASPM
380 struct pcie_link_state *link_state; /* ASPM link state */
381 unsigned int ltr_path:1; /* Latency Tolerance Reporting
382 supported from root to here */
383 int l1ss; /* L1SS Capability pointer */
385 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
387 pci_channel_state_t error_state; /* Current connectivity state */
388 struct device dev; /* Generic device interface */
390 int cfg_size; /* Size of config space */
393 * Instead of touching interrupt line and base address registers
394 * directly, use the values stored here. They might be different!
397 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
399 bool match_driver; /* Skip attaching driver */
401 unsigned int transparent:1; /* Subtractive decode bridge */
402 unsigned int io_window:1; /* Bridge has I/O window */
403 unsigned int pref_window:1; /* Bridge has pref mem window */
404 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
405 unsigned int multifunction:1; /* Multi-function device */
407 unsigned int is_busmaster:1; /* Is busmaster */
408 unsigned int no_msi:1; /* May not use MSI */
409 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
410 unsigned int block_cfg_access:1; /* Config space access blocked */
411 unsigned int broken_parity_status:1; /* Generates false positive parity */
412 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
413 unsigned int msi_enabled:1;
414 unsigned int msix_enabled:1;
415 unsigned int ari_enabled:1; /* ARI forwarding */
416 unsigned int ats_enabled:1; /* Address Translation Svc */
417 unsigned int pasid_enabled:1; /* Process Address Space ID */
418 unsigned int pri_enabled:1; /* Page Request Interface */
419 unsigned int is_managed:1;
420 unsigned int needs_freset:1; /* Requires fundamental reset */
421 unsigned int state_saved:1;
422 unsigned int is_physfn:1;
423 unsigned int is_virtfn:1;
424 unsigned int reset_fn:1;
425 unsigned int is_hotplug_bridge:1;
426 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
427 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
429 * Devices marked being untrusted are the ones that can potentially
430 * execute DMA attacks and similar. They are typically connected
431 * through external ports such as Thunderbolt but not limited to
432 * that. When an IOMMU is enabled they should be getting full
433 * mappings to make sure they cannot access arbitrary memory.
435 unsigned int untrusted:1;
437 * Info from the platform, e.g., ACPI or device tree, may mark a
438 * device as "external-facing". An external-facing device is
439 * itself internal but devices downstream from it are external.
441 unsigned int external_facing:1;
442 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
443 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
444 unsigned int irq_managed:1;
445 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
446 unsigned int is_probed:1; /* Device probing in progress */
447 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
448 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
449 pci_dev_flags_t dev_flags;
450 atomic_t enable_cnt; /* pci_enable_device has been called */
452 u32 saved_config_space[16]; /* Config space saved at suspend time */
453 struct hlist_head saved_cap_space;
454 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
455 int rom_attr_enabled; /* Display of ROM attribute enabled? */
456 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
457 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
459 #ifdef CONFIG_HOTPLUG_PCI_PCIE
460 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
462 #ifdef CONFIG_PCIE_PTM
463 unsigned int ptm_root:1;
464 unsigned int ptm_enabled:1;
467 #ifdef CONFIG_PCI_MSI
468 const struct attribute_group **msi_irq_groups;
471 #ifdef CONFIG_PCIE_DPC
473 unsigned int dpc_rp_extensions:1;
476 #ifdef CONFIG_PCI_ATS
478 struct pci_sriov *sriov; /* PF: SR-IOV info */
479 struct pci_dev *physfn; /* VF: related PF */
481 u16 ats_cap; /* ATS Capability offset */
482 u8 ats_stu; /* ATS Smallest Translation Unit */
484 #ifdef CONFIG_PCI_PRI
485 u16 pri_cap; /* PRI Capability offset */
486 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
487 unsigned int pasid_required:1; /* PRG Response PASID Required */
489 #ifdef CONFIG_PCI_PASID
490 u16 pasid_cap; /* PASID Capability offset */
493 #ifdef CONFIG_PCI_P2PDMA
494 struct pci_p2pdma *p2pdma;
496 u16 acs_cap; /* ACS Capability offset */
497 phys_addr_t rom; /* Physical address if not from BAR */
498 size_t romlen; /* Length if not from BAR */
499 char *driver_override; /* Driver name to force a match */
501 unsigned long priv_flags; /* Private flags for the PCI driver */
504 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
506 #ifdef CONFIG_PCI_IOV
513 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
515 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
516 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
518 static inline int pci_channel_offline(struct pci_dev *pdev)
520 return (pdev->error_state != pci_channel_io_normal);
523 struct pci_host_bridge {
525 struct pci_bus *bus; /* Root bus */
527 struct pci_ops *child_ops;
530 struct list_head windows; /* resource_entry */
531 struct list_head dma_ranges; /* dma ranges resource list */
532 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
533 int (*map_irq)(const struct pci_dev *, u8, u8);
534 void (*release_fn)(struct pci_host_bridge *);
536 struct msi_controller *msi;
537 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
538 unsigned int no_ext_tags:1; /* No Extended Tags */
539 unsigned int native_aer:1; /* OS may use PCIe AER */
540 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
541 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
542 unsigned int native_pme:1; /* OS may use PCIe PME */
543 unsigned int native_ltr:1; /* OS may use PCIe LTR */
544 unsigned int native_dpc:1; /* OS may use PCIe DPC */
545 unsigned int preserve_config:1; /* Preserve FW resource setup */
546 unsigned int size_windows:1; /* Enable root bus sizing */
548 /* Resource alignment requirements */
549 resource_size_t (*align_resource)(struct pci_dev *dev,
550 const struct resource *res,
551 resource_size_t start,
552 resource_size_t size,
553 resource_size_t align);
554 unsigned long private[] ____cacheline_aligned;
557 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
559 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
561 return (void *)bridge->private;
564 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
566 return container_of(priv, struct pci_host_bridge, private);
569 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
570 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
572 void pci_free_host_bridge(struct pci_host_bridge *bridge);
573 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
575 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
576 void (*release_fn)(struct pci_host_bridge *),
579 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
582 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
583 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
584 * buses below host bridges or subtractive decode bridges) go in the list.
585 * Use pci_bus_for_each_resource() to iterate through all the resources.
589 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
590 * and there's no way to program the bridge with the details of the window.
591 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
592 * decode bit set, because they are explicit and can be programmed with _SRS.
594 #define PCI_SUBTRACTIVE_DECODE 0x1
596 struct pci_bus_resource {
597 struct list_head list;
598 struct resource *res;
602 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
605 struct list_head node; /* Node in list of buses */
606 struct pci_bus *parent; /* Parent bus this bridge is on */
607 struct list_head children; /* List of child buses */
608 struct list_head devices; /* List of devices on this bus */
609 struct pci_dev *self; /* Bridge device as seen by parent */
610 struct list_head slots; /* List of slots on this bus;
611 protected by pci_slot_mutex */
612 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
613 struct list_head resources; /* Address space routed to this bus */
614 struct resource busn_res; /* Bus numbers routed to this bus */
616 struct pci_ops *ops; /* Configuration access functions */
617 struct msi_controller *msi; /* MSI controller */
618 void *sysdata; /* Hook for sys-specific extension */
619 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
621 unsigned char number; /* Bus number */
622 unsigned char primary; /* Number of primary bridge */
623 unsigned char max_bus_speed; /* enum pci_bus_speed */
624 unsigned char cur_bus_speed; /* enum pci_bus_speed */
625 #ifdef CONFIG_PCI_DOMAINS_GENERIC
631 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
632 pci_bus_flags_t bus_flags; /* Inherited by child buses */
633 struct device *bridge;
635 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
636 struct bin_attribute *legacy_mem; /* Legacy mem */
637 unsigned int is_added:1;
640 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
642 static inline u16 pci_dev_id(struct pci_dev *dev)
644 return PCI_DEVID(dev->bus->number, dev->devfn);
648 * Returns true if the PCI bus is root (behind host-PCI bridge),
651 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
652 * This is incorrect because "virtual" buses added for SR-IOV (via
653 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
655 static inline bool pci_is_root_bus(struct pci_bus *pbus)
657 return !(pbus->parent);
661 * pci_is_bridge - check if the PCI device is a bridge
664 * Return true if the PCI device is bridge whether it has subordinate
667 static inline bool pci_is_bridge(struct pci_dev *dev)
669 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
670 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
673 #define for_each_pci_bridge(dev, bus) \
674 list_for_each_entry(dev, &bus->devices, bus_list) \
675 if (!pci_is_bridge(dev)) {} else
677 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
679 dev = pci_physfn(dev);
680 if (pci_is_root_bus(dev->bus))
683 return dev->bus->self;
686 #ifdef CONFIG_PCI_MSI
687 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
689 return pci_dev->msi_enabled || pci_dev->msix_enabled;
692 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
695 /* Error values that may be returned by PCI functions */
696 #define PCIBIOS_SUCCESSFUL 0x00
697 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
698 #define PCIBIOS_BAD_VENDOR_ID 0x83
699 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
700 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
701 #define PCIBIOS_SET_FAILED 0x88
702 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
704 /* Translate above to generic errno for passing back through non-PCI code */
705 static inline int pcibios_err_to_errno(int err)
707 if (err <= PCIBIOS_SUCCESSFUL)
708 return err; /* Assume already errno */
711 case PCIBIOS_FUNC_NOT_SUPPORTED:
713 case PCIBIOS_BAD_VENDOR_ID:
715 case PCIBIOS_DEVICE_NOT_FOUND:
717 case PCIBIOS_BAD_REGISTER_NUMBER:
719 case PCIBIOS_SET_FAILED:
721 case PCIBIOS_BUFFER_TOO_SMALL:
728 /* Low-level architecture-dependent routines */
731 int (*add_bus)(struct pci_bus *bus);
732 void (*remove_bus)(struct pci_bus *bus);
733 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
734 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
735 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
739 * ACPI needs to be able to access PCI config space before we've done a
740 * PCI bus scan and created pci_bus structures.
742 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
743 int reg, int len, u32 *val);
744 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
745 int reg, int len, u32 val);
747 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
748 typedef u64 pci_bus_addr_t;
750 typedef u32 pci_bus_addr_t;
753 struct pci_bus_region {
754 pci_bus_addr_t start;
759 spinlock_t lock; /* Protects list, index */
760 struct list_head list; /* For IDs added at runtime */
765 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
766 * a set of callbacks in struct pci_error_handlers, that device driver
767 * will be notified of PCI bus errors, and will be driven to recovery
768 * when an error occurs.
771 typedef unsigned int __bitwise pci_ers_result_t;
773 enum pci_ers_result {
774 /* No result/none/not supported in device driver */
775 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
777 /* Device driver can recover without slot reset */
778 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
780 /* Device driver wants slot to be reset */
781 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
783 /* Device has completely failed, is unrecoverable */
784 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
786 /* Device driver is fully recovered and operational */
787 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
789 /* No AER capabilities registered for the driver */
790 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
793 /* PCI bus error event callbacks */
794 struct pci_error_handlers {
795 /* PCI bus error detected on this device */
796 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
797 pci_channel_state_t error);
799 /* MMIO has been re-enabled, but not DMA */
800 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
802 /* PCI slot has been reset */
803 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
805 /* PCI function reset prepare or completed */
806 void (*reset_prepare)(struct pci_dev *dev);
807 void (*reset_done)(struct pci_dev *dev);
809 /* Device driver may resume normal operations */
810 void (*resume)(struct pci_dev *dev);
817 * struct pci_driver - PCI driver structure
818 * @node: List of driver structures.
819 * @name: Driver name.
820 * @id_table: Pointer to table of device IDs the driver is
821 * interested in. Most drivers should export this
822 * table using MODULE_DEVICE_TABLE(pci,...).
823 * @probe: This probing function gets called (during execution
824 * of pci_register_driver() for already existing
825 * devices or later if a new device gets inserted) for
826 * all PCI devices which match the ID table and are not
827 * "owned" by the other drivers yet. This function gets
828 * passed a "struct pci_dev \*" for each device whose
829 * entry in the ID table matches the device. The probe
830 * function returns zero when the driver chooses to
831 * take "ownership" of the device or an error code
832 * (negative number) otherwise.
833 * The probe function always gets called from process
834 * context, so it can sleep.
835 * @remove: The remove() function gets called whenever a device
836 * being handled by this driver is removed (either during
837 * deregistration of the driver or when it's manually
838 * pulled out of a hot-pluggable slot).
839 * The remove function always gets called from process
840 * context, so it can sleep.
841 * @suspend: Put device into low power state.
842 * @resume: Wake device from low power state.
843 * (Please see Documentation/power/pci.rst for descriptions
844 * of PCI Power Management and the related functions.)
845 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
846 * Intended to stop any idling DMA operations.
847 * Useful for enabling wake-on-lan (NIC) or changing
848 * the power state of a device before reboot.
849 * e.g. drivers/net/e100.c.
850 * @sriov_configure: Optional driver callback to allow configuration of
851 * number of VFs to enable via sysfs "sriov_numvfs" file.
852 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
853 * @groups: Sysfs attribute groups.
854 * @driver: Driver model structure.
855 * @dynids: List of dynamically added device IDs.
858 struct list_head node;
860 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
861 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
862 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
863 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
864 int (*resume)(struct pci_dev *dev); /* Device woken up */
865 void (*shutdown)(struct pci_dev *dev);
866 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
867 const struct pci_error_handlers *err_handler;
868 const struct attribute_group **groups;
869 struct device_driver driver;
870 struct pci_dynids dynids;
873 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
876 * PCI_DEVICE - macro used to describe a specific PCI device
877 * @vend: the 16 bit PCI Vendor ID
878 * @dev: the 16 bit PCI Device ID
880 * This macro is used to create a struct pci_device_id that matches a
881 * specific device. The subvendor and subdevice fields will be set to
884 #define PCI_DEVICE(vend,dev) \
885 .vendor = (vend), .device = (dev), \
886 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
889 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
890 * @vend: the 16 bit PCI Vendor ID
891 * @dev: the 16 bit PCI Device ID
892 * @subvend: the 16 bit PCI Subvendor ID
893 * @subdev: the 16 bit PCI Subdevice ID
895 * This macro is used to create a struct pci_device_id that matches a
896 * specific device with subsystem information.
898 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
899 .vendor = (vend), .device = (dev), \
900 .subvendor = (subvend), .subdevice = (subdev)
903 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
904 * @dev_class: the class, subclass, prog-if triple for this device
905 * @dev_class_mask: the class mask for this device
907 * This macro is used to create a struct pci_device_id that matches a
908 * specific PCI class. The vendor, device, subvendor, and subdevice
909 * fields will be set to PCI_ANY_ID.
911 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
912 .class = (dev_class), .class_mask = (dev_class_mask), \
913 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
914 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
917 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
918 * @vend: the vendor name
919 * @dev: the 16 bit PCI Device ID
921 * This macro is used to create a struct pci_device_id that matches a
922 * specific PCI device. The subvendor, and subdevice fields will be set
923 * to PCI_ANY_ID. The macro allows the next field to follow as the device
926 #define PCI_VDEVICE(vend, dev) \
927 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
928 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
931 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
932 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
933 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
934 * @data: the driver data to be filled
936 * This macro is used to create a struct pci_device_id that matches a
937 * specific PCI device. The subvendor, and subdevice fields will be set
940 #define PCI_DEVICE_DATA(vend, dev, data) \
941 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
942 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
943 .driver_data = (kernel_ulong_t)(data)
946 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
947 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
948 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
949 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
950 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
951 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
952 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
955 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
956 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
957 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
958 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
960 /* These external functions are only available when PCI support is enabled */
963 extern unsigned int pci_flags;
965 static inline void pci_set_flags(int flags) { pci_flags = flags; }
966 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
967 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
968 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
970 void pcie_bus_configure_settings(struct pci_bus *bus);
972 enum pcie_bus_config_types {
973 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
974 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
975 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
976 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
977 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
980 extern enum pcie_bus_config_types pcie_bus_config;
982 extern struct bus_type pci_bus_type;
984 /* Do NOT directly access these two variables, unless you are arch-specific PCI
985 * code, or PCI core code. */
986 extern struct list_head pci_root_buses; /* List of all known PCI buses */
987 /* Some device drivers need know if PCI is initiated */
988 int no_pci_devices(void);
990 void pcibios_resource_survey_bus(struct pci_bus *bus);
991 void pcibios_bus_add_device(struct pci_dev *pdev);
992 void pcibios_add_bus(struct pci_bus *bus);
993 void pcibios_remove_bus(struct pci_bus *bus);
994 void pcibios_fixup_bus(struct pci_bus *);
995 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
996 /* Architecture-specific versions may override this (weak) */
997 char *pcibios_setup(char *str);
999 /* Used only when drivers/pci/setup.c is used */
1000 resource_size_t pcibios_align_resource(void *, const struct resource *,
1004 /* Weak but can be overridden by arch */
1005 void pci_fixup_cardbus(struct pci_bus *);
1007 /* Generic PCI functions used internally */
1009 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1010 struct resource *res);
1011 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1012 struct pci_bus_region *region);
1013 void pcibios_scan_specific_bus(int busn);
1014 struct pci_bus *pci_find_bus(int domain, int busnr);
1015 void pci_bus_add_devices(const struct pci_bus *bus);
1016 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1017 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1018 struct pci_ops *ops, void *sysdata,
1019 struct list_head *resources);
1020 int pci_host_probe(struct pci_host_bridge *bridge);
1021 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1022 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1023 void pci_bus_release_busn_res(struct pci_bus *b);
1024 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1025 struct pci_ops *ops, void *sysdata,
1026 struct list_head *resources);
1027 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1028 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1030 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1032 struct hotplug_slot *hotplug);
1033 void pci_destroy_slot(struct pci_slot *slot);
1035 void pci_dev_assign_slot(struct pci_dev *dev);
1037 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1039 int pci_scan_slot(struct pci_bus *bus, int devfn);
1040 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1041 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1042 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1043 void pci_bus_add_device(struct pci_dev *dev);
1044 void pci_read_bridge_bases(struct pci_bus *child);
1045 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1046 struct resource *res);
1047 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1048 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1049 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1050 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1051 void pci_dev_put(struct pci_dev *dev);
1052 void pci_remove_bus(struct pci_bus *b);
1053 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1054 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1055 void pci_stop_root_bus(struct pci_bus *bus);
1056 void pci_remove_root_bus(struct pci_bus *bus);
1057 void pci_setup_cardbus(struct pci_bus *bus);
1058 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1059 void pci_sort_breadthfirst(void);
1060 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1061 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1063 /* Generic PCI functions exported to card drivers */
1065 int pci_find_capability(struct pci_dev *dev, int cap);
1066 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1067 int pci_find_ext_capability(struct pci_dev *dev, int cap);
1068 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1069 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1070 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1071 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1073 u64 pci_get_dsn(struct pci_dev *dev);
1075 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1076 struct pci_dev *from);
1077 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1078 unsigned int ss_vendor, unsigned int ss_device,
1079 struct pci_dev *from);
1080 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1081 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1082 unsigned int devfn);
1083 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1084 int pci_dev_present(const struct pci_device_id *ids);
1086 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1087 int where, u8 *val);
1088 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1089 int where, u16 *val);
1090 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1091 int where, u32 *val);
1092 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1094 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1095 int where, u16 val);
1096 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1097 int where, u32 val);
1099 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1100 int where, int size, u32 *val);
1101 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1102 int where, int size, u32 val);
1103 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1104 int where, int size, u32 *val);
1105 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1106 int where, int size, u32 val);
1108 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1110 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1111 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1112 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1113 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1114 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1115 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1117 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1118 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1119 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1120 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1121 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1122 u16 clear, u16 set);
1123 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1124 u32 clear, u32 set);
1126 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1129 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1132 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1135 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1138 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1141 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1144 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1147 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1150 /* User-space driven config access */
1151 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1152 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1153 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1154 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1155 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1156 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1158 int __must_check pci_enable_device(struct pci_dev *dev);
1159 int __must_check pci_enable_device_io(struct pci_dev *dev);
1160 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1161 int __must_check pci_reenable_device(struct pci_dev *);
1162 int __must_check pcim_enable_device(struct pci_dev *pdev);
1163 void pcim_pin_device(struct pci_dev *pdev);
1165 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1168 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1169 * writable and no quirk has marked the feature broken.
1171 return !pdev->broken_intx_masking;
1174 static inline int pci_is_enabled(struct pci_dev *pdev)
1176 return (atomic_read(&pdev->enable_cnt) > 0);
1179 static inline int pci_is_managed(struct pci_dev *pdev)
1181 return pdev->is_managed;
1184 void pci_disable_device(struct pci_dev *dev);
1186 extern unsigned int pcibios_max_latency;
1187 void pci_set_master(struct pci_dev *dev);
1188 void pci_clear_master(struct pci_dev *dev);
1190 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1191 int pci_set_cacheline_size(struct pci_dev *dev);
1192 #define HAVE_PCI_SET_MWI
1193 int __must_check pci_set_mwi(struct pci_dev *dev);
1194 int __must_check pcim_set_mwi(struct pci_dev *dev);
1195 int pci_try_set_mwi(struct pci_dev *dev);
1196 void pci_clear_mwi(struct pci_dev *dev);
1197 void pci_intx(struct pci_dev *dev, int enable);
1198 bool pci_check_and_mask_intx(struct pci_dev *dev);
1199 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1200 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1201 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1202 int pcix_get_max_mmrbc(struct pci_dev *dev);
1203 int pcix_get_mmrbc(struct pci_dev *dev);
1204 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1205 int pcie_get_readrq(struct pci_dev *dev);
1206 int pcie_set_readrq(struct pci_dev *dev, int rq);
1207 int pcie_get_mps(struct pci_dev *dev);
1208 int pcie_set_mps(struct pci_dev *dev, int mps);
1209 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1210 enum pci_bus_speed *speed,
1211 enum pcie_link_width *width);
1212 void pcie_print_link_status(struct pci_dev *dev);
1213 bool pcie_has_flr(struct pci_dev *dev);
1214 int pcie_flr(struct pci_dev *dev);
1215 int __pci_reset_function_locked(struct pci_dev *dev);
1216 int pci_reset_function(struct pci_dev *dev);
1217 int pci_reset_function_locked(struct pci_dev *dev);
1218 int pci_try_reset_function(struct pci_dev *dev);
1219 int pci_probe_reset_slot(struct pci_slot *slot);
1220 int pci_probe_reset_bus(struct pci_bus *bus);
1221 int pci_reset_bus(struct pci_dev *dev);
1222 void pci_reset_secondary_bus(struct pci_dev *dev);
1223 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1224 void pci_update_resource(struct pci_dev *dev, int resno);
1225 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1226 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1227 void pci_release_resource(struct pci_dev *dev, int resno);
1228 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1229 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1230 bool pci_device_is_present(struct pci_dev *pdev);
1231 void pci_ignore_hotplug(struct pci_dev *dev);
1232 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1233 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1235 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1236 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1237 const char *fmt, ...);
1238 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1240 /* ROM control related routines */
1241 int pci_enable_rom(struct pci_dev *pdev);
1242 void pci_disable_rom(struct pci_dev *pdev);
1243 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1244 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1246 /* Power management related routines */
1247 int pci_save_state(struct pci_dev *dev);
1248 void pci_restore_state(struct pci_dev *dev);
1249 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1250 int pci_load_saved_state(struct pci_dev *dev,
1251 struct pci_saved_state *state);
1252 int pci_load_and_free_saved_state(struct pci_dev *dev,
1253 struct pci_saved_state **state);
1254 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1255 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1257 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1258 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1259 u16 cap, unsigned int size);
1260 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1261 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1262 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1263 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1264 void pci_pme_active(struct pci_dev *dev, bool enable);
1265 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1266 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1267 int pci_prepare_to_sleep(struct pci_dev *dev);
1268 int pci_back_from_sleep(struct pci_dev *dev);
1269 bool pci_dev_run_wake(struct pci_dev *dev);
1270 void pci_d3cold_enable(struct pci_dev *dev);
1271 void pci_d3cold_disable(struct pci_dev *dev);
1272 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1273 void pci_wakeup_bus(struct pci_bus *bus);
1274 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1276 /* For use by arch with custom probe code */
1277 void set_pcie_port_type(struct pci_dev *pdev);
1278 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1280 /* Functions for PCI Hotplug drivers to use */
1281 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1282 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1283 unsigned int pci_rescan_bus(struct pci_bus *bus);
1284 void pci_lock_rescan_remove(void);
1285 void pci_unlock_rescan_remove(void);
1287 /* Vital Product Data routines */
1288 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1289 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1290 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1292 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1293 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1294 void pci_bus_assign_resources(const struct pci_bus *bus);
1295 void pci_bus_claim_resources(struct pci_bus *bus);
1296 void pci_bus_size_bridges(struct pci_bus *bus);
1297 int pci_claim_resource(struct pci_dev *, int);
1298 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1299 void pci_assign_unassigned_resources(void);
1300 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1301 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1302 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1303 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1304 void pdev_enable_device(struct pci_dev *);
1305 int pci_enable_resources(struct pci_dev *, int mask);
1306 void pci_assign_irq(struct pci_dev *dev);
1307 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1308 #define HAVE_PCI_REQ_REGIONS 2
1309 int __must_check pci_request_regions(struct pci_dev *, const char *);
1310 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1311 void pci_release_regions(struct pci_dev *);
1312 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1313 void pci_release_region(struct pci_dev *, int);
1314 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1315 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1316 void pci_release_selected_regions(struct pci_dev *, int);
1318 /* drivers/pci/bus.c */
1319 void pci_add_resource(struct list_head *resources, struct resource *res);
1320 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1321 resource_size_t offset);
1322 void pci_free_resource_list(struct list_head *resources);
1323 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1324 unsigned int flags);
1325 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1326 void pci_bus_remove_resources(struct pci_bus *bus);
1327 int devm_request_pci_bus_resources(struct device *dev,
1328 struct list_head *resources);
1330 /* Temporary until new and working PCI SBR API in place */
1331 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1333 #define pci_bus_for_each_resource(bus, res, i) \
1335 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1338 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1339 struct resource *res, resource_size_t size,
1340 resource_size_t align, resource_size_t min,
1341 unsigned long type_mask,
1342 resource_size_t (*alignf)(void *,
1343 const struct resource *,
1349 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1350 resource_size_t size);
1351 unsigned long pci_address_to_pio(phys_addr_t addr);
1352 phys_addr_t pci_pio_to_address(unsigned long pio);
1353 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1354 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1355 phys_addr_t phys_addr);
1356 void pci_unmap_iospace(struct resource *res);
1357 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1358 resource_size_t offset,
1359 resource_size_t size);
1360 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1361 struct resource *res);
1363 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1365 struct pci_bus_region region;
1367 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1368 return region.start;
1371 /* Proper probing supporting hot-pluggable devices */
1372 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1373 const char *mod_name);
1375 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1376 #define pci_register_driver(driver) \
1377 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1379 void pci_unregister_driver(struct pci_driver *dev);
1382 * module_pci_driver() - Helper macro for registering a PCI driver
1383 * @__pci_driver: pci_driver struct
1385 * Helper macro for PCI drivers which do not do anything special in module
1386 * init/exit. This eliminates a lot of boilerplate. Each module may only
1387 * use this macro once, and calling it replaces module_init() and module_exit()
1389 #define module_pci_driver(__pci_driver) \
1390 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1393 * builtin_pci_driver() - Helper macro for registering a PCI driver
1394 * @__pci_driver: pci_driver struct
1396 * Helper macro for PCI drivers which do not do anything special in their
1397 * init code. This eliminates a lot of boilerplate. Each driver may only
1398 * use this macro once, and calling it replaces device_initcall(...)
1400 #define builtin_pci_driver(__pci_driver) \
1401 builtin_driver(__pci_driver, pci_register_driver)
1403 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1404 int pci_add_dynid(struct pci_driver *drv,
1405 unsigned int vendor, unsigned int device,
1406 unsigned int subvendor, unsigned int subdevice,
1407 unsigned int class, unsigned int class_mask,
1408 unsigned long driver_data);
1409 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1410 struct pci_dev *dev);
1411 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1414 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1416 int pci_cfg_space_size(struct pci_dev *dev);
1417 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1418 void pci_setup_bridge(struct pci_bus *bus);
1419 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1420 unsigned long type);
1422 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1423 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1425 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1426 unsigned int command_bits, u32 flags);
1429 * Virtual interrupts allow for more interrupts to be allocated
1430 * than the device has interrupts for. These are not programmed
1431 * into the device's MSI-X table and must be handled by some
1432 * other driver means.
1434 #define PCI_IRQ_VIRTUAL (1 << 4)
1436 #define PCI_IRQ_ALL_TYPES \
1437 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1439 /* kmem_cache style wrapper around pci_alloc_consistent() */
1441 #include <linux/dmapool.h>
1443 #define pci_pool dma_pool
1444 #define pci_pool_create(name, pdev, size, align, allocation) \
1445 dma_pool_create(name, &pdev->dev, size, align, allocation)
1446 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1447 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1448 #define pci_pool_zalloc(pool, flags, handle) \
1449 dma_pool_zalloc(pool, flags, handle)
1450 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1453 u32 vector; /* Kernel uses to write allocated vector */
1454 u16 entry; /* Driver uses to specify entry, OS writes */
1457 #ifdef CONFIG_PCI_MSI
1458 int pci_msi_vec_count(struct pci_dev *dev);
1459 void pci_disable_msi(struct pci_dev *dev);
1460 int pci_msix_vec_count(struct pci_dev *dev);
1461 void pci_disable_msix(struct pci_dev *dev);
1462 void pci_restore_msi_state(struct pci_dev *dev);
1463 int pci_msi_enabled(void);
1464 int pci_enable_msi(struct pci_dev *dev);
1465 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1466 int minvec, int maxvec);
1467 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1468 struct msix_entry *entries, int nvec)
1470 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1475 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1476 unsigned int max_vecs, unsigned int flags,
1477 struct irq_affinity *affd);
1479 void pci_free_irq_vectors(struct pci_dev *dev);
1480 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1481 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1484 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1485 static inline void pci_disable_msi(struct pci_dev *dev) { }
1486 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1487 static inline void pci_disable_msix(struct pci_dev *dev) { }
1488 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1489 static inline int pci_msi_enabled(void) { return 0; }
1490 static inline int pci_enable_msi(struct pci_dev *dev)
1492 static inline int pci_enable_msix_range(struct pci_dev *dev,
1493 struct msix_entry *entries, int minvec, int maxvec)
1495 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1496 struct msix_entry *entries, int nvec)
1500 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1501 unsigned int max_vecs, unsigned int flags,
1502 struct irq_affinity *aff_desc)
1504 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1509 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1513 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1515 if (WARN_ON_ONCE(nr > 0))
1519 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1522 return cpu_possible_mask;
1527 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1528 * @d: the INTx IRQ domain
1529 * @node: the DT node for the device whose interrupt we're translating
1530 * @intspec: the interrupt specifier data from the DT
1531 * @intsize: the number of entries in @intspec
1532 * @out_hwirq: pointer at which to write the hwirq number
1533 * @out_type: pointer at which to write the interrupt type
1535 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1536 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1537 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1538 * INTx value to obtain the hwirq number.
1540 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1542 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1543 struct device_node *node,
1545 unsigned int intsize,
1546 unsigned long *out_hwirq,
1547 unsigned int *out_type)
1549 const u32 intx = intspec[0];
1551 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1554 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1558 #ifdef CONFIG_PCIEPORTBUS
1559 extern bool pcie_ports_disabled;
1560 extern bool pcie_ports_native;
1562 #define pcie_ports_disabled true
1563 #define pcie_ports_native false
1566 #define PCIE_LINK_STATE_L0S BIT(0)
1567 #define PCIE_LINK_STATE_L1 BIT(1)
1568 #define PCIE_LINK_STATE_CLKPM BIT(2)
1569 #define PCIE_LINK_STATE_L1_1 BIT(3)
1570 #define PCIE_LINK_STATE_L1_2 BIT(4)
1571 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1572 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1574 #ifdef CONFIG_PCIEASPM
1575 int pci_disable_link_state(struct pci_dev *pdev, int state);
1576 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1577 void pcie_no_aspm(void);
1578 bool pcie_aspm_support_enabled(void);
1579 bool pcie_aspm_enabled(struct pci_dev *pdev);
1581 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1583 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1585 static inline void pcie_no_aspm(void) { }
1586 static inline bool pcie_aspm_support_enabled(void) { return false; }
1587 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1590 #ifdef CONFIG_PCIEAER
1591 bool pci_aer_available(void);
1593 static inline bool pci_aer_available(void) { return false; }
1596 bool pci_ats_disabled(void);
1598 void pci_cfg_access_lock(struct pci_dev *dev);
1599 bool pci_cfg_access_trylock(struct pci_dev *dev);
1600 void pci_cfg_access_unlock(struct pci_dev *dev);
1603 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1604 * a PCI domain is defined to be a set of PCI buses which share
1605 * configuration space.
1607 #ifdef CONFIG_PCI_DOMAINS
1608 extern int pci_domains_supported;
1610 enum { pci_domains_supported = 0 };
1611 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1612 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1613 #endif /* CONFIG_PCI_DOMAINS */
1616 * Generic implementation for PCI domain support. If your
1617 * architecture does not need custom management of PCI
1618 * domains then this implementation will be used
1620 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1621 static inline int pci_domain_nr(struct pci_bus *bus)
1623 return bus->domain_nr;
1626 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1628 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1631 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1634 /* Some architectures require additional setup to direct VGA traffic */
1635 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1636 unsigned int command_bits, u32 flags);
1637 void pci_register_set_vga_state(arch_set_vga_state_t func);
1640 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1642 return pci_request_selected_regions(pdev,
1643 pci_select_bars(pdev, IORESOURCE_IO), name);
1647 pci_release_io_regions(struct pci_dev *pdev)
1649 return pci_release_selected_regions(pdev,
1650 pci_select_bars(pdev, IORESOURCE_IO));
1654 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1656 return pci_request_selected_regions(pdev,
1657 pci_select_bars(pdev, IORESOURCE_MEM), name);
1661 pci_release_mem_regions(struct pci_dev *pdev)
1663 return pci_release_selected_regions(pdev,
1664 pci_select_bars(pdev, IORESOURCE_MEM));
1667 #else /* CONFIG_PCI is not enabled */
1669 static inline void pci_set_flags(int flags) { }
1670 static inline void pci_add_flags(int flags) { }
1671 static inline void pci_clear_flags(int flags) { }
1672 static inline int pci_has_flag(int flag) { return 0; }
1675 * If the system does not have PCI, clearly these return errors. Define
1676 * these as simple inline functions to avoid hair in drivers.
1678 #define _PCI_NOP(o, s, t) \
1679 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1681 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1683 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1684 _PCI_NOP(o, word, u16 x) \
1685 _PCI_NOP(o, dword, u32 x)
1686 _PCI_NOP_ALL(read, *)
1687 _PCI_NOP_ALL(write,)
1689 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1690 unsigned int device,
1691 struct pci_dev *from)
1694 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1695 unsigned int device,
1696 unsigned int ss_vendor,
1697 unsigned int ss_device,
1698 struct pci_dev *from)
1701 static inline struct pci_dev *pci_get_class(unsigned int class,
1702 struct pci_dev *from)
1705 #define pci_dev_present(ids) (0)
1706 #define no_pci_devices() (1)
1707 #define pci_dev_put(dev) do { } while (0)
1709 static inline void pci_set_master(struct pci_dev *dev) { }
1710 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1711 static inline void pci_disable_device(struct pci_dev *dev) { }
1712 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1713 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1715 static inline int __pci_register_driver(struct pci_driver *drv,
1716 struct module *owner)
1718 static inline int pci_register_driver(struct pci_driver *drv)
1720 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1721 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1723 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1726 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1729 static inline u64 pci_get_dsn(struct pci_dev *dev)
1732 /* Power management related routines */
1733 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1734 static inline void pci_restore_state(struct pci_dev *dev) { }
1735 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1737 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1739 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1742 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1746 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1747 struct resource *res)
1749 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1751 static inline void pci_release_regions(struct pci_dev *dev) { }
1753 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1755 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1757 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1760 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1761 unsigned int bus, unsigned int devfn)
1764 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1765 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1767 #define dev_is_pci(d) (false)
1768 #define dev_is_pf(d) (false)
1769 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1771 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1772 struct device_node *node,
1774 unsigned int intsize,
1775 unsigned long *out_hwirq,
1776 unsigned int *out_type)
1779 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1780 struct pci_dev *dev)
1782 static inline bool pci_ats_disabled(void) { return true; }
1784 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1790 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1791 unsigned int max_vecs, unsigned int flags,
1792 struct irq_affinity *aff_desc)
1796 #endif /* CONFIG_PCI */
1799 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1800 unsigned int max_vecs, unsigned int flags)
1802 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1806 /* Include architecture-dependent settings and functions */
1808 #include <asm/pci.h>
1810 /* These two functions provide almost identical functionality. Depending
1811 * on the architecture, one will be implemented as a wrapper around the
1812 * other (in drivers/pci/mmap.c).
1814 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1815 * is expected to be an offset within that region.
1817 * pci_mmap_page_range() is the legacy architecture-specific interface,
1818 * which accepts a "user visible" resource address converted by
1819 * pci_resource_to_user(), as used in the legacy mmap() interface in
1822 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1823 struct vm_area_struct *vma,
1824 enum pci_mmap_state mmap_state, int write_combine);
1825 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1826 struct vm_area_struct *vma,
1827 enum pci_mmap_state mmap_state, int write_combine);
1829 #ifndef arch_can_pci_mmap_wc
1830 #define arch_can_pci_mmap_wc() 0
1833 #ifndef arch_can_pci_mmap_io
1834 #define arch_can_pci_mmap_io() 0
1835 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1837 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1840 #ifndef pci_root_bus_fwnode
1841 #define pci_root_bus_fwnode(bus) NULL
1845 * These helpers provide future and backwards compatibility
1846 * for accessing popular PCI BAR info
1848 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1849 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1850 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1851 #define pci_resource_len(dev,bar) \
1852 ((pci_resource_start((dev), (bar)) == 0 && \
1853 pci_resource_end((dev), (bar)) == \
1854 pci_resource_start((dev), (bar))) ? 0 : \
1856 (pci_resource_end((dev), (bar)) - \
1857 pci_resource_start((dev), (bar)) + 1))
1860 * Similar to the helpers above, these manipulate per-pci_dev
1861 * driver-specific data. They are really just a wrapper around
1862 * the generic device structure functions of these calls.
1864 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1866 return dev_get_drvdata(&pdev->dev);
1869 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1871 dev_set_drvdata(&pdev->dev, data);
1874 static inline const char *pci_name(const struct pci_dev *pdev)
1876 return dev_name(&pdev->dev);
1879 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1880 const struct resource *rsrc,
1881 resource_size_t *start, resource_size_t *end);
1884 * The world is not perfect and supplies us with broken PCI devices.
1885 * For at least a part of these bugs we need a work-around, so both
1886 * generic (drivers/pci/quirks.c) and per-architecture code can define
1887 * fixup hooks to be called for particular buggy devices.
1891 u16 vendor; /* Or PCI_ANY_ID */
1892 u16 device; /* Or PCI_ANY_ID */
1893 u32 class; /* Or PCI_ANY_ID */
1894 unsigned int class_shift; /* should be 0, 8, 16 */
1895 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1898 void (*hook)(struct pci_dev *dev);
1902 enum pci_fixup_pass {
1903 pci_fixup_early, /* Before probing BARs */
1904 pci_fixup_header, /* After reading configuration header */
1905 pci_fixup_final, /* Final phase of device fixups */
1906 pci_fixup_enable, /* pci_enable_device() time */
1907 pci_fixup_resume, /* pci_device_resume() */
1908 pci_fixup_suspend, /* pci_device_suspend() */
1909 pci_fixup_resume_early, /* pci_device_resume_early() */
1910 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1913 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1914 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1915 class_shift, hook) \
1916 __ADDRESSABLE(hook) \
1917 asm(".section " #sec ", \"a\" \n" \
1919 ".short " #vendor ", " #device " \n" \
1920 ".long " #class ", " #class_shift " \n" \
1921 ".long " #hook " - . \n" \
1923 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1924 class_shift, hook) \
1925 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1928 /* Anonymous variables would be nice... */
1929 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1930 class_shift, hook) \
1931 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1932 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1933 = { vendor, device, class, class_shift, hook };
1936 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1937 class_shift, hook) \
1938 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1939 hook, vendor, device, class, class_shift, hook)
1940 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1941 class_shift, hook) \
1942 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1943 hook, vendor, device, class, class_shift, hook)
1944 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1945 class_shift, hook) \
1946 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1947 hook, vendor, device, class, class_shift, hook)
1948 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1949 class_shift, hook) \
1950 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1951 hook, vendor, device, class, class_shift, hook)
1952 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1953 class_shift, hook) \
1954 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1955 resume##hook, vendor, device, class, class_shift, hook)
1956 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1957 class_shift, hook) \
1958 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1959 resume_early##hook, vendor, device, class, class_shift, hook)
1960 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1961 class_shift, hook) \
1962 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1963 suspend##hook, vendor, device, class, class_shift, hook)
1964 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1965 class_shift, hook) \
1966 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1967 suspend_late##hook, vendor, device, class, class_shift, hook)
1969 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1970 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1971 hook, vendor, device, PCI_ANY_ID, 0, hook)
1972 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1973 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1974 hook, vendor, device, PCI_ANY_ID, 0, hook)
1975 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1976 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1977 hook, vendor, device, PCI_ANY_ID, 0, hook)
1978 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1979 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1980 hook, vendor, device, PCI_ANY_ID, 0, hook)
1981 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1982 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1983 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1984 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1985 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1986 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1987 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1988 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1989 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1990 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1991 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1992 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1994 #ifdef CONFIG_PCI_QUIRKS
1995 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1997 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1998 struct pci_dev *dev) { }
2001 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2002 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2003 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2004 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2005 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2007 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2009 extern int pci_pci_problems;
2010 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2011 #define PCIPCI_TRITON 2
2012 #define PCIPCI_NATOMA 4
2013 #define PCIPCI_VIAETBF 8
2014 #define PCIPCI_VSFX 16
2015 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2016 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2018 extern unsigned long pci_cardbus_io_size;
2019 extern unsigned long pci_cardbus_mem_size;
2020 extern u8 pci_dfl_cache_line_size;
2021 extern u8 pci_cache_line_size;
2023 /* Architecture-specific versions may override these (weak) */
2024 void pcibios_disable_device(struct pci_dev *dev);
2025 void pcibios_set_master(struct pci_dev *dev);
2026 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2027 enum pcie_reset_state state);
2028 int pcibios_add_device(struct pci_dev *dev);
2029 void pcibios_release_device(struct pci_dev *dev);
2031 void pcibios_penalize_isa_irq(int irq, int active);
2033 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2035 int pcibios_alloc_irq(struct pci_dev *dev);
2036 void pcibios_free_irq(struct pci_dev *dev);
2037 resource_size_t pcibios_default_alignment(void);
2039 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2040 void __init pci_mmcfg_early_init(void);
2041 void __init pci_mmcfg_late_init(void);
2043 static inline void pci_mmcfg_early_init(void) { }
2044 static inline void pci_mmcfg_late_init(void) { }
2047 int pci_ext_cfg_avail(void);
2049 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2050 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2052 #ifdef CONFIG_PCI_IOV
2053 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2054 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2056 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2057 void pci_disable_sriov(struct pci_dev *dev);
2059 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2060 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2061 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2062 int pci_num_vf(struct pci_dev *dev);
2063 int pci_vfs_assigned(struct pci_dev *dev);
2064 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2065 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2066 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2067 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2068 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2070 /* Arch may override these (weak) */
2071 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2072 int pcibios_sriov_disable(struct pci_dev *pdev);
2073 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2075 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2079 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2083 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2086 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2087 struct pci_dev *virtfn, int id)
2091 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2095 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2097 static inline void pci_disable_sriov(struct pci_dev *dev) { }
2098 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2099 static inline int pci_vfs_assigned(struct pci_dev *dev)
2101 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2103 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2105 #define pci_sriov_configure_simple NULL
2106 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2108 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2111 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2112 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2113 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2117 * pci_pcie_cap - get the saved PCIe capability offset
2120 * PCIe capability offset is calculated at PCI device initialization
2121 * time and saved in the data structure. This function returns saved
2122 * PCIe capability offset. Using this instead of pci_find_capability()
2123 * reduces unnecessary search in the PCI configuration space. If you
2124 * need to calculate PCIe capability offset from raw device for some
2125 * reasons, please use pci_find_capability() instead.
2127 static inline int pci_pcie_cap(struct pci_dev *dev)
2129 return dev->pcie_cap;
2133 * pci_is_pcie - check if the PCI device is PCI Express capable
2136 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2138 static inline bool pci_is_pcie(struct pci_dev *dev)
2140 return pci_pcie_cap(dev);
2144 * pcie_caps_reg - get the PCIe Capabilities Register
2147 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2149 return dev->pcie_flags_reg;
2153 * pci_pcie_type - get the PCIe device/port type
2156 static inline int pci_pcie_type(const struct pci_dev *dev)
2158 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2162 * pcie_find_root_port - Get the PCIe root port device
2165 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2166 * for a given PCI/PCIe Device.
2168 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2171 if (pci_is_pcie(dev) &&
2172 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2174 dev = pci_upstream_bridge(dev);
2180 void pci_request_acs(void);
2181 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2182 bool pci_acs_path_enabled(struct pci_dev *start,
2183 struct pci_dev *end, u16 acs_flags);
2184 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2186 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2187 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2189 /* Large Resource Data Type Tag Item Names */
2190 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2191 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2192 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2194 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2195 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2196 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2198 /* Small Resource Data Type Tag Item Names */
2199 #define PCI_VPD_STIN_END 0x0f /* End */
2201 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2203 #define PCI_VPD_SRDT_TIN_MASK 0x78
2204 #define PCI_VPD_SRDT_LEN_MASK 0x07
2205 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2207 #define PCI_VPD_LRDT_TAG_SIZE 3
2208 #define PCI_VPD_SRDT_TAG_SIZE 1
2210 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2212 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2213 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2214 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2215 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2216 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2219 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2220 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2222 * Returns the extracted Large Resource Data Type length.
2224 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2226 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2230 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2231 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2233 * Returns the extracted Large Resource Data Type Tag item.
2235 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2237 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2241 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2242 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2244 * Returns the extracted Small Resource Data Type length.
2246 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2248 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2252 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2253 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2255 * Returns the extracted Small Resource Data Type Tag Item.
2257 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2259 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2263 * pci_vpd_info_field_size - Extracts the information field length
2264 * @info_field: Pointer to the beginning of an information field header
2266 * Returns the extracted information field length.
2268 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2270 return info_field[2];
2274 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2275 * @buf: Pointer to buffered vpd data
2276 * @off: The offset into the buffer at which to begin the search
2277 * @len: The length of the vpd buffer
2278 * @rdt: The Resource Data Type to search for
2280 * Returns the index where the Resource Data Type was found or
2281 * -ENOENT otherwise.
2283 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2286 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2287 * @buf: Pointer to buffered vpd data
2288 * @off: The offset into the buffer at which to begin the search
2289 * @len: The length of the buffer area, relative to off, in which to search
2290 * @kw: The keyword to search for
2292 * Returns the index where the information field keyword was found or
2293 * -ENOENT otherwise.
2295 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2296 unsigned int len, const char *kw);
2298 /* PCI <-> OF binding helpers */
2302 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2304 /* Arch may override this (weak) */
2305 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2307 #else /* CONFIG_OF */
2308 static inline struct irq_domain *
2309 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2310 #endif /* CONFIG_OF */
2312 static inline struct device_node *
2313 pci_device_to_OF_node(const struct pci_dev *pdev)
2315 return pdev ? pdev->dev.of_node : NULL;
2318 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2320 return bus ? bus->dev.of_node : NULL;
2324 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2327 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2328 bool pci_pr3_present(struct pci_dev *pdev);
2330 static inline struct irq_domain *
2331 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2332 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2336 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2338 return pdev->dev.archdata.edev;
2342 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2343 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2344 int pci_for_each_dma_alias(struct pci_dev *pdev,
2345 int (*fn)(struct pci_dev *pdev,
2346 u16 alias, void *data), void *data);
2348 /* Helper functions for operation of device flag */
2349 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2351 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2353 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2355 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2357 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2359 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2363 * pci_ari_enabled - query ARI forwarding status
2366 * Returns true if ARI forwarding is enabled.
2368 static inline bool pci_ari_enabled(struct pci_bus *bus)
2370 return bus->self && bus->self->ari_enabled;
2374 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2375 * @pdev: PCI device to check
2377 * Walk upwards from @pdev and check for each encountered bridge if it's part
2378 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2379 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2381 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2383 struct pci_dev *parent = pdev;
2385 if (pdev->is_thunderbolt)
2388 while ((parent = pci_upstream_bridge(parent)))
2389 if (parent->is_thunderbolt)
2395 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2396 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2399 /* Provide the legacy pci_dma_* API */
2400 #include <linux/pci-dma-compat.h>
2402 #define pci_printk(level, pdev, fmt, arg...) \
2403 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2405 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2406 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2407 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2408 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2409 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2410 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2411 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2412 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2414 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2415 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2417 #define pci_info_ratelimited(pdev, fmt, arg...) \
2418 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2420 #define pci_WARN(pdev, condition, fmt, arg...) \
2421 WARN(condition, "%s %s: " fmt, \
2422 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2424 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2425 WARN_ONCE(condition, "%s %s: " fmt, \
2426 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2428 #endif /* LINUX_PCI_H */