1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
10 #include <linux/types.h>
11 #include <linux/uuid.h>
13 /* NQN names in commands fields specified one size */
14 #define NVMF_NQN_FIELD_LEN 256
16 /* However the max length of a qualified name is another size */
17 #define NVMF_NQN_SIZE 223
19 #define NVMF_TRSVCID_SIZE 32
20 #define NVMF_TRADDR_SIZE 256
21 #define NVMF_TSAS_SIZE 256
23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25 #define NVME_RDMA_IP_PORT 4420
27 #define NVME_NSID_ALL 0xffffffff
29 enum nvme_subsys_type {
30 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
31 NVME_NQN_NVME = 2, /* NVME type target subsystem */
34 /* Address Family codes for Discovery Log Page entry ADRFAM field */
36 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
37 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
38 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
39 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
40 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
41 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
45 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
47 NVMF_TRTYPE_RDMA = 1, /* RDMA */
48 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
49 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
50 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
54 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
56 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
57 NVMF_TREQ_REQUIRED = 1, /* Required */
58 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
59 #define NVME_TREQ_SECURE_CHANNEL_MASK \
60 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
62 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
65 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
69 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
70 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
73 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
77 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
78 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
79 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
80 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
81 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
84 /* RDMA Connection Management Service Type codes for Discovery Log Page
85 * entry TSAS RDMA_CMS field
88 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
91 #define NVME_AQ_DEPTH 32
92 #define NVME_NR_AEN_COMMANDS 1
93 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
96 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
97 * NVM-Express 1.2 specification, section 4.1.2.
99 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
102 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
103 NVME_REG_VS = 0x0008, /* Version */
104 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
105 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
106 NVME_REG_CC = 0x0014, /* Controller Configuration */
107 NVME_REG_CSTS = 0x001c, /* Controller Status */
108 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
109 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
110 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
111 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
112 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
113 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
114 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
115 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
116 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
119 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
122 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
123 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
124 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
125 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
128 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
131 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
134 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
135 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
136 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
137 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
138 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
139 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
140 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
141 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
143 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
144 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
147 NVME_CMBSZ_SQS = 1 << 0,
148 NVME_CMBSZ_CQS = 1 << 1,
149 NVME_CMBSZ_LISTS = 1 << 2,
150 NVME_CMBSZ_RDS = 1 << 3,
151 NVME_CMBSZ_WDS = 1 << 4,
153 NVME_CMBSZ_SZ_SHIFT = 12,
154 NVME_CMBSZ_SZ_MASK = 0xfffff,
156 NVME_CMBSZ_SZU_SHIFT = 8,
157 NVME_CMBSZ_SZU_MASK = 0xf,
161 * Submission and Completion Queue Entry Sizes for the NVM command set.
162 * (In bytes and specified as a power of two (2^n)).
164 #define NVME_ADM_SQES 6
165 #define NVME_NVM_IOSQES 6
166 #define NVME_NVM_IOCQES 4
169 NVME_CC_ENABLE = 1 << 0,
170 NVME_CC_EN_SHIFT = 0,
171 NVME_CC_CSS_SHIFT = 4,
172 NVME_CC_MPS_SHIFT = 7,
173 NVME_CC_AMS_SHIFT = 11,
174 NVME_CC_SHN_SHIFT = 14,
175 NVME_CC_IOSQES_SHIFT = 16,
176 NVME_CC_IOCQES_SHIFT = 20,
177 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
178 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
179 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
180 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
181 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
182 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
183 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
184 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
185 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
186 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
187 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
188 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
189 NVME_CAP_CSS_NVM = 1 << 0,
190 NVME_CAP_CSS_CSI = 1 << 6,
191 NVME_CSTS_RDY = 1 << 0,
192 NVME_CSTS_CFS = 1 << 1,
193 NVME_CSTS_NSSRO = 1 << 4,
194 NVME_CSTS_PP = 1 << 5,
195 NVME_CSTS_SHST_NORMAL = 0 << 2,
196 NVME_CSTS_SHST_OCCUR = 1 << 2,
197 NVME_CSTS_SHST_CMPLT = 2 << 2,
198 NVME_CSTS_SHST_MASK = 3 << 2,
199 NVME_CMBMSC_CRE = 1 << 0,
200 NVME_CMBMSC_CMSE = 1 << 1,
203 struct nvme_id_power_state {
204 __le16 max_power; /* centiwatts */
207 __le32 entry_lat; /* microseconds */
208 __le32 exit_lat; /* microseconds */
217 __u8 active_work_scale;
222 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
223 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
226 enum nvme_ctrl_attr {
227 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
228 NVME_CTRL_ATTR_TBKAS = (1 << 6),
231 struct nvme_id_ctrl {
310 struct nvme_id_power_state psd[32];
315 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
316 NVME_CTRL_CMIC_ANA = 1 << 3,
317 NVME_CTRL_ONCS_COMPARE = 1 << 0,
318 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
319 NVME_CTRL_ONCS_DSM = 1 << 2,
320 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
321 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
322 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
323 NVME_CTRL_VWC_PRESENT = 1 << 0,
324 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
325 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
326 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
327 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
328 NVME_CTRL_CTRATT_128_ID = 1 << 0,
329 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
330 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
331 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
332 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
333 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
334 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
335 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
379 struct nvme_lbaf lbaf[16];
384 struct nvme_zns_lbafe {
390 struct nvme_id_ns_zns {
398 struct nvme_zns_lbafe lbafe[16];
403 struct nvme_id_ctrl_zns {
409 NVME_ID_CNS_NS = 0x00,
410 NVME_ID_CNS_CTRL = 0x01,
411 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
412 NVME_ID_CNS_NS_DESC_LIST = 0x03,
413 NVME_ID_CNS_CS_NS = 0x05,
414 NVME_ID_CNS_CS_CTRL = 0x06,
415 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
416 NVME_ID_CNS_NS_PRESENT = 0x11,
417 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
418 NVME_ID_CNS_CTRL_LIST = 0x13,
419 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
420 NVME_ID_CNS_NS_GRANULARITY = 0x16,
421 NVME_ID_CNS_UUID_LIST = 0x17,
430 NVME_DIR_IDENTIFY = 0x00,
431 NVME_DIR_STREAMS = 0x01,
432 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
433 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
434 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
435 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
436 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
437 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
438 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
439 NVME_DIR_ENDIR = 0x01,
443 NVME_NS_FEAT_THIN = 1 << 0,
444 NVME_NS_FEAT_ATOMICS = 1 << 1,
445 NVME_NS_FEAT_IO_OPT = 1 << 4,
446 NVME_NS_ATTR_RO = 1 << 0,
447 NVME_NS_FLBAS_LBA_MASK = 0xf,
448 NVME_NS_FLBAS_META_EXT = 0x10,
449 NVME_NS_NMIC_SHARED = 1 << 0,
450 NVME_LBAF_RP_BEST = 0,
451 NVME_LBAF_RP_BETTER = 1,
452 NVME_LBAF_RP_GOOD = 2,
453 NVME_LBAF_RP_DEGRADED = 3,
454 NVME_NS_DPC_PI_LAST = 1 << 4,
455 NVME_NS_DPC_PI_FIRST = 1 << 3,
456 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
457 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
458 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
459 NVME_NS_DPS_PI_FIRST = 1 << 3,
460 NVME_NS_DPS_PI_MASK = 0x7,
461 NVME_NS_DPS_PI_TYPE1 = 1,
462 NVME_NS_DPS_PI_TYPE2 = 2,
463 NVME_NS_DPS_PI_TYPE3 = 3,
466 /* Identify Namespace Metadata Capabilities (MC): */
468 NVME_MC_EXTENDED_LBA = (1 << 0),
469 NVME_MC_METADATA_PTR = (1 << 1),
472 struct nvme_ns_id_desc {
478 #define NVME_NIDT_EUI64_LEN 8
479 #define NVME_NIDT_NGUID_LEN 16
480 #define NVME_NIDT_UUID_LEN 16
481 #define NVME_NIDT_CSI_LEN 1
484 NVME_NIDT_EUI64 = 0x01,
485 NVME_NIDT_NGUID = 0x02,
486 NVME_NIDT_UUID = 0x03,
487 NVME_NIDT_CSI = 0x04,
490 struct nvme_smart_log {
491 __u8 critical_warning;
496 __u8 endu_grp_crit_warn_sumry;
498 __u8 data_units_read[16];
499 __u8 data_units_written[16];
501 __u8 host_writes[16];
502 __u8 ctrl_busy_time[16];
503 __u8 power_cycles[16];
504 __u8 power_on_hours[16];
505 __u8 unsafe_shutdowns[16];
506 __u8 media_errors[16];
507 __u8 num_err_log_entries[16];
508 __le32 warning_temp_time;
509 __le32 critical_comp_time;
510 __le16 temp_sensor[8];
511 __le32 thm_temp1_trans_count;
512 __le32 thm_temp2_trans_count;
513 __le32 thm_temp1_total_time;
514 __le32 thm_temp2_total_time;
518 struct nvme_fw_slot_info_log {
526 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
527 NVME_CMD_EFFECTS_LBCC = 1 << 1,
528 NVME_CMD_EFFECTS_NCC = 1 << 2,
529 NVME_CMD_EFFECTS_NIC = 1 << 3,
530 NVME_CMD_EFFECTS_CCC = 1 << 4,
531 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
532 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
535 struct nvme_effects_log {
541 enum nvme_ana_state {
542 NVME_ANA_OPTIMIZED = 0x01,
543 NVME_ANA_NONOPTIMIZED = 0x02,
544 NVME_ANA_INACCESSIBLE = 0x03,
545 NVME_ANA_PERSISTENT_LOSS = 0x04,
546 NVME_ANA_CHANGE = 0x0f,
549 struct nvme_ana_group_desc {
558 /* flag for the log specific field of the ANA log */
559 #define NVME_ANA_LOG_RGO (1 << 0)
561 struct nvme_ana_rsp_hdr {
567 struct nvme_zone_descriptor {
579 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
582 struct nvme_zone_report {
585 struct nvme_zone_descriptor entries[];
589 NVME_SMART_CRIT_SPARE = 1 << 0,
590 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
591 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
592 NVME_SMART_CRIT_MEDIA = 1 << 3,
593 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
605 NVME_AER_NOTICE_NS_CHANGED = 0x00,
606 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
607 NVME_AER_NOTICE_ANA = 0x03,
608 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
612 NVME_AEN_BIT_NS_ATTR = 8,
613 NVME_AEN_BIT_FW_ACT = 9,
614 NVME_AEN_BIT_ANA_CHANGE = 11,
615 NVME_AEN_BIT_DISC_CHANGE = 31,
619 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
620 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
621 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
622 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
625 struct nvme_lba_range_type {
636 NVME_LBART_TYPE_FS = 0x01,
637 NVME_LBART_TYPE_RAID = 0x02,
638 NVME_LBART_TYPE_CACHE = 0x03,
639 NVME_LBART_TYPE_SWAP = 0x04,
641 NVME_LBART_ATTRIB_TEMP = 1 << 0,
642 NVME_LBART_ATTRIB_HIDE = 1 << 1,
645 struct nvme_reservation_status {
661 enum nvme_async_event_type {
662 NVME_AER_TYPE_ERROR = 0,
663 NVME_AER_TYPE_SMART = 1,
664 NVME_AER_TYPE_NOTICE = 2,
670 nvme_cmd_flush = 0x00,
671 nvme_cmd_write = 0x01,
672 nvme_cmd_read = 0x02,
673 nvme_cmd_write_uncor = 0x04,
674 nvme_cmd_compare = 0x05,
675 nvme_cmd_write_zeroes = 0x08,
677 nvme_cmd_verify = 0x0c,
678 nvme_cmd_resv_register = 0x0d,
679 nvme_cmd_resv_report = 0x0e,
680 nvme_cmd_resv_acquire = 0x11,
681 nvme_cmd_resv_release = 0x15,
682 nvme_cmd_zone_mgmt_send = 0x79,
683 nvme_cmd_zone_mgmt_recv = 0x7a,
684 nvme_cmd_zone_append = 0x7d,
687 #define nvme_opcode_name(opcode) { opcode, #opcode }
688 #define show_nvm_opcode_name(val) \
689 __print_symbolic(val, \
690 nvme_opcode_name(nvme_cmd_flush), \
691 nvme_opcode_name(nvme_cmd_write), \
692 nvme_opcode_name(nvme_cmd_read), \
693 nvme_opcode_name(nvme_cmd_write_uncor), \
694 nvme_opcode_name(nvme_cmd_compare), \
695 nvme_opcode_name(nvme_cmd_write_zeroes), \
696 nvme_opcode_name(nvme_cmd_dsm), \
697 nvme_opcode_name(nvme_cmd_resv_register), \
698 nvme_opcode_name(nvme_cmd_resv_report), \
699 nvme_opcode_name(nvme_cmd_resv_acquire), \
700 nvme_opcode_name(nvme_cmd_resv_release), \
701 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
702 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
703 nvme_opcode_name(nvme_cmd_zone_append))
708 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
710 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
711 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
712 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
713 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
717 NVME_SGL_FMT_ADDRESS = 0x00,
718 NVME_SGL_FMT_OFFSET = 0x01,
719 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
720 NVME_SGL_FMT_INVALIDATE = 0x0f,
724 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
726 * For struct nvme_sgl_desc:
727 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
728 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
729 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
731 * For struct nvme_keyed_sgl_desc:
732 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
734 * Transport-specific SGL types:
735 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
738 NVME_SGL_FMT_DATA_DESC = 0x00,
739 NVME_SGL_FMT_SEG_DESC = 0x02,
740 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
741 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
742 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
745 struct nvme_sgl_desc {
752 struct nvme_keyed_sgl_desc {
759 union nvme_data_ptr {
764 struct nvme_sgl_desc sgl;
765 struct nvme_keyed_sgl_desc ksgl;
769 * Lowest two bits of our flags field (FUSE field in the spec):
771 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
772 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
774 * Highest two bits in our flags field (PSDT field in the spec):
776 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
777 * If used, MPTR contains addr of single physical buffer (byte aligned).
778 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
779 * If used, MPTR contains an address of an SGL segment containing
780 * exactly 1 SGL descriptor (qword aligned).
783 NVME_CMD_FUSE_FIRST = (1 << 0),
784 NVME_CMD_FUSE_SECOND = (1 << 1),
786 NVME_CMD_SGL_METABUF = (1 << 6),
787 NVME_CMD_SGL_METASEG = (1 << 7),
788 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
791 struct nvme_common_command {
798 union nvme_data_ptr dptr;
807 struct nvme_rw_command {
814 union nvme_data_ptr dptr;
825 NVME_RW_LR = 1 << 15,
826 NVME_RW_FUA = 1 << 14,
827 NVME_RW_APPEND_PIREMAP = 1 << 9,
828 NVME_RW_DSM_FREQ_UNSPEC = 0,
829 NVME_RW_DSM_FREQ_TYPICAL = 1,
830 NVME_RW_DSM_FREQ_RARE = 2,
831 NVME_RW_DSM_FREQ_READS = 3,
832 NVME_RW_DSM_FREQ_WRITES = 4,
833 NVME_RW_DSM_FREQ_RW = 5,
834 NVME_RW_DSM_FREQ_ONCE = 6,
835 NVME_RW_DSM_FREQ_PREFETCH = 7,
836 NVME_RW_DSM_FREQ_TEMP = 8,
837 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
838 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
839 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
840 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
841 NVME_RW_DSM_SEQ_REQ = 1 << 6,
842 NVME_RW_DSM_COMPRESSED = 1 << 7,
843 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
844 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
845 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
846 NVME_RW_PRINFO_PRACT = 1 << 13,
847 NVME_RW_DTYPE_STREAMS = 1 << 4,
850 struct nvme_dsm_cmd {
856 union nvme_data_ptr dptr;
863 NVME_DSMGMT_IDR = 1 << 0,
864 NVME_DSMGMT_IDW = 1 << 1,
865 NVME_DSMGMT_AD = 1 << 2,
868 #define NVME_DSM_MAX_RANGES 256
870 struct nvme_dsm_range {
876 struct nvme_write_zeroes_cmd {
883 union nvme_data_ptr dptr;
893 enum nvme_zone_mgmt_action {
894 NVME_ZONE_CLOSE = 0x1,
895 NVME_ZONE_FINISH = 0x2,
896 NVME_ZONE_OPEN = 0x3,
897 NVME_ZONE_RESET = 0x4,
898 NVME_ZONE_OFFLINE = 0x5,
899 NVME_ZONE_SET_DESC_EXT = 0x10,
902 struct nvme_zone_mgmt_send_cmd {
909 union nvme_data_ptr dptr;
918 struct nvme_zone_mgmt_recv_cmd {
924 union nvme_data_ptr dptr;
935 NVME_ZRA_ZONE_REPORT = 0,
936 NVME_ZRASF_ZONE_REPORT_ALL = 0,
937 NVME_REPORT_ZONE_PARTIAL = 1,
943 NVME_TEMP_THRESH_MASK = 0xffff,
944 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
945 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
948 struct nvme_feat_auto_pst {
953 NVME_HOST_MEM_ENABLE = (1 << 0),
954 NVME_HOST_MEM_RETURN = (1 << 1),
957 struct nvme_feat_host_behavior {
963 NVME_ENABLE_ACRE = 1,
968 enum nvme_admin_opcode {
969 nvme_admin_delete_sq = 0x00,
970 nvme_admin_create_sq = 0x01,
971 nvme_admin_get_log_page = 0x02,
972 nvme_admin_delete_cq = 0x04,
973 nvme_admin_create_cq = 0x05,
974 nvme_admin_identify = 0x06,
975 nvme_admin_abort_cmd = 0x08,
976 nvme_admin_set_features = 0x09,
977 nvme_admin_get_features = 0x0a,
978 nvme_admin_async_event = 0x0c,
979 nvme_admin_ns_mgmt = 0x0d,
980 nvme_admin_activate_fw = 0x10,
981 nvme_admin_download_fw = 0x11,
982 nvme_admin_dev_self_test = 0x14,
983 nvme_admin_ns_attach = 0x15,
984 nvme_admin_keep_alive = 0x18,
985 nvme_admin_directive_send = 0x19,
986 nvme_admin_directive_recv = 0x1a,
987 nvme_admin_virtual_mgmt = 0x1c,
988 nvme_admin_nvme_mi_send = 0x1d,
989 nvme_admin_nvme_mi_recv = 0x1e,
990 nvme_admin_dbbuf = 0x7C,
991 nvme_admin_format_nvm = 0x80,
992 nvme_admin_security_send = 0x81,
993 nvme_admin_security_recv = 0x82,
994 nvme_admin_sanitize_nvm = 0x84,
995 nvme_admin_get_lba_status = 0x86,
996 nvme_admin_vendor_start = 0xC0,
999 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1000 #define show_admin_opcode_name(val) \
1001 __print_symbolic(val, \
1002 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1003 nvme_admin_opcode_name(nvme_admin_create_sq), \
1004 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1005 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1006 nvme_admin_opcode_name(nvme_admin_create_cq), \
1007 nvme_admin_opcode_name(nvme_admin_identify), \
1008 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1009 nvme_admin_opcode_name(nvme_admin_set_features), \
1010 nvme_admin_opcode_name(nvme_admin_get_features), \
1011 nvme_admin_opcode_name(nvme_admin_async_event), \
1012 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1013 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1014 nvme_admin_opcode_name(nvme_admin_download_fw), \
1015 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1016 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1017 nvme_admin_opcode_name(nvme_admin_directive_send), \
1018 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1019 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1020 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1021 nvme_admin_opcode_name(nvme_admin_security_send), \
1022 nvme_admin_opcode_name(nvme_admin_security_recv), \
1023 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1024 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1027 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1028 NVME_CQ_IRQ_ENABLED = (1 << 1),
1029 NVME_SQ_PRIO_URGENT = (0 << 1),
1030 NVME_SQ_PRIO_HIGH = (1 << 1),
1031 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1032 NVME_SQ_PRIO_LOW = (3 << 1),
1033 NVME_FEAT_ARBITRATION = 0x01,
1034 NVME_FEAT_POWER_MGMT = 0x02,
1035 NVME_FEAT_LBA_RANGE = 0x03,
1036 NVME_FEAT_TEMP_THRESH = 0x04,
1037 NVME_FEAT_ERR_RECOVERY = 0x05,
1038 NVME_FEAT_VOLATILE_WC = 0x06,
1039 NVME_FEAT_NUM_QUEUES = 0x07,
1040 NVME_FEAT_IRQ_COALESCE = 0x08,
1041 NVME_FEAT_IRQ_CONFIG = 0x09,
1042 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1043 NVME_FEAT_ASYNC_EVENT = 0x0b,
1044 NVME_FEAT_AUTO_PST = 0x0c,
1045 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1046 NVME_FEAT_TIMESTAMP = 0x0e,
1047 NVME_FEAT_KATO = 0x0f,
1048 NVME_FEAT_HCTM = 0x10,
1049 NVME_FEAT_NOPSC = 0x11,
1050 NVME_FEAT_RRL = 0x12,
1051 NVME_FEAT_PLM_CONFIG = 0x13,
1052 NVME_FEAT_PLM_WINDOW = 0x14,
1053 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1054 NVME_FEAT_SANITIZE = 0x17,
1055 NVME_FEAT_SW_PROGRESS = 0x80,
1056 NVME_FEAT_HOST_ID = 0x81,
1057 NVME_FEAT_RESV_MASK = 0x82,
1058 NVME_FEAT_RESV_PERSIST = 0x83,
1059 NVME_FEAT_WRITE_PROTECT = 0x84,
1060 NVME_FEAT_VENDOR_START = 0xC0,
1061 NVME_FEAT_VENDOR_END = 0xFF,
1062 NVME_LOG_ERROR = 0x01,
1063 NVME_LOG_SMART = 0x02,
1064 NVME_LOG_FW_SLOT = 0x03,
1065 NVME_LOG_CHANGED_NS = 0x04,
1066 NVME_LOG_CMD_EFFECTS = 0x05,
1067 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1068 NVME_LOG_TELEMETRY_HOST = 0x07,
1069 NVME_LOG_TELEMETRY_CTRL = 0x08,
1070 NVME_LOG_ENDURANCE_GROUP = 0x09,
1071 NVME_LOG_ANA = 0x0c,
1072 NVME_LOG_DISC = 0x70,
1073 NVME_LOG_RESERVATION = 0x80,
1074 NVME_FWACT_REPL = (0 << 3),
1075 NVME_FWACT_REPL_ACTV = (1 << 3),
1076 NVME_FWACT_ACTV = (2 << 3),
1079 /* NVMe Namespace Write Protect State */
1081 NVME_NS_NO_WRITE_PROTECT = 0,
1082 NVME_NS_WRITE_PROTECT,
1083 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1084 NVME_NS_WRITE_PROTECT_PERMANENT,
1087 #define NVME_MAX_CHANGED_NAMESPACES 1024
1089 struct nvme_identify {
1095 union nvme_data_ptr dptr;
1104 #define NVME_IDENTIFY_DATA_SIZE 4096
1106 struct nvme_features {
1112 union nvme_data_ptr dptr;
1121 struct nvme_host_mem_buf_desc {
1127 struct nvme_create_cq {
1141 struct nvme_create_sq {
1155 struct nvme_delete_queue {
1165 struct nvme_abort_cmd {
1175 struct nvme_download_firmware {
1180 union nvme_data_ptr dptr;
1186 struct nvme_format_cmd {
1196 struct nvme_get_log_page_command {
1202 union nvme_data_ptr dptr;
1204 __u8 lsp; /* upper 4 bits reserved */
1220 struct nvme_directive_cmd {
1226 union nvme_data_ptr dptr;
1239 * Fabrics subcommands.
1241 enum nvmf_fabrics_opcode {
1242 nvme_fabrics_command = 0x7f,
1245 enum nvmf_capsule_command {
1246 nvme_fabrics_type_property_set = 0x00,
1247 nvme_fabrics_type_connect = 0x01,
1248 nvme_fabrics_type_property_get = 0x04,
1251 #define nvme_fabrics_type_name(type) { type, #type }
1252 #define show_fabrics_type_name(type) \
1253 __print_symbolic(type, \
1254 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1255 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1256 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1259 * If not fabrics command, fctype will be ignored.
1261 #define show_opcode_name(qid, opcode, fctype) \
1262 ((opcode) == nvme_fabrics_command ? \
1263 show_fabrics_type_name(fctype) : \
1265 show_nvm_opcode_name(opcode) : \
1266 show_admin_opcode_name(opcode)))
1268 struct nvmf_common_command {
1278 * The legal cntlid range a NVMe Target will provide.
1279 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1280 * Devices based on earlier specs did not have the subsystem concept;
1281 * therefore, those devices had their cntlid value set to 0 as a result.
1283 #define NVME_CNTLID_MIN 1
1284 #define NVME_CNTLID_MAX 0xffef
1285 #define NVME_CNTLID_DYNAMIC 0xffff
1287 #define MAX_DISC_LOGS 255
1289 /* Discovery log page entry */
1290 struct nvmf_disc_rsp_page_entry {
1299 char trsvcid[NVMF_TRSVCID_SIZE];
1301 char subnqn[NVMF_NQN_FIELD_LEN];
1302 char traddr[NVMF_TRADDR_SIZE];
1304 char common[NVMF_TSAS_SIZE];
1316 /* Discovery log page header */
1317 struct nvmf_disc_rsp_page_hdr {
1322 struct nvmf_disc_rsp_page_entry entries[];
1326 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1329 struct nvmf_connect_command {
1335 union nvme_data_ptr dptr;
1345 struct nvmf_connect_data {
1349 char subsysnqn[NVMF_NQN_FIELD_LEN];
1350 char hostnqn[NVMF_NQN_FIELD_LEN];
1354 struct nvmf_property_set_command {
1367 struct nvmf_property_get_command {
1389 struct streams_directive_params {
1401 struct nvme_command {
1403 struct nvme_common_command common;
1404 struct nvme_rw_command rw;
1405 struct nvme_identify identify;
1406 struct nvme_features features;
1407 struct nvme_create_cq create_cq;
1408 struct nvme_create_sq create_sq;
1409 struct nvme_delete_queue delete_queue;
1410 struct nvme_download_firmware dlfw;
1411 struct nvme_format_cmd format;
1412 struct nvme_dsm_cmd dsm;
1413 struct nvme_write_zeroes_cmd write_zeroes;
1414 struct nvme_zone_mgmt_send_cmd zms;
1415 struct nvme_zone_mgmt_recv_cmd zmr;
1416 struct nvme_abort_cmd abort;
1417 struct nvme_get_log_page_command get_log_page;
1418 struct nvmf_common_command fabrics;
1419 struct nvmf_connect_command connect;
1420 struct nvmf_property_set_command prop_set;
1421 struct nvmf_property_get_command prop_get;
1422 struct nvme_dbbuf dbbuf;
1423 struct nvme_directive_cmd directive;
1427 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1429 return cmd->common.opcode == nvme_fabrics_command;
1432 struct nvme_error_slot {
1436 __le16 status_field;
1437 __le16 param_error_location;
1446 static inline bool nvme_is_write(struct nvme_command *cmd)
1451 * Why can't we simply have a Fabrics In and Fabrics out command?
1453 if (unlikely(nvme_is_fabrics(cmd)))
1454 return cmd->fabrics.fctype & 1;
1455 return cmd->common.opcode & 1;
1460 * Generic Command Status:
1462 NVME_SC_SUCCESS = 0x0,
1463 NVME_SC_INVALID_OPCODE = 0x1,
1464 NVME_SC_INVALID_FIELD = 0x2,
1465 NVME_SC_CMDID_CONFLICT = 0x3,
1466 NVME_SC_DATA_XFER_ERROR = 0x4,
1467 NVME_SC_POWER_LOSS = 0x5,
1468 NVME_SC_INTERNAL = 0x6,
1469 NVME_SC_ABORT_REQ = 0x7,
1470 NVME_SC_ABORT_QUEUE = 0x8,
1471 NVME_SC_FUSED_FAIL = 0x9,
1472 NVME_SC_FUSED_MISSING = 0xa,
1473 NVME_SC_INVALID_NS = 0xb,
1474 NVME_SC_CMD_SEQ_ERROR = 0xc,
1475 NVME_SC_SGL_INVALID_LAST = 0xd,
1476 NVME_SC_SGL_INVALID_COUNT = 0xe,
1477 NVME_SC_SGL_INVALID_DATA = 0xf,
1478 NVME_SC_SGL_INVALID_METADATA = 0x10,
1479 NVME_SC_SGL_INVALID_TYPE = 0x11,
1480 NVME_SC_CMB_INVALID_USE = 0x12,
1481 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1482 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1483 NVME_SC_OP_DENIED = 0x15,
1484 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1485 NVME_SC_RESERVED = 0x17,
1486 NVME_SC_HOST_ID_INCONSIST = 0x18,
1487 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1488 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1489 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
1490 NVME_SC_SANITIZE_FAILED = 0x1C,
1491 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1492 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1493 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
1494 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1495 NVME_SC_CMD_INTERRUPTED = 0x21,
1496 NVME_SC_TRANSIENT_TR_ERR = 0x22,
1498 NVME_SC_LBA_RANGE = 0x80,
1499 NVME_SC_CAP_EXCEEDED = 0x81,
1500 NVME_SC_NS_NOT_READY = 0x82,
1501 NVME_SC_RESERVATION_CONFLICT = 0x83,
1502 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
1505 * Command Specific Status:
1507 NVME_SC_CQ_INVALID = 0x100,
1508 NVME_SC_QID_INVALID = 0x101,
1509 NVME_SC_QUEUE_SIZE = 0x102,
1510 NVME_SC_ABORT_LIMIT = 0x103,
1511 NVME_SC_ABORT_MISSING = 0x104,
1512 NVME_SC_ASYNC_LIMIT = 0x105,
1513 NVME_SC_FIRMWARE_SLOT = 0x106,
1514 NVME_SC_FIRMWARE_IMAGE = 0x107,
1515 NVME_SC_INVALID_VECTOR = 0x108,
1516 NVME_SC_INVALID_LOG_PAGE = 0x109,
1517 NVME_SC_INVALID_FORMAT = 0x10a,
1518 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1519 NVME_SC_INVALID_QUEUE = 0x10c,
1520 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1521 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1522 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1523 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1524 NVME_SC_FW_NEEDS_RESET = 0x111,
1525 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1526 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1527 NVME_SC_OVERLAPPING_RANGE = 0x114,
1528 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1529 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1530 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1531 NVME_SC_NS_IS_PRIVATE = 0x119,
1532 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1533 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1534 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1535 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
1536 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1537 NVME_SC_CTRL_ID_INVALID = 0x11f,
1538 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1539 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1540 NVME_SC_RES_ID_INVALID = 0x122,
1541 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1542 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1543 NVME_SC_ANA_ATTACH_FAILED = 0x125,
1546 * I/O Command Set Specific - NVM commands:
1548 NVME_SC_BAD_ATTRIBUTES = 0x180,
1549 NVME_SC_INVALID_PI = 0x181,
1550 NVME_SC_READ_ONLY = 0x182,
1551 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1554 * I/O Command Set Specific - Fabrics commands:
1556 NVME_SC_CONNECT_FORMAT = 0x180,
1557 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1558 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1559 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1560 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1562 NVME_SC_DISCOVERY_RESTART = 0x190,
1563 NVME_SC_AUTH_REQUIRED = 0x191,
1566 * I/O Command Set Specific - Zoned commands:
1568 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1569 NVME_SC_ZONE_FULL = 0x1b9,
1570 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1571 NVME_SC_ZONE_OFFLINE = 0x1bb,
1572 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1573 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1574 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1575 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1578 * Media and Data Integrity Errors:
1580 NVME_SC_WRITE_FAULT = 0x280,
1581 NVME_SC_READ_ERROR = 0x281,
1582 NVME_SC_GUARD_CHECK = 0x282,
1583 NVME_SC_APPTAG_CHECK = 0x283,
1584 NVME_SC_REFTAG_CHECK = 0x284,
1585 NVME_SC_COMPARE_FAILED = 0x285,
1586 NVME_SC_ACCESS_DENIED = 0x286,
1587 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1590 * Path-related Errors:
1592 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1593 NVME_SC_ANA_INACCESSIBLE = 0x302,
1594 NVME_SC_ANA_TRANSITION = 0x303,
1595 NVME_SC_HOST_PATH_ERROR = 0x370,
1596 NVME_SC_HOST_ABORTED_CMD = 0x371,
1598 NVME_SC_CRD = 0x1800,
1599 NVME_SC_DNR = 0x4000,
1602 struct nvme_completion {
1604 * Used by Admin and Fabrics commands to return data:
1611 __le16 sq_head; /* how much of this queue may be reclaimed */
1612 __le16 sq_id; /* submission queue that generated this entry */
1613 __u16 command_id; /* of the command which completed */
1614 __le16 status; /* did the command fail, and if so, why? */
1617 #define NVME_VS(major, minor, tertiary) \
1618 (((major) << 16) | ((minor) << 8) | (tertiary))
1620 #define NVME_MAJOR(ver) ((ver) >> 16)
1621 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1622 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1624 #endif /* _LINUX_NVME_H */