1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
10 #include <linux/types.h>
11 #include <linux/uuid.h>
13 /* NQN names in commands fields specified one size */
14 #define NVMF_NQN_FIELD_LEN 256
16 /* However the max length of a qualified name is another size */
17 #define NVMF_NQN_SIZE 223
19 #define NVMF_TRSVCID_SIZE 32
20 #define NVMF_TRADDR_SIZE 256
21 #define NVMF_TSAS_SIZE 256
23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25 #define NVME_RDMA_IP_PORT 4420
27 #define NVME_NSID_ALL 0xffffffff
29 enum nvme_subsys_type {
30 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
31 NVME_NQN_NVME = 2, /* NVME type target subsystem */
34 /* Address Family codes for Discovery Log Page entry ADRFAM field */
36 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
37 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
38 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
39 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
40 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
41 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
45 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
47 NVMF_TRTYPE_RDMA = 1, /* RDMA */
48 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
49 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
50 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
54 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
56 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
57 NVMF_TREQ_REQUIRED = 1, /* Required */
58 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
59 #define NVME_TREQ_SECURE_CHANNEL_MASK \
60 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
62 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
65 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
69 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
70 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
73 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
77 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
78 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
79 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
80 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
81 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
84 /* RDMA Connection Management Service Type codes for Discovery Log Page
85 * entry TSAS RDMA_CMS field
88 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
91 #define NVME_AQ_DEPTH 32
92 #define NVME_NR_AEN_COMMANDS 1
93 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
96 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
97 * NVM-Express 1.2 specification, section 4.1.2.
99 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
102 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
103 NVME_REG_VS = 0x0008, /* Version */
104 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
105 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
106 NVME_REG_CC = 0x0014, /* Controller Configuration */
107 NVME_REG_CSTS = 0x001c, /* Controller Status */
108 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
109 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
110 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
111 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
112 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
113 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
114 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
115 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
116 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
119 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
120 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
121 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
122 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
125 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
128 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
131 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
132 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
133 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
134 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
135 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
136 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
137 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
139 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
140 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
143 NVME_CMBSZ_SQS = 1 << 0,
144 NVME_CMBSZ_CQS = 1 << 1,
145 NVME_CMBSZ_LISTS = 1 << 2,
146 NVME_CMBSZ_RDS = 1 << 3,
147 NVME_CMBSZ_WDS = 1 << 4,
149 NVME_CMBSZ_SZ_SHIFT = 12,
150 NVME_CMBSZ_SZ_MASK = 0xfffff,
152 NVME_CMBSZ_SZU_SHIFT = 8,
153 NVME_CMBSZ_SZU_MASK = 0xf,
157 * Submission and Completion Queue Entry Sizes for the NVM command set.
158 * (In bytes and specified as a power of two (2^n)).
160 #define NVME_ADM_SQES 6
161 #define NVME_NVM_IOSQES 6
162 #define NVME_NVM_IOCQES 4
165 NVME_CC_ENABLE = 1 << 0,
166 NVME_CC_EN_SHIFT = 0,
167 NVME_CC_CSS_SHIFT = 4,
168 NVME_CC_MPS_SHIFT = 7,
169 NVME_CC_AMS_SHIFT = 11,
170 NVME_CC_SHN_SHIFT = 14,
171 NVME_CC_IOSQES_SHIFT = 16,
172 NVME_CC_IOCQES_SHIFT = 20,
173 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
174 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
175 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
176 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
177 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
178 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
179 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
180 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
181 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
182 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
183 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
184 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
185 NVME_CAP_CSS_NVM = 1 << 0,
186 NVME_CAP_CSS_CSI = 1 << 6,
187 NVME_CSTS_RDY = 1 << 0,
188 NVME_CSTS_CFS = 1 << 1,
189 NVME_CSTS_NSSRO = 1 << 4,
190 NVME_CSTS_PP = 1 << 5,
191 NVME_CSTS_SHST_NORMAL = 0 << 2,
192 NVME_CSTS_SHST_OCCUR = 1 << 2,
193 NVME_CSTS_SHST_CMPLT = 2 << 2,
194 NVME_CSTS_SHST_MASK = 3 << 2,
197 struct nvme_id_power_state {
198 __le16 max_power; /* centiwatts */
201 __le32 entry_lat; /* microseconds */
202 __le32 exit_lat; /* microseconds */
211 __u8 active_work_scale;
216 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
217 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
220 enum nvme_ctrl_attr {
221 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
222 NVME_CTRL_ATTR_TBKAS = (1 << 6),
225 struct nvme_id_ctrl {
304 struct nvme_id_power_state psd[32];
309 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
310 NVME_CTRL_CMIC_ANA = 1 << 3,
311 NVME_CTRL_ONCS_COMPARE = 1 << 0,
312 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
313 NVME_CTRL_ONCS_DSM = 1 << 2,
314 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
315 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
316 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
317 NVME_CTRL_VWC_PRESENT = 1 << 0,
318 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
319 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
320 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
321 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
322 NVME_CTRL_CTRATT_128_ID = 1 << 0,
323 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
324 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
325 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
326 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
327 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
328 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
329 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
373 struct nvme_lbaf lbaf[16];
378 struct nvme_zns_lbafe {
384 struct nvme_id_ns_zns {
392 struct nvme_zns_lbafe lbafe[16];
397 struct nvme_id_ctrl_zns {
403 NVME_ID_CNS_NS = 0x00,
404 NVME_ID_CNS_CTRL = 0x01,
405 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
406 NVME_ID_CNS_NS_DESC_LIST = 0x03,
407 NVME_ID_CNS_CS_NS = 0x05,
408 NVME_ID_CNS_CS_CTRL = 0x06,
409 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
410 NVME_ID_CNS_NS_PRESENT = 0x11,
411 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
412 NVME_ID_CNS_CTRL_LIST = 0x13,
413 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
414 NVME_ID_CNS_NS_GRANULARITY = 0x16,
415 NVME_ID_CNS_UUID_LIST = 0x17,
424 NVME_DIR_IDENTIFY = 0x00,
425 NVME_DIR_STREAMS = 0x01,
426 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
427 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
428 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
429 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
430 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
431 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
432 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
433 NVME_DIR_ENDIR = 0x01,
437 NVME_NS_FEAT_THIN = 1 << 0,
438 NVME_NS_FEAT_ATOMICS = 1 << 1,
439 NVME_NS_FEAT_IO_OPT = 1 << 4,
440 NVME_NS_ATTR_RO = 1 << 0,
441 NVME_NS_FLBAS_LBA_MASK = 0xf,
442 NVME_NS_FLBAS_META_EXT = 0x10,
443 NVME_NS_NMIC_SHARED = 1 << 0,
444 NVME_LBAF_RP_BEST = 0,
445 NVME_LBAF_RP_BETTER = 1,
446 NVME_LBAF_RP_GOOD = 2,
447 NVME_LBAF_RP_DEGRADED = 3,
448 NVME_NS_DPC_PI_LAST = 1 << 4,
449 NVME_NS_DPC_PI_FIRST = 1 << 3,
450 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
451 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
452 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
453 NVME_NS_DPS_PI_FIRST = 1 << 3,
454 NVME_NS_DPS_PI_MASK = 0x7,
455 NVME_NS_DPS_PI_TYPE1 = 1,
456 NVME_NS_DPS_PI_TYPE2 = 2,
457 NVME_NS_DPS_PI_TYPE3 = 3,
460 /* Identify Namespace Metadata Capabilities (MC): */
462 NVME_MC_EXTENDED_LBA = (1 << 0),
463 NVME_MC_METADATA_PTR = (1 << 1),
466 struct nvme_ns_id_desc {
472 #define NVME_NIDT_EUI64_LEN 8
473 #define NVME_NIDT_NGUID_LEN 16
474 #define NVME_NIDT_UUID_LEN 16
475 #define NVME_NIDT_CSI_LEN 1
478 NVME_NIDT_EUI64 = 0x01,
479 NVME_NIDT_NGUID = 0x02,
480 NVME_NIDT_UUID = 0x03,
481 NVME_NIDT_CSI = 0x04,
484 struct nvme_smart_log {
485 __u8 critical_warning;
490 __u8 endu_grp_crit_warn_sumry;
492 __u8 data_units_read[16];
493 __u8 data_units_written[16];
495 __u8 host_writes[16];
496 __u8 ctrl_busy_time[16];
497 __u8 power_cycles[16];
498 __u8 power_on_hours[16];
499 __u8 unsafe_shutdowns[16];
500 __u8 media_errors[16];
501 __u8 num_err_log_entries[16];
502 __le32 warning_temp_time;
503 __le32 critical_comp_time;
504 __le16 temp_sensor[8];
505 __le32 thm_temp1_trans_count;
506 __le32 thm_temp2_trans_count;
507 __le32 thm_temp1_total_time;
508 __le32 thm_temp2_total_time;
512 struct nvme_fw_slot_info_log {
520 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
521 NVME_CMD_EFFECTS_LBCC = 1 << 1,
522 NVME_CMD_EFFECTS_NCC = 1 << 2,
523 NVME_CMD_EFFECTS_NIC = 1 << 3,
524 NVME_CMD_EFFECTS_CCC = 1 << 4,
525 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
526 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
529 struct nvme_effects_log {
535 enum nvme_ana_state {
536 NVME_ANA_OPTIMIZED = 0x01,
537 NVME_ANA_NONOPTIMIZED = 0x02,
538 NVME_ANA_INACCESSIBLE = 0x03,
539 NVME_ANA_PERSISTENT_LOSS = 0x04,
540 NVME_ANA_CHANGE = 0x0f,
543 struct nvme_ana_group_desc {
552 /* flag for the log specific field of the ANA log */
553 #define NVME_ANA_LOG_RGO (1 << 0)
555 struct nvme_ana_rsp_hdr {
561 struct nvme_zone_descriptor {
573 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
576 struct nvme_zone_report {
579 struct nvme_zone_descriptor entries[];
583 NVME_SMART_CRIT_SPARE = 1 << 0,
584 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
585 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
586 NVME_SMART_CRIT_MEDIA = 1 << 3,
587 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
599 NVME_AER_NOTICE_NS_CHANGED = 0x00,
600 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
601 NVME_AER_NOTICE_ANA = 0x03,
602 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
606 NVME_AEN_BIT_NS_ATTR = 8,
607 NVME_AEN_BIT_FW_ACT = 9,
608 NVME_AEN_BIT_ANA_CHANGE = 11,
609 NVME_AEN_BIT_DISC_CHANGE = 31,
613 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
614 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
615 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
616 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
619 struct nvme_lba_range_type {
630 NVME_LBART_TYPE_FS = 0x01,
631 NVME_LBART_TYPE_RAID = 0x02,
632 NVME_LBART_TYPE_CACHE = 0x03,
633 NVME_LBART_TYPE_SWAP = 0x04,
635 NVME_LBART_ATTRIB_TEMP = 1 << 0,
636 NVME_LBART_ATTRIB_HIDE = 1 << 1,
639 struct nvme_reservation_status {
655 enum nvme_async_event_type {
656 NVME_AER_TYPE_ERROR = 0,
657 NVME_AER_TYPE_SMART = 1,
658 NVME_AER_TYPE_NOTICE = 2,
664 nvme_cmd_flush = 0x00,
665 nvme_cmd_write = 0x01,
666 nvme_cmd_read = 0x02,
667 nvme_cmd_write_uncor = 0x04,
668 nvme_cmd_compare = 0x05,
669 nvme_cmd_write_zeroes = 0x08,
671 nvme_cmd_verify = 0x0c,
672 nvme_cmd_resv_register = 0x0d,
673 nvme_cmd_resv_report = 0x0e,
674 nvme_cmd_resv_acquire = 0x11,
675 nvme_cmd_resv_release = 0x15,
676 nvme_cmd_zone_mgmt_send = 0x79,
677 nvme_cmd_zone_mgmt_recv = 0x7a,
678 nvme_cmd_zone_append = 0x7d,
681 #define nvme_opcode_name(opcode) { opcode, #opcode }
682 #define show_nvm_opcode_name(val) \
683 __print_symbolic(val, \
684 nvme_opcode_name(nvme_cmd_flush), \
685 nvme_opcode_name(nvme_cmd_write), \
686 nvme_opcode_name(nvme_cmd_read), \
687 nvme_opcode_name(nvme_cmd_write_uncor), \
688 nvme_opcode_name(nvme_cmd_compare), \
689 nvme_opcode_name(nvme_cmd_write_zeroes), \
690 nvme_opcode_name(nvme_cmd_dsm), \
691 nvme_opcode_name(nvme_cmd_resv_register), \
692 nvme_opcode_name(nvme_cmd_resv_report), \
693 nvme_opcode_name(nvme_cmd_resv_acquire), \
694 nvme_opcode_name(nvme_cmd_resv_release))
698 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
700 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
701 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
702 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
703 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
707 NVME_SGL_FMT_ADDRESS = 0x00,
708 NVME_SGL_FMT_OFFSET = 0x01,
709 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
710 NVME_SGL_FMT_INVALIDATE = 0x0f,
714 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
716 * For struct nvme_sgl_desc:
717 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
718 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
719 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
721 * For struct nvme_keyed_sgl_desc:
722 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
724 * Transport-specific SGL types:
725 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
728 NVME_SGL_FMT_DATA_DESC = 0x00,
729 NVME_SGL_FMT_SEG_DESC = 0x02,
730 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
731 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
732 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
735 struct nvme_sgl_desc {
742 struct nvme_keyed_sgl_desc {
749 union nvme_data_ptr {
754 struct nvme_sgl_desc sgl;
755 struct nvme_keyed_sgl_desc ksgl;
759 * Lowest two bits of our flags field (FUSE field in the spec):
761 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
762 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
764 * Highest two bits in our flags field (PSDT field in the spec):
766 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
767 * If used, MPTR contains addr of single physical buffer (byte aligned).
768 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
769 * If used, MPTR contains an address of an SGL segment containing
770 * exactly 1 SGL descriptor (qword aligned).
773 NVME_CMD_FUSE_FIRST = (1 << 0),
774 NVME_CMD_FUSE_SECOND = (1 << 1),
776 NVME_CMD_SGL_METABUF = (1 << 6),
777 NVME_CMD_SGL_METASEG = (1 << 7),
778 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
781 struct nvme_common_command {
788 union nvme_data_ptr dptr;
797 struct nvme_rw_command {
804 union nvme_data_ptr dptr;
815 NVME_RW_LR = 1 << 15,
816 NVME_RW_FUA = 1 << 14,
817 NVME_RW_APPEND_PIREMAP = 1 << 9,
818 NVME_RW_DSM_FREQ_UNSPEC = 0,
819 NVME_RW_DSM_FREQ_TYPICAL = 1,
820 NVME_RW_DSM_FREQ_RARE = 2,
821 NVME_RW_DSM_FREQ_READS = 3,
822 NVME_RW_DSM_FREQ_WRITES = 4,
823 NVME_RW_DSM_FREQ_RW = 5,
824 NVME_RW_DSM_FREQ_ONCE = 6,
825 NVME_RW_DSM_FREQ_PREFETCH = 7,
826 NVME_RW_DSM_FREQ_TEMP = 8,
827 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
828 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
829 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
830 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
831 NVME_RW_DSM_SEQ_REQ = 1 << 6,
832 NVME_RW_DSM_COMPRESSED = 1 << 7,
833 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
834 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
835 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
836 NVME_RW_PRINFO_PRACT = 1 << 13,
837 NVME_RW_DTYPE_STREAMS = 1 << 4,
840 struct nvme_dsm_cmd {
846 union nvme_data_ptr dptr;
853 NVME_DSMGMT_IDR = 1 << 0,
854 NVME_DSMGMT_IDW = 1 << 1,
855 NVME_DSMGMT_AD = 1 << 2,
858 #define NVME_DSM_MAX_RANGES 256
860 struct nvme_dsm_range {
866 struct nvme_write_zeroes_cmd {
873 union nvme_data_ptr dptr;
883 enum nvme_zone_mgmt_action {
884 NVME_ZONE_CLOSE = 0x1,
885 NVME_ZONE_FINISH = 0x2,
886 NVME_ZONE_OPEN = 0x3,
887 NVME_ZONE_RESET = 0x4,
888 NVME_ZONE_OFFLINE = 0x5,
889 NVME_ZONE_SET_DESC_EXT = 0x10,
892 struct nvme_zone_mgmt_send_cmd {
899 union nvme_data_ptr dptr;
908 struct nvme_zone_mgmt_recv_cmd {
914 union nvme_data_ptr dptr;
925 NVME_ZRA_ZONE_REPORT = 0,
926 NVME_ZRASF_ZONE_REPORT_ALL = 0,
927 NVME_REPORT_ZONE_PARTIAL = 1,
933 NVME_TEMP_THRESH_MASK = 0xffff,
934 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
935 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
938 struct nvme_feat_auto_pst {
943 NVME_HOST_MEM_ENABLE = (1 << 0),
944 NVME_HOST_MEM_RETURN = (1 << 1),
947 struct nvme_feat_host_behavior {
953 NVME_ENABLE_ACRE = 1,
958 enum nvme_admin_opcode {
959 nvme_admin_delete_sq = 0x00,
960 nvme_admin_create_sq = 0x01,
961 nvme_admin_get_log_page = 0x02,
962 nvme_admin_delete_cq = 0x04,
963 nvme_admin_create_cq = 0x05,
964 nvme_admin_identify = 0x06,
965 nvme_admin_abort_cmd = 0x08,
966 nvme_admin_set_features = 0x09,
967 nvme_admin_get_features = 0x0a,
968 nvme_admin_async_event = 0x0c,
969 nvme_admin_ns_mgmt = 0x0d,
970 nvme_admin_activate_fw = 0x10,
971 nvme_admin_download_fw = 0x11,
972 nvme_admin_dev_self_test = 0x14,
973 nvme_admin_ns_attach = 0x15,
974 nvme_admin_keep_alive = 0x18,
975 nvme_admin_directive_send = 0x19,
976 nvme_admin_directive_recv = 0x1a,
977 nvme_admin_virtual_mgmt = 0x1c,
978 nvme_admin_nvme_mi_send = 0x1d,
979 nvme_admin_nvme_mi_recv = 0x1e,
980 nvme_admin_dbbuf = 0x7C,
981 nvme_admin_format_nvm = 0x80,
982 nvme_admin_security_send = 0x81,
983 nvme_admin_security_recv = 0x82,
984 nvme_admin_sanitize_nvm = 0x84,
985 nvme_admin_get_lba_status = 0x86,
986 nvme_admin_vendor_start = 0xC0,
989 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
990 #define show_admin_opcode_name(val) \
991 __print_symbolic(val, \
992 nvme_admin_opcode_name(nvme_admin_delete_sq), \
993 nvme_admin_opcode_name(nvme_admin_create_sq), \
994 nvme_admin_opcode_name(nvme_admin_get_log_page), \
995 nvme_admin_opcode_name(nvme_admin_delete_cq), \
996 nvme_admin_opcode_name(nvme_admin_create_cq), \
997 nvme_admin_opcode_name(nvme_admin_identify), \
998 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
999 nvme_admin_opcode_name(nvme_admin_set_features), \
1000 nvme_admin_opcode_name(nvme_admin_get_features), \
1001 nvme_admin_opcode_name(nvme_admin_async_event), \
1002 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1003 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1004 nvme_admin_opcode_name(nvme_admin_download_fw), \
1005 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1006 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1007 nvme_admin_opcode_name(nvme_admin_directive_send), \
1008 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1009 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1010 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1011 nvme_admin_opcode_name(nvme_admin_security_send), \
1012 nvme_admin_opcode_name(nvme_admin_security_recv), \
1013 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1014 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1017 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1018 NVME_CQ_IRQ_ENABLED = (1 << 1),
1019 NVME_SQ_PRIO_URGENT = (0 << 1),
1020 NVME_SQ_PRIO_HIGH = (1 << 1),
1021 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1022 NVME_SQ_PRIO_LOW = (3 << 1),
1023 NVME_FEAT_ARBITRATION = 0x01,
1024 NVME_FEAT_POWER_MGMT = 0x02,
1025 NVME_FEAT_LBA_RANGE = 0x03,
1026 NVME_FEAT_TEMP_THRESH = 0x04,
1027 NVME_FEAT_ERR_RECOVERY = 0x05,
1028 NVME_FEAT_VOLATILE_WC = 0x06,
1029 NVME_FEAT_NUM_QUEUES = 0x07,
1030 NVME_FEAT_IRQ_COALESCE = 0x08,
1031 NVME_FEAT_IRQ_CONFIG = 0x09,
1032 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1033 NVME_FEAT_ASYNC_EVENT = 0x0b,
1034 NVME_FEAT_AUTO_PST = 0x0c,
1035 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1036 NVME_FEAT_TIMESTAMP = 0x0e,
1037 NVME_FEAT_KATO = 0x0f,
1038 NVME_FEAT_HCTM = 0x10,
1039 NVME_FEAT_NOPSC = 0x11,
1040 NVME_FEAT_RRL = 0x12,
1041 NVME_FEAT_PLM_CONFIG = 0x13,
1042 NVME_FEAT_PLM_WINDOW = 0x14,
1043 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1044 NVME_FEAT_SANITIZE = 0x17,
1045 NVME_FEAT_SW_PROGRESS = 0x80,
1046 NVME_FEAT_HOST_ID = 0x81,
1047 NVME_FEAT_RESV_MASK = 0x82,
1048 NVME_FEAT_RESV_PERSIST = 0x83,
1049 NVME_FEAT_WRITE_PROTECT = 0x84,
1050 NVME_FEAT_VENDOR_START = 0xC0,
1051 NVME_FEAT_VENDOR_END = 0xFF,
1052 NVME_LOG_ERROR = 0x01,
1053 NVME_LOG_SMART = 0x02,
1054 NVME_LOG_FW_SLOT = 0x03,
1055 NVME_LOG_CHANGED_NS = 0x04,
1056 NVME_LOG_CMD_EFFECTS = 0x05,
1057 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1058 NVME_LOG_TELEMETRY_HOST = 0x07,
1059 NVME_LOG_TELEMETRY_CTRL = 0x08,
1060 NVME_LOG_ENDURANCE_GROUP = 0x09,
1061 NVME_LOG_ANA = 0x0c,
1062 NVME_LOG_DISC = 0x70,
1063 NVME_LOG_RESERVATION = 0x80,
1064 NVME_FWACT_REPL = (0 << 3),
1065 NVME_FWACT_REPL_ACTV = (1 << 3),
1066 NVME_FWACT_ACTV = (2 << 3),
1069 /* NVMe Namespace Write Protect State */
1071 NVME_NS_NO_WRITE_PROTECT = 0,
1072 NVME_NS_WRITE_PROTECT,
1073 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1074 NVME_NS_WRITE_PROTECT_PERMANENT,
1077 #define NVME_MAX_CHANGED_NAMESPACES 1024
1079 struct nvme_identify {
1085 union nvme_data_ptr dptr;
1094 #define NVME_IDENTIFY_DATA_SIZE 4096
1096 struct nvme_features {
1102 union nvme_data_ptr dptr;
1111 struct nvme_host_mem_buf_desc {
1117 struct nvme_create_cq {
1131 struct nvme_create_sq {
1145 struct nvme_delete_queue {
1155 struct nvme_abort_cmd {
1165 struct nvme_download_firmware {
1170 union nvme_data_ptr dptr;
1176 struct nvme_format_cmd {
1186 struct nvme_get_log_page_command {
1192 union nvme_data_ptr dptr;
1194 __u8 lsp; /* upper 4 bits reserved */
1210 struct nvme_directive_cmd {
1216 union nvme_data_ptr dptr;
1229 * Fabrics subcommands.
1231 enum nvmf_fabrics_opcode {
1232 nvme_fabrics_command = 0x7f,
1235 enum nvmf_capsule_command {
1236 nvme_fabrics_type_property_set = 0x00,
1237 nvme_fabrics_type_connect = 0x01,
1238 nvme_fabrics_type_property_get = 0x04,
1241 #define nvme_fabrics_type_name(type) { type, #type }
1242 #define show_fabrics_type_name(type) \
1243 __print_symbolic(type, \
1244 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1245 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1246 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1249 * If not fabrics command, fctype will be ignored.
1251 #define show_opcode_name(qid, opcode, fctype) \
1252 ((opcode) == nvme_fabrics_command ? \
1253 show_fabrics_type_name(fctype) : \
1255 show_nvm_opcode_name(opcode) : \
1256 show_admin_opcode_name(opcode)))
1258 struct nvmf_common_command {
1268 * The legal cntlid range a NVMe Target will provide.
1269 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1270 * Devices based on earlier specs did not have the subsystem concept;
1271 * therefore, those devices had their cntlid value set to 0 as a result.
1273 #define NVME_CNTLID_MIN 1
1274 #define NVME_CNTLID_MAX 0xffef
1275 #define NVME_CNTLID_DYNAMIC 0xffff
1277 #define MAX_DISC_LOGS 255
1279 /* Discovery log page entry */
1280 struct nvmf_disc_rsp_page_entry {
1289 char trsvcid[NVMF_TRSVCID_SIZE];
1291 char subnqn[NVMF_NQN_FIELD_LEN];
1292 char traddr[NVMF_TRADDR_SIZE];
1294 char common[NVMF_TSAS_SIZE];
1306 /* Discovery log page header */
1307 struct nvmf_disc_rsp_page_hdr {
1312 struct nvmf_disc_rsp_page_entry entries[];
1316 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1319 struct nvmf_connect_command {
1325 union nvme_data_ptr dptr;
1335 struct nvmf_connect_data {
1339 char subsysnqn[NVMF_NQN_FIELD_LEN];
1340 char hostnqn[NVMF_NQN_FIELD_LEN];
1344 struct nvmf_property_set_command {
1357 struct nvmf_property_get_command {
1379 struct streams_directive_params {
1391 struct nvme_command {
1393 struct nvme_common_command common;
1394 struct nvme_rw_command rw;
1395 struct nvme_identify identify;
1396 struct nvme_features features;
1397 struct nvme_create_cq create_cq;
1398 struct nvme_create_sq create_sq;
1399 struct nvme_delete_queue delete_queue;
1400 struct nvme_download_firmware dlfw;
1401 struct nvme_format_cmd format;
1402 struct nvme_dsm_cmd dsm;
1403 struct nvme_write_zeroes_cmd write_zeroes;
1404 struct nvme_zone_mgmt_send_cmd zms;
1405 struct nvme_zone_mgmt_recv_cmd zmr;
1406 struct nvme_abort_cmd abort;
1407 struct nvme_get_log_page_command get_log_page;
1408 struct nvmf_common_command fabrics;
1409 struct nvmf_connect_command connect;
1410 struct nvmf_property_set_command prop_set;
1411 struct nvmf_property_get_command prop_get;
1412 struct nvme_dbbuf dbbuf;
1413 struct nvme_directive_cmd directive;
1417 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1419 return cmd->common.opcode == nvme_fabrics_command;
1422 struct nvme_error_slot {
1426 __le16 status_field;
1427 __le16 param_error_location;
1436 static inline bool nvme_is_write(struct nvme_command *cmd)
1441 * Why can't we simply have a Fabrics In and Fabrics out command?
1443 if (unlikely(nvme_is_fabrics(cmd)))
1444 return cmd->fabrics.fctype & 1;
1445 return cmd->common.opcode & 1;
1450 * Generic Command Status:
1452 NVME_SC_SUCCESS = 0x0,
1453 NVME_SC_INVALID_OPCODE = 0x1,
1454 NVME_SC_INVALID_FIELD = 0x2,
1455 NVME_SC_CMDID_CONFLICT = 0x3,
1456 NVME_SC_DATA_XFER_ERROR = 0x4,
1457 NVME_SC_POWER_LOSS = 0x5,
1458 NVME_SC_INTERNAL = 0x6,
1459 NVME_SC_ABORT_REQ = 0x7,
1460 NVME_SC_ABORT_QUEUE = 0x8,
1461 NVME_SC_FUSED_FAIL = 0x9,
1462 NVME_SC_FUSED_MISSING = 0xa,
1463 NVME_SC_INVALID_NS = 0xb,
1464 NVME_SC_CMD_SEQ_ERROR = 0xc,
1465 NVME_SC_SGL_INVALID_LAST = 0xd,
1466 NVME_SC_SGL_INVALID_COUNT = 0xe,
1467 NVME_SC_SGL_INVALID_DATA = 0xf,
1468 NVME_SC_SGL_INVALID_METADATA = 0x10,
1469 NVME_SC_SGL_INVALID_TYPE = 0x11,
1471 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1472 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1474 NVME_SC_SANITIZE_FAILED = 0x1C,
1475 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1477 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1478 NVME_SC_CMD_INTERRUPTED = 0x21,
1480 NVME_SC_LBA_RANGE = 0x80,
1481 NVME_SC_CAP_EXCEEDED = 0x81,
1482 NVME_SC_NS_NOT_READY = 0x82,
1483 NVME_SC_RESERVATION_CONFLICT = 0x83,
1486 * Command Specific Status:
1488 NVME_SC_CQ_INVALID = 0x100,
1489 NVME_SC_QID_INVALID = 0x101,
1490 NVME_SC_QUEUE_SIZE = 0x102,
1491 NVME_SC_ABORT_LIMIT = 0x103,
1492 NVME_SC_ABORT_MISSING = 0x104,
1493 NVME_SC_ASYNC_LIMIT = 0x105,
1494 NVME_SC_FIRMWARE_SLOT = 0x106,
1495 NVME_SC_FIRMWARE_IMAGE = 0x107,
1496 NVME_SC_INVALID_VECTOR = 0x108,
1497 NVME_SC_INVALID_LOG_PAGE = 0x109,
1498 NVME_SC_INVALID_FORMAT = 0x10a,
1499 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1500 NVME_SC_INVALID_QUEUE = 0x10c,
1501 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1502 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1503 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1504 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1505 NVME_SC_FW_NEEDS_RESET = 0x111,
1506 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1507 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1508 NVME_SC_OVERLAPPING_RANGE = 0x114,
1509 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1510 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1511 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1512 NVME_SC_NS_IS_PRIVATE = 0x119,
1513 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1514 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1515 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1516 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1517 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1520 * I/O Command Set Specific - NVM commands:
1522 NVME_SC_BAD_ATTRIBUTES = 0x180,
1523 NVME_SC_INVALID_PI = 0x181,
1524 NVME_SC_READ_ONLY = 0x182,
1525 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1528 * I/O Command Set Specific - Fabrics commands:
1530 NVME_SC_CONNECT_FORMAT = 0x180,
1531 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1532 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1533 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1534 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1536 NVME_SC_DISCOVERY_RESTART = 0x190,
1537 NVME_SC_AUTH_REQUIRED = 0x191,
1540 * I/O Command Set Specific - Zoned commands:
1542 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1543 NVME_SC_ZONE_FULL = 0x1b9,
1544 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1545 NVME_SC_ZONE_OFFLINE = 0x1bb,
1546 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1547 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1548 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1549 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1552 * Media and Data Integrity Errors:
1554 NVME_SC_WRITE_FAULT = 0x280,
1555 NVME_SC_READ_ERROR = 0x281,
1556 NVME_SC_GUARD_CHECK = 0x282,
1557 NVME_SC_APPTAG_CHECK = 0x283,
1558 NVME_SC_REFTAG_CHECK = 0x284,
1559 NVME_SC_COMPARE_FAILED = 0x285,
1560 NVME_SC_ACCESS_DENIED = 0x286,
1561 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1564 * Path-related Errors:
1566 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1567 NVME_SC_ANA_INACCESSIBLE = 0x302,
1568 NVME_SC_ANA_TRANSITION = 0x303,
1569 NVME_SC_HOST_PATH_ERROR = 0x370,
1570 NVME_SC_HOST_ABORTED_CMD = 0x371,
1572 NVME_SC_CRD = 0x1800,
1573 NVME_SC_DNR = 0x4000,
1576 struct nvme_completion {
1578 * Used by Admin and Fabrics commands to return data:
1585 __le16 sq_head; /* how much of this queue may be reclaimed */
1586 __le16 sq_id; /* submission queue that generated this entry */
1587 __u16 command_id; /* of the command which completed */
1588 __le16 status; /* did the command fail, and if so, why? */
1591 #define NVME_VS(major, minor, tertiary) \
1592 (((major) << 16) | ((minor) << 8) | (tertiary))
1594 #define NVME_MAJOR(ver) ((ver) >> 16)
1595 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1596 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1598 #endif /* _LINUX_NVME_H */