1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
10 #include <linux/bits.h>
11 #include <linux/types.h>
12 #include <linux/uuid.h>
14 /* NQN names in commands fields specified one size */
15 #define NVMF_NQN_FIELD_LEN 256
17 /* However the max length of a qualified name is another size */
18 #define NVMF_NQN_SIZE 223
20 #define NVMF_TRSVCID_SIZE 32
21 #define NVMF_TRADDR_SIZE 256
22 #define NVMF_TSAS_SIZE 256
23 #define NVMF_AUTH_HASH_LEN 64
25 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
27 #define NVME_RDMA_IP_PORT 4420
29 #define NVME_NSID_ALL 0xffffffff
31 enum nvme_subsys_type {
32 /* Referral to another discovery type target subsystem */
35 /* NVME type target subsystem */
38 /* Current discovery type target subsystem */
43 NVME_CTRL_IO = 1, /* I/O controller */
44 NVME_CTRL_DISC = 2, /* Discovery controller */
45 NVME_CTRL_ADMIN = 3, /* Administrative controller */
49 NVME_DCTYPE_NOT_REPORTED = 0,
50 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
51 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
54 /* Address Family codes for Discovery Log Page entry ADRFAM field */
56 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
57 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
58 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
59 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
60 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
61 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
65 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
67 NVMF_TRTYPE_RDMA = 1, /* RDMA */
68 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
69 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
70 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
74 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
76 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
77 NVMF_TREQ_REQUIRED = 1, /* Required */
78 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
79 #define NVME_TREQ_SECURE_CHANNEL_MASK \
80 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
82 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
85 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
89 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
90 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
93 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
97 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
98 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
99 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
100 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
101 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
104 /* RDMA Connection Management Service Type codes for Discovery Log Page
105 * entry TSAS RDMA_CMS field
108 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
111 /* TSAS SECTYPE for TCP transport */
113 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */
114 NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
115 NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
118 #define NVME_AQ_DEPTH 32
119 #define NVME_NR_AEN_COMMANDS 1
120 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
123 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
124 * NVM-Express 1.2 specification, section 4.1.2.
126 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
129 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
130 NVME_REG_VS = 0x0008, /* Version */
131 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
132 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
133 NVME_REG_CC = 0x0014, /* Controller Configuration */
134 NVME_REG_CSTS = 0x001c, /* Controller Status */
135 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
136 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
137 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
138 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
139 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
140 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
141 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
142 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
143 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
146 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
149 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
150 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
151 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
152 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
153 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
156 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
159 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
162 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
163 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
164 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
165 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
166 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
167 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
168 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
169 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
171 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
172 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
174 #define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
175 #define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
178 NVME_CMBSZ_SQS = 1 << 0,
179 NVME_CMBSZ_CQS = 1 << 1,
180 NVME_CMBSZ_LISTS = 1 << 2,
181 NVME_CMBSZ_RDS = 1 << 3,
182 NVME_CMBSZ_WDS = 1 << 4,
184 NVME_CMBSZ_SZ_SHIFT = 12,
185 NVME_CMBSZ_SZ_MASK = 0xfffff,
187 NVME_CMBSZ_SZU_SHIFT = 8,
188 NVME_CMBSZ_SZU_MASK = 0xf,
192 * Submission and Completion Queue Entry Sizes for the NVM command set.
193 * (In bytes and specified as a power of two (2^n)).
195 #define NVME_ADM_SQES 6
196 #define NVME_NVM_IOSQES 6
197 #define NVME_NVM_IOCQES 4
200 NVME_CC_ENABLE = 1 << 0,
201 NVME_CC_EN_SHIFT = 0,
202 NVME_CC_CSS_SHIFT = 4,
203 NVME_CC_MPS_SHIFT = 7,
204 NVME_CC_AMS_SHIFT = 11,
205 NVME_CC_SHN_SHIFT = 14,
206 NVME_CC_IOSQES_SHIFT = 16,
207 NVME_CC_IOCQES_SHIFT = 20,
208 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
209 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
210 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
211 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
212 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
213 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
214 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
215 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
216 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
217 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
218 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
219 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
220 NVME_CC_CRIME = 1 << 24,
224 NVME_CSTS_RDY = 1 << 0,
225 NVME_CSTS_CFS = 1 << 1,
226 NVME_CSTS_NSSRO = 1 << 4,
227 NVME_CSTS_PP = 1 << 5,
228 NVME_CSTS_SHST_NORMAL = 0 << 2,
229 NVME_CSTS_SHST_OCCUR = 1 << 2,
230 NVME_CSTS_SHST_CMPLT = 2 << 2,
231 NVME_CSTS_SHST_MASK = 3 << 2,
235 NVME_CMBMSC_CRE = 1 << 0,
236 NVME_CMBMSC_CMSE = 1 << 1,
240 NVME_CAP_CSS_NVM = 1 << 0,
241 NVME_CAP_CSS_CSI = 1 << 6,
245 NVME_CAP_CRMS_CRWMS = 1ULL << 59,
246 NVME_CAP_CRMS_CRIMS = 1ULL << 60,
249 struct nvme_id_power_state {
250 __le16 max_power; /* centiwatts */
253 __le32 entry_lat; /* microseconds */
254 __le32 exit_lat; /* microseconds */
263 __u8 active_work_scale;
268 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
269 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
272 enum nvme_ctrl_attr {
273 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
274 NVME_CTRL_ATTR_TBKAS = (1 << 6),
275 NVME_CTRL_ATTR_ELBAS = (1 << 15),
278 struct nvme_id_ctrl {
361 struct nvme_id_power_state psd[32];
366 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
367 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
368 NVME_CTRL_CMIC_ANA = 1 << 3,
369 NVME_CTRL_ONCS_COMPARE = 1 << 0,
370 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
371 NVME_CTRL_ONCS_DSM = 1 << 2,
372 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
373 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
374 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
375 NVME_CTRL_VWC_PRESENT = 1 << 0,
376 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
377 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
378 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
379 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
380 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
381 NVME_CTRL_CTRATT_128_ID = 1 << 0,
382 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
383 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
384 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
385 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
386 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
387 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
388 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
432 struct nvme_lbaf lbaf[64];
436 /* I/O Command Set Independent Identify Namespace Data Structure */
437 struct nvme_id_ns_cs_indep {
451 struct nvme_zns_lbafe {
457 struct nvme_id_ns_zns {
465 struct nvme_zns_lbafe lbafe[64];
469 struct nvme_id_ctrl_zns {
474 struct nvme_id_ns_nvm {
483 NVME_ID_NS_NVM_STS_MASK = 0x7f,
484 NVME_ID_NS_NVM_GUARD_SHIFT = 7,
485 NVME_ID_NS_NVM_GUARD_MASK = 0x3,
488 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
490 return elbaf & NVME_ID_NS_NVM_STS_MASK;
493 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
495 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
498 struct nvme_id_ctrl_nvm {
509 NVME_ID_CNS_NS = 0x00,
510 NVME_ID_CNS_CTRL = 0x01,
511 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
512 NVME_ID_CNS_NS_DESC_LIST = 0x03,
513 NVME_ID_CNS_CS_NS = 0x05,
514 NVME_ID_CNS_CS_CTRL = 0x06,
515 NVME_ID_CNS_NS_CS_INDEP = 0x08,
516 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
517 NVME_ID_CNS_NS_PRESENT = 0x11,
518 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
519 NVME_ID_CNS_CTRL_LIST = 0x13,
520 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
521 NVME_ID_CNS_NS_GRANULARITY = 0x16,
522 NVME_ID_CNS_UUID_LIST = 0x17,
531 NVME_DIR_IDENTIFY = 0x00,
532 NVME_DIR_STREAMS = 0x01,
533 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
534 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
535 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
536 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
537 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
538 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
539 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
540 NVME_DIR_ENDIR = 0x01,
544 NVME_NS_FEAT_THIN = 1 << 0,
545 NVME_NS_FEAT_ATOMICS = 1 << 1,
546 NVME_NS_FEAT_IO_OPT = 1 << 4,
547 NVME_NS_ATTR_RO = 1 << 0,
548 NVME_NS_FLBAS_LBA_MASK = 0xf,
549 NVME_NS_FLBAS_LBA_UMASK = 0x60,
550 NVME_NS_FLBAS_LBA_SHIFT = 1,
551 NVME_NS_FLBAS_META_EXT = 0x10,
552 NVME_NS_NMIC_SHARED = 1 << 0,
553 NVME_LBAF_RP_BEST = 0,
554 NVME_LBAF_RP_BETTER = 1,
555 NVME_LBAF_RP_GOOD = 2,
556 NVME_LBAF_RP_DEGRADED = 3,
557 NVME_NS_DPC_PI_LAST = 1 << 4,
558 NVME_NS_DPC_PI_FIRST = 1 << 3,
559 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
560 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
561 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
562 NVME_NS_DPS_PI_FIRST = 1 << 3,
563 NVME_NS_DPS_PI_MASK = 0x7,
564 NVME_NS_DPS_PI_TYPE1 = 1,
565 NVME_NS_DPS_PI_TYPE2 = 2,
566 NVME_NS_DPS_PI_TYPE3 = 3,
570 NVME_NSTAT_NRDY = 1 << 0,
574 NVME_NVM_NS_16B_GUARD = 0,
575 NVME_NVM_NS_32B_GUARD = 1,
576 NVME_NVM_NS_64B_GUARD = 2,
579 static inline __u8 nvme_lbaf_index(__u8 flbas)
581 return (flbas & NVME_NS_FLBAS_LBA_MASK) |
582 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
585 /* Identify Namespace Metadata Capabilities (MC): */
587 NVME_MC_EXTENDED_LBA = (1 << 0),
588 NVME_MC_METADATA_PTR = (1 << 1),
591 struct nvme_ns_id_desc {
597 #define NVME_NIDT_EUI64_LEN 8
598 #define NVME_NIDT_NGUID_LEN 16
599 #define NVME_NIDT_UUID_LEN 16
600 #define NVME_NIDT_CSI_LEN 1
603 NVME_NIDT_EUI64 = 0x01,
604 NVME_NIDT_NGUID = 0x02,
605 NVME_NIDT_UUID = 0x03,
606 NVME_NIDT_CSI = 0x04,
609 struct nvme_smart_log {
610 __u8 critical_warning;
615 __u8 endu_grp_crit_warn_sumry;
617 __u8 data_units_read[16];
618 __u8 data_units_written[16];
620 __u8 host_writes[16];
621 __u8 ctrl_busy_time[16];
622 __u8 power_cycles[16];
623 __u8 power_on_hours[16];
624 __u8 unsafe_shutdowns[16];
625 __u8 media_errors[16];
626 __u8 num_err_log_entries[16];
627 __le32 warning_temp_time;
628 __le32 critical_comp_time;
629 __le16 temp_sensor[8];
630 __le32 thm_temp1_trans_count;
631 __le32 thm_temp2_trans_count;
632 __le32 thm_temp1_total_time;
633 __le32 thm_temp2_total_time;
637 struct nvme_fw_slot_info_log {
645 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
646 NVME_CMD_EFFECTS_LBCC = 1 << 1,
647 NVME_CMD_EFFECTS_NCC = 1 << 2,
648 NVME_CMD_EFFECTS_NIC = 1 << 3,
649 NVME_CMD_EFFECTS_CCC = 1 << 4,
650 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
651 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
652 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20),
655 struct nvme_effects_log {
661 enum nvme_ana_state {
662 NVME_ANA_OPTIMIZED = 0x01,
663 NVME_ANA_NONOPTIMIZED = 0x02,
664 NVME_ANA_INACCESSIBLE = 0x03,
665 NVME_ANA_PERSISTENT_LOSS = 0x04,
666 NVME_ANA_CHANGE = 0x0f,
669 struct nvme_ana_group_desc {
678 /* flag for the log specific field of the ANA log */
679 #define NVME_ANA_LOG_RGO (1 << 0)
681 struct nvme_ana_rsp_hdr {
687 struct nvme_zone_descriptor {
699 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
702 struct nvme_zone_report {
705 struct nvme_zone_descriptor entries[];
709 NVME_SMART_CRIT_SPARE = 1 << 0,
710 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
711 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
712 NVME_SMART_CRIT_MEDIA = 1 << 3,
713 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
725 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
729 NVME_AER_NOTICE_NS_CHANGED = 0x00,
730 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
731 NVME_AER_NOTICE_ANA = 0x03,
732 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
736 NVME_AEN_BIT_NS_ATTR = 8,
737 NVME_AEN_BIT_FW_ACT = 9,
738 NVME_AEN_BIT_ANA_CHANGE = 11,
739 NVME_AEN_BIT_DISC_CHANGE = 31,
743 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
744 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
745 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
746 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
749 struct nvme_lba_range_type {
760 NVME_LBART_TYPE_FS = 0x01,
761 NVME_LBART_TYPE_RAID = 0x02,
762 NVME_LBART_TYPE_CACHE = 0x03,
763 NVME_LBART_TYPE_SWAP = 0x04,
765 NVME_LBART_ATTRIB_TEMP = 1 << 0,
766 NVME_LBART_ATTRIB_HIDE = 1 << 1,
770 NVME_PR_WRITE_EXCLUSIVE = 1,
771 NVME_PR_EXCLUSIVE_ACCESS = 2,
772 NVME_PR_WRITE_EXCLUSIVE_REG_ONLY = 3,
773 NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY = 4,
774 NVME_PR_WRITE_EXCLUSIVE_ALL_REGS = 5,
775 NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS = 6,
779 NVME_EXTENDED_DATA_STRUCT = 0x1,
782 struct nvme_registered_ctrl {
790 struct nvme_reservation_status {
797 struct nvme_registered_ctrl regctl_ds[];
800 struct nvme_registered_ctrl_ext {
809 struct nvme_reservation_status_ext {
817 struct nvme_registered_ctrl_ext regctl_eds[];
820 enum nvme_async_event_type {
821 NVME_AER_TYPE_ERROR = 0,
822 NVME_AER_TYPE_SMART = 1,
823 NVME_AER_TYPE_NOTICE = 2,
829 nvme_cmd_flush = 0x00,
830 nvme_cmd_write = 0x01,
831 nvme_cmd_read = 0x02,
832 nvme_cmd_write_uncor = 0x04,
833 nvme_cmd_compare = 0x05,
834 nvme_cmd_write_zeroes = 0x08,
836 nvme_cmd_verify = 0x0c,
837 nvme_cmd_resv_register = 0x0d,
838 nvme_cmd_resv_report = 0x0e,
839 nvme_cmd_resv_acquire = 0x11,
840 nvme_cmd_resv_release = 0x15,
841 nvme_cmd_zone_mgmt_send = 0x79,
842 nvme_cmd_zone_mgmt_recv = 0x7a,
843 nvme_cmd_zone_append = 0x7d,
844 nvme_cmd_vendor_start = 0x80,
847 #define nvme_opcode_name(opcode) { opcode, #opcode }
848 #define show_nvm_opcode_name(val) \
849 __print_symbolic(val, \
850 nvme_opcode_name(nvme_cmd_flush), \
851 nvme_opcode_name(nvme_cmd_write), \
852 nvme_opcode_name(nvme_cmd_read), \
853 nvme_opcode_name(nvme_cmd_write_uncor), \
854 nvme_opcode_name(nvme_cmd_compare), \
855 nvme_opcode_name(nvme_cmd_write_zeroes), \
856 nvme_opcode_name(nvme_cmd_dsm), \
857 nvme_opcode_name(nvme_cmd_verify), \
858 nvme_opcode_name(nvme_cmd_resv_register), \
859 nvme_opcode_name(nvme_cmd_resv_report), \
860 nvme_opcode_name(nvme_cmd_resv_acquire), \
861 nvme_opcode_name(nvme_cmd_resv_release), \
862 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
863 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
864 nvme_opcode_name(nvme_cmd_zone_append))
869 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
871 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
872 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
873 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
874 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
878 NVME_SGL_FMT_ADDRESS = 0x00,
879 NVME_SGL_FMT_OFFSET = 0x01,
880 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
881 NVME_SGL_FMT_INVALIDATE = 0x0f,
885 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
887 * For struct nvme_sgl_desc:
888 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
889 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
890 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
892 * For struct nvme_keyed_sgl_desc:
893 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
895 * Transport-specific SGL types:
896 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
899 NVME_SGL_FMT_DATA_DESC = 0x00,
900 NVME_SGL_FMT_SEG_DESC = 0x02,
901 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
902 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
903 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
906 struct nvme_sgl_desc {
913 struct nvme_keyed_sgl_desc {
920 union nvme_data_ptr {
925 struct nvme_sgl_desc sgl;
926 struct nvme_keyed_sgl_desc ksgl;
930 * Lowest two bits of our flags field (FUSE field in the spec):
932 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
933 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
935 * Highest two bits in our flags field (PSDT field in the spec):
937 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
938 * If used, MPTR contains addr of single physical buffer (byte aligned).
939 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
940 * If used, MPTR contains an address of an SGL segment containing
941 * exactly 1 SGL descriptor (qword aligned).
944 NVME_CMD_FUSE_FIRST = (1 << 0),
945 NVME_CMD_FUSE_SECOND = (1 << 1),
947 NVME_CMD_SGL_METABUF = (1 << 6),
948 NVME_CMD_SGL_METASEG = (1 << 7),
949 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
952 struct nvme_common_command {
959 union nvme_data_ptr dptr;
970 struct nvme_rw_command {
978 union nvme_data_ptr dptr;
989 NVME_RW_LR = 1 << 15,
990 NVME_RW_FUA = 1 << 14,
991 NVME_RW_APPEND_PIREMAP = 1 << 9,
992 NVME_RW_DSM_FREQ_UNSPEC = 0,
993 NVME_RW_DSM_FREQ_TYPICAL = 1,
994 NVME_RW_DSM_FREQ_RARE = 2,
995 NVME_RW_DSM_FREQ_READS = 3,
996 NVME_RW_DSM_FREQ_WRITES = 4,
997 NVME_RW_DSM_FREQ_RW = 5,
998 NVME_RW_DSM_FREQ_ONCE = 6,
999 NVME_RW_DSM_FREQ_PREFETCH = 7,
1000 NVME_RW_DSM_FREQ_TEMP = 8,
1001 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
1002 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
1003 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
1004 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
1005 NVME_RW_DSM_SEQ_REQ = 1 << 6,
1006 NVME_RW_DSM_COMPRESSED = 1 << 7,
1007 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
1008 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
1009 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
1010 NVME_RW_PRINFO_PRACT = 1 << 13,
1011 NVME_RW_DTYPE_STREAMS = 1 << 4,
1012 NVME_WZ_DEAC = 1 << 9,
1015 struct nvme_dsm_cmd {
1021 union nvme_data_ptr dptr;
1028 NVME_DSMGMT_IDR = 1 << 0,
1029 NVME_DSMGMT_IDW = 1 << 1,
1030 NVME_DSMGMT_AD = 1 << 2,
1033 #define NVME_DSM_MAX_RANGES 256
1035 struct nvme_dsm_range {
1041 struct nvme_write_zeroes_cmd {
1048 union nvme_data_ptr dptr;
1058 enum nvme_zone_mgmt_action {
1059 NVME_ZONE_CLOSE = 0x1,
1060 NVME_ZONE_FINISH = 0x2,
1061 NVME_ZONE_OPEN = 0x3,
1062 NVME_ZONE_RESET = 0x4,
1063 NVME_ZONE_OFFLINE = 0x5,
1064 NVME_ZONE_SET_DESC_EXT = 0x10,
1067 struct nvme_zone_mgmt_send_cmd {
1074 union nvme_data_ptr dptr;
1083 struct nvme_zone_mgmt_recv_cmd {
1089 union nvme_data_ptr dptr;
1100 NVME_ZRA_ZONE_REPORT = 0,
1101 NVME_ZRASF_ZONE_REPORT_ALL = 0,
1102 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
1103 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
1104 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
1105 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
1106 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
1107 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
1108 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
1109 NVME_REPORT_ZONE_PARTIAL = 1,
1115 NVME_TEMP_THRESH_MASK = 0xffff,
1116 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
1117 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
1120 struct nvme_feat_auto_pst {
1125 NVME_HOST_MEM_ENABLE = (1 << 0),
1126 NVME_HOST_MEM_RETURN = (1 << 1),
1129 struct nvme_feat_host_behavior {
1137 NVME_ENABLE_ACRE = 1,
1138 NVME_ENABLE_LBAFEE = 1,
1141 /* Admin commands */
1143 enum nvme_admin_opcode {
1144 nvme_admin_delete_sq = 0x00,
1145 nvme_admin_create_sq = 0x01,
1146 nvme_admin_get_log_page = 0x02,
1147 nvme_admin_delete_cq = 0x04,
1148 nvme_admin_create_cq = 0x05,
1149 nvme_admin_identify = 0x06,
1150 nvme_admin_abort_cmd = 0x08,
1151 nvme_admin_set_features = 0x09,
1152 nvme_admin_get_features = 0x0a,
1153 nvme_admin_async_event = 0x0c,
1154 nvme_admin_ns_mgmt = 0x0d,
1155 nvme_admin_activate_fw = 0x10,
1156 nvme_admin_download_fw = 0x11,
1157 nvme_admin_dev_self_test = 0x14,
1158 nvme_admin_ns_attach = 0x15,
1159 nvme_admin_keep_alive = 0x18,
1160 nvme_admin_directive_send = 0x19,
1161 nvme_admin_directive_recv = 0x1a,
1162 nvme_admin_virtual_mgmt = 0x1c,
1163 nvme_admin_nvme_mi_send = 0x1d,
1164 nvme_admin_nvme_mi_recv = 0x1e,
1165 nvme_admin_dbbuf = 0x7C,
1166 nvme_admin_format_nvm = 0x80,
1167 nvme_admin_security_send = 0x81,
1168 nvme_admin_security_recv = 0x82,
1169 nvme_admin_sanitize_nvm = 0x84,
1170 nvme_admin_get_lba_status = 0x86,
1171 nvme_admin_vendor_start = 0xC0,
1174 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1175 #define show_admin_opcode_name(val) \
1176 __print_symbolic(val, \
1177 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1178 nvme_admin_opcode_name(nvme_admin_create_sq), \
1179 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1180 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1181 nvme_admin_opcode_name(nvme_admin_create_cq), \
1182 nvme_admin_opcode_name(nvme_admin_identify), \
1183 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1184 nvme_admin_opcode_name(nvme_admin_set_features), \
1185 nvme_admin_opcode_name(nvme_admin_get_features), \
1186 nvme_admin_opcode_name(nvme_admin_async_event), \
1187 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1188 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1189 nvme_admin_opcode_name(nvme_admin_download_fw), \
1190 nvme_admin_opcode_name(nvme_admin_dev_self_test), \
1191 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1192 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1193 nvme_admin_opcode_name(nvme_admin_directive_send), \
1194 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1195 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \
1196 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \
1197 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \
1198 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1199 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1200 nvme_admin_opcode_name(nvme_admin_security_send), \
1201 nvme_admin_opcode_name(nvme_admin_security_recv), \
1202 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1203 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1206 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1207 NVME_CQ_IRQ_ENABLED = (1 << 1),
1208 NVME_SQ_PRIO_URGENT = (0 << 1),
1209 NVME_SQ_PRIO_HIGH = (1 << 1),
1210 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1211 NVME_SQ_PRIO_LOW = (3 << 1),
1212 NVME_FEAT_ARBITRATION = 0x01,
1213 NVME_FEAT_POWER_MGMT = 0x02,
1214 NVME_FEAT_LBA_RANGE = 0x03,
1215 NVME_FEAT_TEMP_THRESH = 0x04,
1216 NVME_FEAT_ERR_RECOVERY = 0x05,
1217 NVME_FEAT_VOLATILE_WC = 0x06,
1218 NVME_FEAT_NUM_QUEUES = 0x07,
1219 NVME_FEAT_IRQ_COALESCE = 0x08,
1220 NVME_FEAT_IRQ_CONFIG = 0x09,
1221 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1222 NVME_FEAT_ASYNC_EVENT = 0x0b,
1223 NVME_FEAT_AUTO_PST = 0x0c,
1224 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1225 NVME_FEAT_TIMESTAMP = 0x0e,
1226 NVME_FEAT_KATO = 0x0f,
1227 NVME_FEAT_HCTM = 0x10,
1228 NVME_FEAT_NOPSC = 0x11,
1229 NVME_FEAT_RRL = 0x12,
1230 NVME_FEAT_PLM_CONFIG = 0x13,
1231 NVME_FEAT_PLM_WINDOW = 0x14,
1232 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1233 NVME_FEAT_SANITIZE = 0x17,
1234 NVME_FEAT_SW_PROGRESS = 0x80,
1235 NVME_FEAT_HOST_ID = 0x81,
1236 NVME_FEAT_RESV_MASK = 0x82,
1237 NVME_FEAT_RESV_PERSIST = 0x83,
1238 NVME_FEAT_WRITE_PROTECT = 0x84,
1239 NVME_FEAT_VENDOR_START = 0xC0,
1240 NVME_FEAT_VENDOR_END = 0xFF,
1241 NVME_LOG_ERROR = 0x01,
1242 NVME_LOG_SMART = 0x02,
1243 NVME_LOG_FW_SLOT = 0x03,
1244 NVME_LOG_CHANGED_NS = 0x04,
1245 NVME_LOG_CMD_EFFECTS = 0x05,
1246 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1247 NVME_LOG_TELEMETRY_HOST = 0x07,
1248 NVME_LOG_TELEMETRY_CTRL = 0x08,
1249 NVME_LOG_ENDURANCE_GROUP = 0x09,
1250 NVME_LOG_ANA = 0x0c,
1251 NVME_LOG_DISC = 0x70,
1252 NVME_LOG_RESERVATION = 0x80,
1253 NVME_FWACT_REPL = (0 << 3),
1254 NVME_FWACT_REPL_ACTV = (1 << 3),
1255 NVME_FWACT_ACTV = (2 << 3),
1258 /* NVMe Namespace Write Protect State */
1260 NVME_NS_NO_WRITE_PROTECT = 0,
1261 NVME_NS_WRITE_PROTECT,
1262 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1263 NVME_NS_WRITE_PROTECT_PERMANENT,
1266 #define NVME_MAX_CHANGED_NAMESPACES 1024
1268 struct nvme_identify {
1274 union nvme_data_ptr dptr;
1283 #define NVME_IDENTIFY_DATA_SIZE 4096
1285 struct nvme_features {
1291 union nvme_data_ptr dptr;
1300 struct nvme_host_mem_buf_desc {
1306 struct nvme_create_cq {
1320 struct nvme_create_sq {
1334 struct nvme_delete_queue {
1344 struct nvme_abort_cmd {
1354 struct nvme_download_firmware {
1359 union nvme_data_ptr dptr;
1365 struct nvme_format_cmd {
1375 struct nvme_get_log_page_command {
1381 union nvme_data_ptr dptr;
1383 __u8 lsp; /* upper 4 bits reserved */
1399 struct nvme_directive_cmd {
1405 union nvme_data_ptr dptr;
1418 * Fabrics subcommands.
1420 enum nvmf_fabrics_opcode {
1421 nvme_fabrics_command = 0x7f,
1424 enum nvmf_capsule_command {
1425 nvme_fabrics_type_property_set = 0x00,
1426 nvme_fabrics_type_connect = 0x01,
1427 nvme_fabrics_type_property_get = 0x04,
1428 nvme_fabrics_type_auth_send = 0x05,
1429 nvme_fabrics_type_auth_receive = 0x06,
1432 #define nvme_fabrics_type_name(type) { type, #type }
1433 #define show_fabrics_type_name(type) \
1434 __print_symbolic(type, \
1435 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1436 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1437 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1438 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \
1439 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1442 * If not fabrics command, fctype will be ignored.
1444 #define show_opcode_name(qid, opcode, fctype) \
1445 ((opcode) == nvme_fabrics_command ? \
1446 show_fabrics_type_name(fctype) : \
1448 show_nvm_opcode_name(opcode) : \
1449 show_admin_opcode_name(opcode)))
1451 struct nvmf_common_command {
1461 * The legal cntlid range a NVMe Target will provide.
1462 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1463 * Devices based on earlier specs did not have the subsystem concept;
1464 * therefore, those devices had their cntlid value set to 0 as a result.
1466 #define NVME_CNTLID_MIN 1
1467 #define NVME_CNTLID_MAX 0xffef
1468 #define NVME_CNTLID_DYNAMIC 0xffff
1470 #define MAX_DISC_LOGS 255
1472 /* Discovery log page entry flags (EFLAGS): */
1474 NVME_DISC_EFLAGS_EPCSD = (1 << 1),
1475 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1478 /* Discovery log page entry */
1479 struct nvmf_disc_rsp_page_entry {
1489 char trsvcid[NVMF_TRSVCID_SIZE];
1491 char subnqn[NVMF_NQN_FIELD_LEN];
1492 char traddr[NVMF_TRADDR_SIZE];
1494 char common[NVMF_TSAS_SIZE];
1509 /* Discovery log page header */
1510 struct nvmf_disc_rsp_page_hdr {
1515 struct nvmf_disc_rsp_page_entry entries[];
1519 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1522 struct nvmf_connect_command {
1528 union nvme_data_ptr dptr;
1539 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18),
1540 NVME_CONNECT_AUTHREQ_ATR = (1U << 17),
1543 struct nvmf_connect_data {
1547 char subsysnqn[NVMF_NQN_FIELD_LEN];
1548 char hostnqn[NVMF_NQN_FIELD_LEN];
1552 struct nvmf_property_set_command {
1565 struct nvmf_property_get_command {
1577 struct nvmf_auth_common_command {
1583 union nvme_data_ptr dptr;
1592 struct nvmf_auth_send_command {
1598 union nvme_data_ptr dptr;
1607 struct nvmf_auth_receive_command {
1613 union nvme_data_ptr dptr;
1622 /* Value for secp */
1624 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9,
1627 /* Defined value for auth_type */
1629 NVME_AUTH_COMMON_MESSAGES = 0x00,
1630 NVME_AUTH_DHCHAP_MESSAGES = 0x01,
1633 /* Defined messages for auth_id */
1635 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00,
1636 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01,
1637 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02,
1638 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03,
1639 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04,
1640 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0,
1641 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1,
1644 struct nvmf_auth_dhchap_protocol_descriptor {
1653 NVME_AUTH_DHCHAP_AUTH_ID = 0x01,
1656 /* Defined hash functions for DH-HMAC-CHAP authentication */
1658 NVME_AUTH_HASH_SHA256 = 0x01,
1659 NVME_AUTH_HASH_SHA384 = 0x02,
1660 NVME_AUTH_HASH_SHA512 = 0x03,
1661 NVME_AUTH_HASH_INVALID = 0xff,
1664 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1666 NVME_AUTH_DHGROUP_NULL = 0x00,
1667 NVME_AUTH_DHGROUP_2048 = 0x01,
1668 NVME_AUTH_DHGROUP_3072 = 0x02,
1669 NVME_AUTH_DHGROUP_4096 = 0x03,
1670 NVME_AUTH_DHGROUP_6144 = 0x04,
1671 NVME_AUTH_DHGROUP_8192 = 0x05,
1672 NVME_AUTH_DHGROUP_INVALID = 0xff,
1675 union nvmf_auth_protocol {
1676 struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1679 struct nvmf_auth_dhchap_negotiate_data {
1686 union nvmf_auth_protocol auth_protocol[];
1689 struct nvmf_auth_dhchap_challenge_data {
1700 /* 'hl' bytes of challenge value */
1702 /* followed by 'dhvlen' bytes of DH value */
1705 struct nvmf_auth_dhchap_reply_data {
1716 /* 'hl' bytes of response data */
1718 /* followed by 'hl' bytes of Challenge value */
1719 /* followed by 'dhvlen' bytes of DH value */
1723 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1726 struct nvmf_auth_dhchap_success1_data {
1735 /* 'hl' bytes of response value */
1739 struct nvmf_auth_dhchap_success2_data {
1747 struct nvmf_auth_dhchap_failure_data {
1757 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01,
1761 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01,
1762 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02,
1763 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03,
1764 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04,
1765 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05,
1766 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06,
1767 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07,
1781 struct streams_directive_params {
1793 struct nvme_command {
1795 struct nvme_common_command common;
1796 struct nvme_rw_command rw;
1797 struct nvme_identify identify;
1798 struct nvme_features features;
1799 struct nvme_create_cq create_cq;
1800 struct nvme_create_sq create_sq;
1801 struct nvme_delete_queue delete_queue;
1802 struct nvme_download_firmware dlfw;
1803 struct nvme_format_cmd format;
1804 struct nvme_dsm_cmd dsm;
1805 struct nvme_write_zeroes_cmd write_zeroes;
1806 struct nvme_zone_mgmt_send_cmd zms;
1807 struct nvme_zone_mgmt_recv_cmd zmr;
1808 struct nvme_abort_cmd abort;
1809 struct nvme_get_log_page_command get_log_page;
1810 struct nvmf_common_command fabrics;
1811 struct nvmf_connect_command connect;
1812 struct nvmf_property_set_command prop_set;
1813 struct nvmf_property_get_command prop_get;
1814 struct nvmf_auth_common_command auth_common;
1815 struct nvmf_auth_send_command auth_send;
1816 struct nvmf_auth_receive_command auth_receive;
1817 struct nvme_dbbuf dbbuf;
1818 struct nvme_directive_cmd directive;
1822 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1824 return cmd->common.opcode == nvme_fabrics_command;
1827 struct nvme_error_slot {
1831 __le16 status_field;
1832 __le16 param_error_location;
1841 static inline bool nvme_is_write(struct nvme_command *cmd)
1846 * Why can't we simply have a Fabrics In and Fabrics out command?
1848 if (unlikely(nvme_is_fabrics(cmd)))
1849 return cmd->fabrics.fctype & 1;
1850 return cmd->common.opcode & 1;
1855 * Generic Command Status:
1857 NVME_SC_SUCCESS = 0x0,
1858 NVME_SC_INVALID_OPCODE = 0x1,
1859 NVME_SC_INVALID_FIELD = 0x2,
1860 NVME_SC_CMDID_CONFLICT = 0x3,
1861 NVME_SC_DATA_XFER_ERROR = 0x4,
1862 NVME_SC_POWER_LOSS = 0x5,
1863 NVME_SC_INTERNAL = 0x6,
1864 NVME_SC_ABORT_REQ = 0x7,
1865 NVME_SC_ABORT_QUEUE = 0x8,
1866 NVME_SC_FUSED_FAIL = 0x9,
1867 NVME_SC_FUSED_MISSING = 0xa,
1868 NVME_SC_INVALID_NS = 0xb,
1869 NVME_SC_CMD_SEQ_ERROR = 0xc,
1870 NVME_SC_SGL_INVALID_LAST = 0xd,
1871 NVME_SC_SGL_INVALID_COUNT = 0xe,
1872 NVME_SC_SGL_INVALID_DATA = 0xf,
1873 NVME_SC_SGL_INVALID_METADATA = 0x10,
1874 NVME_SC_SGL_INVALID_TYPE = 0x11,
1875 NVME_SC_CMB_INVALID_USE = 0x12,
1876 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1877 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1878 NVME_SC_OP_DENIED = 0x15,
1879 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1880 NVME_SC_RESERVED = 0x17,
1881 NVME_SC_HOST_ID_INCONSIST = 0x18,
1882 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1883 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1884 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
1885 NVME_SC_SANITIZE_FAILED = 0x1C,
1886 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1887 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1888 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
1889 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1890 NVME_SC_CMD_INTERRUPTED = 0x21,
1891 NVME_SC_TRANSIENT_TR_ERR = 0x22,
1892 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1893 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
1895 NVME_SC_LBA_RANGE = 0x80,
1896 NVME_SC_CAP_EXCEEDED = 0x81,
1897 NVME_SC_NS_NOT_READY = 0x82,
1898 NVME_SC_RESERVATION_CONFLICT = 0x83,
1899 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
1902 * Command Specific Status:
1904 NVME_SC_CQ_INVALID = 0x100,
1905 NVME_SC_QID_INVALID = 0x101,
1906 NVME_SC_QUEUE_SIZE = 0x102,
1907 NVME_SC_ABORT_LIMIT = 0x103,
1908 NVME_SC_ABORT_MISSING = 0x104,
1909 NVME_SC_ASYNC_LIMIT = 0x105,
1910 NVME_SC_FIRMWARE_SLOT = 0x106,
1911 NVME_SC_FIRMWARE_IMAGE = 0x107,
1912 NVME_SC_INVALID_VECTOR = 0x108,
1913 NVME_SC_INVALID_LOG_PAGE = 0x109,
1914 NVME_SC_INVALID_FORMAT = 0x10a,
1915 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1916 NVME_SC_INVALID_QUEUE = 0x10c,
1917 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1918 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1919 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1920 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1921 NVME_SC_FW_NEEDS_RESET = 0x111,
1922 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1923 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1924 NVME_SC_OVERLAPPING_RANGE = 0x114,
1925 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1926 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1927 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1928 NVME_SC_NS_IS_PRIVATE = 0x119,
1929 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1930 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1931 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1932 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
1933 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1934 NVME_SC_CTRL_ID_INVALID = 0x11f,
1935 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1936 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1937 NVME_SC_RES_ID_INVALID = 0x122,
1938 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1939 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1940 NVME_SC_ANA_ATTACH_FAILED = 0x125,
1943 * I/O Command Set Specific - NVM commands:
1945 NVME_SC_BAD_ATTRIBUTES = 0x180,
1946 NVME_SC_INVALID_PI = 0x181,
1947 NVME_SC_READ_ONLY = 0x182,
1948 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1951 * I/O Command Set Specific - Fabrics commands:
1953 NVME_SC_CONNECT_FORMAT = 0x180,
1954 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1955 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1956 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1957 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1959 NVME_SC_DISCOVERY_RESTART = 0x190,
1960 NVME_SC_AUTH_REQUIRED = 0x191,
1963 * I/O Command Set Specific - Zoned commands:
1965 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1966 NVME_SC_ZONE_FULL = 0x1b9,
1967 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1968 NVME_SC_ZONE_OFFLINE = 0x1bb,
1969 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1970 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1971 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1972 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1975 * Media and Data Integrity Errors:
1977 NVME_SC_WRITE_FAULT = 0x280,
1978 NVME_SC_READ_ERROR = 0x281,
1979 NVME_SC_GUARD_CHECK = 0x282,
1980 NVME_SC_APPTAG_CHECK = 0x283,
1981 NVME_SC_REFTAG_CHECK = 0x284,
1982 NVME_SC_COMPARE_FAILED = 0x285,
1983 NVME_SC_ACCESS_DENIED = 0x286,
1984 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1987 * Path-related Errors:
1989 NVME_SC_INTERNAL_PATH_ERROR = 0x300,
1990 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1991 NVME_SC_ANA_INACCESSIBLE = 0x302,
1992 NVME_SC_ANA_TRANSITION = 0x303,
1993 NVME_SC_CTRL_PATH_ERROR = 0x360,
1994 NVME_SC_HOST_PATH_ERROR = 0x370,
1995 NVME_SC_HOST_ABORTED_CMD = 0x371,
1997 NVME_SC_CRD = 0x1800,
1998 NVME_SC_MORE = 0x2000,
1999 NVME_SC_DNR = 0x4000,
2002 struct nvme_completion {
2004 * Used by Admin and Fabrics commands to return data:
2011 __le16 sq_head; /* how much of this queue may be reclaimed */
2012 __le16 sq_id; /* submission queue that generated this entry */
2013 __u16 command_id; /* of the command which completed */
2014 __le16 status; /* did the command fail, and if so, why? */
2017 #define NVME_VS(major, minor, tertiary) \
2018 (((major) << 16) | ((minor) << 8) | (tertiary))
2020 #define NVME_MAJOR(ver) ((ver) >> 16)
2021 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
2022 #define NVME_TERTIARY(ver) ((ver) & 0xff)
2024 #endif /* _LINUX_NVME_H */